Integrated circuit interruption verification method and device, electronic equipment and computer readable storage medium

Abstract

The embodiment of the invention provides an integrated circuit interruption verification method and device, electronic equipment and a computer readable storage medium, and relates to the technical field of integrated circuits, the method comprises the following steps: obtaining interruption source information of a to-be-verified integrated circuit, the interruption source information comprising configuration information corresponding to each interruption source, the configuration information corresponding to each interrupt source is analyzed, an interface file and a test case are generated, the interface file comprises interface information corresponding to each interrupt source, and interrupt trigger verification is conducted on the integrated circuit to be verified according to the interface information in the interface file. And performing interrupt function verification on each interrupt source of the to-be-verified integrated circuit according to the interface information in the interface file and the test case. The configuration information corresponding to each interrupt source is analyzed to automatically generate the interface file and the test case, and then interrupt verification is performed according to the interface file and the test case, so that manual intervention of interrupt verification is avoided, and the interrupt verification efficiency and accuracy are improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to an integrated circuit interrupt verification method, device, electronic device and computer-readable storage medium. Background Art

[0002] As an important bridge for the interaction between hardware and software, the interrupt system is used to report relevant information to the software through the interrupt mechanism when the hardware detects a situation that requires a timely response from the software, such as when an abnormal situation is detected or certain instructions need to be processed by the software. The software then executes the corresponding processing logic according to the interrupt status. Ensuring the correctness of the interrupt mechanism is crucial to the stable operation of the entire integrated circuit.

[0003] Existing interrupt verification methods often rely on human intervention or manual operation. The operation verification process of registers such as interrupt enable, interrupt mask, interrupt status management, and interrupt clear is cumbersome and complicated. If test cases are written manually, errors are easily introduced, affecting the accuracy and efficiency of the interrupt verification results. Summary of the invention

[0004] The object of the present invention is to provide an integrated circuit interrupt verification method, device, electronic device and computer-readable storage medium to solve the problem of low efficiency and accuracy of interrupt verification.

[0005] In a first aspect, the present invention provides an integrated circuit interrupt verification method, the method comprising:

[0006] Obtaining interrupt source information of the integrated circuit to be verified; the interrupt source information includes configuration information corresponding to each interrupt source;

[0007] Parsing the configuration information corresponding to each of the interrupt sources to generate an interface file and a test case; the interface file includes the interface information corresponding to each of the interrupt sources;

[0008] Performing interrupt trigger verification on the integrated circuit to be verified according to the interface information in the interface file to verify whether the integrated circuit to be verified correctly generates each of the interrupt sources;

[0009] The interrupt function of each interrupt source of the integrated circuit to be verified is verified according to the interface information in the interface file and the test case.

[0010] In an optional implementation manner, performing interrupt trigger verification on the integrated circuit to be verified according to the interface information in the interface file includes:

[0011] A target incentive message is randomly selected from a plurality of preset incentive messages; the target incentive message is an incentive message that triggers a target interrupt source;

[0012] Sending the target stimulus message to the integrated circuit to be verified according to the interface information corresponding to the target interrupt source, and receiving the actual interrupt source generated by the integrated circuit to be verified according to the target stimulus message;

[0013] Acquire an expected interrupt source generated by a simulation model of the integrated circuit to be verified according to the target stimulus message;

[0014] The expected interrupt source is compared with the actual interrupt source to determine whether the integrated circuit to be verified correctly responds to the target interrupt source.

[0015] In an optional implementation manner, the test case includes a test list and a test process, and the interrupt function verification of each interrupt source of the integrated circuit to be verified according to the interface information in the interface file and the test case includes:

[0016] Testing the current test interrupt source according to the test flow corresponding to the current test interrupt source to obtain a test result of the current test interrupt source; the test result indicates whether the interrupt function of the current test interrupt source is normal;

[0017] If the test result of the currently tested interrupt source is passed, the next interrupt source is tested according to the test list.

[0018] In an optional implementation manner, testing the integrated circuit to be verified according to the test flow corresponding to the current test interrupt source to obtain the test result of the current test interrupt source includes:

[0019] Configure the interrupt mask function of the current test interrupt source to be turned off and the interrupt enable function to be turned on, and trigger the current test interrupt source according to the interface information corresponding to the current test interrupt source;

[0020] Determine whether the interrupt mask function of the current test interrupt source is normal according to whether the integrated circuit to be verified currently generates an interrupt signal corresponding to the current test interrupt source, the original interrupt state, and the interrupt mask state;

[0021] If the interrupt mask function of the current test interrupt source is normal, clear the current test interrupt source;

[0022] After clearing the current test interrupt source, judging whether the interrupt clearing function of the current test interrupt source is normal according to whether the interrupt signal, the interrupt original state and the interrupt mask state are cleared;

[0023] If the interrupt clearing function of the current test interrupt source is normal, configure the interrupt enabling function of the current test interrupt source to be turned off, and trigger the current test interrupt source according to the interface information corresponding to the current test interrupt source;

[0024] According to whether the integrated circuit to be verified currently generates the interrupt signal, the original state of the interrupt, and the interrupt mask state, determining whether the interrupt enable function of the current test interrupt source is normal;

[0025] If the enabling function of the interrupt enabling function of the currently tested interrupt source is normal, the test result of the currently tested interrupt source is passed;

[0026] If the interrupt enable function, the interrupt clear function or the interrupt enable function of the interrupt source currently under test is abnormal, the test result of the interrupt source currently under test is failure.

[0027] In an optional implementation, judging whether the interrupt mask function of the current test interrupt source is normal according to whether the integrated circuit to be verified currently generates an interrupt signal corresponding to the current test interrupt source, an interrupt original state, and an interrupt mask state, includes:

[0028] If the integrated circuit to be verified currently generates the interrupt signal, or does not generate the interrupt original state, or generates the interrupt mask state, then the interrupt mask function of the current test interrupt source is abnormal;

[0029] If the integrated circuit to be verified does not currently generate the interrupt signal, generates the interrupt original state, and does not generate the interrupt mask state, then configure the interrupt mask function of the current test interrupt source to be turned on;

[0030] After the interrupt mask function of the current test interrupt source is turned on, if the integrated circuit to be verified does not currently generate the interrupt signal, or does not generate the interrupt original state, or generates the interrupt mask state, then the interrupt mask function of the current test interrupt source is abnormal;

[0031] If the integrated circuit to be verified currently generates the interrupt signal, generates the interrupt original state and does not generate the interrupt mask state, then the interrupt mask function of the current test interrupt source is normal.

[0032] In an optional implementation manner, after clearing the current test interrupt source, judging whether the interrupt clearing function of the current test interrupt source is normal according to whether the interrupt signal, the interrupt original state, and the interrupt mask state are cleared includes:

[0033] After clearing the current test interrupt source, if at least one of the interrupt signal, the interrupt original state, and the interrupt mask state is not cleared, the interrupt clearing function of the current test interrupt source is abnormal;

[0034] If the interrupt signal, the interrupt original state, and the interrupt mask state are all cleared, the interrupt clearing function of the current test interrupt source is normal.

[0035] In an optional implementation manner, judging whether the interrupt enable function of the current test interrupt source is normal according to whether the integrated circuit to be verified currently generates the interrupt signal, the interrupt original state, and the interrupt mask state includes:

[0036] If the integrated circuit to be verified currently generates the interrupt signal, or generates the interrupt original state, or generates the interrupt mask state, then the interrupt enable function of the current test interrupt source is abnormal;

[0037] If the integrated circuit to be verified currently does not generate the interrupt signal, does not generate the interrupt original state, and does not generate the interrupt mask state, then the interrupt enable function of the current test interrupt source is normal.

[0038] In a second aspect, the present invention provides an interrupt verification device, the device comprising:

[0039] An interrupt source information obtaining module, used to obtain the interrupt source information of the integrated circuit to be verified; the interrupt source information includes configuration information corresponding to each interrupt source;

[0040] A configuration information parsing module, used to parse the configuration information corresponding to each of the interrupt sources, and generate an interface file and a test case; the interface file includes the interface information corresponding to each of the interrupt sources;

[0041] An interrupt trigger verification module, used to perform interrupt trigger verification on the integrated circuit to be verified according to the interface information in the interface file, so as to verify whether the integrated circuit to be verified correctly generates each of the interrupt sources;

[0042] The interrupt function verification module is used to verify the interrupt function of each interrupt source of the integrated circuit to be verified according to the interface information in the interface file and the test case.

[0043] In a third aspect, the present invention provides an electronic device, comprising a processor and a memory, wherein the memory stores a computer program executable by the processor, and the computer program executable by the processor is used to implement the integrated circuit interrupt verification method described in any of the aforementioned embodiments.

[0044] In a fourth aspect, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the integrated circuit interrupt verification method as described in any one of the aforementioned embodiments is implemented.

[0045] The embodiment of the present invention provides an integrated circuit interrupt verification method, device, electronic device and computer-readable storage medium, the method comprising: obtaining interrupt source information of the integrated circuit to be verified, the interrupt source information including configuration information corresponding to each interrupt source, parsing the configuration information corresponding to each interrupt source, generating an interface file and a test case, the interface file including interface information corresponding to each interrupt source, performing interrupt trigger verification on the integrated circuit to be verified according to the interface information in the interface file to verify whether the integrated circuit to be verified correctly generates each interrupt source, and performing interrupt function verification on each interrupt source of the integrated circuit to be verified according to the interface information in the interface file and the test case. Interrupt verification is automatically performed by parsing the generated interface file and test case according to the configuration information corresponding to each interrupt source, avoiding manual intervention in interrupt verification, thereby improving the efficiency and accuracy of interrupt verification. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0047] Figure 1 A schematic diagram of a flow chart of an integrated circuit interrupt verification method provided by an embodiment of the present invention is shown;

[0048] Figure 2 Another schematic flow chart of the integrated circuit interrupt verification method provided by an embodiment of the present invention is shown;

[0049] Figure 3 Another schematic flow chart of an integrated circuit interrupt verification method provided by an embodiment of the present invention is shown;

[0050] Figure 4 A module block diagram of an interrupt verification device provided by an embodiment of the present invention is shown;

[0051] Figure 5 A block diagram of an electronic device provided by an embodiment of the present invention is shown.

[0052] Icons: 100 - electronic device; 200 - interruption verification device; 210 - interruption source information acquisition module; 220 - configuration information parsing module; 230 - interruption trigger verification module; 240 - interruption function verification module; 110 - memory; 120 - processor; 130 - communication module. DETAILED DESCRIPTION

[0053] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0054] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0055] It should be noted that relational terms such as "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0056] See also Figure 1 , Figure 1 A schematic diagram of a flow chart of an integrated circuit interrupt verification method provided by an embodiment of the present invention is shown. The integrated circuit interrupt verification method can be applied to electronic devices. The specific flow of this embodiment is described below using electronic devices as an example. Figure 1 The process shown in FIG. 1 is described in detail, and the integrated circuit interrupt verification method may specifically include the following steps:

[0057] Step 110: Obtain interrupt source information of the integrated circuit to be verified; the interrupt source information includes configuration information corresponding to each interrupt source.

[0058] In some implementations, an interrupt verification platform is run in the electronic device, and an RTL (register-transfer level) file of the integrated circuit to be verified is stored in the electronic device. It should be noted that the RTL file is mainly used to describe the logical operations and data flows between registers in the integrated circuit to be verified. The interrupt verification platform can perform interrupt verification on the RTL file of the integrated circuit to be verified to implement interrupt verification of the integrated circuit to be verified.

[0059] The interrupt source information of the integrated circuit to be verified is shown in Table 1. The configuration information corresponding to each interrupt source includes the interrupt status register (int state), the interrupt mask register (int mask), the interrupt raw status register (int rawstate), the interrupt enable register (int en), the corresponding bit position (bit num) and the path (source path) of the interrupt source in the rtl file.

[0060] Table 1

[0061]

[0062] Step 120: Parse the configuration information corresponding to each interrupt source and generate an interface file and a test case.

[0063] The interface file includes interface information corresponding to each interrupt source, including interface information for triggering the corresponding interrupt source and interface information for outputting the corresponding interrupt source.

[0064] In some embodiments, the configuration information corresponding to each interrupt source includes the path of the interrupt source in the rtl file. The interrupt verification platform parses the path of each interrupt source in the rtl file and generates an interface file. The interface file includes interface information of each interrupt source. The interrupt verification platform can trigger and receive the actual interrupt source according to the interface information of each interrupt source.

[0065] In some implementations, the interrupt source information may be an Excel file, which is not limited here. The interrupt verification platform may parse the interrupt source information using a third-party library that parses Excel files. The third-party library that parses Excel files may first identify one of the interrupt sources in the source path column according to the format in Table 1, and then obtain the corresponding interrupt status register, interrupt mask register, interrupt original status register, interrupt enable register, and corresponding bit positions, and generate a corresponding test flow according to the corresponding interrupt status register, interrupt mask register, interrupt original status register, interrupt enable register, and corresponding bit positions, and generate a test case according to the test flow of all interrupt sources.

[0066] The third-party library for parsing the Excel file may be a third-party library of Python, such as openpyxl, xlrd, etc.

[0067] Step 130: Perform interrupt trigger verification on the integrated circuit to be verified according to the interface information in the interface file to verify whether the integrated circuit to be verified correctly generates each interrupt source.

[0068] In some implementations, the interrupt verification platform may trigger the integrated circuit to be verified to generate a corresponding interrupt source according to the interface information of each interrupt source, so as to verify whether the integrated circuit to be verified correctly generates each interrupt source.

[0069] Step 140: Perform interrupt function verification on each interrupt source of the integrated circuit to be verified according to the interface information in the interface file and the test case.

[0070] In some embodiments, the interrupt verification platform can run test cases, and the interrupt verification platform can trigger the corresponding interrupt source through the interface information of the interface file to detect whether the behavior of the integrated circuit to be verified with respect to the interrupt source is consistent with expectations, so as to verify whether the interrupt function of the interrupt source of the integrated circuit to be verified is normal.

[0071] In some implementations, the interrupt verification platform can record any abnormal behaviors and unexpected results that occur during the functional verification process for each interrupt source. The interrupt verification platform can also analyze these abnormal behaviors and unexpected results, determine the cause of the problem, and generate a detailed verification result report. Developers can debug and repair the integrated circuit to be verified in a targeted manner based on these reports, thereby improving the efficiency and quality of integrated circuit development.

[0072] The order in which the interrupt verification platform performs interrupt trigger verification and interrupt function verification can be set according to the actual application and is not limited here. The interrupt verification platform can first perform interrupt trigger verification and then perform interrupt function verification; the interrupt verification platform can also first perform interrupt function verification and then perform interrupt trigger verification.

[0073] The integrated circuit interrupt verification method provided by the embodiment of the present invention obtains the interrupt source information of the integrated circuit to be verified, the interrupt source information includes the configuration information corresponding to each interrupt source, the configuration information corresponding to each interrupt source is parsed, an interface file and a test case are generated, the interface file includes the interface information corresponding to each interrupt source, the interrupt trigger verification is performed on the integrated circuit to be verified according to the interface information in the interface file to verify whether the integrated circuit to be verified correctly generates each interrupt source, and the interrupt function is verified for each interrupt source of the integrated circuit to be verified according to the interface information in the interface file and the test case. The interrupt verification is automatically performed by parsing the generated interface file and test case according to the configuration information corresponding to each interrupt source, avoiding manual intervention in the interrupt verification, thereby improving the efficiency and accuracy of the interrupt verification.

[0074] In order to perform interrupt trigger verification on the IC to be verified in random scenarios, such as Figure 2 As shown, step 130 specifically further includes the following steps:

[0075] Step 131: randomly selecting a target stimulus message from a plurality of preset stimulus messages; the target stimulus message is a stimulus message that triggers a target interrupt source.

[0076] It is understandable that by randomly selecting the target stimulus message to perform interrupt trigger verification on the IC to be verified, it can be verified whether the IC to be verified can normally trigger the corresponding interrupt source under various inputs, rather than just under expected or typical inputs. This helps to discover potential problems of the IC to be verified under atypical inputs, thereby improving the reliability of interrupt verification. And the automated selection of stimulus messages can improve the efficiency of interrupt verification.

[0077] Step 132: Send a target stimulus message to the integrated circuit to be verified according to the interface information corresponding to the target interrupt source, and receive the actual interrupt source generated by the integrated circuit to be verified according to the target stimulus message.

[0078] In some embodiments, the interface information corresponding to the target interrupt source includes interface information for triggering the target interrupt source and interface information for receiving the target interrupt source. The interrupt verification platform can send a target stimulus message to the integrated circuit to be verified based on the interface information for triggering the target interrupt source. The integrated circuit to be verified generates a corresponding interrupt source based on the target stimulus message. The interrupt verification platform receives the actual interrupt source generated by the integrated circuit to be verified based on the target stimulus message based on the interface information for receiving the target interrupt source.

[0079] Step 133: Obtain the expected interrupt source generated by the simulation model of the integrated circuit to be verified according to the target stimulus message.

[0080] In some embodiments, the interrupt verification platform includes a simulation model of the integrated circuit to be verified, and the simulation model of the integrated circuit to be verified may be a refm model (reference model), wherein the refm model is used to simulate the behavior of the integrated circuit to be verified and generate a corresponding expected interrupt source according to the stimulus message. The interrupt verification platform may obtain the expected interrupt source generated by the refm model of the integrated circuit to be verified according to the target stimulus message.

[0081] Step 134: Compare the expected interrupt source with the actual interrupt source to determine whether the integrated circuit to be verified correctly responds to the target interrupt source.

[0082] In some embodiments, the interrupt verification platform includes a SCBD (Scoreboard), which can be used to check whether the interrupt source of the actual output of the integrated circuit to be verified is consistent with the interrupt source of the expected output. The SCBD can compare the expected interrupt source with the actual interrupt source to determine whether the integrated circuit to be verified correctly responds to the target interrupt source. If the expected interrupt source is consistent with the actual interrupt source, the integrated circuit to be verified can correctly respond to the target interrupt source; if the expected interrupt source is inconsistent with the actual interrupt source, the integrated circuit to be verified cannot correctly respond to the target interrupt source, that is, the interrupt processing logic of the integrated circuit to be verified cannot work as expected.

[0083] In order to verify the interrupt function of each interrupt source of the integrated circuit to be verified, the test case includes a test list and a test process. Step 140 specifically also includes the following steps: testing the current test interrupt source according to the test process corresponding to the current test interrupt source to obtain the test result of the current test interrupt source; the test result indicates whether the interrupt function of the current test interrupt source is normal; if the test result of the current test interrupt source is passed, testing the next interrupt source according to the test list.

[0084] As an implementation method, the interrupt verification platform may randomly select the next interrupt source from the test list for testing.

[0085] As another implementation, the interrupt verification platform may also select the next interrupt source of the target interrupt source from the test list for testing.

[0086] like Figure 3 As shown, the test process corresponding to the current test interrupt source is as follows:

[0087] Step 141: configure the interrupt mask function of the current test interrupt source to be turned off and the interrupt enable function to be turned on, and trigger the current test interrupt source according to the interface information corresponding to the current test interrupt source.

[0088] In some implementations, the interrupt verification platform pre-configures a register configuration interface, and the interrupt verification platform can configure the interrupt register of the integrated circuit to be verified through the register configuration interface. The interrupt verification platform can read the interrupt-related register of the integrated circuit to be verified through the register configuration interface, and judge whether the integrated circuit to be verified currently generates or clears the interrupt signal, interrupt original state, and interrupt mask state corresponding to the current test interrupt source according to the result of reading the interrupt-related register. When the interrupt verification platform starts to test the current test interrupt source, it configures the interrupt mask function of the current test interrupt source to be turned off and the interrupt enable function to be turned on through the register configuration interface, and triggers the current test interrupt source according to the interface information corresponding to the current test interrupt source.

[0089] The register configuration interface may be an APB (advanced peripheral bus) interface or the like.

[0090] Step 142: Determine whether the interrupt mask function of the current test interrupt source is normal based on whether the integrated circuit to be verified currently generates an interrupt signal corresponding to the current test interrupt source, the original interrupt state, and the interrupt mask state.

[0091] In some embodiments, if the integrated circuit to be verified currently generates an interrupt signal, or does not generate an interrupt original state, or generates an interrupt mask state, the interrupt mask function of the current test interrupt source is abnormal; if the integrated circuit to be verified currently does not generate an interrupt signal, generates an interrupt original state, and does not generate an interrupt mask state, the interrupt mask function of the current test interrupt source is configured to be turned on.

[0092] It can be understood that when the interrupt enable function of the current test interrupt source is turned on, the current test interrupt source is triggered, and the interrupt original state of the current test interrupt source is correctly latched, that is, the terminal verification platform detects that the integrated circuit to be verified currently generates the interrupt original state, but the interrupt mask function of the current test interrupt source is turned off. Although the interrupt original state of the current test interrupt source is correctly latched, since the interrupt mask function is turned off, the integrated circuit to be verified will not pass the interrupt signal of the current test interrupt source to the interrupt verification platform. Therefore, the interrupt verification platform cannot detect the generation of the interrupt signal of the current test interrupt source. That is, the interrupt verification platform detects that the integrated circuit to be verified currently does not generate an interrupt signal, generates an interrupt original state, and does not generate an interrupt mask state, so that the interrupt mask function of the integrated circuit to be verified is normal.

[0093] After the interrupt mask function of the current test interrupt source is turned on, if the integrated circuit to be verified does not currently generate an interrupt signal, or does not generate an interrupt original state, or generates an interrupt mask state, then the interrupt mask function of the current test interrupt source is abnormal; if the integrated circuit to be verified currently generates an interrupt signal, generates an interrupt original state and does not generate an interrupt mask state, then the interrupt mask function of the current test interrupt source is normal.

[0094] It can be understood that after the interrupt mask function of the current test interrupt source is turned on, the integrated circuit to be verified will pass the interrupt signal of the current test interrupt source to the interrupt verification platform. Therefore, the interrupt verification platform detects the generation of the interrupt signal of the current test interrupt source. That is, the interrupt verification platform detects that the integrated circuit to be verified currently generates an interrupt signal, generates the original interrupt state and does not generate the interrupt mask state. In this way, the interrupt mask function of the integrated circuit to be verified is normal.

[0095] Step 143: If the interrupt mask function of the current test interrupt source is normal, clear the current test interrupt source.

[0096] Step 144: after clearing the current test interrupt source, judging whether the interrupt clearing function of the current test interrupt source is normal according to whether the interrupt signal, the interrupt original state and the interrupt mask state are cleared.

[0097] After the interrupt verification platform executes the operation of clearing the current test interrupt source, the interrupt verification platform can read the bits corresponding to the current test interrupt source in the interrupt status register, interrupt mask register and interrupt original status register through the register configuration interface to detect whether the interrupt signal, interrupt original status and interrupt mask status are cleared.

[0098] In some embodiments, after clearing the current test interrupt source, if at least one of the interrupt signal, the interrupt original state, and the interrupt mask state is not cleared, the interrupt clearing function of the current test interrupt source is abnormal; if the interrupt signal, the interrupt original state, and the interrupt mask state are all cleared, the interrupt clearing function of the current test interrupt source is normal.

[0099] Step 145: If the interrupt clearing function of the current test interrupt source is normal, configure the interrupt enabling function of the current test interrupt source to be disabled, and trigger the current test interrupt source according to the interface information corresponding to the current test interrupt source.

[0100] In some implementations, after the interrupt enable function of the current test interrupt source is configured to be disabled, the current test interrupt source is triggered again according to the interface information corresponding to the current test interrupt source.

[0101] Step 146: Determine whether the interrupt enable function of the current test interrupt source is normal based on whether the integrated circuit to be verified currently generates an interrupt signal, the original interrupt status, and the interrupt mask status.

[0102] After the interrupt verification platform re-triggers the current test interrupt source according to the interface information corresponding to the current test interrupt source, the interrupt verification platform can read the bits corresponding to the current test interrupt source in the interrupt status register, interrupt mask register and interrupt original status register through the register configuration interface to detect whether the interrupt signal, interrupt original status and interrupt mask status are generated.

[0103] In some embodiments, if the integrated circuit to be verified currently generates an interrupt signal, or generates an interrupt original state, or generates an interrupt mask state, the interrupt enable function of the current test interrupt source is abnormal; if the integrated circuit to be verified currently does not generate an interrupt signal, does not generate an interrupt original state, and does not generate an interrupt mask state, the interrupt enable function of the current test interrupt source is normal.

[0104] It is understandable that the interrupt enable function is used to control whether the interrupt can be received by the interrupt verification platform. When the interrupt enable function of the current test interrupt source is turned off, the interrupt signal of the current test interrupt source should not be received by the interrupt verification platform, the interrupt original state of the current test interrupt source is latched, and the interrupt original state of the current test interrupt source should not be updated, that is, the integrated circuit to be verified currently does not generate an interrupt signal, does not generate an interrupt original state, and does not generate an interrupt mask state.

[0105] Step 147: If the enabling function of the interrupt enable function of the current test interrupt source is normal, the test result of the current test interrupt source is passed; if the interrupt enable function, interrupt clear function or interrupt enable function of the current test interrupt source is abnormal, the test result of the current test interrupt source is failed.

[0106] In order to execute the corresponding steps in the above embodiments and various possible methods, a method for implementing the interrupt verification device is given below. Figure 4 , FIG. 1 is a functional module diagram of an interrupt verification device provided by an embodiment of the present invention. It should be noted that the basic principle and technical effect of the interrupt verification device provided by this embodiment are the same as those of the above-mentioned embodiments. For the sake of brief description, for the parts not mentioned in this embodiment, reference can be made to the corresponding contents in the above-mentioned embodiments. The interrupt verification device 200 includes: an interrupt source information acquisition module 210, a configuration information parsing module 220, an interrupt trigger verification module 230 and an interrupt function verification module 240, wherein:

[0107] The interrupt source information obtaining module 210 is used to obtain the interrupt source information of the integrated circuit to be verified; the interrupt source information includes the configuration information corresponding to each interrupt source;

[0108] The configuration information parsing module 220 is used to parse the configuration information corresponding to each interrupt source and generate an interface file and a test case; the interface file includes the interface information corresponding to each interrupt source.

[0109] The interrupt trigger verification module 230 is used to perform interrupt trigger verification on the integrated circuit to be verified according to the interface information in the interface file, so as to verify whether the integrated circuit to be verified correctly generates each interrupt source.

[0110] The interrupt function verification module 240 is used to verify the interrupt function of each interrupt source of the integrated circuit to be verified according to the interface information in the interface file and the test case.

[0111] Furthermore, the interrupt trigger verification module 230 is specifically used to randomly select a target stimulus message from multiple preset stimulus messages; the target stimulus message is a stimulus message that triggers a target interrupt source; the target stimulus message is sent to the integrated circuit to be verified according to the interface information corresponding to the target interrupt source, and the actual interrupt source generated by the integrated circuit to be verified according to the target stimulus message is received; the expected interrupt source generated by the simulation model of the integrated circuit to be verified according to the target stimulus message is obtained; the expected interrupt source is compared with the actual interrupt source to determine whether the integrated circuit to be verified correctly responds to the target interrupt source.

[0112] Furthermore, the test case includes a test list and a test process. The interrupt function verification module 240 is specifically used to test the current test interrupt source according to the test process corresponding to the current test interrupt source to obtain the test result of the current test interrupt source; the test result indicates whether the interrupt function of the current test interrupt source is normal; if the test result of the current test interrupt source is passed, the next interrupt source is tested according to the test list.

[0113] Furthermore, the interrupt function verification module 240 is also specifically used to configure the interrupt mask function of the current test interrupt source to be turned off and the interrupt enable function to be turned on, and to trigger the current test interrupt source according to the interface information corresponding to the current test interrupt source; to judge whether the interrupt mask function of the current test interrupt source is normal according to whether the integrated circuit to be verified currently generates the interrupt signal, the original state of the interrupt, and the interrupt mask state corresponding to the current test interrupt source; if the interrupt mask function of the current test interrupt source is normal, clear the current test interrupt source; after clearing the current test interrupt source, judge the interrupt of the current test interrupt source according to whether the interrupt signal, the original state of the interrupt, and the interrupt mask state are cleared. Whether the clear function is normal; if the interrupt clear function of the current test interrupt source is normal, configure the interrupt enable function of the current test interrupt source to be closed, and trigger the current test interrupt source according to the interface information corresponding to the current test interrupt source; judge whether the interrupt enable function of the current test interrupt source is normal according to whether the integrated circuit to be verified currently generates an interrupt signal, the original state of the interrupt, and the interrupt mask state; if the enabling function of the interrupt enable function of the current test interrupt source is normal, the test result of the current test interrupt source is passed; if the interrupt enable function, interrupt clear function or interrupt enable function of the current test interrupt source is abnormal, the test result of the current test interrupt source is failed.

[0114] Furthermore, the interrupt function verification module 240 is also specifically used to configure the interrupt mask function of the current test interrupt source to be turned on if the integrated circuit to be verified currently generates an interrupt signal, or does not generate an interrupt original state, or generates an interrupt mask state; if the integrated circuit to be verified currently does not generate an interrupt signal, generates an interrupt original state, and does not generate an interrupt mask state, then the interrupt mask function of the current test interrupt source is turned on; after the interrupt mask function of the current test interrupt source is turned on, if the integrated circuit to be verified currently does not generate an interrupt signal, or does not generate an interrupt original state, or generates an interrupt mask state, then the interrupt mask function of the current test interrupt source is abnormal; if the integrated circuit to be verified currently generates an interrupt signal, generates an interrupt original state, and does not generate an interrupt mask state, then the interrupt mask function of the current test interrupt source is normal.

[0115] Furthermore, the interrupt function verification module 240 is specifically used to, after clearing the current test interrupt source, if at least one of the interrupt signal, the interrupt original state and the interrupt mask state is not cleared, then the interrupt clearing function of the current test interrupt source is abnormal; if the interrupt signal, the interrupt original state and the interrupt mask state are all cleared, then the interrupt clearing function of the current test interrupt source is normal.

[0116] Furthermore, the interrupt function verification module 240 is specifically used to determine that if the integrated circuit to be verified currently generates an interrupt signal, or generates an interrupt original state, or generates an interrupt mask state, the interrupt enable function of the current test interrupt source is abnormal; if the integrated circuit to be verified currently does not generate an interrupt signal, does not generate an interrupt original state, and does not generate an interrupt mask state, the interrupt enable function of the current test interrupt source is normal.

[0117] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and modules can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here.

[0118] In several embodiments provided by the present invention, the coupling between modules may be electrical, mechanical or other forms of coupling.

[0119] In addition, each functional module in each embodiment of the present invention may be integrated into one processing module, or each module may exist physically separately, or two or more modules may be integrated into one module. The above-mentioned integrated module may be implemented in the form of hardware or in the form of software functional modules.

[0120] Please refer to Figure 5 , is a block diagram of an electronic device 100 provided in an embodiment of the present invention. The electronic device 100 includes a memory 110, a processor 120, and a communication module 130. The memory 110, the processor 120, and the communication module 130 are electrically connected to each other directly or indirectly to achieve data transmission or interaction. For example, these components can be electrically connected to each other through one or more communication buses or signal lines.

[0121] The memory 110 is used to store programs or data. The memory 110 may be, but is not limited to, a random access memory (RAM), a read only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), etc.

[0122] The processor 120 is used to read / write data or programs stored in the memory and execute corresponding functions. For example, when the computer program stored in the memory 110 is executed by the processor 120, the integrated circuit interrupt verification method disclosed in the above embodiments can be implemented.

[0123] The communication module 130 is used to establish a communication connection between the electronic device 100 and a server through a network, and to send and receive data through the network.

[0124] It should be understood that Figure 5 The structure shown is only a schematic diagram of the structure of the electronic device. The electronic device may also include Figure 5 More or fewer components may be shown. Figure 5 Each component shown in the figure can be implemented by hardware, software or a combination thereof.

[0125] An embodiment of the present invention further provides a computer-readable storage medium, in which a computer program is stored. When the computer program can be executed by a processor, the integrated circuit interrupt verification method described in the above method embodiment is implemented.

[0126] The computer-readable storage medium may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read-only memory), an EPROM, a hard disk, or a ROM. Optionally, the computer-readable storage medium includes a non-transitory computer-readable storage medium. The computer-readable storage medium has storage space for program codes that execute any of the method steps in the above method. These program codes can be read from or written to one or more computer program products. The program code can be compressed, for example, in an appropriate form.

[0127] In several embodiments provided by the present invention, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are merely schematic. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the devices, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and a module, a program segment or a part of the code contains one or more executable instructions for implementing the specified logical functions. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flowchart, and the combination of boxes in the block diagram and / or flowchart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0128] If the function is implemented in the form of a software function module and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods of each embodiment of the present invention. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc. Various media that can store program codes.

[0129] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An integrated circuit interrupt verification method, characterized in that: The method comprises: Obtaining interrupt source information of the integrated circuit to be verified; the interrupt source information includes configuration information corresponding to each interrupt source; Parsing the configuration information corresponding to each of the interrupt sources to generate an interface file and a test case; the interface file includes the interface information corresponding to each of the interrupt sources; Performing interrupt trigger verification on the integrated circuit to be verified according to the interface information in the interface file to verify whether the integrated circuit to be verified correctly generates each of the interrupt sources; The interrupt function of each interrupt source of the integrated circuit to be verified is verified according to the interface information in the interface file and the test case.

2. The method according to claim 1, characterized in that The performing interrupt trigger verification on the integrated circuit to be verified according to the interface information in the interface file includes: A target incentive message is randomly selected from a plurality of preset incentive messages; the target incentive message is an incentive message that triggers a target interrupt source; Sending the target stimulus message to the integrated circuit to be verified according to the interface information corresponding to the target interrupt source, and receiving the actual interrupt source generated by the integrated circuit to be verified according to the target stimulus message; Acquire an expected interrupt source generated by a simulation model of the integrated circuit to be verified according to the target stimulus message; The expected interrupt source is compared with the actual interrupt source to determine whether the integrated circuit to be verified correctly responds to the target interrupt source.

3. The method according to claim 1, characterized in that: The test case includes a test list and a test process, and the interrupt function verification of each interrupt source of the integrated circuit to be verified according to the interface information in the interface file and the test case includes: Testing the current test interrupt source according to the test flow corresponding to the current test interrupt source to obtain a test result of the current test interrupt source; the test result indicates whether the interrupt function of the current test interrupt source is normal; If the test result of the currently tested interrupt source is passed, the next interrupt source is tested according to the test list.

4. The method according to claim 3, characterized in that: The step of testing the integrated circuit to be verified according to the test flow corresponding to the current test interrupt source to obtain the test result of the current test interrupt source includes: Configure the interrupt mask function of the current test interrupt source to be turned off and the interrupt enable function to be turned on, and trigger the current test interrupt source according to the interface information corresponding to the current test interrupt source; Determine whether the interrupt mask function of the current test interrupt source is normal according to whether the integrated circuit to be verified currently generates an interrupt signal corresponding to the current test interrupt source, the original interrupt state, and the interrupt mask state; If the interrupt mask function of the current test interrupt source is normal, clear the current test interrupt source; After clearing the current test interrupt source, judging whether the interrupt clearing function of the current test interrupt source is normal according to whether the interrupt signal, the interrupt original state and the interrupt mask state are cleared; If the interrupt clearing function of the current test interrupt source is normal, configure the interrupt enabling function of the current test interrupt source to be turned off, and trigger the current test interrupt source according to the interface information corresponding to the current test interrupt source; According to whether the integrated circuit to be verified currently generates the interrupt signal, the original state of the interrupt, and the interrupt mask state, determining whether the interrupt enable function of the current test interrupt source is normal; If the enabling function of the interrupt enabling function of the currently tested interrupt source is normal, the test result of the currently tested interrupt source is passed; If the interrupt enable function, the interrupt clear function or the interrupt enable function of the interrupt source currently under test is abnormal, the test result of the interrupt source currently under test is failure.

5. The method according to claim 4, characterized in that The step of judging whether the interrupt mask function of the current test interrupt source is normal according to whether the integrated circuit to be verified currently generates an interrupt signal corresponding to the current test interrupt source, an interrupt original state, and an interrupt mask state, comprises: If the integrated circuit to be verified currently generates the interrupt signal, or does not generate the interrupt original state, or generates the interrupt mask state, then the interrupt mask function of the current test interrupt source is abnormal; If the integrated circuit to be verified does not currently generate the interrupt signal, generates the interrupt original state, and does not generate the interrupt mask state, then configure the interrupt mask function of the current test interrupt source to be turned on; After the interrupt mask function of the current test interrupt source is turned on, if the integrated circuit to be verified does not currently generate the interrupt signal, or does not generate the interrupt original state, or generates the interrupt mask state, then the interrupt mask function of the current test interrupt source is abnormal; If the integrated circuit to be verified currently generates the interrupt signal, generates the interrupt original state and does not generate the interrupt mask state, then the interrupt mask function of the current test interrupt source is normal.

6. The method according to claim 4, characterized in that After clearing the current test interrupt source, judging whether the interrupt clearing function of the current test interrupt source is normal according to whether the interrupt signal, the interrupt original state, and the interrupt mask state are cleared, includes: After clearing the current test interrupt source, if at least one of the interrupt signal, the interrupt original state, and the interrupt mask state is not cleared, the interrupt clearing function of the current test interrupt source is abnormal; If the interrupt signal, the interrupt original state, and the interrupt mask state are all cleared, the interrupt clearing function of the current test interrupt source is normal.

7. The method according to claim 4, characterized in that The step of judging whether the interrupt enable function of the current test interrupt source is normal according to whether the to-be-verified integrated circuit currently generates the interrupt signal, the interrupt original state, and the interrupt mask state includes: If the integrated circuit to be verified currently generates the interrupt signal, or generates the interrupt original state, or generates the interrupt mask state, then the interrupt enable function of the current test interrupt source is abnormal; If the integrated circuit to be verified currently does not generate the interrupt signal, does not generate the interrupt original state, and does not generate the interrupt mask state, then the interrupt enable function of the current test interrupt source is normal.

8. An interrupt verification device, characterized in that: The device comprises: An interrupt source information obtaining module, used to obtain the interrupt source information of the integrated circuit to be verified; the interrupt source information includes configuration information corresponding to each interrupt source; A configuration information parsing module, used to parse the configuration information corresponding to each of the interrupt sources, and generate an interface file and a test case; the interface file includes the interface information corresponding to each of the interrupt sources; An interrupt trigger verification module, used to perform interrupt trigger verification on the integrated circuit to be verified according to the interface information in the interface file, so as to verify whether the integrated circuit to be verified correctly generates each of the interrupt sources; The interrupt function verification module is used to verify the interrupt function of each interrupt source of the integrated circuit to be verified according to the interface information in the interface file and the test case.

9. An electronic device, characterized in that: It comprises a processor and a memory, wherein the memory stores a computer program executable by the processor, and the computer program executable by the processor is used to implement the integrated circuit interrupt verification method described in any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the integrated circuit interrupt verification method according to any one of claims 1 to 7 is implemented.

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