Gate drive circuit and display panel

Abstract

The invention discloses a gate driving circuit and a display panel, and the gate driving circuit comprises a plurality of cascaded gate driving units, and each gate driving unit at least comprises a cascaded driving unit which is connected with the gate driving unit of the previous stage; the first output unit is connected with the cascade driving unit and is used for outputting a first pulse signal; wherein the first pulse signal is a normal-state high-potential low-potential pulse signal; the second output unit is connected with the cascade driving unit and is used for outputting a second pulse signal; wherein the second pulse signal is a normal low-potential high-potential pulse signal. Through the circuit, output of different scanning signals is realized.

Description

Technical Field

[0001] The present invention relates to the field of display panels, and in particular to a gate driving circuit and a display panel. Background Art

[0002] With the development of display technology, OLED (Organic Light Emitting Display) has begun to move towards the small-size mainstream display market. Small-size OLED display products usually use GOA (gate on array) circuits to generate and process the scanning signals required by pixel driving circuits.

[0003] In order to achieve the low refresh function, it is necessary to extend the holding time of the gate voltage of the driving transistor in principle. The current mainstream solution is to introduce a new material with lower Ioff (leakage current) characteristics, indium gallium zinc oxide (IGZO) to make transistors, or to use phosphorus channel doping process to make different types of transistors.

[0004] To further reduce leakage, MOS (transistor) with IGZO as the substrate is injected with P to form NMOS (N-type transistor) with lower carrier mobility rate. NMOS needs to be driven by positive pulses, which is opposite to other PMOS (P-type transistors). Therefore, in the design of GOA circuit, in addition to the switching pulse (EM) and low-level pulse (Pscan), an additional GOA circuit for generating high-level pulses (Nscan) needs to be designed. However, the additional design of a GOA circuit for generating high-level pulses will occupy a large amount of border area. Summary of the invention

[0005] The main technical problem solved by the present application is to provide a gate drive circuit and a display panel to achieve the output of different scanning signals.

[0006] To solve the above problems, the present application provides a gate drive circuit in the first aspect, wherein the gate drive circuit includes: a plurality of cascaded gate drive units, each of the gate drive units includes at least: a cascade drive unit, connected to the gate drive unit of the previous level; a first output unit, connected to the cascade drive unit, for outputting a first pulse signal; wherein the first pulse signal is a low-potential pulse signal with a normal high potential; and a second output unit, connected to the cascade drive unit, for outputting a second pulse signal; wherein the second pulse signal is a high-potential pulse signal with a normal low potential.

[0007] Wherein, the cascade driving unit is connected to the first output unit of the gate driving unit of the previous stage.

[0008] Among them, the first output unit includes a first control unit and a second control unit; the input end of the first control unit is connected to the low-potential power line, the input end of the second control unit is connected to the high-potential power line, and the control ends of the first control unit and the second control unit are connected to the cascade drive unit; the cascade drive unit controls the first control unit and the second control unit to be staggered to control the first output unit to output the first pulse signal; the second output unit includes a third control unit and a fourth control unit; the input end of the third control unit is connected to the low-potential power line, the input end of the fourth control unit is connected to the high-potential power line, and the control ends of the third control unit and the fourth control unit are connected to the cascade drive unit, and the cascade drive unit controls the third control unit and the fourth control unit to be staggered to control the second output unit to output the second pulse signal.

[0009] Among them, the second control unit includes a first sub-control unit and a second sub-control unit, the input ends of the first sub-control unit and the second sub-control unit are both connected to the high-potential power line, and the control ends are both connected to the cascade drive unit, which are used to control the first output unit to output the first pulse signal.

[0010] Wherein, the cascade drive unit includes: a first cascade unit, connected to the first output unit of the gate drive unit of the previous level; a first storage unit, the first electrode plate of the first storage unit and the first cascade unit are used to store high potential signals and low potential signals; a first storage output unit, connected to the first electrode plate of the first storage unit, used to control the on / off of the first control unit and the second control unit according to the potential signal stored in the first storage unit; a second storage unit, used to store high potential signals and low potential signals; a second storage output unit, connected to the first electrode plate of the second storage unit, used to control the on / off of the third control unit and the fourth control unit according to the potential signal stored in the second storage unit.

[0011] Wherein, the cascade drive unit includes: a first cascade unit, connected to the first output unit of the gate drive unit of the previous level; a first storage unit, the first electrode plate of the first storage unit and the first cascade unit are used to store high potential signals and low potential signals; a first storage output unit, connected to the first electrode plate of the first storage unit and the control end of the first control unit and the first sub-control unit, and is used to control the on / off of the first control unit and the first sub-control unit according to the potential signal stored on the first storage unit; a second storage unit, used to store high potential signals and low potential signals; a second storage output unit, connected to the first electrode plate of the second storage unit and the control end of the first sub-control unit, the second sub-control unit, the third control unit, and the fourth control unit, and is used to control the on / off of the first sub-control unit, the second sub-control unit, the third control unit, and the fourth control unit according to the potential signal stored on the second storage unit.

[0012] Wherein, the cascade driving unit also includes: a pull-down unit, connected to the first electrode plate of the second storage unit, used for storing a low potential signal in the second storage unit; a pull-up unit, connected to the first electrode plate of the second storage unit, used for storing a high potential signal in the second storage unit; wherein the pull-down unit and the pull-up unit do not work at the same time, and the pull-down unit and the pull-up unit include a group of transistors with opposite driving polarities.

[0013] Among them, the control ends of the first cascade unit and the first storage output unit are controlled by a group of drive signal lines with opposite pulse phases; and / or; the control ends of the second storage output unit and the first storage output unit are controlled by a group of drive signal lines with opposite pulse phases.

[0014] Wherein, the cascade drive unit also includes a charging control unit; the charging control unit is connected to the pull-up unit, the pull-down unit and the second electrode plate of the second storage unit, and is used to control the pull-up unit and the pull-down unit to store a high potential signal or a low potential signal in the first electrode plate of the second storage unit; and / or; the charging control unit and the control end of the second storage output unit are controlled by a group of drive signal lines with opposite pulse phases.

[0015] Among them, the cascade driving unit also includes: a first sub-pull-up unit, connected to the output end of the first storage output unit, used to pull up the low potential output by the first storage output unit; a second sub-pull-up unit, connected to the output end of the second storage output unit, used to pull up the low potential output by the second storage output unit.

[0016] The first sub-pull-up unit includes a first resistor and a high-potential signal line; the second sub-pull-up unit includes a second resistor and a high-potential signal line.

[0017] The fourth control unit further includes a third storage unit, a first plate of the third storage unit is connected to the cascade drive unit, and a second plate of the third storage unit is connected to the high potential power line for storing an initial voltage signal.

[0018] Wherein, the cascade drive unit also includes: a second cascade unit, connected to the first plate of the third storage unit and the first output unit of the gate drive unit of the previous level, used to charge the first plate of the third storage unit with an initial voltage signal; a third cascade unit, connected to the second plate of the third storage unit and the high-potential power line, used to charge the second plate of the third storage unit with an initial voltage signal; wherein, the control ends of the second cascade unit and the third cascade unit are connected to the first output unit of the gate drive unit of the previous level.

[0019] Among them, the fourth control unit also includes a first switch unit and a second switch unit; the first switch unit is connected to the first plate of the third storage unit and the high-potential power line, and is used to pull up the initial voltage signal stored in the third storage unit; the second switch unit is connected to the second plate of the third storage unit, and is used to control the output of the second pulse signal according to the voltage signal stored in the third storage unit.

[0020] To solve the above problem, the present application provides a display panel in a second aspect, wherein the display panel includes the gate driving circuit described in any embodiment of the first aspect.

[0021] The beneficial effect of the present application is that, by designing the cascade unit, while minimizing the use of input signals, a GOA circuit can output different first pulse signals and second pulse signals to different types of transistors (TFTs) in the pixel unit, thereby saving circuit expenses and reducing the border width. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 A schematic diagram of the structure of an embodiment of a gate driving circuit provided in the present application; Figure 2A timing signal diagram of an embodiment of a first pulse signal and a second pulse signal provided in the present application; Figure 3 A schematic structural diagram of a first specific embodiment of a gate driving unit provided in the present application; Figure 4 A schematic structural diagram of a second specific embodiment of a gate driving unit provided in the present application; Figure 5 A schematic structural diagram of a third specific embodiment of a gate driving unit provided in the present application; Figure 6 A schematic structural diagram of a fourth specific embodiment of a gate driving unit provided in the present application; Figure 7 A schematic structural diagram of a fifth specific embodiment of a gate driving unit is provided for the present application; Figure 8 A schematic diagram of the circuit structure of a sixth specific embodiment of a gate driving unit provided in the present application; Fig. 9 A driving timing diagram of a sixth specific embodiment of a gate driving unit provided in the present application; Fig.10 A circuit diagram of the first driving stage of a sixth specific embodiment of a gate driving unit provided in the present application; Fig.11 A circuit diagram of the second driving stage of a sixth specific embodiment of a gate driving unit provided in the present application; Fig.12 A circuit diagram of the third driving stage of the sixth specific embodiment of the gate driving unit provided in the present application; Fig.13 A circuit diagram of a fourth driving stage of a sixth specific embodiment of a gate driving unit provided in the present application; Fig.14 A circuit diagram of the fifth driving stage of the sixth specific embodiment of the gate driving unit provided in the present application; Fig.15 A schematic structural diagram of an embodiment of a display panel provided in the present application.

[0024] First output unit 10; second output unit 20; cascade drive unit 30; previous stage first pulse signal Pscan(n-1); first pulse signal Pscan(n); second pulse signal Nscan(n); A first control unit 11; a second control unit 12; a third control unit 21; a fourth control unit 22; a high potential power line VGH; a low potential power line VGL; a first sub-control unit 121; a second sub-control unit 122; First cascade unit 311; first storage unit C1; first storage output unit 312; second storage unit C2; second storage output unit 321; pull-down unit 322; pull-up unit 323; first sub-pull-up unit 31; second sub-pull-up unit 32; first resistor R1; second resistor R2; charging control unit 324; A first driving signal line XCK; a second driving signal line CK; a third storage unit C3; a second cascade unit 331; a third cascade unit 332; a first switch unit 221; a second switch unit 222; a first transistor T1; a second transistor T2; a third transistor T3; a fourth transistor T4; a low potential signal line VGL1; a fifth transistor T5; a high potential signal line VGH1; a sixth transistor T6; a seventh transistor T7; an eighth transistor T8; a ninth transistor T9; a tenth transistor T10; an eleventh transistor T11; a twelfth transistor T12; a thirteenth transistor T13; a fourteenth transistor T14; a fifteenth transistor T15; Display panel 100 ; display area 101 ; non-display area 102 . DETAILED DESCRIPTION

[0025] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0026] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms of "a", "said", and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless otherwise clearly indicated above, and "multiple" generally includes at least two, but does not exclude the inclusion of at least one.

[0027] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0028] It should be understood that the terms "include", "comprises" or any other variations used herein are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of more restrictions, the elements defined by the sentence "includes..." do not exclude the presence of other identical elements in the process, method, article or device that includes the elements.

[0029] It should be noted that if the embodiments of the present application involve directional indications (such as up, down, left, right, front, back...), such directional indications are only used to explain the relative position relationship, movement status, etc. between the components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0030] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The presence of the phrase at each location in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0031] It should be noted that the high potential power line VGH is also called the high potential signal line, which is used to transmit high potential signals; the low potential power line VGL is also called the low potential signal line, which is used to transmit low potential signals. The high potential signal is also called the high potential voltage or the high potential level, and the low potential signal is also called the low potential voltage or the low potential level. The input end of the transistor is also the source of the transistor, the output end of the transistor is also the drain of the transistor, and the control end of the transistor is also the gate of the transistor, wherein the source and drain of the transistor can be interchanged. Turning off, cutting off or disconnecting a transistor have the same meaning.

[0032] The present application provides a gate driving circuit, which includes: a plurality of cascaded gate driving units, for details, please refer to Figure 1 , Figure 1 This is a schematic diagram of the structure of an embodiment of the gate drive circuit provided by the present application. Figure 1 As shown, each of the gate driving units at least includes: a first output unit 10 , a second output unit 20 and a cascade driving unit 30 .

[0033] Among them, the cascade drive unit 30 is used to connect to the previous gate drive unit. Specifically, the cascade drive unit 30 of the Nth gate drive unit GOA(n) is connected to the output end of the first output unit 10 of the N-1th gate drive unit GOA(n-1), that is, connected to the previous first pulse signal Pscan(n-1). Among them, the low potential pulse of the previous first pulse signal Pscan(n-1) is used as a trigger signal and a pull-down signal to enable the Nth gate drive unit GOA(n) to start working. It should be noted that most of the transistors in this embodiment are P-type transistors that are turned on at a low potential. Therefore, the input end of the cascade drive unit 30 is connected to the previous first pulse signal Pscan(n-1). In other embodiments, the input end of the cascade drive unit 30 can also be connected to the second pulse signal Pscan(n-1) of the previous stage, that is, the cascade drive unit 30 of the Nth stage gate drive unit GOA(n) is connected to the first output unit 10 of the N-1th stage gate drive unit GOA(n-1). This is not limited here and can be designed specifically according to actual conditions.

[0034] The first output unit 10 is connected to the cascade drive unit 30, and is used to output the first pulse signal Pscan(n). The first pulse signal Pscan(n) is a low-potential pulse signal with a normal high potential. Specifically, the control end of the first output unit 10 is connected to the cascade drive unit 30, and the input end of the first output unit 10 is respectively connected to the high-potential power line VGH and the low-potential power line VGL, and is used to generate the first pulse signal Pscan(n).

[0035] The second output unit 20 is connected to the cascade drive unit 30, and is used to output the second pulse signal Nscan(n). The second pulse signal Nscan(n) is a high potential pulse signal with a normal low potential. Specifically, the control end of the second output unit 20 is connected to the cascade drive unit 30, and the input end of the second output unit 20 is respectively connected to the high potential power line VGH and the low potential power line VGL, and is used to generate the second pulse signal Nscan(n).

[0036] Please refer to the following for details Figure 2 , Figure 2 This is a timing signal diagram of an embodiment of the first pulse signal and the second pulse signal provided by the present application. Figure 2As shown, the first pulse signal Pscan(n) is a low-potential pulse signal with a normal high potential. The second pulse signal Nscan(n) is a high-potential pulse signal with a normal low potential. Among them, the low potential of the first pulse signal Pscan(n) comes from the low-potential power supply, and the high potential comes from the high-potential power supply, so a more stable and high-quality low-potential pulse signal can be provided. Among them, the low potential of the second pulse signal Nscan(n) comes from the low-potential power supply, and the high potential comes from the previous level first pulse signal Pscan(n-1) and the high-potential power supply.

[0037] In some embodiments, the pulse timing of the second pulse signal Nscan(n) is delayed than the pulse timing of the first pulse signal Pscan(n). In this specific embodiment, the pulse timing of the second pulse signal Nscan(n) is delayed by one timing sequence than the pulse timing of the first pulse signal Pscan(n). In other embodiments, multiple timing sequences may be delayed. In other embodiments, the pulse timing of the first pulse signal Pscan(n) may be delayed than the pulse timing of the second pulse signal Nscan(n), which may be specifically designed according to the model of the thin film transistor.

[0038] Among them, the first pulse signal Pscan(n) output by the Nth gate driving unit GOA(n) is delayed by one timing sequence than the first pulse signal Pscan(n-1) output by the N-1th gate driving unit GOA(n-1). Similarly, the second pulse signal Nscan(n) output by the Nth gate driving unit GOA(n) is delayed by one timing sequence than the second pulse signal Nscan(n-1) output by the N-1th gate driving unit GOA(n-1), thereby providing a gate scan signal to each row in the display panel in turn.

[0039] See further Figure 3 , Figure 3 This is a schematic diagram of the structure of the first specific embodiment of the gate driving unit provided in this application. Figure 3 As shown, the first output unit 10 includes a first control unit 11 and a second control unit 12. The input end of the first control unit 11 is connected to the low potential power line VGL, which is used to control the first output unit 10 to output a low potential signal, and the input end of the second control unit 12 is connected to the high potential power line VGH, which is used to control the first output unit 10 to output a high potential signal. Among them, the control ends of the first control unit 11 and the second control unit 12 are connected to the cascade driving unit 30, and the cascade driving unit 30 controls the first control unit 11 and the second control unit 12 to be staggered to control the first output unit 10 to output the first pulse signal Pscan(n). Among them, staggered conduction means that they are not turned on at the same time, and the second control unit 12 is turned on most of the time.

[0040] The second output unit 20 includes a third control unit 21 and a fourth control unit 22. The input end of the third control unit 21 is connected to the low potential power line VGL, and is used to control the second output unit 20 to output a low potential signal. The input end of the fourth control unit 22 is connected to the high potential power line VGH, and is used to control the second output unit 20 to output a high potential signal. Among them, the control ends of the third control unit 21 and the fourth control unit 22 are connected to the cascade drive unit 30, and the cascade drive unit 30 controls the third control unit 21 and the fourth control unit 22 to be staggered to control the second output unit 20 to output the second pulse signal Nscan(n). Among them, staggered conduction means that they are not turned on at the same time, and the third control unit 21 is turned on most of the time.

[0041] It should be noted that the cascade drive unit 30 is connected to the control ends of the first control unit 11, the second control unit 12, the third control unit 21 and the fourth control unit 22. Figure 3 As shown by the dotted line, it is used to control the on / off of the first control unit 11, the second control unit 12, the third control unit 21 and the fourth control unit 22. The first control unit 11, the second control unit 12, the third control unit 21 and the fourth control unit 22 each include one or more thin film transistors TFT. The thin film transistor TFT includes a P-type transistor and an N-type transistor, which is not limited here.

[0042] See further Figure 4 , Figure 4 This is a schematic diagram of the structure of the second specific embodiment of the gate driving unit provided in this application. Figure 4 As shown, the second control unit 12 also includes a first sub-control unit 121 and a second sub-control unit 122, the input ends of the first sub-control unit 121 and the second sub-control unit 122 are both connected to the high potential power line VGH, and the control ends are both connected to the cascade drive unit 30, which is used to control the first output unit 10 to output the first pulse signal Pscan(n). The first sub-control unit 121 and the second sub-control unit 122 are not turned on at the same time.

[0043] Specifically, each stage of the gate driving unit includes a first stage (sampling stage), a second stage (P output stage), a third stage (N output stage) and a fourth stage (holding stage).

[0044] In the first stage, the cascade driving unit 30 controls the first control unit 11 to be turned off, the first sub-control unit 121 in the second control unit 12 to be turned on, and the second sub-control unit 122 in the second control unit 12 to be turned off, so that the first output unit 10 outputs a high potential signal through the first sub-control unit 121. The cascade driving unit 30 controls the third control unit 21 to be turned on, and the fourth control unit 22 to be turned off, so that the second output unit 20 outputs a low potential signal through the third control unit 21.

[0045] In the second stage, the cascade driving unit 30 controls the first control unit 11 to be turned on and the second control unit 12 to be turned off, so that the first output unit 10 outputs a low potential signal through the first control unit 11. The cascade driving unit 30 controls the third control unit 21 to be turned on and the fourth control unit 22 to be turned off, so that the second output unit 20 outputs a low potential signal through the third control unit 21.

[0046] In the third stage, the cascade drive unit 30 controls the first control unit 11 to turn off, the second sub-control unit 122 in the second control unit 12 to turn on, and the first sub-control unit 121 in the second control unit 12 to turn off, so that the first output unit 10 outputs a high potential signal through the second sub-control unit 122. The cascade drive unit 30 controls the third control unit 21 to turn off, and the fourth control unit 22 to turn on, so that the second output unit 20 outputs a high potential signal through the fourth control unit 22.

[0047] In the fourth stage, the cascade driving unit 30 controls the first control unit 11 to turn off, the first sub-control unit 121 in the second control unit 12 to turn on, and the second sub-control unit 122 in the second control unit 12 to turn off, so that the first output unit 10 outputs a high potential signal through the first sub-control unit 121. The cascade driving unit 30 controls the third control unit 21 to turn on, and the fourth control unit 22 to turn off, so that the second output unit 20 outputs a low potential signal through the third control unit 21.

[0048] Please refer to the following for details Figure 5 , Figure 5 This is a schematic diagram of the structure of the third specific embodiment of the gate driving unit provided in this application. Figure 5 As shown, in some embodiments, the cascade driving unit 30 specifically includes: a first cascade unit 311 , a first storage unit C1 , a first storage output unit 312 , a second storage unit C2 , and a second storage output unit 321 .

[0049] In this specific embodiment, the input end of the first cascade unit 311 is connected to the first pulse signal Pscan(n-1) output by the previous gate driving unit, and the output end is connected to the first electrode plate of the first storage unit C1. Since the first pulse signal Pscan(n-1) of the previous stage is a pulse signal, including a high potential and a low potential, the first storage unit C1 can store a high potential signal and a low potential signal.

[0050] The first storage unit C1 is a first storage capacitor, and the first electrode plate of the first storage unit C1 is connected to the first cascade unit 311, and is used to store high potential signals and low potential signals. The second electrode plate of the first storage unit C1 is connected to a fixed signal line, preferably grounded. In other embodiments, other fixed signal lines, such as a high potential signal line or a low potential signal line, may also be connected, which is not limited here.

[0051] The first storage output unit 312 is connected to the first electrode plate of the first storage unit C1, and is used to control the on / off of the first control unit 11 and the first sub-control unit 121 according to the potential signal stored in the first storage unit C1. Specifically, the first storage output unit 312 is arranged between the first electrode plate of the first storage unit C1 and the control end of the first control unit 11 and the first sub-control unit 121, and is used to transmit the potential signal (high potential signal and low potential signal) stored in the first storage unit C1 to the control end of the first control unit 11 and the first sub-control unit 121, so as to control the on / off of the first control unit 11 and the first sub-control unit 121, and further control whether the first pulse signal Pscan(n) is high potential or low potential.

[0052] The second storage unit C2 is a second storage capacitor, and the first plate of the second storage unit C2 is also used to store high potential signals and low potential signals. In a specific embodiment, the first plate of the second storage unit C2 is respectively connected to the pull-down unit 322 and the pull-up unit 323, and the pull-down unit 322 and the pull-up unit 323 do not work at the same time, so as to charge the high potential signal and the low potential signal to the first plate of the second storage unit C2 at different stages. Preferably, the second plate of the second storage unit C2 is grounded. In other embodiments, it can also be connected to other fixed signal lines, such as a high potential signal line or a low potential signal line, which is not limited here.

[0053] The second storage output unit 321 is connected to the first electrode plate of the second storage unit C2, and is used to control the on / off of the first sub-control unit 121, the second sub-control unit 122, the third control unit 21, and the fourth control unit 22 according to the potential signal stored in the second storage unit C2. The second storage output unit 321 is set at the first electrode plate of the second storage unit C2 and the control end of the first sub-control unit 121, the second sub-control unit 122, the third control unit 21, and the fourth control unit 22, and is used to transmit the potential signal (high potential signal and low potential signal) stored in the second storage unit C2 to the control end of the first sub-control unit 121, the second sub-control unit 122, the third control unit 21, and the fourth control unit 22, so as to control the on / off of the first sub-control unit 121, the second sub-control unit 122, the third control unit 21, and the fourth control unit 22, and further control whether the first pulse signal Pscan(n) and the second pulse signal Nscan(n) output a high potential or a low potential. The first sub-control unit 121 , the second sub-control unit 122 , the third control unit 21 , and the fourth control unit 22 include N-type transistors and P-type transistors with opposite driving characteristics so that they are not turned on at the same time.

[0054] In a preferred embodiment, one end of the pull-down unit 322 is connected to the low potential power line VGL, and the other end is connected to the first plate of the second storage unit C2, for charging the low potential signal to the first plate of the second storage unit C2 in the second stage. One end of the pull-up unit 323 is connected to the high potential power line VGH, and the other end is connected to the first plate of the second storage unit C2, for charging the high potential signal to the first plate of the second storage unit C2 in the fourth stage. In other embodiments, the pull-down unit 322 includes the low potential power line VGL, and the pull-up unit 323 includes the high potential power line VGH.

[0055] In a preferred embodiment, the control ends of the pull-down unit 322 and the pull-up unit 323 are also connected to the output end of the first storage output unit 312, wherein the pull-down unit 322 and the pull-up unit 323 include a group of transistors with opposite driving polarities. That is, when the transistor in the pull-down unit 322 is turned on, the transistor in the pull-up unit 323 is turned off (off), so that a low potential signal is stored in the first plate of the second storage unit C2 through the pull-down unit 322; when the transistor in the pull-down unit 322 is turned off, the transistor in the pull-up unit 323 is turned on, so that a high potential signal is stored in the first plate of the second storage unit C2 through the pull-up unit 323. In other embodiments, the control ends of the pull-down unit 322 and the pull-up unit 323 can also be controlled by a group of driving signal lines with opposite polarities, which is not limited here.

[0056] In a preferred embodiment, the cascade driving unit 30 further includes a first sub-pull-up unit 31 and a second sub-pull-up unit 32. The first sub-pull-up unit 31 is connected to the output end of the first storage output unit 312, and is used to pull up the low potential output by the first storage output unit 312. The second sub-pull-up unit 32 is connected to the output end of the second storage output unit 321, and is used to pull up the low potential output by the second storage output unit 321.

[0057] In the third specific embodiment, the first sub-pull-up unit 31 is specifically connected to the control end of the first control unit 11 and the first sub-control unit 121, and is used to control the on / off of the first control unit 11 and the first sub-control unit 121 when the first storage output unit 312 is not working (that is, when it is turned off). The second sub-pull-up unit 32 is specifically connected to the control end of the first sub-control unit 121, the second sub-control unit 122, the third control unit 21, and the fourth control unit 22, and is used to control the on / off of the first sub-control unit 121, the second sub-control unit 122, the third control unit 21, and the fourth control unit 22 when the second storage output unit 321 is not working (that is, when it is turned off).

[0058] In a preferred embodiment, the first sub-pull-up unit 31 includes a first resistor R1 and a high potential signal line VGH1, and the second sub-pull-up unit 32 includes a second resistor R2 and a high potential signal line VGH1. The high potential signal line VGH1 may also be a high potential power supply line VGH. It should be noted that both the first resistor R1 and the second resistor R2 are large resistors, and their resistance values ​​are between 4.7-10K. Thus, when the first storage output unit 312 outputs a low potential signal to the control end of the first control unit 11 and the first sub-control unit 121, the control end of the first control unit 11 and the first sub-control unit 121 is less affected by the high potential signal transmitted on the high potential signal line VGH1, and the first control unit 11 and the first sub-control unit 121 are preferentially controlled by the discharge of the first storage unit C1. Similarly, the first sub-control unit 121, the second sub-control unit 122, the third control unit 21 and the fourth control unit 22 are preferentially controlled by the discharge of the second storage unit C2. The control time of each control unit by the low potential signal stored in the first storage unit C1 and the second storage unit C2 is affected by the discharge time of the first storage unit C1 and the second storage unit C2, and the discharge time is related to its own capacitance value and the resistance value of the first resistor R1 and the second resistor R2.

[0059] In the third specific embodiment, the driving stages of the gate driving unit include a first stage, a second stage, a third stage, and a fourth stage.

[0060] In the first stage, the first cascade unit 311 charges the first storage unit C1 with the low potential signal of the first pulse signal Pscan(n-1) of the previous stage. The second storage unit C2 stores a high potential signal through the pull-up unit 323 in the previous stage, or the second storage unit C2 stores a high potential signal through the pull-up unit 323 in this stage. In short, a high potential signal is stored on the first plate of the second storage unit C2. In the first stage, the high potential signal stored on the second storage unit C2 is transmitted to the control ends of the first sub-control unit 121, the second sub-control unit 122, the third control unit 21, and the fourth control unit 22 through the second storage output unit 321, and the third control unit 21 and the first sub-control unit 121 are controlled to be turned on, and the second sub-control unit 122 and the fourth control unit 22 are controlled to be turned off. In the first stage, a high potential signal line VGH1 is used to control the first control unit 11 to be turned off and the first sub-control unit 121 to be turned on, wherein the high potential signal line VGH1 can be a high potential power line or other signal lines, wherein the first control unit 11 includes a P-type transistor that is turned on at a low potential.

[0061] In the second stage, the low potential signal stored in the first storage unit C1 in the first stage is transmitted to the control end of the first control unit 11 and the first sub-control unit 121 through the first storage output unit 312 to control the first control unit 11 to be turned on and the first sub-control unit 121 to be turned off, so that the first pulse signal Pscan(n) output by the N-th level gate driving unit is a low potential signal. At the same time, the control ends of the third control unit 21, the second sub-control unit 122 and the fourth control unit 22 are also connected to a high potential signal line VGH1, which is used to control the third control unit 21 to remain turned on, the second sub-control unit 122 and the fourth control unit 22 to remain turned off, so that the output second pulse signal Nscan(n) remains a low potential signal. In the second stage, the low potential signal stored in the first storage unit C1 is also transmitted to the control end of the pull-down unit 322 through the first storage output unit 312 to control the pull-down unit 322 to be turned on, and at the same time, the second storage output unit 321 is turned off, so that the pull-down unit 322 charges the low potential signal to the first plate of the second storage unit C2.

[0062] In the third stage, the second storage unit C2 outputs the low potential signal stored in the second stage to the control terminals of the first sub-control unit 121, the second sub-control unit 122, the third control unit 21, and the fourth control unit 22 through the second storage output unit 321, controls the second sub-control unit 122 and the fourth control unit 22 to be turned on, and controls the first sub-control unit 121 and the third control unit 21 to be turned off. At the same time, the first control unit 11 controls its turn-off through a high potential signal line VGH1. Thus, the output first pulse signal Pscan(n) is a high potential signal, and the second pulse signal Nscan(n) is a high potential signal. In the third stage, the first cascade unit 311 is turned on, the first storage output unit 312 is turned off, and the first cascade unit 311 stores the high potential signal of the previous first pulse signal Pscan(n-1) to the first plate of the first storage unit C1.

[0063] In the fourth stage, the high potential signal stored in the first storage unit C1 in the third stage is transmitted to the first control unit 11 and the first sub-control unit 121 through the first storage output unit 312, the first control unit 11 is controlled to be turned off, the first sub-control unit 121 is controlled to be turned on, and the high potential power line VGH is output to the first pulse signal Pscan(n) through the first sub-control unit 121, so that the output first pulse signal Pscan(n) is a high potential signal. At the same time, the second sub-control unit 122, the third control unit 21 and the fourth control unit 22 are controlled by a high potential signal line, the third control unit 21 is controlled to be turned on, and the second sub-control unit 122 and the fourth control unit 22 are turned off, so that the output second pulse signal Nscan(n) is a low potential signal.

[0064] In the subsequent stage of the fourth stage, the first control unit 11 and the first sub-control unit 121 are controlled by the first storage output unit 312 or a high potential signal line VGH1, so that the first control unit 11 remains turned off and the first sub-control unit 121 remains turned on, so that the output first pulse signal Pscan(n) remains a high potential signal output. The first sub-control unit 121, the second sub-control unit 122, the third control unit 21, and the fourth control unit 22 are controlled by the second storage output unit 321 or a high potential signal line VGH1, so that the first sub-control unit 121 and the third control unit 21 remain turned on, and the second sub-control unit 122, the third control unit 21, and the fourth control unit 22 remain turned off, so that the output second pulse signal Nscan(n) remains a low potential signal output. In this embodiment, the first sub-control unit 121 includes two transistors, which are controlled by the first storage output unit 312 and the second storage output unit 321 respectively. When both transistors are turned on, the first sub-control unit 121 is turned on, that is, when both the first storage output unit 312 and the second storage output unit 321 output high-potential signals, the first sub-control unit 121 is turned on. Among them, the first control unit 11 includes a P-type transistor; the first sub-control unit 121 includes an N-type transistor; the first sub-control unit 121 and the third control unit 21 include N-type transistors; the second sub-control unit 122, the third control unit 21, and the fourth control unit 22 include P-type transistors.

[0065] See further Figure 6 , Figure 6 This is a schematic diagram of the structure of the fourth specific embodiment of the gate driving unit provided in this application. Figure 6 As shown, the cascade drive unit 30 includes: a first cascade unit 311, a first storage unit C1, a first storage output unit 312, a second storage unit C2, and a second storage output unit 321. This specific embodiment is a further embodiment of the first specific embodiment. The third specific embodiment is a further embodiment of the second specific embodiment.

[0066] In this specific embodiment, the input end of the first cascade unit 311 is connected to the first pulse signal Pscan(n-1) output by the previous gate driving unit, and the output end is connected to the first electrode plate of the first storage unit C1.

[0067] The first storage unit C1 is a first storage capacitor. The first electrode of the first storage unit C1 is connected to the first cascade unit 311 and is used to store the high potential signal and the low potential signal transmitted by the previous stage first pulse signal Pscan(n-1).

[0068] One end of the first storage output unit 312 is connected to the first electrode of the first storage unit C1, and the other end is connected to the first control unit 11 and the second control unit 12, and is used to control the on / off of the first control unit 11 and the second control unit 12 according to the potential signal stored in the first storage unit C1.

[0069] The second storage unit C2 is a second storage capacitor, and the first plate of the second storage unit C2 is also used to store high potential signals and low potential signals. The first plate of the second storage unit C2 is respectively connected to the pull-down unit 322 and the pull-up unit 323, and is used to store high potential signals and low potential signals at different stages.

[0070] One end of the second storage output unit 321 is connected to the first electrode of the second storage unit C2, and the other end is connected to the third control unit 21 and the fourth control unit 22, and is used to control the on / off of the third control unit 21 and the fourth control unit 22 according to the potential signal stored on the second storage unit C2.

[0071] In this embodiment, the driving stages of the gate driving unit include a first stage, a second stage, a third stage, and a fourth stage.

[0072] In the first stage, the first cascade unit 311 charges the first storage unit C1 with the low potential signal of the first pulse signal Pscan(n-1) of the previous stage. It should be noted that the low potential signal of the first pulse signal Pscan(n-1) of the previous stage is also a trigger signal / drive signal, which is used to control the Nth stage gate drive unit to start working. The second storage unit C2 stores a high potential signal. The second storage unit C2 is transmitted to the control end of the third control unit 21 and the fourth control unit 22 through the second storage output unit 321, and the third control unit 21 is controlled to be turned on and the fourth control unit 22 is turned off, so that the output second pulse signal Nscan(n) is a low potential signal. In this stage, the control ends of the first control unit 11 and the second control unit 12 are also connected to a high potential signal line VGH1, and the first control unit 11 is controlled to be turned off and the second control unit 12 is turned on by a high potential signal line VGH1, so that the output first pulse signal Pscan(n) is a high potential signal.

[0073] In the second stage, the low potential signal stored in the first storage unit C1 is transmitted to the control end of the first control unit 11 and the second control unit 12 through the first storage output unit 312 to control the first control unit 11 to turn on and the second control unit 12 to turn off, so that the output first pulse signal Pscan(n) is a low potential signal. At the same time, the control end of the third control unit 21 and the fourth control unit 22 is also connected to a high potential signal line VGH1, which is used to control the third control unit 21 to turn on and the fourth control unit 22 to turn off, so that the output second pulse signal Nscan(n) is a low potential signal. In this stage, the pull-down unit 322 is turned on and starts to work, and the low potential signal is charged to the first electrode plate of the second storage unit C2 through the pull-down unit 322.

[0074] In the third stage, the second storage unit C2 outputs the low potential signal stored in the second stage to the control ends of the third control unit 21 and the fourth control unit 22 through the second storage output unit 321, thereby controlling the third control unit 21 to be turned off and the fourth control unit 22 to be turned on, so that the output second pulse signal Nscan(n) is a high potential signal. At the same time, the control ends of the first control unit 11 and the second control unit 12 are controlled by a high potential signal line VGH1, the first control unit 11 is turned off, and the second control unit 12 is turned on, so that the output first pulse signal Pscan(n) is a high potential signal. In the third stage, the first cascade unit 311 is turned on, the first storage output unit 312 is turned off, and the first cascade unit 311 also stores the high potential signal of the previous level first pulse signal Pscan(n-1) to the first plate of the first storage unit C1. After the third stage, the first plate of the first storage unit C1 continues to store the high potential signal.

[0075] In the fourth stage, the high potential signal stored in the first storage unit C1 in the third stage is transmitted to the first control unit 11 and the second control unit 12 through the first storage output unit 312, and the first control unit 11 is controlled to be turned off, and the second control unit 12 is controlled to be turned on, so that the output first pulse signal Pscan(n) is a high potential signal. At the same time, the third control unit 21 and the fourth control unit 22 are controlled by a high potential signal line, and the third control unit 21 is controlled to be turned on, and the fourth control unit 22 is turned off, so that the output second pulse signal Nscan(n) is a low potential signal.

[0076] In the subsequent stage of the fourth stage, the first control unit 11 and the second control unit 12 are controlled by the first storage output unit 312 (that is, the high potential signal stored in the first storage unit C1 in the third stage) or a high potential signal line VGH1, so that the first control unit 11 remains turned off and the second control unit 12 remains turned on, so that the output first pulse signal Pscan(n) remains a high potential signal output. The third control unit 21 and the fourth control unit 22 are controlled by the second storage output unit 321 (that is, the high potential signal stored in the second storage unit C2 in the fourth stage) or a high potential signal line VGH1, so that the third control unit 21 remains turned on and the fourth control unit 22 remains turned off, so that the output second pulse signal Nscan(n) remains a low potential signal output.

[0077] In this specific embodiment, the cascade driving unit 30 also includes a first sub-pull-up unit 31 and a second sub-pull-up unit 32. The first sub-pull-up unit 31 is connected to the control end of the first control unit 11 and the second control unit 12, and is used to control the on / off of the first control unit 11 and the second control unit 12 when the first storage output unit 312 is not working. Specifically, in the first stage, the first control unit 11 is controlled to be turned off and the second control unit 12 is turned on. In the second stage, the low potential signal output by the first storage output unit 312 is pulled up, so as to control the control time of the first storage output unit 312 on the first control unit 11 and the second control unit 12. In the third stage, the first control unit 11 is controlled to be turned off and the second control unit 12 is turned on. The second sub-pull-up unit 32 is connected to the control end of the third control unit 21 and the fourth control unit 22, and is used to control the on / off of the third control unit 21 and the fourth control unit 22 when the second storage output unit 321 is not working. Specifically, the second sub-pull-up unit 32 controls the third control unit 21 to be turned on and the fourth control unit 22 to be turned off in the second stage. In the third stage, the low potential signal output by the second storage output unit 321 is slowly pulled up, thereby controlling the control time of the second storage output unit 321 on the third control unit 21 and the fourth control unit 22 .

[0078] In the above embodiment, the first sub-pull-up unit 31 and the second sub-pull-up unit 32 include a resistor and a high potential signal line VGH1. Specifically, a first resistor R1 is provided between the high potential signal line VGH1 and the control end of the first control unit 11 and the second control unit 12. A second resistor R2 is provided between the high potential signal line VGH1 and the control end of the third control unit 21 and the fourth control unit 22. Among them, the first resistor R1 and the second resistor R2 are both large resistors, and their resistance values ​​are between 4.7-10K. When the first storage output unit 312 outputs a low potential signal to the control end of the first control unit 11 and the second control unit 12, the control end of the first control unit 11 and the second control unit 12 is less affected by the high potential signal transmitted on the high potential signal line VGH1, and the first control unit 11 and the second control unit 12 are preferentially controlled by the discharge of the first storage unit C1. Similarly, the third control unit 21 and the fourth control unit 22 are preferentially controlled by the discharge of the second storage unit C2. In other embodiments, the first sub-pull-up unit 31 and the second sub-pull-up unit 32 may also be composed of other circuit devices, such as normally open transistors, etc., which are not limited here.

[0079] It should be noted that the output stage of the first pulse signal Pscan(n) and the second pulse signal Nscan(n) depends on the discharge time of the first storage unit C1 and the second storage unit C2. The high potential signal line VGH1 has a neutralizing effect on the low potential signal stored in the first storage unit C1 and the second storage unit C2 during discharge, and the neutralization time is related to its own capacitance value and the resistance values ​​of the first resistor R1 and the second resistor R2.

[0080] In some preferred embodiments, the control ends of the first cascade unit 311 and the first storage output unit 312 are controlled by a group of drive signal lines with opposite pulse phases. Specifically, a first drive signal line XCK and a second drive signal line CK are provided, and pulse voltages with the same frequency are provided on the first drive signal line XCK and the second drive signal line CK, and their pulse phases are opposite. When the first drive signal line XCK provides a high potential signal, the second drive signal CK provides a low potential signal; when the first drive signal line XCK provides a low potential signal, the second drive signal CK provides a high potential signal. In other embodiments, the control ends of the first cascade unit 311 and the first storage output unit 312 are controlled by the same drive signal line, and the first cascade unit 311 and the first storage output unit 312 include N-type transistors and P-type transistors with different conduction conditions, which are not limited here.

[0081] In some preferred embodiments, the control terminals of the second storage output unit 321 and the first storage output unit 312 are controlled by a set of drive signal lines with the same pulse frequency and opposite pulse phases. That is, the second storage output unit 321 and the first storage output unit 312 are not turned on at the same time. They can be the first drive signal line XCK and the second drive signal line CK.

[0082] In some preferred embodiments, the control terminals of the pull-down unit 322 and the pull-up unit 323 are controlled by the same control signal line, and the pull-down unit 322 and the pull-up unit 323 include an N-type transistor and a P-type transistor with opposite driving characteristics. Preferably, the control terminals of the pull-down unit 322 and the pull-up unit 323 are connected to the output terminal of the first storage output unit 312, and are used to control the pull-down unit 322 to be turned on or the pull-up unit 323 to be turned on according to the high potential signal and the low potential signal stored in the first storage unit C1.

[0083] Furthermore, the cascade drive unit 30 further includes a charging control unit 324, which is disposed between the output ends of the pull-up unit 323 and the pull-down unit 322 and the first electrode plate of the second storage unit C2, and connects the output ends of the pull-up unit 323 and the pull-down unit 322 with the first electrode plate of the second storage unit C2, and is used to control the pull-up unit 323 and the pull-down unit 322 to store a high potential signal or a low potential signal in the first electrode plate of the second storage unit C2. Specifically, the charging control unit 324 is turned on in the second stage and the fourth stage, so that the pull-down unit 322 can charge the low potential signal to the first electrode plate of the second storage unit C2 in the second stage, and the pull-up unit 323 can charge the high potential signal to the first electrode plate of the second storage unit C2 in the fourth stage.

[0084] It should be noted that, in other embodiments, the pull-up unit 323 and the pull-down unit 322 may be controlled by other control lines to charge the second storage unit C2 in the second stage and the fourth stage, and this embodiment is not limiting.

[0085] Preferably, the charging control unit 324 and the control end of the second storage output unit 321 are controlled by a set of drive signal lines with opposite pulse phases. Refer to the first drive signal line XCK and the second drive signal line CK. The charging control unit 324 and the second storage output unit 321 are not turned on at the same time. The charging control unit 324 is turned on in the second stage and the fourth stage to charge the second storage unit C2. The second storage output unit 321 is turned on in the first stage and the third stage to control the second storage unit C2 to discharge.

[0086] For further information, see Figure 7 , Figure 7 The present application provides a schematic structural diagram of a fifth specific embodiment of a gate driving unit. Figure 7As shown, the fourth control unit 22 also includes a third storage unit C3, the first plate of the third storage unit C3 is connected to the cascade driving unit 30, and the second plate of the third storage unit C3 is connected to the high potential power line VGH, for storing the initial voltage signal. By changing the voltage on the first plate of the third storage unit C3, the output of the voltage on the second plate of the third storage unit C3 is controlled.

[0087] Furthermore, the cascade driving unit 30 further includes a second cascade unit 331 and a third cascade unit 332. The second cascade unit 331 is connected to the first plate of the third storage unit C3, and is used to charge the initial voltage signal to the first plate of the third storage unit C3. The third cascade unit 332 is connected to the second plate of the third storage unit C3, and is used to charge the initial voltage signal to the second plate of the third storage unit C3.

[0088] Specifically, the second cascade unit 331 is arranged between the first output unit 10 of the previous gate drive unit GOA(n-1) and the first plate of the third storage unit C3, and is used to control the charging of the initial voltage signal into the first plate of the third storage unit C3. Preferably, it is controlled to charge the low potential signal of the previous first pulse signal Pscan(n-1) into the first plate of the third storage unit C3 in the first stage. The third cascade unit 332 is arranged between the high potential power line VGH and the second plate of the third storage unit C3, and is used to control the charging of the initial voltage signal into the second plate of the third storage unit C3. Among them, the second cascade unit 331 and the third cascade unit 332 charge different voltage signals into the first plate and the second plate of the third storage unit C3 respectively, so that the initial voltage difference is stored in the third storage unit C3. It can be understood that the second cascade unit 331 and the third cascade unit 332 can be connected to other signal lines or other circuit designs, so that the first plate and the second plate of the third storage unit C3 can be charged with different voltage signals, which is not limited here.

[0089] Preferably, the control ends of the second cascade unit 331 and the third cascade unit 332 are connected to the first pulse signal Pscan(n-1) output by the first output unit 10 of the previous gate drive unit GOA(n-1). That is, the second cascade unit 331 and the third cascade unit 332 are controlled by the same low-potential pulse signal line with a normal high potential, and are turned on in the low-potential pulse stage and turned off in other stages, thereby controlling the initial voltage to be stored in the third storage unit C3. The second cascade unit 331 and the third cascade unit 332 control the writing of voltage to the third storage unit C3 in the first stage.

[0090] Further, the fourth control unit 22 also includes a first switch unit 221 and a second switch unit 222. The first switch unit 221 is connected between the first plate of the third storage unit C3 and the high potential power line VGH, and is used to pull up the initial voltage signal stored on the third storage unit C3. Specifically, in the high potential output stage, the voltage on the first plate of the third storage unit C3 is pulled up, and then the voltage on the second plate of the third storage unit C3 is pulled up, thereby realizing high potential output. Further, the second switch unit 222 is connected between the second plate of the third storage unit C3 and the output end of the second pulse signal Nscan(n), and is used to control the output of the second pulse signal Nscan(n) according to the voltage signal stored on the third storage unit C3, specifically controlling the high potential output of the second pulse signal Nscan(n). Among them, the control ends of the first switch unit 221 and the second switch unit 222 are controlled by the same control signal line, and preferably, the control ends of the first switch unit 221 and the second switch unit 222 are connected to the output end of the second storage output unit 321. In this embodiment, the first switch unit 221 and the second switch unit 222 are turned on in the third phase, so as to control the second pulse signal Nscan(n) to be output as a high potential signal.

[0091] For more details, please refer to Figure 8 , Figure 8 This is a schematic diagram of the circuit structure of the sixth specific embodiment of the gate driving unit provided in this application. Figure 8 shown.

[0092] The first cascade unit 311 includes a first transistor T1. The first storage output unit 312 includes a second transistor T2. The second storage output unit 321 includes a third transistor T3. The pull-down unit 322 includes a low potential signal line VGL1 and a fourth transistor T4. The pull-up unit 323 includes a high potential signal line VGH1 and a fifth transistor T5. The charging control unit 324 includes a sixth transistor T6. The second cascade unit 331 includes a seventh transistor T7. The third cascade unit 332 includes an eighth transistor T8.

[0093] The first control unit 11 includes a ninth transistor T9. The first sub-control unit 121 includes a tenth transistor T10 and an eleventh transistor T11. The second sub-control unit 122 includes a twelfth transistor T12. The third control unit 21 includes a thirteenth transistor T13. The fourth control unit 22 includes a fourteenth transistor T14, a fifteenth transistor T15 and a third storage unit (third capacitor) C3.

[0094] The first sub-pull-up unit 31 includes a first resistor R1 and a high potential signal line VGH1, and the second sub-pull-up unit 32 includes a second resistor R2 and a high potential signal line VGH1. The high potential signal line VGH1 may be a high potential power line VGH, and the low potential signal line VGL1 may be a low potential power line VGL.

[0095] In this specific embodiment, the tenth transistor T10 , the eleventh transistor T11 , and the thirteenth transistor T13 are N-type transistors, and the other transistors are P-type transistors.

[0096] This application also provides a driving timing diagram of a sixth specific embodiment of a gate driving unit. Fig. 9 , Fig. 9 The driving timing diagram of the sixth specific embodiment of the gate driving unit provided in this application. The driving stage includes the first stage, the second stage, the third stage and the fourth stage. For further details, please refer to Figures 10 to 14 . Fig.10 This is a circuit diagram of the first driving stage of the sixth specific embodiment of the gate driving unit provided in the present application. Fig.11 This is a circuit diagram of the second driving stage of the sixth specific embodiment of the gate driving unit provided in the present application. Fig.12 This is a circuit diagram of the third driving stage of the sixth specific embodiment of the gate driving unit provided in the present application. Fig.13 This is a circuit diagram of the fourth driving stage of the sixth specific embodiment of the gate driving unit provided in the present application. Fig.14 This is a circuit diagram of the fifth driving stage of the sixth specific embodiment of the gate driving unit provided in the present application.

[0097] The first stage is also called the sampling stage. In the first stage, the first pulse signal Pscan(n-1) of the previous stage is a low potential signal. At the same time, the first drive signal line XCK transmits a low potential signal, and the second drive signal line CK transmits a high potential signal. The first drive signal line XCK and the second drive signal line CK control the first transistor T1 to be turned on and the second transistor T2 to be turned off. The first pulse signal Pscan(n-1) of the previous stage stores a low potential signal on the first plate of the first storage unit C1. The first pulse signal Pscan(n-1) of the previous stage controls the seventh transistor T7 and the eighth transistor T8 to be turned on. The first pulse signal Pscan(n-1) of the previous stage charges a low potential signal to the first plate of the third storage unit C3 through the seventh transistor T7, and the high potential power line VGH charges a high potential signal to the second plate of the third storage unit C3 through the eighth transistor T8. Among them, the initial voltage difference stored in the third storage unit C3 is VGH-Vpscan(n-1). At this stage, the first drive signal line XCK controls the third transistor T3 to turn on. Since the second storage unit C2 stores a high potential signal in the previous stage, the high potential signal line VGH1 also provides a high potential signal to the output end of the second storage unit C2 through the second resistor R2 (the second sub-pull-up unit). Therefore, the second storage unit C2 discharges and outputs a high potential signal, controls the thirteenth transistor T13 and the eleventh transistor T11 to turn on, and controls the twelfth transistor T12, the fourteenth transistor T14, and the fifteenth transistor T15 to turn off. At this stage, the high potential signal line VGH1 also transmits a high potential signal to the ninth transistor T9 and the tenth transistor T10 through the first resistor R1, controls the ninth transistor T9 to turn off, and the tenth transistor T10 to turn on. Therefore, at this stage, the first pulse signal Pscan(n) outputs a high potential signal (VGH), and the second pulse signal Nscan(n) outputs a low potential signal (VGL). Please refer to Fig.10 , Fig.10 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0098] The second stage is the P output stage (low potential output stage). In the second stage, the first pulse signal Pscan (n-1) of the previous stage is a high potential signal. At the same time, the first drive signal line XCK transmits a high potential signal, and the second drive signal line CK transmits a low potential signal. The second drive signal line CK controls the second transistor T2 to be turned on, and the low potential signal stored in the first storage unit C1 in the first stage is discharged through the second transistor T2. In this stage, the pull-up effect of the first sub-pull-up unit on the output end of the second transistor T2 is less than the discharge of the first storage unit C1. The first storage unit C1 transmits a low potential signal to the control end of the ninth transistor T9 and the tenth transistor T10 through the second transistor T2, controls the ninth transistor T9 to be turned on, and the tenth transistor T10 to be turned off. The first storage unit C1 also transmits a low potential signal to the control end of the fourth transistor T4 and the fifth transistor T5 through the second transistor T2, controls the fourth transistor T4 to be turned on, and the fifth transistor T5 to be turned off. At the same time, the second drive signal line CK controls the sixth transistor T6 to be turned on, and the low potential signal line VGL1 transmits a low potential signal to the first electrode plate of the second storage unit C2 through the fourth transistor T4 and the sixth transistor T6, and stores it. At this stage, the first drive signal line XCK controls the third transistor T3 to be turned off, and the high potential signal line VGH1 continues to transmit a high potential signal to the control end of the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 through the second resistor R2, controls the thirteenth transistor T13 and the eleventh transistor T11 to be turned on, and controls the twelfth transistor T12, the fourteenth transistor T14, and the fifteenth transistor T15 to be turned off. At this stage, the low potential power line VGL outputs a low potential signal to the first output unit and the second output unit through the ninth transistor T9 and the thirteenth transistor T13, respectively, that is, the first pulse signal Pscan(n) outputs a low potential signal (VGL), and the second pulse signal Nscan(n) outputs a low potential signal (VGL). Please refer to Fig.11 , Fig.11 The solid line in the middle indicates signal transmission, the dotted line indicates no signal transmission, the red line indicates high potential signal transmission, and the blue line indicates low potential signal transmission. In this stage, the third storage unit C3 does not work, and maintains the initial voltage difference stored in the first stage.

[0099] The third stage is also called the N output stage (high potential output stage). In the third stage, the first pulse signal Pscan(n-1) of the previous stage is a high potential signal. At the same time, the first drive signal line XCK transmits a low potential signal, and the second drive signal line CK transmits a high potential signal. The first drive signal line XCK controls the first transistor T1 to turn on, and the first pulse signal Pscan(n-1) of the previous stage stores a high potential signal on the first electrode of the first storage unit C1, that is, the first storage unit C1 restores the storage of the high potential signal. The first drive signal line XCK controls the third transistor T3 to turn on, and the low potential signal stored in the second stage of the second storage unit C2 is transmitted to the control end of the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 through the third transistor T3. The thirteenth transistor T13 and the eleventh transistor T11 are turned off, and the twelfth transistor T12, the fourteenth transistor T14, and the fifteenth transistor T15 are turned on, so that the high potential power line VGH is turned on through the fourteenth transistor T3. The transistor T14 charges a high potential signal to the first plate of the third storage unit C3. According to Kirchhoff's voltage law (KVL), the voltage on the second plate of the third storage unit C3 is coupled to VGH-Vpscan(n-1)+VGH=2VGH-Vpscan(n-1), which is a high potential signal. The high potential signal on the second plate of the third storage unit C3 is transmitted to the output end of the second pulse signal Nscan(n) through the fifteenth transistor T15, so that the output second pulse signal Nscan(n) is a high potential signal. At the same time, the high potential unit line VGH transmits a high potential signal to the output end of the first pulse signal Pscan(n) through the twelfth transistor T12, so that the output first pulse signal Pscan(n) is a high potential signal. At this stage, the high potential signal line VGH1 also slowly pulls up the low potential signal output by the second storage unit C2 through the second resistor R2 until the second storage unit C2 is completely discharged, thereby controlling the conduction time of the twelfth transistor T12, the fourteenth transistor T14, and the fifteenth transistor T15. In this stage, the second driving signal line CK controls the second transistor T2 to be turned off, and the high potential signal line VGH1 provides a high potential signal to the ninth transistor T9 and the tenth transistor T10 through the first resistor R1, so that the ninth transistor T9 is turned off and the tenth transistor T10 is turned on. Fig.12 , Fig.12 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0100] The fourth stage is a holding stage, which includes a first holding stage h1 and a second holding stage h2, wherein the first holding stage h1 and the second holding stage h2 are performed alternately.

[0101] In the first holding stage h1, the first pulse signal Pscan(n-1) of the previous stage is a high potential signal, and at the same time, the first drive signal line XCK transmits a high potential signal, and the second drive signal line CK transmits a low potential signal. The high potential signal stored in the first storage unit C1 in the third stage is transmitted to the control end of the ninth transistor T9 and the tenth transistor T10 through the second transistor T2, and the ninth transistor T9 is controlled to be turned off and the tenth transistor T10 is turned on. At the same time, the high potential signal line VGH1 transmits a high potential signal to the first plate of the second storage unit C2 through the fifth transistor T5 and the sixth transistor T6, and stores it. At the same time, the high potential signal line VGH1 transmits a high potential signal to the control end of the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 through the second resistor R2, and the thirteenth transistor T13 and the eleventh transistor T11 are controlled to be turned on, and the twelfth transistor T12, the fourteenth transistor T14, and the fifteenth transistor T15 are controlled to be turned off. In this stage, the high potential power line VGH transmits a high potential signal to the output end (that is, the first output unit) of the first pulse signal Pscan(n) through the tenth transistor T10 and the eleventh transistor T11, so that the output first pulse signal Pscan(n) is a high potential signal. The low potential power line VGL transmits a low potential signal to the output end (that is, the first output unit) of the second pulse signal Nscan(n) through the thirteenth transistor T13, so that the output second pulse signal Nscan(n) is a low potential signal. For details, please refer to Fig.13 , Fig.13 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0102] In the second holding stage, the first pulse signal Pscan(n-1) of the previous stage is a high potential signal, and at the same time, the first drive signal line XCK transmits a low potential signal, and the second drive signal line CK transmits a high potential signal. The first pulse signal Pscan(n-1) of the previous stage stores a high potential signal on the first electrode plate of the first storage unit C1 through the first transistor T1. The first drive signal line XCK controls the third transistor T3 to be turned on, and the low potential signal stored in the second storage unit C2 in the first holding stage transmits a high potential signal to the control end of the eleventh transistor T11, the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 through the third transistor T3, and controls the thirteenth transistor T13 and the eleventh transistor T11 to be turned on, and the twelfth transistor T12, the fourteenth transistor T14, and the fifteenth transistor T15 to be turned off. At the same time, the high potential signal line VGH1 provides a high potential signal to the ninth transistor T9 and the tenth transistor T10 through the first resistor R1, so that the ninth transistor T9 is turned off and the tenth transistor T10 is turned on. In this stage, the high potential power line VGH transmits a high potential signal to the output end (that is, the first output unit) of the first pulse signal Pscan(n) through the tenth transistor T10 and the eleventh transistor T11, so that the output first pulse signal Pscan(n) is a high potential signal. The low potential power line VGL transmits a low potential signal to the output end (that is, the first output unit) of the second pulse signal Nscan(n) through the thirteenth transistor T13, so that the output second pulse signal Nscan(n) is a low potential signal. For details, please refer to Fig.14 , Fig.14 The solid line in the middle represents signal transmission, the dotted line represents no signal transmission, the red line represents high-potential signal transmission, and the blue line represents low-potential signal transmission.

[0103] The fourth stage includes a plurality of alternating first holding stages and second holding stages. In the fourth stage, no matter how the signals on the first drive signal line XCK and the second drive signal line CK change, the outputs of the first pulse signal Pscan(n) and the second pulse signal Nscan(n) remain unchanged. The first pulse signal Pscan(n) keeps outputting a high potential signal, and the second pulse signal Nscan(n) keeps outputting a low potential signal.

[0104] The present application also provides a display panel. Fig.15 , Fig.15 FIG. 1 is a schematic diagram of the structure of an embodiment of a display panel of the present application. Fig.15As shown, the display panel 100 includes a display area 101 and a non-display area 102. The non-display area 102 on one side or opposite sides of the display panel 100 is provided with a gate driving circuit as described in any of the above embodiments, and the gate driving circuit includes a plurality of cascaded gate driving units. The gate driving circuit sequentially transmits a first scanning signal and a second scanning signal to each row of pixel units in the display area 101. The first scanning signal is a first pulse signal Pscan(n) of a low potential pulse with a normal high potential, and the second scanning signal is a second pulse signal Nscan(n) of a high potential pulse with a normal low potential.

[0105] Furthermore, the driving circuit in each pixel unit of the display area 101 includes an N-type transistor and a P-type transistor. By sequentially outputting the first scanning signal and the second scanning signal to the driving unit of the pixel unit, the requirement of outputting different scanning signals to different types of transistors (TFTs) in the pixel unit is met.

[0106] The present application designs the above-mentioned gate drive circuit to minimize the use of input signals while enabling a GOA circuit to output different scanning signals to different types of transistors (TFTs) in the pixel unit, thereby saving circuit expenses and reducing the border width.

[0107] The above are merely embodiments of the present application and are not intended to limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made using the contents of the present application specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A gate drive circuit, characterized in that: include: A plurality of cascaded gate drive units, each of the gate drive units at least comprising: A cascade drive unit connected to the gate drive unit of the previous stage; A first output unit, connected to the cascade drive unit, for outputting a first pulse signal; wherein the first pulse signal is a low-potential pulse signal with a normal high potential; The second output unit is connected to the cascade driving unit and is used to output a second pulse signal; wherein the second pulse signal is a high-potential pulse signal with a normal low potential.

2. The gate driving circuit according to claim 1, characterized in that: The cascade driving unit is connected to the first output unit of the gate driving unit at the previous stage.

3. The gate driving circuit according to claim 1, characterized in that: The first output unit includes a first control unit and a second control unit; an input end of the first control unit is connected to a low-potential power line, an input end of the second control unit is connected to a high-potential power line, and control ends of the first control unit and the second control unit are connected to the cascade drive unit; the cascade drive unit controls the first control unit and the second control unit to be switched on alternately to control the first output unit to output the first pulse signal; The second output unit includes a third control unit and a fourth control unit; an input end of the third control unit is connected to the low-potential power line, an input end of the fourth control unit is connected to the high-potential power line, control ends of the third control unit and the fourth control unit are connected to the cascade drive unit, and the cascade drive unit controls the third control unit and the fourth control unit to be alternately turned on to control the second output unit to output the second pulse signal.

4. The gate driving circuit according to claim 3, characterized in that: The second control unit includes a first sub-control unit and a second sub-control unit, the input ends of the first sub-control unit and the second sub-control unit are both connected to the high-potential power line, and the control ends are both connected to the cascade drive unit for controlling the first output unit to output the first pulse signal.

5. The gate driving circuit according to claim 3, characterized in that: The cascade drive unit comprises: A first cascade unit connected to the first output unit of the gate driving unit of the previous stage; A first storage unit, wherein the first electrode plate of the first storage unit and the first cascade unit are used to store a high potential signal and a low potential signal; a first storage output unit connected to the first electrode plate of the first storage unit and used for controlling the on / off of the first control unit and the second control unit according to the potential signal stored in the first storage unit; A second storage unit, used for storing a high potential signal and a low potential signal; The second storage output unit is connected to the first electrode plate of the second storage unit, and is used to control the on / off of the third control unit and the fourth control unit according to the potential signal stored in the second storage unit.

6. The gate driving circuit according to claim 4, characterized in that: The cascade drive unit comprises: A first cascade unit connected to the first output unit of the gate driving unit of the previous stage; A first storage unit, wherein the first electrode plate of the first storage unit and the first cascade unit are used to store a high potential signal and a low potential signal; A first storage output unit, connected to the first electrode plate of the first storage unit and the control ends of the first control unit and the first sub-control unit, and used for controlling the on and off of the first control unit and the first sub-control unit according to the potential signal stored in the first storage unit; A second storage unit, used for storing a high potential signal and a low potential signal; A second storage output unit is connected to the first electrode plate of the second storage unit and the control ends of the first sub-control unit, the second sub-control unit, the third control unit and the fourth control unit, and is used to control the on / off of the first sub-control unit, the second sub-control unit, the third control unit and the fourth control unit according to the potential signal stored on the second storage unit.

7. The gate drive circuit according to claim 5 or 6, characterized in that: The cascade drive unit further includes: A pull-down unit connected to the first electrode plate of the second storage unit and used for storing a low potential signal in the second storage unit; A pull-up unit, connected to the first electrode plate of the second storage unit, for storing a high potential signal in the second storage unit; The pull-down unit and the pull-up unit do not work simultaneously, and the pull-down unit and the pull-up unit include a group of transistors with opposite driving polarities.

8. The gate driving circuit according to claim 7, characterized in that: The control ends of the first cascade unit and the first storage output unit are controlled by a group of drive signal lines with opposite pulse phases; and / or; The control ends of the second storage output unit and the first storage output unit are controlled by a group of driving signal lines with opposite pulse phases.

9. The gate driving circuit according to claim 7, characterized in that: The cascade drive unit also includes a charging control unit; The charging control unit is connected to the pull-up unit, the pull-down unit and the second electrode plate of the second storage unit, and is used to control the pull-up unit and the pull-down unit to store a high potential signal or a low potential signal in the first electrode plate of the second storage unit; and / or; the control end of the charging control unit and the second storage output unit is controlled by a group of drive signal lines with opposite pulse phases.

10. The gate driving circuit according to claim 5, characterized in that: The cascade drive unit further includes: A first sub-pull-up unit, connected to the output end of the first storage output unit, and used for pulling up the low potential output by the first storage output unit; The second sub-pull-up unit is connected to the output end of the second storage output unit, and is used for pulling up the low potential output by the second storage output unit.

11. The gate driving circuit according to claim 10, characterized in that: The first sub-pull-up unit includes a first resistor and a high-potential signal line; the second sub-pull-up unit includes a second resistor and a high-potential signal line.

12. The gate driving circuit according to claim 3, characterized in that: The fourth control unit further includes a third storage unit, a first plate of the third storage unit is connected to the cascade driving unit, and a second plate of the third storage unit is connected to the high potential power line, for storing an initial voltage signal.

13. The gate driving circuit according to claim 12, characterized in that: The cascade drive unit further includes: A second cascade unit, connected to the first electrode plate of the third storage unit and the first output unit of the gate driving unit of the previous stage, for charging an initial voltage signal to the first electrode plate of the third storage unit; A third cascade unit, connected to the second electrode plate of the third storage unit and the high potential power line, and used for charging the second electrode plate of the third storage unit with an initial voltage signal; Wherein, the control ends of the second cascade unit and the third cascade unit are connected to the first output unit of the gate driving unit of the previous stage.

14. The gate driving circuit according to claim 13, characterized in that: The fourth control unit further includes a first switch unit and a second switch unit; The first switch unit is connected to the first electrode plate of the third storage unit and the high potential power line, and is used to pull up the initial voltage signal stored in the third storage unit; The second switch unit is connected to the second electrode plate of the third storage unit, and is used for controlling the output of the second pulse signal according to the voltage signal stored in the third storage unit.

15. A display panel, characterized in that: The display panel comprises the gate driving circuit according to any one of claims 1 to 14.

Images