Semiconductor device and preparation method thereof
By simultaneously performing an ion implantation process on the polycrystalline semiconductor layer corresponding to the active region and the resistive region on the semiconductor substrate, the problem of additional photocaps and ion implantation processes required for the preparation of polycrystalline semiconductor resistors in the prior art is solved, and the effect of reducing preparation costs and improving process efficiency is achieved.
Patent Information
- Application Number
- CN202311378948.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-24
- Publication Date
- 2025-04-29
AI Technical Summary
In the prior art, the preparation of polycrystalline semiconductor resistors requires an additional photocopy and an ion implantation process, which increases the production cost and reduces the process efficiency.
By simultaneously performing an ion implantation process on the polycrystalline semiconductor layer corresponding to the active region and the resistive region on the semiconductor substrate, a polycrystalline semiconductor gate and resistive structure are formed, thereby reducing the number of ion implantation processes.
The additional ion implantation process required to form a polycrystalline semiconductor resistive structure in the resistive region is reduced, and the production cost is reduced and production efficiency is improved.
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Figure CN119905391A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a method for preparing a semiconductor integrated circuit, and in particular to a semiconductor device and a method for preparing the same. Background Art
[0002] As the critical dimension (CD) of semiconductor devices becomes smaller and smaller, the integration of semiconductor chips becomes higher and higher, and the number and types of devices that need to be formed per unit area are increasing, the requirements for semiconductor processes are also increasing. How to reasonably arrange the positions of various devices and use the common points of manufacturing of various devices to save semiconductor process steps and materials has become a hot topic of research.
[0003] Resistors are an important component of digital and analog CMOS integrated circuits, and their main functions are current limiting and voltage division. Resistors can be divided into active resistors and passive resistors. Active resistors usually use the resistance characteristics of transistors in a specific working area, while passive resistors are usually formed by doping, such as polysilicon resistors, diffusion region resistors, etc. Passive resistors are used in most integrated circuit designs because they are not affected by current and voltage and have stable performance.
[0004] In the design of semiconductor chip circuits, polysilicon resistors are used in large quantities. Polysilicon resistors are generally prepared by ion doping of polysilicon. Commonly used N+ doped polysilicon resistors and P+ doped polysilicon resistors are formed by the injection of N-type ions and P-type ions, and diffusion after annealing. The currently commonly used resistivity is about 1000ohm / sq-2000ohm / sq. When preparing polysilicon resistors with higher resistivity, the prior art usually requires the use of an additional mask and an additional ion implantation process to obtain a passive polysilicon resistor with a preset resistance value. However, this method requires an additional mask and an ion implantation process, which increases the preparation cost and reduces the process efficiency. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a semiconductor device and a method for preparing the same, so as to solve the problem that the preparation of polycrystalline semiconductor resistors in the prior art requires an additional mask and an ion implantation process, which increases the preparation cost and reduces the process efficiency.
[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a semiconductor device, the method comprising:
[0007] Providing a semiconductor substrate, wherein the semiconductor substrate has a resistance region and two active regions for forming an NMOS tube and a PMOS tube;
[0008] forming a polycrystalline semiconductor layer on the semiconductor substrate;
[0009] Simultaneously performing an ion implantation process on at least one of the active regions and the polycrystalline semiconductor layer corresponding to the resistance region;
[0010] The polycrystalline semiconductor layer is etched to form polycrystalline semiconductor gates in the two active regions and to form polycrystalline semiconductor resistors in the resistor region.
[0011] Optionally, the method further includes: forming sidewalls on both sides of the polycrystalline semiconductor gate and on both sides of the polycrystalline semiconductor resistor; and forming a source and a drain in the semiconductor substrate on both sides of the polycrystalline semiconductor gate.
[0012] Optionally, an insulating isolation structure is provided in the semiconductor substrate where the resistance region is located.
[0013] Optionally, after the ion implantation process is performed, the method further includes performing an annealing process on the polycrystalline semiconductor layer.
[0014] Optionally, the ions implanted in the ion implantation process are P-type ions or N-type ions.
[0015] Furthermore, the ion implantation dosage of the P-type ions is 1E14 to 1E15, including the endpoint value; the ion implantation dosage of the N-type ions is 1E14 to 1E15, including the endpoint value.
[0016] Optionally, the material of the polycrystalline semiconductor layer is one of polycrystalline silicon, polycrystalline gallium arsenide, polycrystalline germanium and polycrystalline germanium silicon.
[0017] Optionally, before forming the polycrystalline semiconductor layer on the semiconductor substrate, a step of forming a gate dielectric layer on the semiconductor substrate is also included; when etching the polycrystalline semiconductor layer, a step of etching the gate dielectric layer corresponding to the active area except for the area where the polycrystalline semiconductor gate is located is also included.
[0018] Optionally, when an ion implantation process is performed simultaneously on the polycrystalline semiconductor layer corresponding to the active region and the resistance region, the process steps include:
[0019] Coating a first photoresist layer on the polycrystalline semiconductor layer, and patterning the first photoresist layer to form a patterned first photoresist layer, wherein the patterned first photoresist layer exposes the polycrystalline semiconductor layer corresponding to the active area and the resistance area that need to be subjected to an ion implantation process;
[0020] Performing an ion implantation process on the polycrystalline semiconductor layer based on the patterned first photoresist layer;
[0021] removing the patterned first photoresist layer;
[0022] When the ion implantation process is performed simultaneously on the two polycrystalline semiconductor layers corresponding to the active region and the resistance region, the process steps include:
[0023] Coating a second photoresist layer on the polycrystalline semiconductor layer, and patterning the second photoresist layer to form a patterned second photoresist layer, wherein the patterned second photoresist layer exposes the polycrystalline semiconductor layer corresponding to one of the active regions and the resistance region;
[0024] Performing a first ion implantation process on the polycrystalline semiconductor layer based on the patterned second photoresist layer;
[0025] removing the patterned second photoresist layer;
[0026] Coating a third photoresist layer on the polycrystalline semiconductor layer, and patterning the third photoresist layer to form a patterned third photoresist layer, wherein the patterned third photoresist layer exposes the polycrystalline semiconductor layer corresponding to another active region and the resistance region;
[0027] Based on the patterned third photoresist layer, a second ion implantation process is performed on the polycrystalline semiconductor layer, the doping type of which is opposite to that of the first ion implantation process;
[0028] The patterned third photoresist layer is removed.
[0029] The present invention also provides a semiconductor device, which is prepared by using any one of the methods for preparing a semiconductor device as described above.
[0030] As described above, the semiconductor device and the preparation method thereof of the present invention simultaneously perform ion implantation processes on the corresponding polycrystalline semiconductor layers on the active region and the resistance region, and simultaneously obtain the polycrystalline semiconductor gate structure required for the active region and the polycrystalline semiconductor resistance structure required for the resistance region, thereby reducing the need for an additional ion implantation process to form the polycrystalline semiconductor resistance structure in the resistance region. For the ion implantation process, a photoresist is generally required to block the area where ion implantation is not required, so the preparation method of this embodiment can reduce a mask, a photolithography process, and an ion implantation process, effectively reducing the preparation cost and improving production efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Figures 1 to 12 It is a schematic diagram of the cross-sectional structure presented after each step in the method for preparing a semiconductor device of the present invention is completed.
[0032] Description of Reference Numerals
[0033] 10 Semiconductor substrate
[0034] 11 Well region
[0035] 110 First well region
[0036] 111 Second well region
[0037] 12 Insulation isolation structure
[0038] 13 Active area
[0039] 130 First active region
[0040] 131 Second active region
[0041] 14 Resistance Zone
[0042] 15. Gate dielectric layer
[0043] 16 Polycrystalline semiconductor layer
[0044] 160 first photoresist layer
[0045] 161 Patterned first photoresist layer
[0046] 162 second photoresist layer
[0047] 163 Patterned second photoresist layer
[0048] 164 third photoresist layer
[0049] 165 Patterned third photoresist layer
[0050] 17 Polycrystalline semiconductor gate
[0051] 18 Polycrystalline semiconductor resistor
[0052] 19 Sidewall
[0053] 20 Source
[0054] 21 Drain DETAILED DESCRIPTION
[0055] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0056] See also Figures 1 to 12It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0057] This embodiment provides a method for preparing a semiconductor device, which focuses on the process of preparing a polycrystalline semiconductor resistor and specifically includes the following steps:
[0058] S1, providing a semiconductor substrate, wherein the semiconductor substrate has a resistance region and two active regions for forming an NMOS tube and a PMOS tube;
[0059] S2, forming a polycrystalline semiconductor layer on the semiconductor substrate;
[0060] S3, simultaneously performing an ion implantation process on at least one of the active regions and the polycrystalline semiconductor layer corresponding to the resistance region;
[0061] S4, etching the polycrystalline semiconductor layer to form polycrystalline semiconductor gates in the two active regions and polycrystalline semiconductor resistors in the resistor region.
[0062] The two active areas described here are mainly aimed at the existing CMOS process, one of which is used to prepare NMOS tubes, and the other is used to prepare PMOS tubes; the purpose of the ion implantation process on the polycrystalline semiconductor layer is mainly to pre-dope the polycrystalline semiconductor gate in the CMOS transistor to reduce the polycrystalline depletion effect of the PMOS and / or NMOS tubes. It should be noted here that the purpose of pre-doping the polycrystalline semiconductor gate in the MOS tube is to improve the polycrystalline depletion, and its doping concentration can be freely adjusted within a certain range. Therefore, the ion doping concentration in the ion implantation process in the preparation method is mainly based on the doping concentration requirements of the polycrystalline semiconductor resistor as the main standard for doping, so as to ensure that the polycrystalline depletion effect of the polycrystalline semiconductor gate is improved while obtaining a polycrystalline semiconductor resistor with a precise resistance value.
[0063] The method for preparing the semiconductor device of the present embodiment simultaneously performs an ion implantation process on the corresponding polycrystalline semiconductor layers on the active region and the resistance region, and simultaneously obtains the polycrystalline semiconductor gate structure required for the active region and the polycrystalline semiconductor resistance structure required for the resistance region, thereby reducing the need for an additional ion implantation process to form the polycrystalline semiconductor resistance structure in the resistance region. For the ion implantation process, a photoresist is generally required to block the area where the ion implantation is not required, so the method for preparing the present embodiment can reduce a mask, a photolithography process, and an ion implantation process, effectively reducing the preparation cost and improving the production efficiency.
[0064] The preparation method of this embodiment is described in detail below with reference to the specific drawings.
[0065] like Figure 1 As shown, step S1 is first performed to provide a semiconductor substrate 10 , wherein the semiconductor substrate 10 has a resistor region 14 and two active regions 13 for forming an NMOS transistor and a PMOS transistor.
[0066] like Figure 1 As shown, the two active regions 13 can be Figure 1 The first active area 130 on the left and the second active area 131 on the right. The two active areas 13 are designed according to the actual device structure. The corresponding MOS device structure, such as CMOS structure, will be formed in the interior of the area or on the upper surface of the area. NMOS tube and PMOS tube will be formed in the first active area 130 and the second active area 131 respectively. The source and drain will be formed in the semiconductor substrate 10 in the corresponding area. The gate dielectric layer and the polycrystalline semiconductor gate, as well as the metal electrode lead-out structure of the back stage, will be formed on the semiconductor substrate 10 in the corresponding area. When the device structure formed in the active area 13 is a MOS tube, a deep well ion implanted well area 11 is generally formed in the semiconductor substrate 10 in the corresponding area. For example, a first well area 110 is formed in the semiconductor substrate 10 of the first active area 130, and a second well area 111 is formed in the semiconductor substrate 10 of the second active area 131. The doping type of the first well area 110 and the second well area 111 is determined by the type of the MOS tube actually formed. For example, a P well is formed for an NMOS tube, and an N well is formed for a PMOS tube.
[0067] like Figure 1 As shown, as an example, an insulating isolation structure 12 is provided in the semiconductor substrate 10 where the resistor region 14 is located. The insulating isolation structure 12 can be formed by etching a groove in the semiconductor substrate 10 and filling the groove with an insulating material. In addition, the insulating isolation structure 12 can also be provided between two adjacent active regions 13 to achieve electrical isolation between the two active regions 13, such as Figure 1The active region 130 on the left and the active region 131 on the right are electrically isolated by the insulating isolation structure 12 .
[0068] As an example, the semiconductor substrate 10 is any semiconductor base material known to those skilled in the art for carrying components of semiconductor integrated circuits, and may be a bare chip or a wafer processed by an epitaxial growth process, for example, the semiconductor substrate 10 is a silicon-on-insulator (SOI) substrate, a bulk silicon substrate, a germanium substrate, a germanium silicon substrate, an indium phosphide substrate, a sapphire substrate, a silicon carbide substrate, a gallium arsenide substrate, a germanium-on-insulator substrate, and the like.
[0069] like Figure 3 As shown, step S2 is then performed to form a polycrystalline semiconductor layer 16 on the semiconductor substrate 10 .
[0070] The polycrystalline semiconductor layer 16 is subsequently used to form a polycrystalline semiconductor resistor and a polycrystalline semiconductor gate structure corresponding to the active region. The material of the polycrystalline semiconductor layer 16 can be any suitable polycrystalline semiconductor material, such as polycrystalline silicon, polycrystalline gallium arsenide, polycrystalline germanium, polycrystalline germanium silicon, etc. At present, the material of the polycrystalline semiconductor layer 16 is preferably polycrystalline silicon material.
[0071] like Figure 2 As shown, before forming the polycrystalline semiconductor layer 16, a gate dielectric layer 15 will be formed on the surface of the semiconductor substrate 10. Generally, the gate dielectric layer of the semiconductor gate MOS tube is formed by a thermal oxidation process. Therefore, when an insulating isolation structure 12 is provided in the semiconductor substrate 10 where the resistor region 14 is located, the gate dielectric layer 15 will not be formed by thermal oxidation on the surface of the semiconductor substrate 10 in this region. In addition, when the semiconductor substrate 10 is a silicon substrate, the gate dielectric layer 15 is a silicon oxide gate dielectric layer. Any suitable deposition process, such as a CVD process, can be used to form the polycrystalline semiconductor layer 16. Preferably, after the polycrystalline semiconductor layer 16 is deposited and formed, a CMP process can be used to grind the surface to make its surface flat.
[0072] It should be noted that the thickness of the polycrystalline semiconductor layer 16 is set according to actual needs and is not excessively limited here.
[0073] Then, step S3 is performed to simultaneously perform an ion implantation process on at least one of the active region 13 and the polycrystalline semiconductor layer 16 corresponding to the resistance region 14 .
[0074] The ion implantation of the active area 13 is specifically selected according to different design requirements. For example, ion implantation can be performed on one of the active areas 13, or on both of the two active areas 13. When ion implantation is performed on one of the active areas 13, the polycrystalline semiconductor gate subsequently formed by the corresponding active area 13 is in a pre-doped form. Generally, NMOS tubes are more commonly used, but PMOS tubes can also pre-dope their polycrystalline semiconductor gates according to actual conditions; when ion implantation is performed on both of the two active areas 13, generally this situation corresponds to a CMOS structure, and the polycrystalline semiconductor gates of NMOS and PMOS subsequently formed in the two active areas are both in a pre-doped form.
[0075] like Figures 4 to 6 As shown, the specific process steps of simultaneously performing an ion implantation process on the polycrystalline semiconductor layer 16 corresponding to the active region 13 and the resistance region 14 include:
[0076] like Figure 4 As shown, a first photoresist layer 160 is first coated on the polycrystalline semiconductor layer 16. Figure 5 and Figure 6 As shown, the first photoresist layer 160 is patterned to form a patterned first photoresist layer 161, and the patterned first photoresist layer 161 exposes the polycrystalline semiconductor layer 16 corresponding to the active area 13 and the resistor area 14 that need to be subjected to an ion implantation process, such as Figure 5 And refer to Figure 1 , exposing the second active region 131 on the right and the corresponding polycrystalline semiconductor layer 16 on the resistance region 14, as shown in FIG. Figure 6 And refer to Figure 1 , exposing the first active region 130 on the left and the corresponding polycrystalline semiconductor layer 16 on the resistance region 14 .
[0077] like Figure 5 and Figure 6 As shown, an ion implantation process is then performed on the polycrystalline semiconductor layer 16 based on the patterned first photoresist layer 161. At this time, the ion implantation concentration of the ion implantation process determines the resistance value of the polycrystalline semiconductor resistor formed subsequently.
[0078] Finally, the patterned first photoresist layer 161 is removed.
[0079] like Figures 7 to 10 As shown in FIG. 1 , specific process steps for simultaneously performing an ion implantation process on the polycrystalline semiconductor layer 16 corresponding to the two active regions 13 and the resistance region 14 include:
[0080] like Figure 7As shown, a second photoresist layer 162 is first coated on the polycrystalline semiconductor layer 16. Figure 8 As shown, the second photoresist layer 162 is patterned to form a patterned second photoresist layer 163, and the patterned second photoresist layer 163 exposes the polycrystalline semiconductor layer 16 corresponding to the active area 13 and the resistor area 14, for example Figure 8 And refer to Figure 1 In the figure, the second active region 131 on the right and the corresponding polycrystalline semiconductor layer 16 on the resistance region 14 are exposed.
[0081] like Figure 8 As shown, a first ion implantation process is then performed on the polycrystalline semiconductor layer 16 based on the patterned second photoresist layer 163 .
[0082] Then, the patterned second photoresist layer 163 is removed.
[0083] like Fig. 9 As shown, a third photoresist layer 164 is then coated on the polycrystalline semiconductor layer 16. Fig.10 As shown, the third photoresist layer 164 is patterned to form a patterned third photoresist layer 165, and the patterned third photoresist layer 165 exposes the polycrystalline semiconductor layer 16 corresponding to the other active region 13 and the resistor region 14, for example Fig.10 And refer to Figure 1 In the figure, the first active region 130 on the left and the corresponding polycrystalline semiconductor layer 16 on the resistance region 14 are exposed.
[0084] like Fig.10 As shown, a second ion implantation process with a doping type opposite to that of the first ion implantation process is then performed on the polycrystalline semiconductor layer 16 based on the patterned third photoresist layer 165. At this time, the difference between the ion implantation concentration of the second ion implantation process and the ion implantation concentration of the first ion implantation process determines the resistance value of the polycrystalline semiconductor resistor formed subsequently.
[0085] Finally, the patterned third photoresist layer 165 is removed.
[0086] It should be noted that the thickness, material and other parameters of the first photoresist layer 160, the second photoresist layer 162 and the third photoresist layer 164 can be the same or different. In this embodiment, since the photoresist layers are all formed on the polycrystalline semiconductor layer 16 and are all used as barrier layers for the ion implantation process, their thickness, material and other parameters are preferably the same.
[0087] As an example, after the ion implantation process is performed, the polycrystalline semiconductor layer 16 is further subjected to an annealing process to activate the implanted ions. The annealing process adopts an existing conventional processing process, such as furnace annealing or rapid thermal processing equipment. The parameters of the annealing process select conventional annealing parameters, and the annealing atmosphere is generally performed in a nitrogen atmosphere.
[0088] As an example, the ions implanted in the ion implantation process are P-type ions or N-type ions. N-type doping can be formed by using VA group elements, such as phosphorus doping or arsenic doping, and P-type doping can be formed by using IIIA group elements, such as boron doping. However, it is not limited to this, and other N-type ions and P-type ions can also achieve the formation of corresponding doping types. The ion implantation dose of the P-type ions is 1E14~1E15, including the endpoint values; the ion implantation dose of the N-type ions is 1E14~1E15, including the endpoint values.
[0089] like Fig.11 As shown, step S4 is finally performed to etch the polycrystalline semiconductor layer 16 to form polycrystalline semiconductor gates 17 in the two active regions 13 and polycrystalline semiconductor resistors 18 in the resistor region 14 .
[0090] like Figure 2 and Fig.11 As shown, as an example, when a gate dielectric layer 15 is formed on the surface of the semiconductor substrate 10, etching the polycrystalline semiconductor layer 16 also includes the step of etching at least the gate dielectric layer 15 corresponding to the active area 13 except the area where the polycrystalline semiconductor gate 17 is located.
[0091] like Fig.12 As shown, after forming the polycrystalline semiconductor gate 17 and the polycrystalline semiconductor resistor 18, conventional steps for preparing MOS tubes are also included, such as the steps of forming sidewalls 19 on both sides of the polycrystalline semiconductor gate 17 and on both sides of the polycrystalline semiconductor resistor 18; the steps of forming a source 20 and a drain 21 in the semiconductor substrate 10 on both sides of the polycrystalline semiconductor gate 17, etc.
[0092] This embodiment also provides a semiconductor device, which is manufactured using the semiconductor device manufacturing method described above.
[0093] In summary, the present invention provides a semiconductor device and a method for preparing the same. By simultaneously performing an ion implantation process on the corresponding polycrystalline semiconductor layers on the active region and the resistance region, the polycrystalline semiconductor gate structure required for the active region and the polycrystalline semiconductor resistance structure required for the resistance region are obtained, thereby reducing the need for an additional ion implantation process to form a polycrystalline semiconductor resistance structure in the resistance region. For the ion implantation process, a photoresist is generally required to block the area that does not require ion implantation. Therefore, by using the preparation method of this embodiment, a mask, a photolithography process, and an ion implantation process can be reduced, effectively reducing the preparation cost and improving the production efficiency. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has a high industrial utilization value.
[0094] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: Providing a semiconductor substrate, wherein the semiconductor substrate has a resistance region and two active regions for forming an NMOS tube and a PMOS tube; forming a polycrystalline semiconductor layer on the semiconductor substrate; Simultaneously performing an ion implantation process on at least one of the active regions and the polycrystalline semiconductor layer corresponding to the resistance region; The polycrystalline semiconductor layer is etched to form polycrystalline semiconductor gates in the two active regions and to form polycrystalline semiconductor resistors in the resistor region.
2. The method for preparing a semiconductor device according to claim 1, wherein: Also includes: The step of forming sidewalls on both sides of the polycrystalline semiconductor gate and both sides of the polycrystalline semiconductor resistor; The step of forming a source and a drain in the semiconductor substrate on both sides of the polycrystalline semiconductor gate.
3. The method for preparing a semiconductor device according to claim 1, wherein: An insulating isolation structure is arranged in the semiconductor substrate where the resistance area is located.
4. The method for preparing a semiconductor device according to claim 1, wherein: After the ion implantation process is performed, the method further includes performing an annealing process on the polycrystalline semiconductor layer.
5. The method for preparing a semiconductor device according to claim 1, wherein: The ions implanted in the ion implantation process are P-type ions or N-type ions.
6. The method for preparing a semiconductor device according to claim 5, characterized in that: The ion implantation dosage of the P-type ions is 1E14 to 1E15, including the endpoint value; the ion implantation dosage of the N-type ions is 1E14 to 1E15, including the endpoint value.
7. The method for preparing a semiconductor device according to claim 1, wherein: The material of the polycrystalline semiconductor layer is one of polycrystalline silicon, polycrystalline gallium arsenide, polycrystalline germanium and polycrystalline germanium silicon.
8. The method for preparing a semiconductor device according to claim 1, wherein: Before forming the polycrystalline semiconductor layer on the semiconductor substrate, the method further includes forming a gate dielectric layer on the semiconductor substrate; The etching of the polycrystalline semiconductor layer also includes the step of etching at least the gate dielectric layer corresponding to the active area except the area where the polycrystalline semiconductor gate is located.
9. The method for preparing a semiconductor device according to claim 1, wherein: When the ion implantation process is performed simultaneously on the polycrystalline semiconductor layer corresponding to the active region and the resistance region, the process steps include: Coating a first photoresist layer on the polycrystalline semiconductor layer, and patterning the first photoresist layer to form a patterned first photoresist layer, wherein the patterned first photoresist layer exposes the polycrystalline semiconductor layer corresponding to the active area and the resistance area that need to be subjected to an ion implantation process; Performing an ion implantation process on the polycrystalline semiconductor layer based on the patterned first photoresist layer; removing the patterned first photoresist layer; When the ion implantation process is performed simultaneously on the two polycrystalline semiconductor layers corresponding to the active region and the resistance region, the process steps include: Coating a second photoresist layer on the polycrystalline semiconductor layer, and patterning the second photoresist layer to form a patterned second photoresist layer, wherein the patterned second photoresist layer exposes the polycrystalline semiconductor layer corresponding to one of the active regions and the resistance region; Performing a first ion implantation process on the polycrystalline semiconductor layer based on the patterned second photoresist layer; removing the patterned second photoresist layer; Coating a third photoresist layer on the polycrystalline semiconductor layer, and patterning the third photoresist layer to form a patterned third photoresist layer, wherein the patterned third photoresist layer exposes the polycrystalline semiconductor layer corresponding to another active region and the resistance region; Based on the patterned third photoresist layer, a second ion implantation process is performed on the polycrystalline semiconductor layer, the doping type of which is opposite to that of the first ion implantation process; The patterned third photoresist layer is removed.
10. A semiconductor device, characterized in that: The semiconductor device is prepared by the method for preparing the semiconductor device as claimed in any one of claims 1 to 9.