Metal bonding pad structure and preparation method thereof
By forming openings and separation patterns in the inter-metal wire layer of the semiconductor device and gradually forming metal pads, the N-type peripheral leakage problem is solved and the reliability of the device is improved.
Patent Information
- Application Number
- CN202311400010.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-10-26
- Publication Date
- 2025-04-29
AI Technical Summary
In the RE test of semiconductor devices, there is a tendency to leakage in the N-type peripheral region, resulting in failure of reliability tests and affecting the reliability of the entire semiconductor device.
By forming a first opening in the interlayer dielectric layer of the metal wire and providing a partition pattern, a first pad layer is formed and the partition pattern is removed to form a second opening, and then a second pad layer is formed to reduce the contact time and area of the metal wire and plasma, thereby reducing damage to the gate structure.
The reliability of semiconductor devices is improved and plasma damage to the gate structure under the metal wire is reduced when preparing metal pads.
Smart Images
Figure CN119905402A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to a metal pad structure and a preparation method thereof. Background Art
[0002] With the advancement of semiconductor technology, the manufacturing process of semiconductor devices is constantly developing towards a higher integration process. In a higher integration process, the core area usually uses a metal gate with a high dielectric constant gate dielectric layer, usually abbreviated as HKMG, where HK represents a high dielectric constant (HK) gate dielectric layer and MG represents a metal gate; in some cases, due to the large voltage and current in the peripheral area (i.e., IO area, including P-type peripheral area and N-type peripheral area) and the premise that its integration requirement is lower than that of the core area, a silicon oxide gate dielectric layer polysilicon gate is still used in the peripheral area to save low-node process resources.
[0003] A metal pad is provided on the top layer of the semiconductor device for electrical lead-out. When performing RE (Radiated emission) test on some semiconductor devices having HKMG (metal gate with high dielectric constant dielectric layer), it is found that the N-type peripheral region (for example, a polysilicon gate with silicon oxide gate dielectric layer) is more prone to leakage, causing the reliability test of the N-type peripheral region of the semiconductor device to fail (RE test failure), thereby affecting the reliability of the entire semiconductor device. Summary of the invention
[0004] The object of the present invention is to provide a metal pad structure and a preparation method thereof, so as to improve the reliability of semiconductor devices.
[0005] In order to solve the above technical problems, the present invention provides a method for preparing a metal pad, comprising:
[0006] Providing a substrate, wherein a metal line and an interlayer dielectric layer covering the metal line are formed in the substrate;
[0007] A first opening is formed in the interlayer dielectric layer on the metal line to expose the surface of the metal line, and a separation pattern is provided at the bottom of the first opening to cover a part of the surface of the metal line;
[0008] Forming a first pad layer to conformally cover the surface of the interlayer dielectric layer, the inner wall of the first opening and the outer wall of the separation pattern;
[0009] Removing the first pad layer on the separation pattern and the separation pattern to form a second opening in the first pad layer of the first opening and expose the surface of the metal line;
[0010] A second pad layer is formed to conformally cover the first pad layer and the inner wall of the second opening, and the first pad layer and the second pad layer are used as the metal pad.
[0011] Optionally, the interlayer dielectric layer includes a first dielectric layer and a second dielectric layer sequentially covering the metal wires, the separation pattern is formed by the first dielectric layer, and the separation pattern is located at a bottom middle position of the first opening.
[0012] Optionally, the step of forming the first opening includes:
[0013] Performing a patterning process on the second dielectric layer above the metal line to form a third opening to expose the surface of the first dielectric layer, wherein the opening size of the third opening is the same as the opening size of the first opening;
[0014] The first dielectric layer in the third opening is patterned to form at least two fourth openings to expose the surface of the metal line, the first dielectric layer between the fourth openings is used as the separation pattern, and the third opening and the fourth opening constitute the first opening.
[0015] Optionally, the partition pattern is in the shape of a line, a cross or a grid.
[0016] Optionally, the materials of the first pad layer and the second pad layer both include metal aluminum.
[0017] Optionally, the material of the metal wire includes metal copper, and before forming the first pad layer and / or the second pad layer, a titanium nitride layer and a tantalum nitride layer are further formed as metal barrier layers.
[0018] Optionally, the metal pad has a preset thickness, and the thickness of the first pad layer is one third to two thirds of the preset thickness.
[0019] Optionally, the substrate includes a core region, a P-type peripheral region and an N-type peripheral region, and the first opening and the separation pattern are formed in an interlayer dielectric layer on a metal line in the N-type peripheral region, and then the first pad layer and the second pad layer are formed.
[0020] Optionally, a fifth opening is formed in the interlayer dielectric layer on the metal wires in the core area and / or the P-type peripheral area to expose the surface of the corresponding metal wires, and a corresponding third pad layer and a fourth pad layer are formed in the fifth opening synchronously with the first pad layer and the second pad layer to form corresponding metal pads.
[0021] According to another aspect of the present invention, a metal pad structure is further provided, comprising:
[0022] a substrate having metal lines formed therein;
[0023] an interlayer dielectric layer, covering the substrate and the metal line, and a first opening is formed in the interlayer dielectric layer to expose the surface of the metal line;
[0024] A first pad layer conformally covers the surface of the interlayer dielectric layer, the sidewall of the first opening and a portion of the surface of the metal line, and the first pad layer is formed with a second opening in the first opening to expose the remaining surface of the metal line;
[0025] The second pad layer conformally covers the surface of the first pad layer and the inner wall of the second opening, and the first pad layer and the second pad layer serve as the metal pad.
[0026] In summary, the present invention forms a first opening in the interlayer dielectric layer on the metal wire to expose the surface of the metal wire, a partition pattern is provided at the bottom of the first opening to partially cover the surface of the metal wire, and then a first pad layer is formed to conformally cover the surface of the interlayer dielectric layer, the inner wall of the first opening and the outer wall of the partition pattern, and then the first pad layer and the partition pattern on the partition pattern are removed to form a second opening in the first opening and expose the surface of the metal wire, and then, a second pad layer is formed to conformally cover the first pad layer and the inner wall of the second opening, and the first pad layer and the second pad layer are used as metal pads. Compared with forming a metal pad in an opening once, the present invention forms a first pad layer and a second pad layer separately, that is, by forming the metal pad twice, the contact time of the metal wire (and the gate structure thereunder) with plasma (the metal pad is prepared by a PVD process) is reduced each time when the metal pad is prepared, so as to reduce the plasma damage to the gate structure (gate oxide layer) under the metal wire, and a separation pattern is set at the bottom of the first opening, thereby reducing the contact area of the metal wire with the plasma of the pad material each time when the metal pad is prepared, thereby reducing the plasma damage to the gate structure under the metal wire during sputtering, so as to improve the corresponding reliability of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Those skilled in the art should understand that the drawings are provided for a better understanding of the present invention, but do not constitute any limitation on the scope of the present invention.
[0028] Figure 1 is a flow chart of a method for preparing a metal pad provided in Example 1;
[0029] Figure 2a to Figure 2h A schematic structural diagram corresponding to the corresponding steps of the method for preparing the metal pad provided in Example 1;
[0030] Figure 3a to Figure 3d A schematic top view of four partition patterns in the first opening provided in Example 2;
[0031] Figure 4a to Figure 4d This is a schematic structural diagram corresponding to the corresponding steps of the method for preparing the metal pad provided in Example 3.
[0032] In the attached figure:
[0033] 10-substrate; 11-metal line; AA-N-type peripheral area; BB-other area; 21-interlayer dielectric layer; 21a first dielectric layer; 21b-second dielectric layer; 22-third opening; 12-patterned mask; 23-fourth opening; 24-first opening; 25-separation pattern; 26-first pad layer; 27-second opening; 28-second pad layer; 31-fifth opening; 32-third pad layer; 33-fourth pad layer. DETAILED DESCRIPTION
[0034] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.
[0035] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used only for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of indicated technical features. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, unless the content clearly indicates otherwise.
[0036] Embodiment 1
[0037] Embodiment 1 provides a method for preparing a metal pad.
[0038] Figure 1 A flow chart of a method for preparing a metal pad provided in Example 1.
[0039] like Figure 1 As shown, the method for preparing the metal pad provided in this embodiment includes:
[0040] S01: providing a substrate, wherein a metal line and an interlayer dielectric layer covering the metal line are formed in the substrate;
[0041] S02: forming a first opening in the interlayer dielectric layer on the metal line to expose the surface of the metal line, and a separation pattern is provided at the bottom of the first opening to cover a part of the surface of the metal line;
[0042] S03: forming a first pad layer to conformally cover the surface of the interlayer dielectric layer, the inner wall of the first opening and the outer wall of the separation pattern;
[0043] S04: removing the first pad layer on the separation pattern and the separation pattern to form a second opening in the first pad layer of the first opening and expose the surface of the metal line;
[0044] S05: forming a second pad layer to conformally cover the first pad layer and the inner wall of the second opening, and using the first pad layer and the second pad layer as the metal pad.
[0045] Figure 2a to Figure 2h The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the metal pad provided in the first embodiment. Next, Figure 2a to Figure 2h The preparation method of the metal pad is described in detail.
[0046] First, please refer to Figure 2a , step S01 is performed to provide a substrate 10 , in which a metal line 11 and an interlayer dielectric layer 21 covering the metal line 11 are formed.
[0047] The material of the substrate 10 may include any suitable base material known to those skilled in the art, for example, it may be at least one of the following materials: silicon, glass, quartz, plastic, etc.
[0048] The substrate 10 has a P-type core region, an N-type core region, a P-type peripheral region and an N-type peripheral region. The core region (i.e., the Core region) is used to form semiconductor devices, and the peripheral region (i.e., the IO region) is used to form peripheral circuits. Semiconductor device layers and interconnection layers connected to the semiconductor device layers can be sequentially formed in the substrate 10 on the core region and the peripheral region. The semiconductor device layer can include corresponding logic devices, and the interconnection layer can include an Nth interconnection layer and a corresponding interlayer dielectric layer for electrically leading out the corresponding semiconductor device or peripheral circuit, where N is an integer greater than or equal to 1. In the present embodiment, taking the formation of a metal pad in an N-type peripheral region as an example, the logic device in the N-type peripheral region may include a polysilicon gate (without a high dielectric constant dielectric layer and a metal work function layer), the metal line 11 may be a top interconnect layer, the material of the metal line 11 may, for example, include copper, and the corresponding interlayer dielectric layer 21 may include a first dielectric layer 21a and a second dielectric layer 21b formed in sequence, wherein the first dielectric layer 21a may be an insulating material layer with a harder material, such as a silicon nitride layer or a silicon nitride oxide layer, and the thickness of the second dielectric layer 21b may be greater than the thickness of the first dielectric layer 21a, and its material may, for example, include silicon oxide.
[0049] In addition, the metal line 11 may also be the top interconnect layer of the region (core region or peripheral region) having a metal gate (having a high dielectric constant dielectric layer and a metal work function layer). It is not difficult to understand that, compared with the gate structure formed by the silicon oxide gate oxide layer and the polysilicon gate material, the high dielectric constant dielectric layer and the metal work function layer have higher resistance to the voltage (plasma) in the manufacturing process and RE test, and the region including the metal gate (having a high dielectric constant dielectric layer and a metal work function layer) has higher reliability (RE test or leakage performance).
[0050] Next, step S02 is performed to form a first opening 24 in the interlayer dielectric layer 21 on the metal line 11 to expose the surface of the metal line 11, and a separation pattern 25 is provided at the bottom of the first opening 24 to cover part of the surface of the metal line 11 to reduce the exposed area of the metal line 11 in the first opening 24.
[0051] In the example of this embodiment, the separation pattern 25 is formed by the first dielectric layer 21a remaining after etching, which covers the surface of the metal line 11 to reduce the exposed area of the metal line 11. The separation pattern 25 can also be located in the middle or close to the center of the bottom of the first opening 24 to divide the larger exposed area of the metal line 11 into at least two smaller exposed areas with similar areas.
[0052] For details, please refer to Figure 2b , a patterning process is performed on the second dielectric layer 21b above the metal line 11 to form a third opening 22 to expose the surface of the first dielectric layer 21a. The opening size of the third opening 22 can be the same as or close to the opening size of the metal pad to be formed subsequently.
[0053] The first dielectric layer 21a exposed by the third opening 22 is patterned to form at least two fourth openings 23 to expose the surface of the metal line 11 , and the remaining first dielectric layer 21a between the fourth openings 23 is used as a separation pattern 25 , and the third opening 22 and the fourth opening 23 constitute a first opening 24 .
[0054] In this embodiment, the third opening 22 may be rectangular (top view), and the partition pattern 25 may be in a straight line (long strip) and located in the middle of the surface of the exposed metal line 11, so as to form two fourth openings 23 of similar size on the surface of the metal line 11. The steps of forming the two fourth openings 23 may include: Figure 2c , a patterned mask is formed on the second dielectric layer 21b, the patterned mask covers the surface of the second dielectric layer 21b, and a stripe-shaped mask pattern is formed on the first dielectric layer 21a in the third opening 22, the mask pattern is located in the middle of the third opening 22 and two openings are formed on both sides of the mask pattern to expose the surface of the first dielectric layer 21a on both sides thereof; then, please refer to Figure 2d and Figure 2e , Figure 2d is a cross-sectional schematic diagram, Figure 2e As a top view, the first dielectric layer 21a is etched using the patterned mask to form two fourth openings 23 in the first dielectric layer 21a to expose the surface of the metal line 11, and then the patterned mask is removed, and the remaining first dielectric layer 21a under the third opening 22 is used as the separation pattern 25, and the third opening 22 and the fourth opening 23 constitute the first opening 24. Taking this embodiment as an example, the opening size (width) of the third opening 22 can be 1500 nanometers, and the width of the separation pattern 25 can be 400 nanometers to 600 nanometers, and is located at the bottom middle position of the first opening 24.
[0055] Next, please refer to Figure 2f , step S03 is executed to form a first pad layer 26 to conformally cover the surface of the second dielectric layer 21 b , the inner wall of the first opening 24 and the outer wall of the partition pattern 25 .
[0056] Before forming the first pad layer 26, a metal barrier layer (not shown in the figure) may be formed to cover the surface of the second dielectric layer 21b, the inner wall of the first opening 24 and the outer wall of the partition pattern 25 in a forward direction, and then the first pad layer 26 may be formed to cover the metal barrier layer in a forward direction. The material of the first pad layer 26 may be any suitable pad material, such as a metal material, and may be formed, for example, by a PVD process (sputtering process), and the material of the metal barrier layer matches the material of the metal wire 11 and the first pad layer 26. In the present embodiment, the material of the first pad layer 26 may include aluminum, the material of the metal wire 11 may include copper, and the material of the metal barrier layer may include a titanium nitride layer and a tantalum nitride layer formed in sequence.
[0057] It should be noted that the thickness of the first pad layer 26 can be one-third to two-thirds of the preset thickness of the metal pad to be formed, so as to reduce the time of a single PVD process, thereby reducing the high voltage damage formed downward by the plasma bombarding the metal line 11 (for example, the gate oxide layer of the gate structure) when the first pad layer 26 is formed. Moreover, the separation pattern 25 provided at the bottom of the first opening 24 can also reduce the area of the plasma bombarding the metal line 11, so as to further reduce the charge accumulation on the surface of the metal line 11. Of course, from one aspect, the separation pattern 25 can also be regarded as a protective layer (barrier layer) that partially covers the surface of the metal line 11 when the sputtering process is performed, so as to reduce the plasma damage during sputtering. In particular, the separation pattern 25 also divides the first opening 24 into two openings, each of which is composed of a fourth opening 23 and a part of the third opening 22, so that under the condition that the actual depth remains unchanged, it is similar to improving the aspect ratio of the first opening 24 when the sputtering process is performed, thereby reducing the high voltage damage formed by the plasma to the structure below the metal line 11.
[0058] Next, please refer to Figure 2g , step S04 is performed to remove the first pad layer 26 and the separation pattern 25 on the separation pattern 25 to form a second opening 27 in the first opening 24 and expose the surface of the metal line 11.
[0059] Specifically, a patterned mask 12 may be formed to cover the surface of the first pad layer 26 on the second dielectric layer 21b and the first pad layer 26 on the inner wall of the first opening 24, and the opening of the patterned mask 12 exposes the first pad layer 26 on the partition pattern 25, and then the patterned mask 12 is used to perform an etching process to sequentially remove the first pad layer 26 and the partition pattern 25 on the partition pattern 25, expose the surface of the metal line 11, and then remove the patterned mask 12, and use the opening surrounded by the remaining first pad layer 26 in the first opening 24 and the exposed surface of the metal line 11 as the second opening 27. In addition, the opening width of the patterned mask 12 may also be appropriately larger than the width of the partition pattern 25 to ensure that the partition pattern 25 is completely removed to prevent residue, and at the same time, the opening width of the second opening 27 in the first pad layer 26 is appropriately enlarged to facilitate subsequent pad material filling.
[0060] Next, please refer to Figure 2h , executing step S05, forming a second pad layer 28 to conformally cover the first pad layer 26 and the inner wall of the second opening 27, and using the first pad layer 26 and the second pad layer 28 as metal pads.
[0061] Similar to the formation of the first pad layer 26, before forming the second pad layer 28, a metal barrier layer (not shown in the figure) may be formed to cover the surface of the first pad layer 26 and the inner wall of the second opening 27 (including the exposed surface of the metal line 11) in a forward direction, and then the second pad layer 28 may be formed to cover the metal barrier layer in a forward direction. The material of the second pad layer 28 may be any suitable pad material, such as a metal material, and may be formed, for example, by a PVD process (sputtering process), and the material of the metal barrier layer matches the material of the metal line 11, the first pad layer 26, and the second pad layer 28. In the present embodiment, the material of the metal line 11 may include copper, the material of the second pad layer 28 may be the same as that of the first pad layer 26, and its material may include, for example, aluminum, and the material of the metal barrier layer may include a titanium nitride layer and a tantalum nitride layer formed in sequence. In other examples of this embodiment, the material of the first pad layer 26 may be different from the material of the second pad layer 28. For example, the first pad layer 26 may have a higher conductivity than the second pad layer 28, and the second pad layer 28 may have better resistance to the external environment than the first pad layer 26, and the second pad layer 28 is used to protect the first pad layer 26.
[0062] The thickness of the second pad layer 28 may be the remaining thickness of the preset thickness of the metal pad to be formed. Similar to the formation of the first pad layer 26, when forming the second pad layer 28, the area of the metal line 11 exposed at the bottom of the second opening 27 is smaller than the opening area of the metal pad to be formed, and the thickness of the second pad layer 28 is also less than the preset thickness of the metal pad to compress the sputtering time, thereby reducing the high voltage damage caused by plasma to the structure under the metal line 11. In addition, the opening of the second opening 27 is much smaller than the opening of the first opening 24, which is also conducive to reducing plasma damage during sputtering.
[0063] Thus, a metal pad consisting of a first pad layer 26 and a second pad layer 28 can be formed in the first opening 24 above the metal wire 11. Compared with forming the metal pad in the opening once, forming the first pad layer 26 and the second pad layer 28 twice reduces the contact time of the metal wire 11 (and the gate structure thereunder) with the plasma (high voltage) each time. In addition, a separation pattern 25 is provided at the bottom of the first opening 24, thereby reducing the contact area between the metal wire 11 and the plasma of the pad material each time, thereby reducing the plasma damage to the gate structure (gate oxide layer) below the metal wire 11 during sputtering, thereby improving the corresponding reliability of the semiconductor device.
[0064] Embodiment 2
[0065] Embodiment 2 provides a method for preparing a metal pad.
[0066] Figure 1 A flow chart of a method for preparing a metal pad provided in Example 2.
[0067] like Figure 1 As shown, the method for preparing the metal pad provided in this embodiment includes:
[0068] S01: providing a substrate, wherein a metal line and an interlayer dielectric layer covering the metal line are formed in the substrate;
[0069] S02: forming a first opening in the interlayer dielectric layer on the metal line to expose the surface of the metal line, and a separation pattern is provided at the bottom of the first opening to cover a part of the surface of the metal line;
[0070] S03: forming a first pad layer to conformally cover the surface of the interlayer dielectric layer, the inner wall of the first opening and the outer wall of the separation pattern;
[0071] S04: removing the first pad layer on the separation pattern and the separation pattern to form a second opening in the first pad layer of the first opening and expose the surface of the metal line;
[0072] S05: forming a second pad layer to conformally cover the first pad layer and the inner wall of the second opening, and using the first pad layer and the second pad layer as the metal pad.
[0073] The preparation method of the metal pad provided in the second embodiment is similar to the preparation method provided in the first embodiment, and the difference is only that the separation pattern 25 formed in step S02 is different. In the second embodiment, the separation pattern 25 formed at the bottom of the first opening 24 can be one, two or more than two, and the separation pattern 25 can also be any other suitable pattern or combination of patterns, and the separation pattern 25 can also be located at any suitable position at the bottom of the first opening 24, and is limited to the middle position of the bottom of the first opening 24. In addition, the separation pattern 25 can also be formed by other materials, that is, not formed by the first dielectric layer 21a, for example, the first opening 24 is formed in the interlayer dielectric layer 21 to expose the surface of the metal line 11, and then the separation pattern 25 is formed at the bottom of the first opening 24 using other materials (such as mask materials).
[0074] In an example, see Figure 3a At least two (two in the figure) spaced-apart straight-line partition patterns 25 are formed at the bottom of the first opening 24 to partition the larger exposed surface of the metal wire 11 into at least three smaller exposed surfaces.
[0075] In an example, see Figure 3b A cross-shaped separation pattern 25 is formed at the bottom of the first opening 24 to separate the larger exposed surface of the metal line 11 into four smaller exposed surfaces.
[0076] In an example, see Figure 3c A grid-like separation pattern 25 is formed at the bottom of the first opening 24 to separate the larger exposed surface of the metal line 11 into four or more smaller exposed surfaces.
[0077] In an example, see Figure 3d A straight-line separation pattern 25 is formed at the bottom of the first opening 24. The separation pattern 25 is close to (or closely attached to) the side wall of the first opening 24, and separates the larger exposed surface of the metal line 11 into a smaller exposed surface.
[0078] Embodiment 3
[0079] Embodiment 3 provides a method for preparing a metal pad.
[0080] Figure 1 This is a flow chart of the method for preparing the metal pad provided in Example 3.
[0081] like Figure 1 As shown, the method for preparing the metal pad provided in this embodiment includes:
[0082] S01: providing a substrate, wherein a metal line and an interlayer dielectric layer covering the metal line are formed in the substrate;
[0083] S02: forming a first opening in the interlayer dielectric layer on the metal line to expose the surface of the metal line, and a separation pattern is provided at the bottom of the first opening to cover a part of the surface of the metal line;
[0084] S03: forming a first pad layer to conformally cover the surface of the interlayer dielectric layer, the inner wall of the first opening and the outer wall of the separation pattern;
[0085] S04: removing the first pad layer on the separation pattern and the separation pattern to form a second opening in the first pad layer of the first opening and expose the surface of the metal line;
[0086] S05: forming a second pad layer to conformally cover the first pad layer and the inner wall of the second opening, and using the first pad layer and the second pad layer as the metal pad.
[0087] The preparation method of the metal pad provided in Example 3 is similar to the preparation method of Example 1 or Example 2, and the only difference is that in Example 3, while the above-mentioned metal pad is formed in the N-type peripheral area AA of the substrate 10, a corresponding metal pad is simultaneously formed in the core area and / or the P-type peripheral area (hereinafter collectively referred to as other areas BB). Figure 2a to Figure 2h The schematic diagram of the structure corresponding to the corresponding steps of the method for preparing the metal pad provided in the third embodiment. Next, Figure 2a to Figure 2h The preparation method of the metal pad is described in detail.
[0088] Specifically, in step S02, please refer to Figure 4a A first opening 24 is formed in the interlayer dielectric layer 21 on the metal line 11 in the N-type peripheral area AA to expose the surface of the metal line 11, and a separation pattern 25 is provided at the bottom of the first opening 24 to partially cover the metal line 11 to reduce the exposed area of the metal line 11; at the same time, a fifth opening 31 is formed in the interlayer dielectric layer 21 on the metal line 11 in the other area BB to expose the surface of the corresponding metal line 11, that is, a separation pattern 25 or a structure with similar functions is not formed at the bottom of the fifth opening 31.
[0089] In step S03, please refer to Figure 4b, forming a first pad layer 26 conformally covering the surface of the second dielectric layer 21b, the inner wall of the first opening 24 and the outer wall of the partition pattern 25, and forming a third pad layer 32 conformally covering the surface of the second dielectric layer 21b and the inner wall of the fifth opening 31. Among them, the first pad layer 26 and the third pad layer 32 are made of the same pad material and are formed simultaneously using the same process. Of course, before forming the first pad layer 26 and the third pad layer 32, a metal barrier layer (not shown in the figure) can also be formed to conformally cover the surface of the second dielectric layer 21b, the inner wall of the first opening 24, the outer wall of the partition pattern 25 and the inner wall of the fifth opening 31.
[0090] In step S04, please refer to Figure 4c , the first pad layer 26 and the separation pattern 25 on the separation pattern 25 are removed to form a second opening 27 in the first opening 24 and expose the surface of the metal line 11. In this step, the other areas BB are not treated in the same way (a mask is used to protect the other areas BB when etching the first pad layer 26 and the separation pattern 25).
[0091] In step S05, please refer to Figure 4d , forming a second pad layer 28 to conformally cover the first pad layer 26 and the inner wall of the second opening 27, and forming a fourth pad layer 33 to conformally cover the third pad layer 32 and the inner wall of the fifth opening 31, and using the first pad layer 26 and the second pad layer 28 as the metal pads of the N-type peripheral area AA, and using the third pad layer 32 and the fourth pad layer 33 as the metal pads of other areas BB (core area and / or P-type peripheral area). Of course, before forming the second pad layer 28 and the fourth pad layer 33, a metal barrier layer (not shown in the figure) can also be formed to conformally cover the surface of the first pad layer 26, the inner wall of the second opening 27, the surface of the third pad layer 32 and the inner wall of the fifth opening 31.
[0092] In this embodiment, metal pads of different structures can be formed in different regions in combination with actual conditions to improve the operability of the process. It can be understood that on the same substrate 10, the size of the metal pad in the core region is usually smaller than that of the metal pad in the peripheral region, that is, when forming the metal pad, the depth-to-width ratio of the opening in the core region is greater than the depth-to-width ratio of the opening in the peripheral region. If the depth-to-width ratio of the opening in the core region is large, the opening in the core region is divided into openings with a large depth-to-width ratio, which puts higher requirements on the material for filling the pad in the PVD process, which is not conducive to production line operation; on the other hand, in some examples, a high dielectric constant metal gate is usually used in the core region and the P-type peripheral region, while only a polysilicon gate of a silicon oxide gate dielectric layer is used in the N-type peripheral region AA. The reliability performance of the RE resistance test of the N-type peripheral region AA is relatively poor compared to the core region and the P-type peripheral region. Therefore, only in the N-type peripheral region AA, the metal pad of the above structure is formed by the above method, so as to take into account the reliability of the semiconductor device and the operability of the process.
[0093] Embodiment 4
[0094] Embodiment 4 provides a metal pad structure.
[0095] Figure 2h It is a schematic diagram of a metal pad structure provided in Example 4.
[0096] The metal pad structure provided in this embodiment can be prepared by any one of the preparation methods in Embodiments 1 to 3 or a combination of any of the preparation methods. Figure 2h As shown, the metal pad structure provided in the fourth embodiment includes a substrate 10, an interlayer dielectric layer 21, a first pad layer 26 and a second pad layer 28. The substrate 10 is formed with a metal line 11; the interlayer dielectric layer 21 covers the substrate 10 and the metal line 11, and a first opening 24 is formed in the interlayer dielectric layer 21 to expose the surface of the metal line 11; the first pad layer 26 conformally covers the surface of the interlayer dielectric layer 21, the sidewall of the first opening 24 and a part of the surface of the metal line 11, and the first pad layer 26 forms a second opening 27 in the first opening 24 to expose the remaining surface of the metal line 11; the second pad layer 28 conformally covers the surface of the first pad layer 26 and the inner wall of the second opening 27, and the first pad layer 26 and the second pad layer 28 are used as metal pads.
[0097] The substrate 10 has a P-type core region, an N-type core region, a P-type peripheral region and an N-type peripheral region AA, the core region is used to form a semiconductor device, and the peripheral region is used to form a peripheral circuit. A semiconductor device layer and an interconnection layer connected to the semiconductor device layer can be formed in sequence in the substrate 10 on the core region and the peripheral region, the semiconductor device layer can include a corresponding logic device, the interconnection layer can include an Nth interconnection layer and an interlayer dielectric layer 21 for electrically leading out the corresponding semiconductor device or peripheral circuit, N is an integer greater than or equal to 1. The metal wire 11 can be a top interconnection layer, the material of the metal wire 11 can include copper, for example, the corresponding interlayer dielectric layer 21 can include a first dielectric layer 21a and a second dielectric layer 21b formed in sequence, wherein the first dielectric layer 21a can be a harder insulating material layer, such as a silicon nitride layer or a silicon nitride oxide layer, the thickness of the second dielectric layer 21b can be greater than the thickness of the first dielectric layer 21a, and its material can include silicon oxide, for example.
[0098] A first opening 24 is formed in the interlayer dielectric layer 21 to expose the surface of the metal line 11, and a first pad layer 26 conformally covers the surface of the interlayer dielectric layer 21, the sidewall of the first opening 24, and a portion of the surface of the metal line 11, and the first pad layer 26 forms a second opening 27 in the first opening 24, and the second opening 27 exposes the surface of the metal line 11 in the first opening 24 that is not covered by the first pad layer 26 (the remaining surface of the metal line 11). The second pad layer 28 conformally covers the surface of the first pad layer 26 and the inner wall of the second opening 27 (including the sidewall of the second opening 27 and the exposed surface of the metal line 11), and the first pad layer 26 and the second pad layer 28 are used as metal pads. Before forming the first pad layer 26 and the second pad layer 28, a metal barrier layer (not shown in the figure) may be formed to conformally cover the corresponding exposed surface. The thickness of the first pad layer 26 may be one third to two thirds of the preset thickness of the metal pad to be formed, so as to reduce the time of performing a single PVD process, thereby reducing the high voltage damage formed downward by plasma bombarding the metal line 11 (for example, to the gate oxide layer of the gate structure) when forming the first pad layer 26. The thickness of the second pad layer 28 may be the remaining thickness of the preset thickness of the metal pad to be formed.
[0099] The material of the first pad layer 26 and the second pad layer 28 may be any suitable pad material, such as a metal material, and may be formed, for example, by a PVD process (sputtering process), and the material of the metal barrier layer matches the material of the metal line 11, the first pad layer 26, and the second pad layer 28. In the present embodiment, the material of the metal line 11 may include copper, the material of the first pad layer 26 may be the same as the material of the second pad layer 28, such as aluminum, and the material of the metal barrier layer may include a titanium nitride layer and a tantalum nitride layer formed in sequence.
[0100] In summary, the present invention forms a first opening in the interlayer dielectric layer on the metal wire to expose the surface of the metal wire, a partition pattern is provided at the bottom of the first opening to partially cover the surface of the metal wire, and then a first pad layer is formed to conformally cover the surface of the interlayer dielectric layer, the inner wall of the first opening and the outer wall of the partition pattern, and then the first pad layer and the partition pattern on the partition pattern are removed to form a second opening in the first opening and expose the surface of the metal wire, and then, a second pad layer is formed to conformally cover the first pad layer and the inner wall of the second opening, and the first pad layer and the second pad layer are used as metal pads. Compared with forming a metal pad in an opening once, the present invention forms a first pad layer and a second pad layer separately, that is, by forming the metal pad twice, the contact time of the metal wire (and the gate structure thereunder) with plasma (the metal pad is prepared by a PVD process) is reduced each time when the metal pad is prepared, so as to reduce the plasma damage to the gate structure (gate oxide layer) under the metal wire, and a separation pattern is set at the bottom of the first opening, thereby reducing the contact area of the metal wire with the plasma of the pad material each time when the metal pad is prepared, thereby reducing the plasma damage to the gate structure under the metal wire during sputtering, so as to improve the corresponding reliability of the semiconductor device.
[0101] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.
Claims
1. A method for preparing a metal pad, characterized in that: include: Providing a substrate, wherein a metal line and an interlayer dielectric layer covering the metal line are formed in the substrate; A first opening is formed in the interlayer dielectric layer on the metal line to expose the surface of the metal line, and a separation pattern is provided at the bottom of the first opening to cover a part of the surface of the metal line; Forming a first pad layer to conformally cover the surface of the interlayer dielectric layer, the inner wall of the first opening and the outer wall of the separation pattern; Removing the first pad layer on the separation pattern and the separation pattern to form a second opening in the first pad layer of the first opening and expose the surface of the metal line; A second pad layer is formed to conformally cover the first pad layer and the inner wall of the second opening, and the first pad layer and the second pad layer are used as the metal pad.
2. The method for preparing a metal pad according to claim 1, characterized in that: The interlayer dielectric layer includes a first dielectric layer and a second dielectric layer which sequentially cover the metal wires. The separation pattern is formed by the first dielectric layer, and the separation pattern is located at the middle position of the bottom of the first opening.
3. The method for preparing a metal pad according to claim 2, characterized in that: The step of forming the first opening comprises: Performing a patterning process on the second dielectric layer above the metal line to form a third opening to expose the surface of the first dielectric layer, wherein the opening size of the third opening is the same as the opening size of the first opening; The first dielectric layer in the third opening is patterned to form at least two fourth openings to expose the surface of the metal line, the first dielectric layer between the fourth openings is used as the separation pattern, and the third opening and the fourth opening constitute the first opening.
4. The method for preparing a metal pad according to claim 2 or 3, characterized in that: The partition pattern is in a straight line shape, a cross shape or a grid shape.
5. The method for preparing a metal pad according to claim 1, characterized in that: The materials of the first pad layer and the second pad layer both include metal aluminum.
6. The method for preparing a metal pad according to claim 5, characterized in that: The material of the metal wire includes metal copper. Before forming the first pad layer and / or the second pad layer, a titanium nitride layer and a tantalum nitride layer are further formed as metal barrier layers.
7. The method for preparing a metal pad according to claim 1, characterized in that: The metal pad has a preset thickness, and the thickness of the first pad layer is one third to two thirds of the preset thickness.
8. The method for preparing a metal pad according to claim 1, characterized in that: The substrate includes a core region, a P-type peripheral region and an N-type peripheral region. The first opening and the separation pattern are formed in the interlayer dielectric layer on the metal line of the N-type peripheral region, and then the first pad layer and the second pad layer are formed.
9. The method for preparing a metal pad according to claim 8, characterized in that: A fifth opening is formed in the interlayer dielectric layer on the metal lines in the core area and / or the P-type peripheral area to expose the surface of the corresponding metal lines, and a corresponding third pad layer and a fourth pad layer are formed in the fifth opening synchronously with the first pad layer and the second pad layer to form corresponding metal pads.
10. A metal pad structure, characterized in that: include: a substrate having metal lines formed therein; an interlayer dielectric layer, covering the substrate and the metal line, and a first opening is formed in the interlayer dielectric layer to expose the surface of the metal line; A first pad layer conformally covers the surface of the interlayer dielectric layer, the sidewall of the first opening and a portion of the surface of the metal line, and the first pad layer is formed with a second opening in the first opening to expose the remaining surface of the metal line; The second pad layer conformally covers the surface of the first pad layer and the inner wall of the second opening, and the first pad layer and the second pad layer serve as the metal pad.