Cooling system, semiconductor device and forming method thereof

Abstract

A method of forming a semiconductor device includes forming a metallization structure over an integrated circuit (IC) substrate from a first side. A patterning process is performed on the metallized structure from the first side. The metallization structure is patterned into a plurality of metallization islands by a patterning process. A plurality of metal-containing structures are respectively formed over the plurality of metallization islands from the first side. A second side of the IC substrate is coupled to the organic substrate. The second side is opposite the first side. The embodiment of the invention also provides a semiconductor device and a cooling system.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to cooling systems, semiconductor devices, and methods of forming the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced generations of ICs, each with smaller and more complex circuits than the previous one. Over the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased, while geometry size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and reducing associated costs.

[0003] However, as semiconductor manufacturing progresses to more advanced technology nodes, additional challenges may arise. For example, IC devices may generate heat during their operation, and this heat should be quickly removed to ensure the normal and continuous operation of the IC devices. To this end, a direct boiling enhanced layer (BEL) can be attached to the IC device to facilitate heat removal. However, BELs are usually attached to IC devices through thermal interface materials (TIMs) and metal cover structures, which will increase additional thermal resistance and may therefore be undesirable. In addition, the implementation of BELs may cause excessive warping of IC devices, which is also undesirable. Therefore, although existing IC devices and their manufacturing methods are generally sufficient to meet their intended purposes, they are not satisfactory in every aspect. Summary of the invention

[0004] Some embodiments of the present disclosure provide a method for forming a semiconductor device, the method comprising: forming a metallization structure above an integrated circuit (IC) substrate from a first side; performing a patterning process on the metallization structure from the first side, wherein the metallization structure is patterned into a plurality of metallization islands by the patterning process; forming a plurality of metal-containing structures respectively above the plurality of metallization islands from the first side; and coupling a second side of the IC substrate to an organic substrate, wherein the second side is opposite to the first side.

[0005] Other embodiments of the present disclosure provide a semiconductor device, which includes: a substrate containing a circuit; a plurality of metallization structures, which are directly disposed on the substrate in a cross-sectional side view; and a plurality of metal-containing structures, which are respectively directly disposed on the plurality of metallization structures in a cross-sectional side view; wherein: the metallization structure and the metal-containing structure have different material components; the circuit includes a plurality of hot spot areas distributed in different positions of the substrate; and in the cross-sectional side view, each metal-containing structure is vertically aligned with a corresponding one of the hot spot areas.

[0006] Another embodiment of the present disclosure provides a cooling system, comprising: a chamber; a cooling fluid, partially filling the chamber; a condenser; a plurality of printed circuit boards (PCBs), immersed in the cooling fluid; and a plurality of integrated circuit (IC) devices, located on each PCB; wherein: each IC device comprises a substrate, a plurality of metallized islands directly disposed on the substrate, and a plurality of metal-containing islands directly disposed on the metallized islands; the metallized islands drive the cooling fluid into steam in response to heat generated by the IC devices; and the steam is converted back into the cooling fluid after contacting the condenser. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the sizes of the various components may be arbitrarily increased or reduced. It should also be emphasized that the drawings illustrate only typical embodiments of the present application and, therefore, should not be considered limiting in scope, as the present application may be equally applicable to other embodiments.

[0008] Figure 1 A cooling system according to an embodiment of the present disclosure is shown.

[0009] Figures 2 to 4 Various cross-sectional side views of IC structures according to embodiments of the present disclosure are shown.

[0010] Figures 5 to 10 A series of cross-sectional side views of an IC structure at various stages of fabrication are shown in accordance with an embodiment of the present disclosure.

[0011] Figures 11 to 13 Various planar top views of IC structures according to embodiments of the present disclosure are shown.

[0012] Fig.14 An integrated circuit manufacturing system according to various aspects of the present disclosure is shown.

[0013] Fig.15 A flow chart of a method according to various aspects of the present disclosure is shown. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for implementing the different components of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] Still further, when "about," "approximately," etc. are used to describe a value or a range of values, the term is intended to encompass values ​​within a reasonable range including the described value, such as within + / -10% of the described value, or other values ​​understood by those skilled in the art. For example, the term "about 5 nm" encompasses a size range from 4.5 nm to 5.5 nm.

[0017] The present disclosure is generally related to the implementation of a direct boiling enhancement layer (BEL) for two-phase immersion cooling. In more detail, many computing environments today involve IC devices that generate a large amount of heat during operation. For example, a data center configured to host computer servers or perform other data-intensive operations (e.g., machine learning) may employ hundreds or thousands of central processing units (CPUs) and / or graphics processing units (GPUs) that are constantly running (e.g., performing computing tasks). These CPUs and / or GPUs generate heat when performing computing tasks. If this heat is not dissipated quickly, this heat may degrade the performance of the CPU / GPU (or other nearby IC devices), and / or shorten the life of the CPU / GPU, and / or cause the CPU / GPU to fail prematurely.

[0018] In order to ensure the rapid removal of heat generated by the IC device, the IC device can be placed inside a cooling system containing a cooling fluid. The cooling fluid may become steam in response to the heat generated by the IC device. The cooling system may also include a condenser. When the steam (generated in response to the heat) rises and meets the condenser, the condenser changes the steam back into liquid form and then recirculates it back to the cooling fluid system. Thus, the heat generated by the IC device is removed in this process. A direct boiling enhancement layer (BEL) (which is a metal-containing layer) can be implemented on the IC device to promote the formation / generation of steam. However, the implementation of BEL is usually accompanied by a thermal interface material (TIM) and a metal cover structure. The TIM and metal cover structure can be formed between the BEL and the substrate of the IC device and are quite thick. Therefore, the TIM and metal structure may introduce additional thermal resistance, which is undesirable.

[0019] The present disclosure solves the above problems by forming a BEL-containing structure directly on the substrate of the IC device. By doing so, the TIM and metal cover structures can be eliminated, which helps to reduce the overall thermal resistance of the resulting IC device. In addition, the present disclosure can configure the BEL-containing structure as a plurality of discrete islands (separated from each other) vertically aligned with the location of the hot spot area. This island scheme can help reduce the substrate warpage problem that may occur. Similarly, the reduction in substrate warpage can be converted into better IC device performance and / or longer life. The following will refer to Figures 1 to 15

[0013] Various aspects of the disclosure are discussed in further detail below.

[0020] Reference now Figure 1 , an exemplary two-phase immersion cooling system 100 is shown. The two-phase immersion cooling system 100 includes an immersion chamber 110, which contains a cooling fluid 120. The cooling fluid 120 may be in liquid form and may have electrical insulating properties. In some embodiments, the cooling fluid 120 may include pure water, which is substantially free of impurities that may be conductive. A plurality of printed circuit boards (PCBs) 130 may be partially or completely immersed in the cooling fluid 120. The PCBs 130 may each include a plurality of IC devices 140, such as CPUs, GPUs, or other types of IC chips. During operation of the IC devices 140 (e.g., when the CPUs and / or GPUs perform computationally intensive tasks), a large amount of thermal energy in the form of heat may be generated as a result. As described above, if this heat cannot be quickly dissipated, the performance and / or life of the IC devices 140 may be adversely affected.

[0021] The two-phase immersion cooling system 100 is configured to quickly and efficiently dissipate heat generated by the IC devices 140. For example, the IC devices 140 can each include a BEL, which is a metal-containing material, as discussed in more detail below. The BEL promotes the formation of vapor 160, which is generated based on the cooling fluid 120 in response to the heat generated by the IC devices 140. In other words, the heat generated by the IC devices 140 transforms the cooling fluid 120 near the IC devices 140 from a liquid form to a vapor form (e.g., a phase change of the cooling fluid 120), and as a result, the BEL on the IC devices 140 makes the vapor 160 easier and / or faster to form.

[0022] The vapor 160 rises upward within the immersion chamber 110 until the vapor 160 comes into contact with a condenser 170 that is also implemented within the immersion chamber 110. In some embodiments, the condenser 170 may include a plurality of coils that may also contain a coolant. When the vapor 160 comes into contact with the condenser 170, the heat within the vapor 160 is absorbed by the condenser 170, causing the vapor 160 to be converted back into a fluid 180. The fluid 180 is recirculated downward to the cooling fluid 120 (e.g., becomes part of the cooling fluid 120 again), while the heat transferred to the condenser 170 is released to the exterior of the immersion chamber 110. In this manner, the two-phase immersion cooling system 100 can quickly and efficiently dissipate heat generated by the IC devices 140 housed therein.

[0023] Reference now Figure 2 , shows a schematic partial cross-sectional side view of an IC structure 200 on which an exemplary BEL 210 is implemented. In more detail, the IC structure 200 includes a substrate 220. In some embodiments, the substrate 220 can be a semiconductor substrate, such as a silicon substrate. In other embodiments, the substrate 220 can include a silicon-on-insulator (SoI) substrate. The substrate 220 can also be referred to as a carrier. In some embodiments, the substrate 220 has a thickness in a range between about 500 microns and about 900 microns, for example, between 600 microns and about 800 microns. In some embodiments, the substrate 220 has a thermal conductivity in a range between about 100 Watts / meter-Kelvin (W / mK) and about 140 W / mK. In some embodiments, the substrate 220 has a thermal resistance of about 5 millimeters*degrees Celsius per Watt (mm 2 C / W) to about 6.5mm 2 In the range between C / W.

[0024] The IC structure 200 also includes a back side metallization (BSM) 230 disposed over the substrate 220. The BSM 230 may be implemented directly on the surface of the substrate 220. In some embodiments, the BSM 230 plays the role of a seed layer (e.g., an anode) in a subsequently performed electroplating process, wherein the electroplating process may be used to form a BEL structure according to various aspects of the present disclosure. However, in some other embodiments, a BEL structure (formed later) may be formed directly on the substrate 220 using a physical vapor deposition (PVD) process or an epitaxial process, and as such, the BSM 230 does not need to be implemented in these embodiments because a seed layer is not required. In any case, in some embodiments in which the BSM 230 is formed, the BSM 230 may include a plurality of metal layers, such as a titanium (Ti) layer, a nickel (Ni) layer disposed over the Ti layer, and a copper (Cu) layer (which may be a porous structure) disposed over the Ni layer. The Cu layer may serve as the main conductive portion of the BSM 230, the Ti layer may serve as a barrier layer to prevent or at least mitigate diffusion between the Cu layer and the substrate 220, and the Ni layer may serve as an interface material between the Cu layer and the Ti layer. In such an embodiment, the Ti layer of the BSM 230 may be in direct contact with the surface of the substrate 220. It is worth noting that the Ni layer may also serve as a diffusion barrier layer. Other candidate materials for such a diffusion barrier layer (besides Ni) may include MoS 2 , TiW, TiN, Ta or TaN. It is also worth noting that the Ti layer can also be replaced by other suitable diffusion barrier layer candidates, such as SiN, SiON, SiO 2 , SiC or SiCN.

[0025] In some embodiments implementing BSM 230 in a Ti / Ni / Cu configuration, the Cu layer has a thickness in a range of about 600 nanometers (nm) to about 1000 nm, the Ni layer has a thickness in a range of about 100 nm to about 300 nm, and the Ti layer has a thickness in a range of about 50 nm to about 200 nm. In some embodiments, BSM 230 has a thickness in a range of about 0.6 micrometers to about 1 micrometer, such as between 0.7 micrometers to about 0.9 micrometers. In some embodiments, BSM 230 has a thermal conductivity in a range of about 300 W / mK to about 500 W / mK. In some embodiments, BSM 230 has a thermal resistance of about 0.001 mm / s. 2 C / W to about 0.003mm 2C / W. It is worth noting that the above configuration of BSM 230 is not intended to be limiting unless otherwise stated. For example, in some embodiments, BSM 230 does not include a copper layer. Instead, BSM 230 can be implemented using other layers that can serve as an adhesive layer between substrate 220 and a yet-to-be-formed BEL structure. For example, in some embodiments, BSM 230 can be implemented at least in part using a highly conductive adhesive material, such as a silver paste (e.g., silver particles mixed with an epoxy resin). In such embodiments, the manufacturing process flow can be different. Unlike a deposition->patterning->etching->plating process flow (as will be discussed in more detail below), the manufacturing process flow can involve singulating the BEL structure (to be formed in a subsequent process) before attaching the BEL structure to substrate 220.

[0026] Back to Figure 2 In the illustrated embodiment, the IC structure 200 implements the BEL 210 directly on the BSM 230. In other words, the BSM 230 is implemented directly between the substrate 220 and the BEL 210. In some embodiments, the BEL 210 and the BSM have different material compositions. It is worth noting that the configuration of the IC structure 200 does not require a thermal interface material or a metal cover structure, which is not desirable. In more detail, the BEL 210 is configured to promote effective heat dissipation. For example, when the IC structure 200 is in an operating state, the heat source 250 can be located below the substrate 220 (e.g., on a side opposite to the side of the BSM 230). In some embodiments, the heat source 250 can be a device or apparatus external to the IC structure 200 (e.g., heat generated by an IC device external to the IC structure 200). In other embodiments, the heat source 250 can correspond to an area inside the IC structure 200. For example, the heat source 250 can include a hot spot area located within the substrate 220, wherein the temperature of the hot spot area is higher than the temperature of the rest of the substrate 220. For example, substrate 220 may contain various circuits, and some circuits (or portions thereof) may generate excessive heat during their operation. As a result, these circuits may increase the temperature of the areas corresponding to these circuits in substrate 220 higher than the rest of substrate 220.

[0027] Regardless of the details of the heat source 250, the IC structure 200 herein is configured to quickly and efficiently dissipate the heat generated by the heat source 250. One reason for the quick and efficient heat dissipation is that the material composition of the BEL 210 is specifically configured to achieve such a goal. For example, the BEL 210 may include metal materials and other additives that, when the IC structure 200 is placed in a similar manner to the above reference Figure 1BEL 210 promotes the formation of vapor when immersed in the environment of the two-phase immersion cooling system 100 discussed above. That is, when IC structure 200 is immersed in an environment similar to Figure 1 When the cooling fluid 120 is in the fluid, the BEL 210 makes it similar to Figure 1 The vapor bubbles of vapor 160 are more easily formed in response to heat transferred by heat source 250. Easier formation of vapor means that heat can be transferred away from IC structure 200 (via the vapor) more quickly, which is desirable.

[0028] In addition to promoting the formation of vapor, the material composition of BEL 210 is also configured to have high conductivity. In some embodiments, BEL 210 includes a metal-containing material. For example, BEL 210 may include ceramic particles or modified metals having a porous structure. In some embodiments, BEL 210 may be a metal (such as copper) or a ceramic (such as AlN). Other candidate materials for BEL may include silver and / or gold (as metals other than copper), or SiC and / or diamond (as ceramics other than AlN). It is worth noting that for ceramic BEL 210, electroplating may not be feasible, but may require the application of singulation and then attachment process flow. Regardless of the exact material composition of BEL 210, BEL 210 can quickly and efficiently transfer heat energy. BEL 210 can also be thin enough so that its thinness also allows fast heat transfer. For example, in some embodiments, the thickness of BEL 210 can be in the range of about 10 microns to about 200 microns.

[0029] In addition, the structural configuration of the IC structure 200 also improves heat dissipation. As described above, the IC structure 200 implements the BEL 210 directly on the BSM 230, which itself is implemented directly on the substrate 220. As a result, no metal cover structure or thermal interface material is required in the IC structure 200. The thermal interface material, while thinner than the metal cover structure, can still be much thicker than the BSM 230 of the IC structure 200 herein. In addition, the thermal interface material can have a thermal resistivity that is greater than the BSM 230. The higher thermal resistivity of the thermal interface material, combined with the greater thickness, means that the thermal interface material alone may contribute more to the overall thermal resistance than the BSM 230 herein. This problem is exacerbated by the presence of the metal cover structure, which is also typically quite thick, which may also result in a relatively high overall thermal resistance.

[0030] For comparison purposes, an IC structure utilizing a thermal interface material and a metal cap structure to couple the BEL to the substrate may have a BEL at approximately 25 mm. 2 C / W to about 30mm 2C / W, wherein the majority (e.g., 75% to 85%) of the total thermal resistance is attributed to the thermal interface material and the metal lid structure, and only a small portion (e.g., 15% to 25%) of the total thermal resistance is attributed to the substrate. In contrast, the IC structure 200 herein may have a thermal resistance in the range of about 5.3 mm. 2 C / W to approximately 6.3mm 2 C / W, wherein a majority (e.g., >99%) of the total thermal resistance of the IC structure 200 is attributed to the substrate 220, and only a small portion (e.g., <1%) of the total thermal resistance of the IC structure 200 is attributed to the BSM 230 and the BEL 210. In addition, the IC structure 200 herein achieves a smaller size compared to other IC structures (e.g., because the BSM 230 has a much smaller thickness than the metal lid structure and the thermal interface material), which is also advantageous.

[0031] Reference now Figure 3 , a schematic partial cross-sectional side view of another embodiment of a portion of a structure 200 is shown. For consistency and clarity, similar components are labeled the same. Although Figure 2 The BSM 230 and the BEL 210 in the structure 200 are each implemented as a continuous structure, but Figure 3 The BSMs 230A, 230B, and 230C and the BELs 210A, 210B, and 210C in the IC structure 200 are each implemented as a plurality of discrete islands.

[0032] Figure 3 Also shown are multiple hot spot regions 270A, 270B, 270C. As described above, a hot spot region may be a region within (or outside of) substrate 220 where the temperature is higher than the temperature of the rest of substrate 220. In some cases, the temperature difference may be attributed to certain types of circuits generating more heat than other types of circuits. Regardless of what causes hot spot regions 270A, 270B, or 270C, it is desirable to be able to quickly dissipate the heat generated by these hot spot regions, or the performance and / or life of IC structure 200 may be reduced.

[0033] In order to accelerate the heat dissipation associated with the hot spot areas 270A, 270B and 270C, the present disclosure configures the IC structure 200 so that each island 210A / 230A, 210B / 230B, 210C / 230C is vertically aligned with a corresponding one of the hot spot areas. For example, the BEL island 210A and the BSM island 230A together form an island structure vertically aligned with the hot spot area 270A, the BEL island 210B and the BSM island 230B together form an island structure vertically aligned with the hot spot area 270B, and the BEL island 210C and the BSM island 230C together form an island structure vertically aligned with the hot spot area 270C. This configuration of the IC structure helps to prevent (or at least reduce) wafer warpage. It is worth noting that in some embodiments, the BEL layer 210A / 210B / 210C can also be formed on the sidewalls of the BSM layer 230A / 230B / 230C, respectively. However, for simplicity, this feature may not be included. Figure 3 (or discussed below Figure 4 ) is specifically shown in FIG.

[0034] For example, now refer to Figure 4 , Figure 4 is another schematic partial cross-sectional side view of an embodiment of a portion of structure 200 . Figure 4 2 shows wafer warpage that may occur. For example, due to a mismatch between the coefficient of thermal expansion (CTE) of the material of substrate 220 and the CTE of the material of BSM 230 (or the CTE of BEL 210), substrate 220 and BSM 230 (or BEL 210) may expand and / or contract at different rates, thereby causing warpage. For example, portion 200A and / or portion 200B of IC structure 200 may experience bowing. The bowing may manifest as a concave upper surface of BEL 210, BSM 230, and substrate 220, and / or as a convex lower surface of BEL 210, BSM 230, and substrate 220, or vice versa.

[0035] Although the IC structure 200 herein may experience some degree of warping, it will be appreciated that the island structure implementation of the BSM 230 and the BEL 210 may still provide reduced warping. This is because any warping in the IC structure 200 is localized. In other words, if the BSM 230 and the BEL 210 were formed over the entire substrate 220 rather than in an island structure, the result would be a much greater degree of warping of the substrate 220, the BSM 230, and the BEL 210, respectively. In contrast, the island structure of the BSM 230A / 230B and the BEL 210A / 210B herein means that any warping is confined to the localized portions 200A and 200B of the IC structure 200. As a result, the overall extent of warping or other structural deformation of the IC structure 200 is minimized.

[0036] Figures 5 to 10 is a series of schematic partial cross-sectional side views of an embodiment of an IC structure 200 at various stages of fabrication according to various aspects of the present disclosure. For consistency and clarity, Figures 5 to 10 and Figures 1 to 4 Similar components appearing in the drawings will be marked as identical.

[0037] refer to Figure 5 , the IC structure 200 includes a substrate 220. In an embodiment, the substrate 220 may include an element (single element) semiconductor, such as silicon. In other embodiments, the element semiconductor of the substrate 220 may include germanium and / or other suitable materials. In some other embodiments, the substrate 220 may include a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, and / or other suitable materials. In still other embodiments, the substrate 220 may include an alloy semiconductor, such as SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, and / or other suitable materials. In some embodiments, the substrate 220 may be a single layer of material with a uniform composition. Alternatively, the substrate 220 may include multiple material layers with similar or different compositions suitable for IC device manufacturing. In one example, the substrate 220 may be a silicon-on-insulator (SOI) substrate having a semiconductor silicon layer formed on a silicon oxide layer. In another example, the substrate 220 may include a conductive layer, a semiconductor layer, a dielectric layer, other layers, or a combination thereof.

[0038] Various doped regions, such as source / drain regions, may be formed in or on the substrate 220. The doped regions may be doped with n-type dopants (such as phosphorus or arsenic) and / or p-type dopants (such as boron), depending on the design requirements. The doped regions may be formed directly on the substrate 220, in a p-well structure, in an n-well structure, in a double-well structure, or using a raised structure. The doped regions may be formed by implanting dopant atoms, in-situ doping epitaxial growth, and / or other suitable techniques. The substrate 220 may also include various types of circuits that are at least partially formed in or on the substrate 220. The circuit may include a planar transistor or a three-dimensional transistor, such as a FinFET device (in which a gate structure partially surrounds an active area protruding vertically in a fin shape) or a multi-channel all-around gate (GAA) device.

[0039] Still refer to Figure 5, a back-end-of-line (BEOL) structure 310 is formed above the surface of the substrate 220 from one side 320. In some embodiments, the BEOL structure 310 may include a multi-layer interconnect (MLI) structure that provides electrical connections for various devices (e.g., transistors, resistors, capacitors, and / or inductors) and / or components (e.g., gate structures, and / or source / drain components) formed in or on the substrate 220. For example, the BEOL structure 310 may include a combination of conductive layers (e.g., metal layers, such as nickel, gold, aluminum, etc.) and dielectric layers configured to form various interconnect layers. The conductive layers are configured to form vertical interconnect components (e.g., provide vertical connections and / or vertical electrical wiring between components), such as contacts and / or vias, and / or horizontal interconnect components (e.g., provide horizontal electrical wiring), such as wires. The vertical interconnect components typically connect horizontal interconnect components in different layers (or different planes) of the BEOL structure 310. During operation, the MLI structure of the BEOL structure 310 may route electrical signals between devices and / or components of the substrate 220 and / or distribute signals (e.g., clock signals, voltage signals, and / or ground signals) to these devices and / or components. It will be appreciated that, in some embodiments, whether the BEOL structure 310 is implemented as including a single interconnect layer or as multiple interconnect layers in some other embodiments, for simplicity herein, Figure 5 The BEOL structure 310 is shown in FIG. 3 as a single layer structure.

[0040] Reference now Figure 6 , a singulation process may be performed on the IC structure 200 to divide the IC structure 200 into a plurality of smaller IC workpieces. Each IC workpiece of the IC structure 200 may still include a portion of the substrate 220 and a portion of the BEOL structure 310 formed thereon. Each IC workpiece of the IC structure 200 is then turned vertically upside down and bonded to the interposer 350. For example, the side 320 of the BEOL 310 of the IC workpiece is bonded to the interposer 350 by a plurality of microbumps 340, which in some embodiments may include a plurality of solder balls or solder bumps. In some embodiments, the interposer 350 includes an electrical interface that facilitates electrical wiring. For example, the interposer 350 may include an electrically insulating material and a plurality of conductive vias and / or conductive interconnect components embedded in the electrically insulating material and / or located on the surface of the electrically insulating material. Through the conductive vias and / or the conductive interconnect components, electrical access to the circuit of the IC workpiece (e.g., the circuit in the substrate 220) may be obtained from the outside, for example, by connecting to the side 320 of the interposer 350.

[0041] Molding material 370 is formed over interposer 350 from side 321 of the IC structure, where side 321 is opposite side 320. Molding material 370 is also formed on sides of substrate 220, sides of BEOL 310, and sides of microbumps 340. It should be understood that molding material 370 can be formed in a manner that covers surface 380 of substrate 220. In this case, a grinding process or another suitable molding material removal process can be performed to partially remove molding material 370 from side 321 until surface 380 of substrate 220 is exposed again. As a result, in a top view, the remaining molding material 370 can surround each IC workpiece (e.g., including substrate 220, BEOL 310, and microbumps 340) in a 360-degree circumference, which will be shown in FIG. Figures 11 to 13 Molding compound 370 protects the IC workpiece from corrosion, contamination, mechanical deformation, or other undesirable factors.

[0042] Reference now Figure 7 , a backside metallization (BSM) 230 is formed directly on the surface 380 of the substrate 220 from the side 321. The BSM 230 is also formed directly on the molding compound 370. As described above with reference to Figure 2 As discussed, BSM 230 may include a plurality of conductive sublayers. For example, BSM 230 may include a Ti-containing layer formed directly on surface 380 of substrate 220 (as a barrier layer), a Ni-containing layer formed directly on the surface of the Ti-containing layer (as an interface layer), and a Cu-containing layer formed directly on the surface of the Ni-containing layer (as a main conductive portion of BSM 230). In some embodiments, the formation of BSM 230 involves one or more deposition processes. For example, a corresponding physical vapor deposition (PVD) process or a corresponding chemical vapor deposition (CVD) process may be performed to form each sublayer of BSM 230.

[0043] Reference now Figure 8, a patterning process 420 is performed on the BSM 230 from the side 321. The patterning process 420 may include a photolithography process, which may include one or more pre-exposure baking processes, exposure processes, post-exposure baking processes, development processes, etc. As a result of the patterning process 420, the BSM 230 is transformed into a plurality of BSM islands 230A, 230B, and 230C. The BSM islands 230A, 230B, and 230C are separated from each other in the horizontal direction. As discussed above, the positions of the BSM islands 230A, 230B, and 230C are also configured to be vertically aligned with hot spot areas within the substrate 220 (or even outside the substrate 220), such as the hot spot areas 430A, 430B, and 430C, respectively. That is, the BSM island 230A is vertically aligned with the hot spot area 430A, the BSM island 230B is vertically aligned with the hot spot area 430B, and the BSM island 230C is vertically aligned with the hot spot area 430C. Such an alignment scheme means that the heat generated by hot spot regions 430A, 430B, and 430C can be propagated out of IC structure 200 through the shortest possible path (eg, a linear and straight path), thereby allowing for faster and more efficient heat dissipation.

[0044] Reference now Fig. 9 , a BEL formation process 450 is performed on the IC structure from the side 321 to form a plurality of BEL islands above the BSM islands 230A / 230B / 230C, respectively. For example, the BEL island 210A is formed directly on the upper surface and the side of the BSM island 230A, the BEL island 210B is formed directly on the upper surface and the side of the BSM island 230B, and the BEL island 210C is formed directly on the upper surface and the side of the BSM island 230C. In some embodiments, the BEL formation process 450 includes an electroplating process (which may be isotropic) so that the BEL islands 210A, 210B, and 210C are selectively formed directly on the upper surfaces and the side of the BSM islands 230A, 230B, and 230C, respectively, but not formed on the substrate 220 or the molding compound 370. However, since portions of the sides of the BSM islands 230A / 230B / 230C are covered by segments of the BEL islands 210A / 210B / 210C, respectively, it is understood that some small portions of the BEL islands 210A / 210B / 210C may extend onto the surface of the substrate 220 or the molding compound 270. In some other embodiments, a continuous unpatterned BSM layer 230 may be formed, and a continuous unpatterned BEL layer 210 may be formed on the continuous unpatterned BSM layer 230. Thereafter, a patterning process may be performed to define the BSM / BEL islands. In such a process flow, the BEL islands 210A / 210B / 210C may be formed only on the upper surfaces of the BSM islands 230A / 230B / 230C, and not on the sides of the BSM islands 230A / 230B / 230C.

[0045] In some embodiments, BEL islands 210A, 210B, and 210C have different material compositions than BSMs 230A, 230B, and 230C, although they may all contain metal materials. In some embodiments, BEL islands 210A, 210B, and 210C may include modified copper particles. In some embodiments, BEL islands 210A, 210B, and 210C may also include glue and / or solvent. Regardless of the specific material composition of BEL islands 210A, 210B, and 210C, it is understood that when IC structure 200 is placed on a substrate such as the above Figure 1 When in the environment of system 100, BEL islands 210A, 210B, and 210C are configured to promote the formation of steam.

[0046] Reference now Fig.10 , the interposer 350 may be singulated so that the IC workpieces of the IC structure 200 are separated from each other (although the corresponding portions of the interposer 350 are attached thereto). Each IC workpiece may then be attached to the organic substrate 500 via a plurality of bumps 510. For example, the bumps 510 may include an electrically and thermally conductive material, such as solder balls, deposited on the side 321 of the organic substrate 500. The interposer 350 of the IC workpiece may then be bonded to the organic substrate 500 via the bumps 510, for example, via a flip chip method. It will be appreciated that the IC workpieces as well as the organic substrate may also be attached to a PCB, such as Figure 1 PCB 130. However, for simplicity, Fig.10 The PCB is not shown.

[0047] Reference now Figures 11 to 13 , which shows a schematic partial top view of various embodiments of the IC structure 200. Fig.11, the IC structure 200 includes a plurality of discrete island structures aligned with a plurality of hotspot regions 430D, 430E, and 430F. For example, the island structure aligned with the hotspot region 430D includes the BEL island 210D and the BSM island 230D, another island structure aligned with the hotspot region 430E includes the BEL island 210E and the BSM island 230E, and another island structure aligned with the hotspot region 430F includes the BEL island 210F and the BSM island 230F. It is worth noting that the alignment between the hotspot regions and their corresponding BEL / BSM island structures is manifested as an overlap between them in a top view. In addition, in order to improve heat dissipation, the size (e.g., area) of the island structure is larger than the hotspot regions to which they correspond. In some embodiments, the area of ​​the island structure composed of the BEL 210D and the BSM 230D may be at least twice as large as the area of ​​the corresponding hotspot region 430D. For example, in a top view, the hotspot region 430D may be completely covered by the island structure composed of the BEL 210D and the BSM 230D. It will also be appreciated that although the shapes of the BEL islands and BSM islands are shown herein as being rectangular, other top view shapes may be implemented for them, such as circular, diamond, triangular, or any other suitable arbitrary shape.

[0048] Fig.11 Also shown is molding compound 370, which may surround all four sides of IC structure 200 (e.g., in a 360 degree manner), including hot spot regions 430D, 430E, and 430F, and corresponding island structures aligned with the hot spot regions. Fig.11 In the embodiment of FIG. 4 , in the top view, the molding compound 370 may also overlap with one of the island structures (e.g., the island structure composed of the BEL 210D and the BSM 230D). This may be due to the location of the hot spot area 430D being very close to the molding compound 370. However, this is not necessarily the case in other embodiments. For example, in Fig.12 In the illustrated embodiment, in the top view, the molding compound 370 does not overlap with the island structure composed of the BEL 210D and the BSM 230D. Instead, in the top view, the inner boundary of the molding compound 370 may form an interface with the outer boundary of the island structure composed of the BEL 210D and the BSM 230D. As another example, in Fig.13 In the illustrated embodiment, not only is there no overlap between the molding compound 370 and the island structure composed of the BEL 210D and the BSM 230D, but there may be a gap 550 between the island structure and the molding compound 370. Likewise, the location of the island structure may be flexibly configured based on the location of the hot spot area.

[0049] Fig.14An integrated circuit manufacturing system 900 according to an embodiment of the present disclosure is shown. Manufacturing system 900 includes multiple entities 902, 904, 906, 908, 910, 912, 914, 916, ..., N connected by a communication network 918. Network 918 can be a single network, or can be a variety of different networks, such as an intranet and the Internet, and can include both wired and wireless communication channels.

[0050] In an embodiment, entity 902 represents a service system for manufacturing collaboration; entity 904 represents a user, such as a product engineer who monitors a product of interest; entity 906 represents an engineer, such as a process engineer who controls a process and related recipes, or an equipment engineer who monitors or adjusts the conditions and settings of a process tool; entity 908 represents a metrology tool for IC testing and measurement; entity 910 represents a semiconductor process tool, such as a process tool that performs the various deposition processes described above; entity 912 represents a virtual metrology module associated with process tool 910; entity 914 represents an advanced process control module associated with process tool 910 and additional other process tools; and entity 916 represents a sampling module associated with process tool 910.

[0051] Each entity can interact with other entities and can provide integrated circuit manufacturing, processing control, and / or computing capabilities to other entities, and / or receive these capabilities from other entities. Each entity can also include one or more computer systems for performing calculations and implementing automation. For example, the high-level processing control module of entity 914 can include a plurality of computer hardware with coded software instructions therein. The computer hardware can include a hard drive, a flash drive, a CD-ROM, a RAM memory, a display device (e.g., a monitor), an input / output device (e.g., a mouse and a keyboard). The software instructions can be written in any suitable programming language and can be designed to implement specific tasks.

[0052] The integrated circuit manufacturing system 900 enables interaction between entities for the purpose of integrated circuit (IC) manufacturing and advanced process control of IC manufacturing. In an embodiment, the advanced process control includes adjusting the processing conditions, settings and / or recipes of a processing tool applied to the associated wafer based on the metrology results.

[0053] In another embodiment, metrology results are measured from a subset of processed wafers according to an optimal sampling rate determined based on process quality and / or product quality. In yet another embodiment, metrology results are measured from selected fields and points of the subset of processed wafers according to optimal sampling fields / points determined based on various characteristics of process quality and / or product quality.

[0054] One of the capabilities provided by the IC manufacturing system 900 can ensure collaboration and information access in areas such as design, engineering and processing, metrology, and advanced process control. Another capability provided by the IC manufacturing system 900 can integrate systems between facilities (such as between metrology tools and process tools). Such integration enables facilities to coordinate their activities. For example, integrating metrology tools and process tools can enable manufacturing information to be more effectively incorporated into manufacturing processes or APC modules, and can enable wafer data from online or field measurements using metrology tools integrated in related process tools.

[0055] Fig.15 1 is a flow chart illustrating a method 1000 according to an embodiment of the present disclosure. The method 1000 includes step 1010 of forming a metallization structure over an integrated circuit (IC) substrate from a first side.

[0056] The method 1000 includes step 1020 of performing a patterning process on the metallization structure from the first side. The metallization structure is patterned into a plurality of metallization islands by the patterning process.

[0057] The method 1000 includes step 1030 of forming a plurality of metal-containing structures respectively over the plurality of metallization islands from a first side.

[0058] The method 1000 includes coupling a second side of the IC substrate to the organic substrate at step 1040. The second side is opposite to the first side.

[0059] In some embodiments, the substrate includes a plurality of hot spot regions. In some embodiments, the patterning process is performed so that each metallized island is aligned with a corresponding one of the hot spot regions. In some embodiments, in a top view, the area of ​​each metallized island is greater than the area of ​​the hot spot region aligned therewith.

[0060] In some embodiments, the forming of the plurality of metal-containing structures is performed such that the plurality of metal-containing structures are selectively formed on surfaces of the metallization islands and not formed on a surface of the IC substrate.

[0061] In some embodiments, forming the plurality of metal-containing structures includes an electroplating process.

[0062] In some embodiments, forming a metallization structure includes: forming a titanium-containing layer over a first side of a substrate as a first sublayer of the metallization structure; forming a nickel-containing layer over the titanium-containing layer as a second sublayer of the metallization structure; and forming a copper-containing layer over the nickel-containing layer as a third sublayer of the metallization structure.

[0063] In some embodiments, the metallization structure and the metal-containing structure have different material compositions.

[0064] It is understood that additional processes may be performed before, during, or after steps 1010-1040 of method 1000. For example, method 1000 may include the step of performing a cooling process in which the IC substrate is immersed in a cooling fluid. The heat generated by the IC substrate is dissipated by the vapor formed by the cooling fluid. The metal-containing structure promotes the formation of the vapor. As another example, method 1000 may also include the following steps performed before forming the metallization structure: singulating a wafer containing an IC substrate into a plurality of IC devices; after singulation, coupling the second side of the IC substrate of each IC device to an interposer; forming a molding compound structure above the first side of the interposer and above the first side of the IC substrate of each IC device; and grinding the molding compound from the first side until the surface of the IC substrate of each IC device is exposed to the first side. In some embodiments, the metallization structure is formed above the first side of the molding compound structure and above the surface of the IC substrate. In some embodiments, at least a subset of the metal-containing structures are formed to overlap vertically with the molding compound structure. For simplicity, other additional steps are not discussed in detail herein.

[0065] In summary, the present disclosure relates to coupling a BEL to an IC structure via a BSM such that the BSM (which may include multiple metal-containing sublayers) is directly between the BEL and the substrate of the IC structure. The BEL and the BSM are also configured as multiple discrete island structures that are aligned with multiple hot spot areas, respectively. By doing so, the present disclosure provides advantages over other IC structures. However, it is understood that other embodiments may provide additional advantages, and not all advantages are necessarily disclosed herein, and no particular advantage is required by all embodiments. One advantage is improved device performance. In more detail, the BEL is formed to facilitate the above reference Figure 1 The formation of steam in the two-phase cooling system discussed above can help to quickly dissipate the heat generated by the IC structure. However, some IC structures may require a thermal interface material and a metal cover structure to couple the BEL to the substrate of the IC structure. The thermal interface material and the metal cover structure may be thick and / or have a high thermal resistivity, which may excessively increase the overall thermal resistance of the IC structure. In contrast, implementing the BEL directly on the substrate via the BSM means that the thermal interface material and the metal cover structure are no longer required. The BSM in this article is much thinner than the thermal interface material and the metal cover structure and has a lower thermal resistivity. As a result, the IC structure can have a lower overall thermal resistance, which allows for faster cooling.

[0066] The alignment scheme between the hot spot area and the BEL / BSM island structure also promotes better heat dissipation. In more detail, the IC structure may include one or more IC dies containing circuits, wherein the heat generated by some circuits may cause the temperature of the hot spot area to rise compared to the rest of the IC structure. If the heat cannot be dissipated quickly, it may cause the device performance to deteriorate and / or the life of the IC structure to be shortened. Here, the island (composed of BSM and BEL) can be vertically aligned with the hot spot area. In this way, a short path can be established between the hot spot area and the island structure, and the heat can be quickly dissipated. Therefore, the IC structure can be operated in a colder environment as a whole, which improves the device performance (e.g., faster speed or lower power consumption). Another advantage is that the life of the IC structure is longer. In this regard, when the IC structure is operated for a long time in a high temperature environment, the life it has may be shortened. Here, fast and effective heat dissipation (possibly achieved by aligning the BSM / BEL island structure with the hot spot area) can help prevent or at least reduce the operation of the IC structure in a high temperature environment. Accordingly, the life of the IC structure of the present disclosure can be extended. Other advantages include compatibility with existing manufacturing and / or packaging processes, so the present disclosure does not require additional processing and is therefore easy and inexpensive to implement.

[0067] One aspect of the present disclosure relates to a method. A metallization structure is formed over an integrated circuit (IC) substrate from a first side. A patterning process is performed on the metallization structure from the first side. The metallization structure is patterned into a plurality of metallization islands by the patterning process. A plurality of metal-containing structures are formed over the plurality of metallization islands from the first side, respectively. A second side of the IC substrate is coupled to an organic substrate. The second side is opposite to the first side. In some embodiments, the method further comprises performing a cooling process, in which the IC substrate is immersed in a cooling fluid; wherein: heat generated by the IC substrate is dissipated by vapor formed by the cooling fluid; and the metal-containing structure promotes the formation of the vapor. In some embodiments, the IC substrate includes a plurality of hot spot regions; and the patterning process is performed so that each metallization island is aligned with a corresponding one of the hot spot regions. In some embodiments, in a top view, an area of ​​each metallization island is greater than an area of ​​the hot spot region aligned therewith. In some embodiments, the formation of a plurality of metal-containing structures is performed so that a plurality of metal-containing structures are selectively formed on a surface of the metallization island but not on a surface of the IC substrate. In some embodiments, the formation of the plurality of metal-containing structures comprises an electroplating process. In some embodiments, forming the metallization structure includes: forming a titanium-containing layer as a first sublayer of the metallization structure over a first side of the substrate; forming a nickel-containing layer as a second sublayer of the metallization structure over the titanium-containing layer; and forming a copper-containing layer as a third sublayer of the metallization structure over the nickel-containing layer. In some embodiments, the metallization structure and the metal-containing structure have different material compositions. In some embodiments, the method further includes, before forming the metallization structure: singulating a wafer containing an IC substrate into a plurality of IC devices; after singulation, coupling a second side of the IC substrate of each IC device to an interposer; forming a molding compound structure over a first side of the interposer and over a first side of the IC substrate of each IC device; and grinding the molding compound structure from the first side until a surface of the IC substrate of each IC device is exposed to the first side; wherein the metallization structure is formed over the first side of the molding compound structure and over a surface of the IC substrate. In some embodiments, at least a subset of the metal-containing structures are formed to vertically overlap the molding compound structure.

[0068] Another aspect of the present disclosure relates to a device. The device includes: a substrate containing a circuit. The device includes a plurality of metallization structures, which are directly disposed on the substrate in a cross-sectional side view. The device includes a plurality of metal-containing structures, which are respectively directly disposed on the plurality of metallization structures in a cross-sectional side view. The metallization structures and the metal-containing structures have different material compositions. The circuit includes a plurality of hot spots distributed in different locations of the substrate. In the cross-sectional side view, each metal-containing structure is vertically aligned with a corresponding one of the hot spots. In some embodiments, in a top view, the metal-containing structure is not in direct contact with any other metal-containing structure of the metal-containing structure. In some embodiments, in a top view, each hot spot region is surrounded by a corresponding one of the metal-containing structures. In some embodiments, when the device is in electrical operation, each hot spot region has an increased temperature compared to the rest of the substrate. In some embodiments, the device also includes a molding compound structure, which surrounds at least a portion of the substrate in a top view, wherein, in a top view, at least a subset of the metal-containing structures overlaps the molding compound structure. In some embodiments, the device also includes a molding compound structure, which completely surrounds the plurality of metal-containing structures in a top view. In some embodiments, the metallization structures each include: a titanium-containing layer disposed directly on the substrate; a nickel-containing layer disposed directly on the titanium-containing layer; and a copper-containing layer disposed directly on the nickel-containing layer.

[0069] Another aspect of the present disclosure relates to a system. The system includes a chamber. The system cools a fluid that partially fills the chamber. The system includes a condenser. The system includes a plurality of printed circuit boards (PCBs) immersed in the cooling fluid. The system includes a plurality of integrated circuit (IC) devices located on each PCB. Each IC device includes a substrate, a plurality of metallized islands disposed directly on the substrate, and a plurality of metal-containing islands disposed directly on the metallized islands, respectively. The metallized islands drive the cooling fluid to transform into steam in response to heat generated by the IC devices. The steam transforms back into the cooling fluid after contacting the condenser. In some embodiments, each of the IC devices includes a plurality of hot spot regions; and the metallized islands and the corresponding metal-containing islands disposed thereon are aligned with the hot spot regions, respectively. In some embodiments, the metallized islands and the metal-containing islands have different material compositions.

[0070] Some embodiments of the present application provide a method, comprising: forming a metallization structure over an integrated circuit substrate from a first side; performing a patterning process on the metallization structure from the first side, wherein the metallization structure is patterned into a plurality of metallization islands by the patterning process; forming a plurality of metal-containing structures over the plurality of metallization islands from the first side, respectively; and coupling a second side of the integrated circuit substrate to an organic substrate, wherein the second side is opposite to the first side. In some embodiments, the method further comprises performing a cooling process, wherein the integrated circuit substrate is immersed in a cooling fluid; wherein: the heat generated by the integrated circuit substrate is dissipated by vapor formed by the cooling fluid; and the metal-containing structure promotes the formation of the vapor. In some embodiments, the integrated circuit substrate includes a plurality of hot spot regions; and the patterning process is performed so that each of the metallization islands is aligned with a corresponding one of the hot spot regions. In some embodiments, in a top view, the area of ​​each of the metallization islands is greater than the area of ​​the hot spot region aligned therewith. In some embodiments, the formation of the plurality of metal-containing structures is performed so that the plurality of metal-containing structures are selectively formed on the surface of the metallization islands but not on the surface of the integrated circuit substrate. In some embodiments, forming the plurality of metal-containing structures comprises an electroplating process. In some embodiments, forming the metallization structure comprises: forming a titanium-containing layer as a first sublayer of the metallization structure over the first side of the substrate; forming a nickel-containing layer as a second sublayer of the metallization structure over the titanium-containing layer; and forming a copper-containing layer as a third sublayer of the metallization structure over the nickel-containing layer. In some embodiments, the metallization structure and the metal-containing structure have different material compositions. In some embodiments, the method further comprises, before forming the metallization structure: singulating a wafer containing the integrated circuit substrate into a plurality of integrated circuit devices; coupling the second side of the integrated circuit substrate of each of the integrated circuit devices to an interposer after the singulation; forming a molding compound structure over the first side of the interposer and over the first side of the integrated circuit substrate of each of the integrated circuit devices; and grinding the molding compound structure from the first side until a surface of the integrated circuit substrate of each of the integrated circuit devices is exposed to the first side; wherein the metallization structure is formed over the first side of the molding compound structure and over the surface of the integrated circuit substrate. In some embodiments, at least a subset of the metal-containing structures are formed to vertically overlap the molding compound structure.

[0071] Some other embodiments of the present application provide a device, comprising: a substrate, including a circuit; a plurality of metallization structures, in a cross-sectional side view, directly disposed on the substrate; and a plurality of metal-containing structures, in the cross-sectional side view, respectively disposed directly on the plurality of metallization structures; wherein: the metallization structures and the metal-containing structures have different material compositions; the circuit comprises a plurality of hot spots distributed in different locations of the substrate; and in the cross-sectional side view, each of the metal-containing structures is vertically aligned with a corresponding one of the hot spots. In some embodiments, in a top view, the metal-containing structure is not in direct contact with any other metal-containing structure of the metal-containing structure. In some embodiments, in a top view, each of the hot spots is surrounded by a corresponding one of the metal-containing structures. In some embodiments, when the semiconductor device is in electrical operation, each of the hot spots has an elevated temperature compared to the rest of the substrate. In some embodiments, the semiconductor device further comprises a molding compound structure, in a top view, the molding compound structure surrounds at least a portion of the substrate, wherein, in the top view, at least a subset of the metal-containing structures overlap the molding compound structure. In some embodiments, the semiconductor device further comprises a molding compound structure, in a top view, the molding compound structure completely surrounds the plurality of metal-containing structures. In some embodiments, the metallization structures each include: a titanium-containing layer disposed directly on the substrate; a nickel-containing layer disposed directly on the titanium-containing layer; and a copper-containing layer disposed directly on the nickel-containing layer.

[0072] Still other embodiments of the present application provide a system comprising: a chamber; a cooling fluid partially filling the chamber; a condenser; a plurality of printed circuit boards immersed in the cooling fluid; and a plurality of integrated circuit devices located on each of the printed circuit boards; wherein: each of the integrated circuit devices comprises a substrate, a plurality of metallized islands directly disposed on the substrate, and a plurality of metal-containing islands directly disposed on the metallized islands; the metallized islands drive the cooling fluid into vapor in response to heat generated by the integrated circuit devices; and the vapor is converted back into the cooling fluid after contacting the condenser.

[0073] In some embodiments, the integrated circuit devices each include a plurality of hot spot regions; and the metallized islands and the corresponding metal-containing islands disposed thereon are aligned with the hot spot regions, respectively. In some embodiments, the metallized islands and the metal-containing islands have different material compositions.

[0074] The features of several embodiments are summarized above so that those skilled in the art can better understand the detailed description below. Those skilled in the art should understand that they can easily use this disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: forming a metallization structure over the integrated circuit substrate from a first side; performing a patterning process on the metallization structure from the first side, wherein the metallization structure is patterned into a plurality of metallization islands by the patterning process; forming a plurality of metal-containing structures respectively over the plurality of metallization islands from the first side; and A second side of the integrated circuit substrate is coupled to an organic substrate, wherein the second side is opposite to the first side.

2. The method according to claim 1, further comprising performing a cooling process, in which the integrated circuit substrate is immersed in a cooling fluid; in: heat generated by the integrated circuit substrate is dissipated by vapor formed by the cooling fluid; and The metal-containing structure facilitates the formation of the vapor.

3. The method according to claim 1, wherein: The integrated circuit substrate includes a plurality of hot spot regions; and The patterning process is performed such that each of the metallization islands is aligned with a corresponding one of the hot spot regions.

4. The method according to claim 3, wherein: In a top view, the area of ​​each of the metallized islands is larger than the area of ​​the hot spot region aligned therewith.

5. The method according to claim 1, wherein: The forming of the plurality of metal-containing structures is performed such that the plurality of metal-containing structures are selectively formed on surfaces of the metallization islands but not on a surface of the integrated circuit substrate.

6. The method according to claim 1, wherein: Forming the plurality of metal-containing structures includes an electroplating process.

7. The method according to claim 1, wherein: Forming the metallization structure includes: forming a titanium-containing layer as a first sublayer of the metallization structure over the first side of the substrate; forming a nickel-containing layer as a second sublayer of the metallization structure over the titanium-containing layer; and A copper-containing layer is formed over the nickel-containing layer as a third sublayer of the metallization structure.

8. The method according to claim 1, wherein: The metallization structure and the metal-containing structure have different material compositions.

9. A semiconductor device comprising: a substrate, containing the circuit; a plurality of metallization structures disposed directly on the substrate in a cross-sectional side view; as well as a plurality of metal-containing structures, respectively disposed directly on the plurality of metallization structures in the cross-sectional side view; in: The metallized structure and the metal-containing structure have different material compositions; The circuit includes a plurality of hot spots distributed in different locations of the substrate; as well as In the cross-sectional side view, each of the metal-containing structures is vertically aligned with a corresponding one of the hot spot regions.

10. A cooling system comprising: Chamber; a cooling fluid partially filling the chamber; Condenser; a plurality of printed circuit boards immersed in the cooling fluid; as well as a plurality of integrated circuit devices located on each of said printed circuit boards; in: Each of the integrated circuit devices comprises a substrate, a plurality of metallized islands disposed directly on the substrate, and a plurality of metal-containing islands disposed directly on the metallized islands; The metallized islands promote the transformation of the cooling fluid into vapor in response to heat generated by the integrated circuit device; and The vapor is converted back into the cooling fluid after contacting the condenser.

Images