Semiconductor device and forming method thereof

Abstract

In an embodiment, a method includes attaching a die to an interposer; attaching and electrically coupling an interposer to the package substrate; attaching a package cap and a first thermal interface material to the die and the package substrate; attaching and electrically coupling a package substrate to the component substrate; and attaching a heat sink and a second thermal interface material to the package cover using a screw extending between the heat sink and the component substrate, the heat sink including a first sensing module in physical contact with the second thermal interface material. The embodiment of the invention also relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor devices and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement of the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density comes from the repeated reduction of the minimum component size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, there is a demand for packaging technologies for smaller and more innovative semiconductor dies. An example of such a packaging system is a three-dimensional stacked package (PoP) technology. In a PoP device, a top semiconductor package is stacked on top of a bottom semiconductor package to provide a high level of integration and component density. PoP technology is generally capable of producing semiconductor devices with enhanced functionality and a small footprint on a printed circuit board (PCB). Summary of the invention

[0003] An embodiment of the present disclosure provides a method for forming a semiconductor device, comprising: attaching a die to an interposer; attaching and electrically coupling the interposer to a packaging substrate; attaching a packaging cover and a first thermal interface material to the die and the packaging substrate; attaching and electrically coupling the packaging substrate to a component substrate; and attaching a heat sink and a second thermal interface material to the packaging cover using screws, the screws extending between the heat sink and the component substrate, the heat sink including a first sensing module in physical contact with the second thermal interface material.

[0004] Another embodiment of the present disclosure provides a semiconductor device, comprising: a printed circuit board; a semiconductor package disposed on the printed circuit board; a heat sink disposed on the semiconductor package; a first thermal interface material disposed between the semiconductor package and the heat sink; and a first sensor disposed between the semiconductor package and the heat sink.

[0005] Another embodiment of the present disclosure provides a semiconductor device, comprising: a semiconductor package, comprising: a packaging substrate; and a packaging component attached and electrically connected to the packaging substrate; a first thermal interface material, disposed above the packaging component and physically contacting the packaging component; a packaging cover, disposed above the first thermal interface material, the packaging cover comprising: a thermally conductive ring attached to the packaging substrate; and a covering portion, physically contacting the first thermal interface material; a heat sink, disposed above the packaging cover, the heat sink comprising a first pressure sensor; and a component substrate, disposed below the packaging substrate and electrically connected to the packaging substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the dimensions of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0007] Figures 1 to 3F Cross-sectional and plan views illustrate intermediate steps in the formation of semiconductor devices according to various embodiments.

[0008] FIG. 4A to FIG. 4C Cross-sectional views and plan views of semiconductor devices according to various embodiments are shown.

[0009] Figure 5 A cross-sectional view of a semiconductor device according to various embodiments is shown.

[0010] Fig. 6A and Figure 6B Cross-sectional views and plan views of semiconductor devices according to various embodiments are shown.

[0011] Fig. 7A and Figure 7B Cross-sectional views and plan views of semiconductor devices according to various embodiments are shown.

[0012] Fig. 8A and Figure 8B Cross-sectional views and plan views of semiconductor devices according to various embodiments are shown.

[0013] 9A to 9C Cross-sectional views and plan views of semiconductor devices according to various embodiments are shown.

[0014] FIG. 10A to FIG. 10D An exemplary sensing module according to various embodiments is shown. DETAILED DESCRIPTION

[0015] The following disclosure provides many different embodiments or examples for implementing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the embodiments and / or configurations discussed.

[0016] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0017] Three-dimensional integrated circuits (3D-ICs) offer many solutions to reduce the physical size of packaged assemblies and allow a greater number of components to be placed in a given chip area. One solution provided by 3D-IC assemblies is to stack dies on top of each other and interconnect or route them through connectors such as through silicon vias (TSVs). For example, some benefits of 3D-ICs include exhibiting a smaller footprint, reducing power consumption by reducing the length of signal interconnects, and improving yield and manufacturing costs if individual dies are tested individually before assembly. One challenge with 3D-IC assemblies is dealing with heat dissipation and managing hot spots during operation.

[0018] Embodiments described herein relate to semiconductor devices (e.g., semiconductor systems) that include a heat sink disposed above a semiconductor package, such as a chip on wafer on substrate (CoWoS) application or a system on integrated chip (SoIC) application and a method for manufacturing the same. However, other suitable types of semiconductor packages may be incorporated into embodiments of semiconductor systems. In an embodiment, a sensing module is integrated into a heat sink, a package cover, and / or elsewhere in a semiconductor device. The sensing module may be configured to measure one or more properties (e.g., pressure, displacement, stress, etc.) during a formation process (such as installation of a heat sink). The measured values ​​(e.g., key performance indicators (KPIs)) may be monitored to make real-time adjustments to components of the semiconductor system. For example, real-time adjustments prevent pumping out (e.g., extrusion or offset) of thermal interface materials disposed between components, while also preventing cracks from forming and propagating near high-performance die (e.g., central processing units and graphics processing units). Semiconductor systems can be manufactured with higher yields and functionality, with improved performance, reliability, stability, and life.

[0019] Figure 1A semiconductor package 100 (e.g., a CoWoS device or a SoIC device) is shown, and the semiconductor package 100 includes a package assembly 101 (e.g., a CoW device) bonded to a package substrate 103. The package assembly 101 includes a chip module 105 (e.g., a 3D-IC module) attached to an interposer 107. The package assembly 101 may be referred to herein as an interposer package, a semiconductor chip package, a stacked chip package, a stacked semiconductor device package, a stacked device package, etc. According to some embodiments, the package assembly 101 may include one or more first semiconductor dies 115 disposed on the interposer 107 and adjacent to one or more second semiconductor dies 117.

[0020] Each first semiconductor die 115 and each second semiconductor die 117 can be a single die or a die stack and can be referred to as a chip. The first semiconductor die 115 can be a processor, such as a system on a chip (SoC), a central processing unit (CPU), a graphics processing unit (GPU), etc. The second semiconductor die 117 can be a memory die, such as a DRAM, a high bandwidth memory (HBM), a memory cube, a memory stack, etc. Although the cross-section shown shows the package assembly 101 as having one first semiconductor die 115 and two second semiconductor dies 117, other embodiments may include any number of semiconductor dies 115 / 117. The chip module 105 may include semiconductor stacked dies, such as memory, flash memory, converters, sensors, logic dies, etc.

[0021] In some embodiments, the interposer 107 can be formed of various semiconductor substrate materials, such as silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc. A combination of active and / or passive devices (such as transistors, diodes, resistors, capacitors, etc.) can be formed as part of the interposer 107 to build a functional circuit. In addition, the interposer 107 can include a series of alternating conductive material layers (such as copper, aluminum, alloys, doped polysilicon, combinations thereof, etc.) that can be used between dielectric material layers to form interconnects between active and passive devices and also provide access to external connectors 109 (e.g., external connectors of a 3D-IC module). As shown, the external connectors 109 can include solder areas formed on under-bump metallization (UBM).

[0022] Although interposer 107 is shown as a redistribution structure, it should be understood that interposer 107 can be a silicon interposer, a local silicon interconnect (LSI) die, or a bottom die with bonding features on opposite sides. In addition, although chip module 105 and package substrate 103 are described as being attached through external connectors 109, which can be solder areas, in some embodiments, the attachment process can be a direct bonding process to form dielectric-to-dielectric bonds and metal-to-metal bonds.

[0023] According to some embodiments, the chip module 105 may include a plurality of high-performance integrated circuit dies (e.g., semiconductor dies), such as may be used to process 3D smart Internet TV graphics or other processing-intensive applications. For example, the first semiconductor die 115 may include a 3D-IC processor 115 (e.g., a CPU, a graphics processing unit (GPU)), and the second semiconductor die 117 may include a 3D-IC memory die 117 (e.g., a high bandwidth memory (HBM), a memory cube, a memory stack, etc.).

[0024] The semiconductor die 115 / 117 can be bonded to the interposer 107 via a plurality of surface side contacts 121. In an embodiment, the surface side contacts 121 can be microbumps. An underfill material 122 (e.g., epoxy) can be formed between the semiconductor die 115 / 117 and the interposer 107 and around the surface side contacts 121. In some embodiments, the underfill material 122 can diffuse upward toward the upper surface between adjacent semiconductor dies 115 / 117 by a capillary effect. After attaching the semiconductor die 115 / 117, an encapsulant 125 (e.g., a molding compound) can be formed above, around, and between the semiconductor die 115 / 117. The package assembly 101 can be singulated from the wafer by, for example, sawing through the interposer 107 and the encapsulant 125 to form discrete package assemblies 101.

[0025] After singulation, the interposer 107 of the package component 101 can be bonded to the package substrate 103 using external connectors 109 (e.g., solder balls). The external connectors 109 provide electrical and thermal connections between the package component 101 and the package substrate 103. Note that other methods of electrically and physically attaching the package component 101 to the package substrate 103 can be utilized, such as C4 bumps, microbumps, pillars, columns, or other structures formed of conductive materials (such as solder, metals, or metal alloys). An underfill material 110 (e.g., epoxy) can be applied between the package substrate 103 and the package component 101 (e.g., between and around the external connectors 109).

[0026] In an embodiment, the packaging substrate 103 may be a mother substrate and may include a first semiconductor die, such as a logic die / interposer including a plurality of structures, such as a substrate formed of various semiconductor substrate materials, such as silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), etc. A combination of active and / or passive devices, such as transistors, diodes, resistors, capacitors, etc., may be formed as part of the packaging substrate 103 to build functional circuits. In addition, alternating layers of conductive materials, such as copper, aluminum, alloys, doped polysilicon, combinations thereof, etc., may be utilized between the dielectric material layers to form interconnects between the active and passive devices and also provide access to external connections of the packaging substrate 103. Through substrate vias (TSVs) may also be formed to provide electrical connections from one side of the packaging substrate 103 to the other side of the packaging substrate 103. According to some embodiments, the packaging substrate 103 is a printed circuit board (PCB) or a silicon interposer.

[0027] As shown, the package substrate 103 may include external connectors 124, which may be, for example, solder balls, for subsequent bonding to another substrate. The external connectors 124 of the package substrate 103 may provide electrical and thermal connections between the package substrate 103 and the substrate (to which the package substrate 103 is subsequently bonded). However, other methods of electrically and physically attaching the package substrate 103 to another substrate may be utilized, such as C4 bumps, microbumps, columns, pillars, or other structures formed of conductive materials (such as solder, metals, or metal alloys) to facilitate electrical, physical, and thermal connections between the package substrate 103 and the substrate (to which the package substrate 103 is subsequently bonded).

[0028] Figure 2 The formation of a packaging arrangement 200 according to various embodiments is shown. The packaging arrangement 200 may include a thermal interface material (TIM), such as a thermal interface adhesive 111 and a first thermal interface material 113, and a packaging cover 131 attached to the semiconductor package 100. For example, the thermal interface adhesive 111 is applied to the top surface of the packaging substrate 103, the first thermal interface material (TIM) 113 is applied to the top surface of the chip module 105, and the packaging cover 131 is applied to the packaging substrate 103 and the chip module 105 using the thermal interface adhesive 111 and the first thermal interface material 113, respectively.

[0029] In an embodiment, the thermal interface adhesive 111 may be a viscous silicone compound with mechanical properties similar to grease or gel. The thermal interface adhesive 111 is used to improve electrical and / or thermal conduction by filling tiny air pockets generated between tiny uneven surfaces (such as the area between the surface of the package substrate 103 and the material above); the thermal interface adhesive 111 may also have a thermal conductivity (i.e., "k value") in Watts per meter-Kelvin (W / mK) between about 1 W / mK and about 10 W / mK (e.g., such as about 4 W / mK).

[0030] In some embodiments, the thermal interface adhesive 111 is a metal-based thermal paste containing silver, nickel or aluminum particles suspended in silicone grease. In other embodiments, a non-conductive ceramic-based paste filled with ceramic powder (such as beryllium oxide, aluminum nitride, aluminum oxide or zinc oxide) can be applied. In other embodiments, the thermal interface adhesive 111 can be a solid material, rather than a paste with a consistency similar to gel or grease. In this embodiment, the thermal interface adhesive 111 can be a thin sheet of a thermally conductive solid material. In a specific embodiment, the solid thermal interface adhesive 111 can be a thin sheet of indium, nickel, silver, aluminum, a combination of these and an alloy, etc., or other thermally conductive solid materials. Any suitable thermally conductive material can also be utilized, and all such materials are fully intended to be included in the scope of the embodiment. The thermal interface adhesive 111 is injected or placed on the package substrate 103, around the chip module 105 but laterally separated from the chip module 105.

[0031] A first thermal interface material 113 may be applied to the chip module 105 to provide a thermal interface between the chip module 105 and the upper package cover 131. In an embodiment, the first thermal interface material 113 may be similar to the thermal interface adhesive 111 and may be applied simultaneously with the thermal interface adhesive 111, but the first thermal interface material 113 may also be different from the thermal interface adhesive 111.

[0032] In an embodiment, the first thermal interface material 113 may be applied in a solid, grease, or gel consistency, or may be applied as a film-type TIM, such as a carbon nanotube-based (CNT) or graphite-based TIM. According to some embodiments, the first thermal interface material 113 may have a thermal conductivity (i.e., a "k value") in Watts per meter-Kelvin (W / mK) between about 1 W / mK and about 30 W / mK (e.g., such as about 4 W / mK). However, any suitable thermal conductivity value may be used. In some embodiments, the first thermal interface material 113 may have a footprint that is substantially the same as or greater than the area of ​​the upper surface of the chip module 105.

[0033] Still refer to Figure 2, attaching a package cover 131 (e.g., a thermally conductive ring and a cover portion), wherein a thermally conductive ring 127 (e.g., a conductive ring) of the package cover 131 is attached to the thermal interface adhesive 111. As shown, both the thermal interface adhesive 111 and the thermally conductive ring 127 can be laterally spaced apart from the package component 101, and surround the package component 101, forming a cavity or gap within the inner wall of the thermally conductive ring 127. In an embodiment, the lateral spacing between the thermally conductive ring 127 and the package component 101 can be substantially equidistant around each side of the package component 101. In other embodiments, the lateral spacing between the thermally conductive ring 127 and the package component 101 can be different around each side of the package component 101. In an embodiment, the thermally conductive ring 127 is used to provide a thermal path from the thermal interface adhesive 111 to the rest of the package cover 131.

[0034] In an embodiment, the thermally conductive ring 127 may include a thermally conductive material, such as a material having a thermal conductivity (i.e., a "k value") greater than about 1 W / mK in Watts per meter-Kelvin (W / mK), such as a thermal conductivity between about 10 W / mK and about 400 W / mK, such as about 380 W / mK. However, any suitable thermal conductivity may be used. In a particular embodiment, the thermally conductive ring 127 may include a metal such as copper, but any other suitable metal such as aluminum may also be used. Similarly, dielectric materials such as silicones may also be utilized as long as they are suitable for transferring heat from the package substrate 103 to the package cover 131.

[0035] In some embodiments, the thermally conductive ring 127 may be a different component than the package lid 131. Furthermore, the thermally conductive ring 127 and the thermal interface adhesive 111 may be placed on the package substrate 103 before attaching the package assembly 101 (e.g., the interposer 107 and the chip module 105) to the package substrate 103. In some such embodiments, the thermal interface adhesive 111 may serve as a flow barrier for the bottom fill material 110 of the subsequently formed interposer 107. Additionally, the package lid 131 may be attached to the thermally conductive ring 127 using another thermal interface adhesive (not specifically shown), which may be applied similarly to that described in conjunction with the thermal interface adhesive 111.

[0036] In another embodiment, rather than having a single thermally conductive ring 127 surrounding the package assembly 101 on the package substrate 103, multiple thermally conductive rings 127 may be used. In this embodiment, multiple thermally conductive rings 127 are placed on the thermal interface adhesive 111, for example, one ring is located within (e.g., concentrically with) another thermally conductive ring 127. By using multiple thermally conductive rings 127 rather than a single thermally conductive ring, additional support may be provided.

[0037] In an embodiment, a heat treatment may be performed where the thermal interface adhesive 111 is in a liquid or semi-solid form to cure the thermal interface adhesive 111 so that the thermal interface adhesive 111 becomes solid. The heat treatment may be performed by placing the thermal interface adhesive 111 in, for example, a furnace and heating the thermal interface adhesive 111. However, curing is not intended to be limited thereto. Instead, any suitable method for curing the thermal interface adhesive 111 may be utilized, such as irradiating the thermal interface adhesive 111 or even allowing the thermal interface adhesive 111 to cure at room temperature. All suitable methods for curing the thermal interface adhesive 111 are fully intended to be included within the scope of the embodiment.

[0038] As mentioned above, Figure 2 Also shown is the placement of a package cover 131 over the package substrate 103, the chip module 105 (e.g., the package assembly 101), and the thermally conductive ring 127 (if different from the package cover 131). In an embodiment, the package cover 131 is deployed to protect the package substrate 103, the package assembly 101, and any underlying substrates, and also to help spread the heat generated by the package substrate 103 and the package assembly 101 to a larger area, particularly for high power applications, such as 3D-IC packaging applications (e.g., SoIC and / or Chip on Wafer on Substrate (CoWoS)).

[0039] In some embodiments, the package cover 131 may include copper, aluminum, other metals, alloys, combinations thereof, or other materials with high electrical and thermal conductivity. According to some embodiments, the package cover 131 may have a thermal conductivity (i.e., a "k value") in Watts per meter-Kelvin (W / mK), for example, between about 10,000 W / mK and about 20,000 W / mK in a first heat diffusion direction (e.g., parallel to a major surface of the package cover 131), and a thermal conductivity in a second heat diffusion direction (e.g., through the depth of the package cover 131), for example, between about 200 W / mK and about 7,000 W / mK. However, any suitable thermal conductivity value may be used.

[0040] The package cover 131 includes a material having high thermal conductivity and a low coefficient of thermal expansion (CTE). According to an embodiment, the package cover 131 includes a material such as copper, a copper alloy, copper tungsten (CuW), or aluminum silicon carbide (AlSiC). Other suitable thermally conductive materials and / or thermally insulating materials may also be used. In an embodiment, the package cover 131 has a low coefficient of thermal expansion that is substantially similar to the low coefficient of thermal expansion of the package substrate 103.

[0041] exist FIG. 3A to FIG. 3F, a system-in-package assembly 300A is formed by mounting a heat sink 201 and a component substrate 203 to a packaging arrangement 200 (e.g., a semiconductor package 100 and a packaging cover 131). In an embodiment, the heat sink 201 can be mounted above the packaging cover 131 and thermally coupled to the packaging cover 131, thereby indirectly thermally coupling to the chip module 105 and the packaging substrate 103 of the packaging arrangement 200. In addition, the packaging arrangement 200 can be attached to a component substrate 203 (e.g., a printed circuit board (PCB)), wherein the back plate 205 is attached to the component substrate 203. A plurality of screws 207 can be used to secure the heat sink 201 to the component substrate 203 and the back plate 205, but any suitable mechanism can be used. In addition, a spring 209 embedded in the heat sink 201 and around the screw 207 can support the head of the screw 207. Thus, the spring 209 introduces flexibility between the screw 207 and the heat sink 201, while also contributing to stability and rigidity.

[0042] In various embodiments, the package substrate 103 is electrically coupled and physically coupled to the component substrate 203 on one side of the package substrate 103 opposite to the package assembly 101. The component substrate 203 provides a structural basis and an electrical interface from the package substrate 103 and / or the package assembly 101 to other devices and systems. For example, the component substrate 203 can be used to interconnect various electronic components to each other so as to provide the desired functions to the user. In some embodiments (not specifically shown), the component substrate 203 can be bonded to other electronic components, such as resistors, capacitors, signal distribution circuits, combinations of these, etc. These electronic components can be active, passive, or a combination thereof. In other embodiments, the component substrate 203 can be a non-electrical substrate that does not contain active and passive electronic components (or is electrically isolated from active and passive electronic components). All such combinations are fully intended to be included within the scope of the embodiments.

[0043] The heat sink 201 can be formed using materials that exhibit high thermal conductivity, such as aluminum, copper, other metals, alloys, combinations thereof, and the like, and helps cool the package substrate 103 and the package assembly 101 by increasing the given surface area exposed to the coolant (such as air or liquid) around it. The heat transfer mechanism is through convection of the surrounding air, conduction in the air, and radiation. For example, the heat sink 201 can exhibit a larger surface area for convection than the surface area of ​​the package cover 131, the package substrate 103, and the package assembly 101. In some embodiments, the heat sink 201 can achieve this by adopting a large number of fins in the form of a matrix of geometrically shaped pins or an array of straight or flared fins. In another example, such as where convection is low, a matte black surface color can radiate more effectively than a shiny metallic color in the visible spectrum. Any suitable form of heat sink can be utilized.

[0044] As described above, the heat sink 201 of the packaged system assembly 300A can be an air cooling system with certain additional components described herein but not necessarily shown. In some embodiments, the heat sink 201 or the thermally conductive ring 127 can be configured to include fins that direct airflow into and through the heat sink 201. For example, heat from the semiconductor package 100 is transferred to a heat transfer assembly (e.g., thermal interface material 113 / 213 and cover 131), and air removes heat from the heat transfer assembly. The heat sink 201 can also employ a series of fans and / or other devices to generate or enhance convection to direct heated air away from the heat transfer assembly and cooler air toward the heat transfer assembly. According to various embodiments, the sensing module 221H of the heat sink 201 is positioned along the interface between the heat sink 201 and the heat transfer assembly (e.g., the second heat transfer material 213 or the cover 131). As discussed below in conjunction with other embodiments, the cover 131 may also or alternatively include a sensing module (e.g., see FIG. 4A to FIG. 4C ).

[0045] As described above, the heat sink 201 of the package system component 300A can be a liquid cooling system with additional components described herein but not necessarily shown. In some embodiments, the heat sink 201 can similarly include a plurality of fins that guide the liquid coolant to flow through the heat sink 201. For example, heat from the semiconductor package 100 is transferred to the heat transfer component (e.g., the thermal interface material 113 / 213 and the cover 131), and the liquid coolant removes heat from the heat transfer component. The heat sink 201 can also use a pump to cause the heated liquid coolant to flow out of the heat transfer component, while the cooler liquid coolant flows to the heat transfer component. In some embodiments, the heat sink 201 also includes a cold plate and a reservoir or tank, the cold plate is used to cool the heated liquid coolant shortly after the heated liquid coolant flows out of the heat transfer component, and the cold liquid coolant is pumped from the reservoir or tank to the heat transfer component. In addition, the cold plate can be incorporated into the heat sink 201 or incorporated into the cover 131. In these corresponding cases, the sensing module 221H may be located on the bottom surface of the heat sink 201 and / or the cover 131 near the semiconductor package 100 (eg, see FIG. 4A to FIG. 4C ). In other embodiments, heated liquid coolant exits the radiator 201 while cooler liquid coolant enters the radiator 201 from an external source.

[0046] Still refer to FIG. 3A to FIG. 3F, the heat sink 201 may have a contact area thermally coupled to the package cover 131 through a second thermal interface material (TIM) 213. The second thermal interface material 213 may be placed on the top surface of the package cover 131 (or the lower surface of the heat sink 201) to provide a thermal interface between the package cover 31 and the heat sink 201 above. In an embodiment, the second thermal interface material 213 may be similar to the first thermal interface material 113, but the second thermal interface material 213 may also be different from the first thermal interface material 113. According to some embodiments, the second thermal interface material 213 may have a thermal conductivity (i.e., a "k value") in Watts per meter-Kelvin (W / mK), for example, between about 5 W / mK and about 10 W / mK. However, any suitable thermal conductivity value may be used.

[0047] As shown, the heat sink 201 may include one or more embedded first sensing modules 221H (e.g., heat sink sensing modules), which are configured to measure properties related to the condition of the packaged system component 300A. For example, the first sensing module 221H can measure pressure, force, displacement, stress, strain, temperature, humidity, chemicals, etc. or a combination thereof. For simplicity, the embodiments discussed herein may refer to the sensing module as a pressure sensor, however, sensors for any of the metrics discussed above may be utilized.

[0048] In some embodiments, during installation of the heat sink 201, the sensing module 221H takes measurements to determine if the installation is straight and even. For example, the pressure readings provide a real-time assessment of whether different parts of the packaging system assembly 300A are unbalanced. As a result, adjustments can be made automatically and / or manually to rebalance or maintain balance during the installation process. For example, the measurements can be displayed on a screen for a user to interpret and take manual action in response to the measurements. Optionally, the measurements (whether displayed or not) can be sent to a controller, which takes automatic action in response to the measurements. According to some embodiments, such adjustments may include tightening or loosening some of the screws 207 and / or bolts 233 (see Figure 5 ), repositioning (e.g., straightening) the thermal interface material 113 / 213, repositioning (e.g., straightening) the heat sink 201, stopping and restarting the installation process of the heat sink 201, and any other useful activities.

[0049] There are many benefits to the installation process. For example, the first thermal interface material 113 and the second thermal interface material 213 remain aligned and prevent sliding out (e.g., pumping out) or offset. In addition, this ensures that uniform pressure is applied to the chip module 105 from the thermal interface material 113 / 213, the package cover 131, and the heat sink 201 above. As a result, the entire surface of the chip module 105 is subjected to uniform pressure and cooling, which prevents the formation and propagation of cracks (e.g., particularly close to high-performance chips such as CPUs and GPUs). The sensing module 221H allows real-time measurements during the installation process, thereby allowing real-time adjustments to prevent damage or weakening of the packaging system component 300A. The bond wire thickness of components such as thermal interface materials 113 / 213 can be kept constant, and the stress level on the chip module 105 can be fully maintained within the safety protocol. The resulting packaging system component 300A can be manufactured with a higher yield and maintain improved performance and life.

[0050] It should be understood that the sensing module 221H can achieve these benefits through various measurements. For example, the sensing module 221H can make measurements related to pressure, force, displacement, stress, and strain, such as using a sensing device, which can be a pneumatic (see Fig. 10A ), hydraulic (see Fig. 10B ), strain gauge (see Fig. 10C ) and / or capacitor unit (see Fig. 10D ). The sensing module 221H may also or alternatively be used to measure temperature, humidity, and / or chemicals (or other materials and chemical properties) to detect non-uniformities or other factors that may reduce the success rate of the installation process.

[0051] According to various embodiments, the sensing module 221H can be electrically connected to the monitoring system 225 with a wire. In some embodiments, the sensing module 221H can be wirelessly connected to the monitoring system 225. Although the embodiments discussed above or below may be described with respect to a wired or wireless sensing module 221H, any suitable combination of wired and wireless connections can be used for the sensing module 211H. In the case of a wireless sensing module 221H, the load measurement of the sensing module 211H can be monitored directly, such as using a handheld probe. In addition, the sensing module 221H can be coupled to a transmission device (not specifically shown), which can be part of the monitoring system 225 or can send data to the monitoring system 225 or cloud storage. Thus, the load measurement data can be transmitted from the sensing module 221H to the transmission device, and then the transmission device uploads the load measurement data to the monitoring system 225 or a storage system.

[0052] FIG. 3B to FIG. 3F223H, the sensing module 221H may transmit data to the monitoring system 225 via the line 223H. In some embodiments (not specifically shown), the monitoring system 225 may be attached to the package substrate 103 or the component substrate 203. The line 223H may extend through the radiator 201 or along the lower surface of the radiator 201 toward one or more sides of the radiator 201. Although not specifically shown, the monitoring system 225 may be electrically connected to a computing system, which may include a controller. The controller may be connected to a device configured to adjust a component of the packaging system assembly 300A or adjust a parameter of the environment in response to a measurement value.

[0053] exist FIG. 3B to FIG. 3F In FIG. 1 , the cover surface area 131R depicts the projection (eg, footprint or boundary) of the package cover 131 (or the second TIM 213 ). As shown, the sensing module 221H may be located within the cover surface area 131R of the heat sink 201 . Figure 3B The sensing modules 221H are shown arranged near the corners and at the center of the cover surface area 131R. Figure 3C Sensing modules 221H are shown arranged along or near the sides and center of the cover surface area 131R. Figure 3D The sensing modules 221H are shown arranged near the corners of the cover surface area 131R, along or near the sides of the cover surface area 131R, and at the center of the cover surface area 131R (eg, Figure 3B and Figure 3C a combination or combination of the configurations depicted in ). Figure 3E Shows Figure 3B A variation of the configuration depicted in , in which the sensing modules 221H are arranged near the corners of the cover surface area 131R, while there is no sensing module 221H in the center. Figure 3F Shows Figure 3C , where the sensing modules 221H are arranged along or near the sides of the cover surface area 131R, and there is no sensing module 221H in the center. It should be understood that the illustrated embodiments represent exemplary configurations, and any suitable arrangement of the sensing modules 221H may be utilized.

[0054] FIG. 4A to FIG. 4CA packaging system assembly 300B is shown according to an additional embodiment, wherein the packaging cover 131 includes one or more second sensing modules 221L (e.g., cover sensing modules). Unless otherwise stated, the packaging system assembly 300B can be similarly formed and can include components similar to those described above. The sensing module 221L can be configured to measure one or more properties discussed above in conjunction with the sensing module 221H. As shown, the heat sink 201 of the packaging system assembly 300B can also include the sensing module 221H. In some embodiments (not specifically shown), the heat sink 201 may be without the sensing module 221H.

[0055] Figure 4B and Figure 4C 223L may extend through the second thermal interface material 213 and through the heat sink 201 (e.g., along line 223H) or along the upper surface of the package cover 131 toward one or more sides of the package cover 131.

[0056] Figure 4B The sensing modules 221H disposed on the lower surface of the heat sink 201 near the corners and the center of the cover surface area 131R and the sensing modules 221L disposed on the upper surface of the package cover 131 along or near the sides of the cover surface area 131R are shown. Figure 4C The sensing modules 221L arranged on the upper surface of the package cover 131 near the corners and at the center of the cover surface area 131R, and the sensing modules 221H arranged on the lower surface of the heat sink 201 along or near the sides of the cover surface area 131R are shown. In various embodiments (not specifically shown), each set of sensing modules 221H / 221L can have other suitable configurations (for example, including those discussed in the previous embodiments), and the corresponding configurations can be complementary or overlapping.

[0057] Figure 5A packaging system component 300C having a pressure sensor 231 is shown according to various embodiments, the pressure sensor 231 being located around the screw 207 and sandwiched between the component substrate 203 and the bolt 233 (e.g., a bolt or nut). Unless otherwise stated, the packaging system component 300C can be formed similarly to the above and can include components similar to the above. The pressure sensor 231 can be configured to measure the pressure or pressure change caused by the force acting on the screw 207 uniformly or unevenly with respect to the heat sink 201 and / or the component substrate 203. The packaging system component 300C can also include a sensing module 221L (as shown) and / or a sensing module 221H (not specifically shown) as described above in conjunction with the previous embodiments. Although not specifically shown, the pressure sensor 231 can be wirelessly connected to the monitoring system or connected to the monitoring system with a wire, similar to that described in conjunction with other embodiments (e.g., from outside the packaging system component 300C or through the component substrate 203).

[0058] FIG. 6A to FIG. 6B A lidless packaging system component 300D is shown according to an additional embodiment, wherein the heat sink 201 includes a sensing module 221H adjacent to the first thermal interface material 113. Unless otherwise stated, the packaging system component 300D can be formed similarly to the above and can include components similar to the above. In some embodiments, the heat sink 201 can protrude downward from the main surface to physically contact the first thermal interface material 113. As a result, the sensing module 221H can be positioned along the lowermost surface of the heat sink 201. As shown, a gap can be retained between the thermally conductive ring 127 and the heat sink 201 to prevent the thermally conductive ring 127 from affecting the sensing module 221H. In some embodiments (not specifically shown), the heat sink 201 can be in physical contact with the top surface of the thermally conductive ring 127 to impart additional stability to the packaging system component 300D.

[0059] Figure 6B 223H. 223H may extend through the radiator 201 or extend along the lowermost surface of the radiator 201 toward one of the sides of the radiator 201.

[0060] In the illustrated embodiment, the chip module surface area 105R depicts the projection (e.g., footprint or boundary) of the chip module 105 (or the first thermal interface material 113 or the downward protrusion of the heat sink 201). In addition, the conductive ring surface area 127R depicts the projection (e.g., footprint or boundary) of the thermal conductive ring 127. As shown, the sensing module 221H can be located within the chip module surface area 105R of the heat sink 201. Figure 6B The sensing modules 221H are shown arranged near the corners and at the center of the chip module surface area 105R. As discussed above, the configuration of the sensing module 221H can be similar to the configuration discussed above in conjunction with the previous embodiments, although located within or along the chip module surface area 105R (e.g., as opposed to the cover surface area 131R of the previous embodiments).

[0061] FIG. 7A to FIG. 7B A packaging system component 300E is shown according to various embodiments, wherein one or both of the sensing module 221H and the sensing module 241L along the lower surface of the packaging cover 131 are wire-free. Unless otherwise noted, the packaging system component 300E can be formed similarly to the above and can include components similar to the above. In particular, the packaging system component 300E can be similar to any previous embodiment, although without the wires 223H / 223L. For example, the packaging system component 300E can include the sensing module 221H in the heat sink 201, the sensing module 241L in the packaging cover 131, or both. Figure 7B 2 is a plan view showing an exemplary layout or configuration of the sensing modules 221H / 241L according to some embodiments. However, the configuration of each group of sensing modules 221H / 241L can have the same layout as the similar configuration of the previous embodiment. The measurements from the sensing modules 221H / 241L are sent to the wireless monitoring system 225W as wireless signals (e.g., radio waves or any suitable frequency range).

[0062] FIG. 8A to FIG. 8B A packaging system component 300F is shown according to an additional embodiment, wherein the packaging cover 131 includes a wireless sensing module 221L along an upper surface and a wireless sensing module 241L along a lower surface. Unless otherwise stated, the packaging system component 300F can be formed similarly to the above and can include components similar to the above. Each sensing module 221L / 241L can be configured to measure one or more of the properties discussed above. As shown, the heat sink 201 may be free of the sensing module 221H. In some embodiments (not specifically shown), the heat sink 201 of the packaging system component 300F may also include a sensing module 221H.

[0063] Figure 8Bis a plan view showing an exemplary layout or configuration of sensing modules 221L / 241L according to some embodiments. The selected configuration can be similar to the embodiments discussed above or any suitable pattern to facilitate the measurement of the desired property. For example, sensing module 221L can measure similar or different properties than sensing module 241L.

[0064] Figure 8B The sensing modules 221L arranged on the upper surface of the heat sink 201 near the corners and the center of the cover surface area 131R are shown, as well as the sensing modules 241L arranged on the lower surface of the package cover 131 along or near the sides of the chip module surface area 105R. In various embodiments (not specifically shown), each group of sensing modules 221H / 221L can have other suitable configurations (for example, including those discussed in the previous embodiments), and the corresponding configurations can be complementary or overlapping. However, the configuration of each group of sensing modules 221L / 241L can have the same layout as the similar configurations of the previous embodiments.

[0065] 9A to 9C A packaging system assembly 300G is shown according to various embodiments, wherein the chip module 105 includes one or more sensor dies 119. The sensor die 119 can be configured to measure one or more of the properties discussed above. In some embodiments, the sensor die 119 may include a pressure sensor die, wherein a strain gauge pressure sensor is built into the sensor die 119. Unless otherwise stated, the packaging system assembly 300G can be formed similarly to the above and can include components similar to the above. Although the packaging system assembly 300G is shown as being lidless (e.g., see lidless packaging system assembly 300D), the packaging system assembly 300G can include a packaging cover 131 as described in the previous embodiments.

[0066] In various embodiments, the sensor die 119 is a dummy die that includes the sensor 119D, for example, in an area of ​​the sensor die 119 adjacent to the first thermal interface material 113 when incorporated into the packaging arrangement 200. The remainder of the sensor die 119 can be dedicated to routing the measurement signal to the external connector 109, through the interposer 107, through the package substrate 103, through the assembly substrate 203, and to the monitoring system 225. In some embodiments (not specifically shown), the monitoring system 225 can be attached to the package substrate 103 or the assembly substrate 203. In some embodiments, the sensor die 119 can be configured to measure pressure or pressure changes.

[0067] Fig. 9B and Fig. 9Cis a plan view illustrating an exemplary layout or configuration of sensor die 119 of chip module 105 projected over heat sink 201 according to various embodiments. Fig. 9B A sensor die 119 is shown located at or near a corner of chip module 105, and Fig. 9C Sensor dies 119 are shown located at or near a corner of chip module 105 and at a side of chip module 105. However, any suitable configuration may be utilized.

[0068] Advantages can be obtained. The formation of a semiconductor system (e.g., formed as a packaged system component 300) involves mounting larger thermally conductive components (e.g., package cover 131, thermal interface material 113 / 213, heat sink 201, and component substrate 203) to smaller and more delicate semiconductor components (e.g., semiconductor package 100). The above embodiments disclose at least some sensing modules 221 / 241 embedded in some thermally conductive components (e.g., heat sink 201 and / or package cover 131) to detect imbalances or deviations in other key performance indicators (KPIs) during the installation of certain thermally conductive components (e.g., heat sink 201). In addition, other sensing devices may be included in the dummy die 119, or integrated into attachments to the heat sink 201 and component substrate 203, for similar KPI measurements. The various sensing devices allow real-time measurement of KPIs to allow fine-tuning and adjustment during the installation process. As a result, semiconductor systems can be manufactured with higher yields and improved specifications.

[0069] In an embodiment, a method includes: attaching a die to an interposer; attaching and electrically coupling the interposer to a package substrate; attaching a package lid and a first thermal interface material to the die and the package substrate; attaching and electrically coupling the package substrate to an assembly substrate; and attaching a heat sink and a second thermal interface material to the package lid using a screw extending between the heat sink and the assembly substrate, the heat sink including a first sensing module in physical contact with the second thermal interface material. In another embodiment, the first thermal interface material is directly between the package lid and the die. In another embodiment, the first thermal interface adhesive is directly between the package lid and the package substrate. In another embodiment, the method further includes threading a bolt around the screw; and threading a pressure sensor around the screw, wherein the pressure sensor is between the bolt and the assembly substrate. In another embodiment, in a plan view, the first sensing module is located at a corner of a projection of a cover surface area. In another embodiment, the package lid includes a second sensing module. In another embodiment, in a plan view, the second sensing module is located at a side of the cover surface area. In another embodiment, the die is a pressure sensing die. In another embodiment, the method further comprises obtaining a pressure measurement using the first sensing module; and sending the pressure measurement to a pressure monitoring system. In another embodiment, the method further comprises adjusting the screw based on the pressure measurement.

[0070] In an embodiment, a semiconductor device includes: a printed circuit board; a semiconductor package disposed on the printed circuit board; a heat sink disposed on the semiconductor package; a first thermal interface material disposed between the semiconductor package and the heat sink; and a first sensor disposed between the semiconductor package and the heat sink. In another embodiment, the first sensor is in contact with the first thermal interface material. In another embodiment, the semiconductor package includes: a first die and a second die attached to an interposer; a package cover disposed over the first die and the second die, wherein the first thermal interface material is between the first die and the package cover; and a second thermal interface material is between the package cover and the heat sink. In another embodiment, the semiconductor device further includes a second sensor, wherein the first sensor is in contact with the first thermal interface material, and wherein the second sensor is in contact with the second thermal interface material. In another embodiment, the first die is a logic die, and wherein the second die is a pressure sensor die.

[0071] In an embodiment, a semiconductor device includes: a semiconductor package, the semiconductor package including: a package substrate; and a package component attached and electrically connected to the package substrate; a first thermal interface material, disposed above the package component and physically contacting the package component; a package cover, disposed above the first thermal interface material, the package cover including: a thermally conductive ring, attached to the package substrate; and a cover portion, physically contacting the first thermal interface material; a heat sink, disposed above the package cover, the heat sink including a first pressure sensor; and a component substrate, disposed below the package substrate and electrically connected to the package substrate. In another embodiment, the semiconductor device also includes a second thermal interface material between the package cover and the heat sink. In another embodiment, the first pressure sensor physically contacts the second thermal interface material. In another embodiment, the semiconductor device also includes a second pressure sensor embedded in the package cover. In another embodiment, the second pressure sensor physically contacts the first thermal interface material.

[0072] Some embodiments of the present application provide a method, including: attaching a tube die to an interposer; attaching and electrically coupling the interposer to a packaging substrate; attaching a packaging cover and a first thermal interface material to the tube die and the packaging substrate; attaching and electrically coupling the packaging substrate to a component substrate; and attaching a heat sink and a second thermal interface material to the packaging cover using screws, the screws extending between the heat sink and the component substrate, the heat sink including a first sensing module in physical contact with the second thermal interface material.

[0073] In some embodiments, the first thermal interface material is directly between the package cover and the die. In some embodiments, the first thermal interface adhesive is directly between the package cover and the package substrate. In some embodiments, the method further includes: threading a bolt around the screw; and threading a pressure sensor around the screw, wherein the pressure sensor is between the bolt and the component substrate. In some embodiments, in a plan view, the first sensing module is located at a corner of a projection of the cover surface area. In some embodiments, the package cover includes a second sensing module. In some embodiments, in the plan view, the second sensing module is located at a side of the cover surface area. In some embodiments, the die is a pressure sensing die. In some embodiments, the method further includes: obtaining a pressure measurement using the first sensing module; and sending the pressure measurement to a pressure monitoring system. In some embodiments, the method further includes adjusting the screw based on the pressure measurement.

[0074] Other embodiments of the present application provide a semiconductor device, comprising: a printed circuit board; a semiconductor package disposed on the printed circuit board; a heat sink disposed on the semiconductor package; a first thermal interface material disposed between the semiconductor package and the heat sink; and a first sensor disposed between the semiconductor package and the heat sink.

[0075] In some embodiments, the first sensor is in contact with the first thermal interface material. In some embodiments, the semiconductor package includes: a first die and a second die attached to an interposer; a package cover disposed over the first die and the second die, wherein the first thermal interface material is interposed between the first die and the package cover; and a second thermal interface material is interposed between the package cover and the heat sink. In some embodiments, the semiconductor device further includes a second sensor, wherein the first sensor is in contact with the first thermal interface material, and wherein the second sensor is in contact with the second thermal interface material. In some embodiments, the first die is a logic die, and wherein the second die is a pressure sensor die.

[0076] Some other embodiments of the present application provide a semiconductor device, including: a semiconductor package, including: a packaging substrate; and a packaging component attached and electrically connected to the packaging substrate; a first thermal interface material, disposed above the packaging component and physically contacting the packaging component; a packaging cover, disposed above the first thermal interface material, the packaging cover including: a thermally conductive ring attached to the packaging substrate; and a covering portion, physically contacting the first thermal interface material; a heat sink, disposed above the packaging cover, the heat sink including a first pressure sensor; and a component substrate, disposed below the packaging substrate and electrically connected to the packaging substrate.

[0077] In some embodiments, the semiconductor device further comprises a second thermal interface material between the package cover and the heat sink. In some embodiments, the first pressure sensor physically contacts the second thermal interface material. In some embodiments, the semiconductor device further comprises a second pressure sensor embedded in the package cover. In some embodiments, the second pressure sensor physically contacts the first thermal interface material.

[0078] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method for forming a semiconductor device, comprising: attaching the die to the interposer; attaching and electrically coupling the interposer to a package substrate; attaching a package lid and a first thermal interface material to the die and the package substrate; attaching and electrically coupling the package substrate to a component substrate; as well as A heat sink and a second thermal interface material are attached to the package lid using screws extending between the heat sink and the component substrate, the heat sink including a first sensing module in physical contact with the second thermal interface material.

2. The method according to claim 1, wherein: The first thermal interface material is directly between the package lid and the die.

3. The method according to claim 1, wherein: A first thermal interface adhesive is directly interposed between the package lid and the package substrate.

4. The method according to claim 1, further comprising: Passing a bolt around the screw; as well as A pressure sensor is threaded around the screw, wherein the pressure sensor is interposed between the bolt and the component substrate.

5. The method according to claim 1, wherein: In a plan view, the first sensing module is located at a corner of a projection of the cover surface area.

6. The method according to claim 5, wherein: The packaging cover includes a second sensing module.

7. The method according to claim 6, wherein: In the plan view, the second sensing module is located at a side of the cover surface area.

8. The method according to claim 1, wherein: The die is a pressure sensing die.

9. A semiconductor device comprising: Printed circuit boards; A semiconductor package is disposed on the printed circuit board; A heat sink is disposed on the semiconductor package; A first thermal interface material is disposed between the semiconductor package and the heat sink; as well as The first sensor is disposed between the semiconductor package and the heat sink.

10. A semiconductor device comprising: Semiconductor packages, including: a package substrate; and a packaging assembly attached and electrically connected to the packaging substrate; a first thermal interface material disposed over and in physical contact with the package assembly; A packaging cover is arranged above the first thermal interface material, and the packaging cover comprises: a thermally conductive ring attached to the package substrate; and a covering portion in physical contact with the first thermal interface material; a heat sink disposed above the packaging cover, the heat sink comprising a first pressure sensor; and A component substrate is disposed under the package substrate and electrically connected to the package substrate.

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