Contact structure and forming method thereof

Abstract

The embodiment of the invention provides a contact structure and a forming method thereof. A contact structure according to the present disclosure includes a conductive feature, an etch stop layer (ESL) over the conductive feature, a dielectric layer over the ESL, and a contact feature extending through the dielectric layer and the ESL to contact the conductive feature. The dielectric layer includes a low-k dielectric substrate and nanotubes disposed in the low-k dielectric substrate and configured to reduce thermal resistance of the dielectric layer.

Description

Technical Field

[0001] Embodiments of the present invention generally relate to the field of semiconductors, and more particularly, to contact structures and methods of forming the same. Background Art

[0002] The electronics industry has a growing demand for smaller, faster electronic devices that are able to simultaneously support more increasingly complex and sophisticated functions. As a result, there is a continuing trend in the semiconductor industry to manufacture low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have been achieved in large part by shrinking semiconductor IC dimensions (e.g., minimum feature size), thereby increasing production efficiency and reducing associated costs. However, this scaling has also increased the complexity of semiconductor manufacturing processes. Therefore, achieving continued advancements in semiconductor ICs and devices requires similar advances in semiconductor manufacturing processes and technologies.

[0003] As device dimensions continue to shrink, higher performance requirements are placed on back-end-of-line (BEOL) interconnect structures. Low dielectric constant (low-k) materials have been incorporated into interconnect structures to reduce capacitance. While the purpose of low-k materials is to reduce capacitance, their poor thermal conductivity poses a challenge to heat dissipation in front-end-of-line (FEOL) devices. Summary of the invention

[0004] One embodiment of the present invention provides a contact structure, comprising: a conductive component; an etch stop layer (ESL) located above the conductive component; a dielectric layer located above the etch stop layer; and a contact component extending through the dielectric layer and the etch stop layer to contact the conductive component, wherein the dielectric layer comprises: a low-k dielectric substrate, and nanotubes disposed in the low-k dielectric substrate and configured to reduce the thermal resistance of the dielectric layer.

[0005] Another embodiment of the present invention provides a method for forming a contact structure, comprising: depositing an etch stop layer (ESL) over a metal component; depositing a solution over the etch stop layer, the solution comprising a solvent, a low-k dielectric precursor, and at least one high thermal conductivity particle; treating the solution to cause self-aggregation of the at least one high thermal conductivity particle; curing the solution to form a low-k dielectric layer on the etch stop layer; forming an opening through the low-k dielectric layer and the etch stop layer; depositing a conductive material in the opening; and performing planarization to expose a top surface of the low-k dielectric layer.

[0006] Another embodiment of the present invention provides a method for forming a contact structure, comprising: depositing an etch stop layer (ESL) above a metal component; forming a low-k dielectric layer above the etch stop layer, wherein the low-k dielectric layer includes nanotubes arranged along a direction; forming an opening through the low-k dielectric layer and the etch stop layer; depositing a conductive material in the opening; and performing planarization to expose a top surface of the low-k dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Various aspects of the present invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, the sizes of the various components may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1 is a flow chart of a method 100 for forming a contact structure through a dielectric layer according to one or more aspects of the present disclosure.

[0009] Figures 2 to 9 According to one or more aspects of the present disclosure, Figure 1 Partial cross-sections of the workpiece at different manufacturing stages.

[0010] Fig.10 is a flow chart of a method 300 for forming a contact structure through a dielectric layer according to one or more aspects of the present disclosure.

[0011] Figures 11 to 19 According to one or more aspects of the present disclosure, Fig.10 Partial cross-sections of the workpiece at different manufacturing stages.

[0012] Fig. 20 is a flow chart of a method 400 for forming a contact structure through a dielectric layer according to one or more aspects of the present disclosure.

[0013] Figure 21 to Figure 29 According to one or more aspects of the present disclosure, Fig. 20 Partial cross-sections of the workpiece at different manufacturing stages.

[0014] Fig.30 Included are graphs showing how the presence of nanotubes in a low-k dielectric substrate reduces thermal resistance in simulations according to one or more aspects of the present disclosure.

[0015] Fig.31 and Fig.32 Schematic cross-sectional views of interconnect structures including a low-k dielectric layer with embedded nanotubes according to one or more aspects of the present disclosure are provided. DETAILED DESCRIPTION

[0016] The present invention provides many different embodiments or examples for realizing the different features of the present disclosure. Specific examples of components and arrangements are described below to simplify the present invention. Of course, these are merely examples and are not intended to limit the present invention. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are formed in direct contact, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present invention may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity, but does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0017] Furthermore, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0018] In addition, when a number or series of numbers is described using the term "approximately," "approximately," etc., the term is intended to include numbers within a reasonable range, taking into account variations inherent in manufacturing processes as understood by those of ordinary skill in the art. For example, based on known manufacturing tolerances associated with manufacturing components with the number associated with it, the number or range includes a reasonable range including the described number, such as within + / - 10% of the described number. For example, a material layer having a thickness of "about 5 nm" may include a size range of 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with deposited material layers is known to those of ordinary skill in the art to be + / - 15%. The source / drain regions may be referred to individually or collectively as source or drain, depending on the context.

[0019] As front-end-of-line (FEOL) devices become smaller, back-end-of-line (BEOL) interconnect structures play a larger role in meeting power, performance, and area requirements. BEOL interconnect structures can include low-k dielectric materials to reduce parasitic capacitance. In general, low-k dielectric materials have lower thermal conductivity than high-k dielectric materials, metals, or semiconductor materials. For example, the thermal conductivity of silicon oxide is two orders of magnitude lower than that of silicon. The low thermal conductivity of low-k dielectric materials prevents them from effectively dissipating the heat generated by FEOL devices. When it comes to dielectric materials in BEOL interconnect structures, the industry is scrambling to find a solution that can achieve high thermal conductivity while maintaining low parasitic capacitance.

[0020] The present disclosure provides a method for improving the thermal conductivity of a low-k dielectric layer in a contact structure. In an exemplary process, a mixture of a low-k dielectric precursor solution and high thermal conductivity nanoparticles is deposited on an etch stop layer (ESL). A heat treatment or a combination of a heat treatment and an electromagnetic field is applied to the mixture to cause the high thermal conductivity nanoparticles to self-aggregate to form high thermal conductivity nanotubes. The mixture is then cured to form a low-k dielectric layer. In another exemplary process, a low-k dielectric precursor is deposited above the ESL. Nanoparticles or preformed nanotubes are injected into the deposited low-k dielectric precursor. After injection, the low-k dielectric precursor is cured to form a low-k dielectric layer. In another exemplary process, low-k dielectric layers and high thermal conductivity layers are alternately deposited and cured to form a multilayer structure. The multilayer structure includes a low dielectric constant but has a relatively high thermal conductivity to achieve effective heat dissipation.

[0021] Various aspects of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 , Fig.10 and Fig.18 1 is a flow chart illustrating methods 100, 300, and 400 for forming contact structures on workpiece 200. Methods 100, 300, and 400 are merely examples and are not intended to limit the present disclosure to what is explicitly shown in method 100, method 300, or method 400. Additional steps may be provided before, during, and after method 100, method 300, or method 400, and some of the steps described may be replaced, eliminated, or moved for additional embodiments. For simplicity, not all steps are described in detail. Figures 2 to 9 Describing method 100, Figures 2 to 9 is a partial cross-sectional view of a workpiece 200 at different manufacturing stages according to an embodiment of the method 100. Figures 11 to 19 Describing method 300, Figures 11 to 19 is a partial cross-sectional view of the workpiece 200 at different manufacturing stages according to an embodiment of the method 300. Figure 21 to Figure 29 The method 400 is described, and these figures are partial cross-sectional views of a workpiece 200 at different manufacturing stages according to an embodiment of the method 400. Because the workpiece 200 will be manufactured into a semiconductor structure 200 after the manufacturing process is completed, the workpiece 200 may be referred to as a semiconductor structure 200 as the context requires. In addition, throughout the present application and different embodiments, unless otherwise specified, the same reference numerals represent the same components with similar structures and compositions.

[0022] refer to Figure 1 and Figure 2, the method 100 includes block 102, where an etch stop layer (ESL) 204 is deposited over a conductive feature 202. In the depicted embodiment, the conductive feature 202 may be a metal line in a back-end-of-line (BEOL) interconnect structure. Figure 2 In some other embodiments not explicitly shown in the drawings, the conductive component 202 may be a contact via or a dual damascene component including a metal line and a contact via. The conductive component 202 may include copper (Cu), nickel (Ni), cobalt (Co), aluminum (Al), or a combination thereof. In one embodiment, the conductive component 202 includes copper (Cu). The ESL 204 may include nitrogen-doped silicon carbide (SiC:N or silicon carbonitride), aluminum nitride (AlN), aluminum oxide (AlO), silicon nitride, oxygen-doped silicon carbide (SiC or:O carbon oxide silicon) or a combination thereof. In one embodiment, the ESL 204 includes nitrogen-doped silicon carbide. In some embodiments, the ESL 204 may be deposited using atomic layer deposition (ALD), chemical vapor deposition (CVD), or physical vapor deposition (PVD). The conductive component 202, the ESL 204, and other structures to be fabricated above the ESL may be collectively referred to as a workpiece 200.

[0023] refer to Figure 1 and Figure 3 , method 100 includes block 104, where a mixture 206 of a low-k dielectric precursor 10 and high thermal conductivity particles is deposited above ESL 204. Here, mixture 206 can be a solution, a slurry, a suspension, or a sol-gel, as the present disclosure contemplates all reasonable mixtures of low-k components and high thermal conductivity components. Mixture 206 includes low-k dielectric precursor 10 and at least one high thermal conductivity particle. In the depicted embodiment, at least one high thermal conductivity particle includes one-dimensional (1D) nanoparticles 20 and two-dimensional (2D) nanoparticles 30. Examples of 1D nanoparticles 20 are graphene or carbon nanotubes (CNTs). Examples of 2D nanoparticles 30 are boron nitride (BN). Other examples of high thermal conductivity particles may include diamond, silicon carbide (SiC), beryllium oxide (BeO), boron phosphide (BP), aluminum nitride (AlN), beryllium sulfide (BeS), boron arsenide (BAs), gallium nitride (GaN), aluminum phosphide (AlP), gallium phosphide (GaP) or aluminum oxide (Al2O3). In some embodiments, in order to promote subsequent self-aggregation, the high thermal conductivity particles can be chemically treated to carry a positive charge or a negative charge. For example, boron nitride nanoparticles can be chemically treated to carry a positive charge, and carbon nanotubes can be chemically treated to carry a negative charge. In some embodiments, the mixture 206 may include only one type of high thermal conductivity particles. For example, the mixture 206 may include only 1D nanoparticles 20 or only 2D nanoparticles 30.

[0024] The low-k dielectric precursor 10 may include silicon (Si), carbon (C), oxygen (O), and hydrogen (H), and is suitable for spin coating or flowable chemical vapor deposition (FCVD). In some embodiments, the low-k dielectric precursor 10 may include hydrogen-silsesquioxane (HSSQ), methyl-silsesquioxane (MSSQ), or carbon-doped silicon oxide (i.e., silicon-doped quartz glass). In order for subsequent self-aggregation to occur, the mixture 206 is fluid or flowable when deposited at block 104. The fluidity or flowability of the mixture 206 allows the at least one high thermal conductivity particle to move or orient in the mixture 206 in response to dipole-dipole forces, electric fields, magnetic fields, or electrostatic attraction. In some cases, the mixture 206 may also include a solvent and a surfactant. Example solvents may include dimethylformamide (DMF), tetrahydrofuran (THF), n-butyl acetate (nBA), or n-methyl-2-pyrrolidone (NMP). The surfactant helps the at least one high thermal conductivity particle to be dispersed in the mixture 206 without agglomeration. At block 104 , the mixture 206 may be deposited over the ESL 204 by spin coating or flowable CVD (FCVD).

[0025] In order to maintain a low dielectric constant and prevent aggregation due to high particle loading, the volume percentage of the at least one high thermal conductivity particle in the mixture 206 can be between 10% and about 25%. When the volume percentage is less than 10%, the amount of the at least one high thermal conductivity particle may be insufficient to form a thermal conduction path. When the volume percentage is greater than 25%, the amount of the at least one high thermal conductivity particle can increase the dielectric constant of the dielectric layer formed by the mixture 206. The volume percentage of the high thermal conductivity particles is related to the density of the nanotubes formed by the high thermal conductivity particles. Fig.30 Includes graphs that illustrate how the presence of nanotubes in a low-k dielectric substrate reduces thermal resistance in simulations. The simulations show that thermal conductivity can be cut in half when the density of nanotubes in the low-k substrate is about 10%. While additional nanotubes have the effect of reducing thermal resistance, this effect becomes less significant after the density of nanotubes reaches about 40%.

[0026] refer to Figure 1 , Figure 4 and Figure 5 , the method 100 includes block 106, wherein the mixture 206 is treated to cause the high thermal conductivity particles in the mixture 206 to self-aggregate. Figure 4 In some embodiments shown, the processing at block 106 may include a heat treatment 260, such as an annealing process. The heat treatment 260 is intended to provide energy to the at least one high thermal conductivity particle in the mixture 206 without solidifying the mixture 206 or causing a large amount of solvent to evaporate. Therefore, the process temperature of the heat treatment 260 is lower than the annealing temperature of the annealing process for solidifying the mixture 206. In some embodiments, the process temperature of the heat treatment 260 may be between about 80°C and about 180°C.

[0027] exist Figure 5 In some other embodiments shown, the treatment at block 106 includes heat treatment 260 and electromagnetic field 280. Figure 5 In the illustrated embodiments, the heat treatment 260 provides energy to at least one type of high thermal conductivity particle, causing it to have Brownian motion and rotation in the mixture 206, while the electromagnetic field 280 provides an additional driving force for at least one type of high thermal conductivity particle, causing it to have aligned self-aggregation. Depending on the functional groups on the at least one type of high thermal conductivity particle, the electromagnetic field 280 can be an electric field, a magnetic field, or both. In some embodiments, when the at least one type of high thermal conductivity particle includes a ceramic material, such as beryllium oxide (BeO), aluminum oxide (Al2O3), the heat treatment 260 and the electromagnetic field 280 can cause the high thermal conductivity particles to form chemically bonded boundaries, which can form nanotubes or thermally conductive networks in the mixture 206.

[0028] like Figure 4 and Figure 5 As shown, the treatment at box 106 may cause at least some of the high thermal conductivity particles to self-aggregate under the action of van der Waals forces, chemical bonds, dipole moments, or electrostatic forces. As a result, nanotubes 40 may be formed. In some embodiments, nanotubes 40 may include 1D nanoparticles 20, 2D nanoparticles 30, or a combination thereof. For example, when 1D nanoparticles 20 include negatively charged carbon nanotubes and 2D nanoparticles 30 include positively charged boron nitride (BN), a mixture of heat treatment 260 and an electric field (i.e., in the form of an electromagnetic field 280) may cause 1D nanoparticles 20 and 2D nanoparticles 30 to attract each other through electrostatic forces and align with the electric field. When the direction of the electric field is perpendicular to (i.e., orthogonal to) the top surface of the conductive component 202 along the Z direction, the nanotubes 40 may be arranged longitudinally along the Z direction. Because the nanoparticles in the nanotubes 40 have high thermal conductivity, the nanotubes 40 provide a high thermal conductivity heat conduction path in the deposited mixture 206. When the nanotubes 40 are aligned longitudinally, they provide a directional high thermal conductivity heat conduction path.

[0029] refer to Figure 1 and Figure 6, the method 100 includes a block 108, in which the mixture 206 is cured to form a first dielectric layer 2060. The first dielectric layer 2060 includes silicon (Si), carbon (C), oxygen (O), and hydrogen (H). In one embodiment, the first dielectric layer 2060 may include carbon-doped quartz glass (SiCOH). In some embodiments, the curing of the mixture 206 at block 108 may include an annealing process or an ultraviolet (UV) curing process. Generally, the annealing process or the UV curing process may evaporate the solvent in the mixture 206 or induce a reduction reaction in the mixture 206 to form the first dielectric layer 2060. Because the mixture 206 includes the low-k dielectric precursor 10, the first dielectric layer 2060 may still have a low dielectric constant and may be referred to as a low-k dielectric layer 2060. In general, the first dielectric layer 2060 may be considered as a low-k dielectric matrix in which the high thermal conductivity nanotubes 40 are embedded. The low-k dielectric matrix keeps the overall dielectric constant of the first dielectric layer 2060 low, while the high thermal conductivity nanotubes 40 provide a high thermal conductivity path for heat dissipation. When the curing at block 108 includes an annealing process, the annealing process has an annealing temperature greater than the process temperature of the thermal treatment 260 at block 106 .

[0030] refer to Figure 1 and Figure 6 , the method 100 includes a block 110, in which a second dielectric layer 208 is deposited over the first dielectric layer 2060. The second dielectric layer 208 acts as a hard mask during the subsequent formation of contact openings through the first dielectric layer 2060 and the ESL 204. To achieve its purpose, the second dielectric layer 208 has a greater density and structural integrity than the first dielectric layer 2060. In some embodiments, the second dielectric layer 208 may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphosilicate glass (PSG), fluorine-doped silicon dioxide, silicon oxide, or a combination thereof. In one embodiment, the second dielectric layer 208 includes silicon oxide. In some embodiments, the second dielectric layer 208 may be deposited using spin coating, CVD, atmospheric pressure CVD (APCVD), or FCVD.

[0031] refer to Figure 1 and Figure 7, the method 100 includes block 112, where a contact opening 210 is formed through the second dielectric layer 208, the first dielectric layer 2060, and the ESL 204. In an exemplary process, a patterned mask is first formed by a photolithography process, and a dry etching process is performed to form a via opening through the second dielectric layer 208, the first dielectric layer 2060, and the ESL 204. Then a second patterned mask is formed, and another dry etching process is performed to form a trench opening overlapping the via opening. The dry etching at block 112 may be performed with oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, CH3F, C4H8, C4F6, and / or C2F6), carbon-containing gas (e.g., CO, CH4, and / or C3H8), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBR3), iodine-containing gas, other suitable gas and / or plasma, and / or combinations thereof. Figure 7 In some of the illustrated embodiments, each contact opening 210 includes a via opening 210V and a line opening 210L above the via opening 210V.

[0032] refer to Figure 1 , Figure 8 and Fig. 9 , the method 100 includes block 114, in which a contact feature 212 is formed in the contact opening 210. The operation at block 114 may include depositing a metal fill layer 211 (eg, Figure 8 ), and planarizing the workpiece 200 to remove excess material (as shown Fig. 9 See Figure 8 , a metal fill layer 211 may be deposited over the contact opening 210 using physical vapor deposition (PVD), electroplating, or electroless plating. In some embodiments, the metal fill layer 211 may include copper (Cu), cobalt (Co), nickel (Ni), ruthenium (Ru), or tungsten (W). In one embodiment, the metal fill layer 211 includes copper (Cu). For example, the metal fill layer 211 may be deposited using electroplating. In this example process, a seed layer may be deposited on the workpiece 200 using PVD or CVD. The seed layer may include titanium, copper, or both. Copper is then deposited over the seed layer using electroplating. In some embodiments not explicitly shown in the drawings, a barrier layer is deposited over the contact opening 210 before depositing the metal fill layer 211. In some cases, the barrier layer may include a metal nitride, such as titanium nitride, cobalt nitride, manganese nitride, nickel nitride, tungsten nitride, or tantalum nitride. In one embodiment, the barrier layer includes titanium nitride. The barrier layer may be deposited using CVD, plasma enhanced CVD (PECVD), ALD, or plasma enhanced ALD (PEALD). Refer to Fig. 9After the barrier layer and the metal filling layer 211 are deposited, the workpiece 200 is planarized to expose the first dielectric layer 2060, thereby forming the contact feature 212. The planarization may include chemical mechanical polishing (CMP). Fig. 9 As shown, the workpiece 200 is planarized until a planar top surface of the workpiece 200 includes top surfaces of the first dielectric layer 2060 and the metal fill layer 211 .

[0033] Method 100 forms nanotubes 40 in first dielectric layer 2060 by including highly thermally conductive nanoparticles in mixture 206, depositing mixture 206 over a workpiece, and treating mixture 206 before curing to allow the highly thermally conductive nanoparticles to self-aggregate. Instead of depositing mixture 206 over a workpiece, Fig.10 The method 300 includes injecting high thermal conductivity nanoparticles or nanotubes into a low-k dielectric precursor layer deposited above a workpiece. Figures 11 to 19 Method 300 is described with reference to a partial cross-sectional view of workpiece 200 in FIG.

[0034] refer to Fig.10 and Fig.11 , method 300 includes block 302, where an etch stop layer (ESL) 204 is deposited over conductive feature 202. The operations at block 302 are similar to the operations described above with respect to block 102. For the sake of brevity, a detailed description of the operations at block 302 is omitted.

[0035] refer to Fig.10 and Fig.12 , the method 300 includes a block 304, where a low-k dielectric precursor 10 is deposited over the ESL 204. In some embodiments, the low-k dielectric precursor 10 may include silicon (Si), carbon (C), oxygen (O), and hydrogen (H), and is suitable for spin coating or FCVD. In some embodiments, the low-k dielectric precursor 10 may include hydrogen-silsesquioxane (HSSQ), methyl-silsesquioxane (MSSQ), or carbon-doped silicon oxide (i.e., silicon-doped quartz glass). In order to make the subsequent implantation step effective, the low-k dielectric precursor 10 is fluid or flowable when deposited at block 304. The fluidity or flowability of the low-k dielectric precursor 10 allows the nanoparticles or nanotubes to penetrate into the low-k dielectric precursor 10. At block 304, the low-k dielectric precursor 10 may be deposited over the ESL 204 by spin coating or FCVD.

[0036] refer to Fig.10 , Fig.13 and Fig.14 The method 300 includes block 306, where high thermal conductivity nanotubes 40 are formed in the low-k dielectric precursor 10. Fig.13 and Fig.14In some embodiments shown, nanotubes 40 are formed in low-k dielectric precursor 10 by an injection process 360. In some embodiments, nanoparticles (such as 1D nanoparticles 20 and 2D nanoparticles 30) are injected into low-k dielectric precursor 10 deposited above ESL 204. In these embodiments, the nanoparticles are driven by pressure through a mold or nozzle, and the shear stress at the mold or nozzle aligns the nanoparticles along the injection direction to form nanotubes 40. In some other embodiments, nanotubes 40 are pre-formed and dispersed in a suspension, solution, or sol-gel liquid, and injected into low-k dielectric precursor 10 deposited above ESL 204. Depending on the nature and shape of the nanoparticles, the nanotubes formed by the injection process 360 can be vertical or horizontal to the top surface of the conductive feature 202. For example, in Fig.13 In the embodiment, when the nanotubes 40 include 1D nanoparticles 20, the nanotubes 40 in the low-k dielectric precursor 10 may be longitudinally aligned along the Z direction, because this orientation exhibits the lowest resistance. Fig.14 When the dumbbell-shaped nanotube 50 having the bulk end group 60 is implanted into the low-k dielectric precursor 10, the resistance imposed on the bulk end group 60 may cause the dumbbell-shaped nanotube 50 to have a horizontal orientation. The nanotube 40 or dumbbell-shaped nanotube 50 may include carbon nanotube (CNT), boron nitride (BN), diamond, silicon carbide (SiC), beryllium oxide (BeO), boron phosphide (BP), aluminum nitride (AlN), beryllium sulfide (BeS), boron arsenide (BA), gallium nitride (GaN), aluminum phosphide (AlP), gallium phosphide (GaP), or aluminum oxide (Al2O3).

[0037] refer to Fig.10 and Fig.15 , the method 300 includes block 308, where the low-k dielectric precursor 10 is cured to form the first dielectric layer 2060. The operations of curing the low-k dielectric precursor 10 at block 308 are similar to the operations described above at block 108 with respect to curing of the mixture 206. For the sake of brevity, a detailed description of the operations at block 308 is omitted.

[0038] refer to Fig.10 and Fig.15 , the method 300 includes block 310, where the second dielectric layer 208 is deposited over the first dielectric layer 2060. The operations at block 310 are similar to the operations described above with respect to block 110. For the sake of brevity, a detailed description of the operations at block 310 is omitted.

[0039] refer to Fig.10 and Fig.16, method 300 includes block 312, where contact opening 210 is formed through second dielectric layer 208, first dielectric layer 2060, and ESL 204. Operations at block 312 are similar to operations described above with respect to block 112. For the sake of brevity, detailed description of operations at block 312 is omitted.

[0040] refer to Fig.10 and 17 to Fig.19 The method 300 includes block 314 in which the contact feature 212 is formed in the contact opening 210 . Fig.18 A contact feature 212 is shown extending through a first dielectric layer 2060 including vertically oriented nanotubes 40 . Fig.19 The contact feature 212 is shown extending through the first dielectric layer 2060 including the horizontally oriented dumbbell-shaped nanotubes 50. The operations at block 314 are similar to the operations described above with respect to block 114. For the sake of brevity, a detailed description of the operations at block 314 is omitted.

[0041] Fig. 20 The method 400 in the embodiment includes alternately forming low-k dielectric layers and high thermal conductivity layers to form a multilayer having a low dielectric constant and providing directional heat dissipation, without forming nanotubes in the low-k dielectric layers.

[0042] refer to Fig. 20 and Fig.21 , method 400 includes block 402, where an etch stop layer (ESL) 204 is deposited over conductive feature 202. The operations at block 402 are similar to the operations described above with respect to block 102. For the sake of brevity, a detailed description of the operations at block 402 is omitted.

[0043] refer to Fig. 20 and Fig. 22 , the method 400 includes a block 404, wherein a bottom low-k dielectric layer 216 is deposited over the ESL 204. In some embodiments, the deposition of the bottom low-k dielectric layer 216 includes depositing a low-k dielectric precursor 10 over the ESL 204 and curing the low-k dielectric precursor 10. In some embodiments, the low-k dielectric precursor 10 may include silicon (Si), carbon (C), oxygen (O), and hydrogen (H). In some embodiments, the low-k dielectric precursor 10 may include hydrogen-silsesquioxane (HSSQ), methyl-silsesquioxane (MSSQ), or carbon-doped silicon oxide (i.e., silicon-doped quartz glass). At block 404, the low-k dielectric precursor 10 may be deposited over the ESL 204 by spin coating or FCVD. The deposited low-k dielectric precursor 10 is then cured using an annealing process or an ultraviolet (UV) curing process. After curing, a bottom low-k dielectric layer 216 is formed.

[0044] refer to Fig. 20 and Fig.23 , the method 400 includes a block 406, wherein a first high thermal conductivity layer 218 is deposited over the bottom low-k dielectric layer 216. In some embodiments, the first high thermal conductivity layer 218 includes carbon nanotubes (CNTs), boron nitride (BN), diamond, silicon carbide (SiC), beryllium oxide (BeO), boron phosphide (BP), aluminum nitride (AlN), beryllium sulfide (BeS), boron arsenide (BA), gallium nitride (GaN), aluminum phosphide (AlP), gallium phosphide (GaP), or aluminum oxide (Al2O3). In some embodiments, the first high thermal conductivity layer 218 can be deposited using spin coating, PVD, CVD, FCVD, or ALD. For example, when the first high thermal conductivity layer 218 includes diamond, the first high thermal conductivity layer 218 can be deposited using spin coating. When the first high thermal conductivity layer 218 includes aluminum nitride (AlN) or silicon carbide (SiC), the first high thermal conductivity layer 218 can be deposited using CVD or PVD. When the first high thermal conductivity layer 218 is deposited using spin coating, a curing process such as an annealing process or a UV curing process may be required to cure the first high thermal conductivity layer 218. When the first high thermal conductivity layer 218 is deposited using CVD, PVD, or ALD, a separate curing process may not be required.

[0045] refer to Fig. 20 and Fig.24 , the method 400 includes a block 408, wherein a top low-k dielectric layer 220 is deposited on the first high thermal conductivity layer 218. In some embodiments, the top low-k dielectric layer 220 may be similar to the bottom low-k dielectric layer 216 in terms of composition and formation process. In some embodiments, the deposition of the top low-k dielectric layer 220 includes depositing a low-k dielectric precursor 10 over the first high thermal conductivity layer 218 and curing the low-k dielectric precursor 10. In some embodiments, the low-k dielectric precursor 10 may include silicon (Si), carbon (C), oxygen (O), and hydrogen (H). In some embodiments, the low-k dielectric precursor 10 may include hydrogen-silsesquioxane (HSSQ), methyl-silsesquioxane (MSSQ), or carbon-doped silicon oxide (i.e., silicon-doped quartz glass). At block 408, the low-k dielectric precursor 10 may be deposited over the first high thermal conductivity layer 218 by spin coating or FCVD. The deposited low-k dielectric precursor 10 is then cured using an annealing process or an ultraviolet (UV) curing process. After curing, a top low-k dielectric layer 220 is formed. At this point, the bottom low-k dielectric layer 216, the first high thermal conductive layer 218, and the top low-k dielectric layer 220 form a first multilayer 230. Due to the presence of the bottom low-k dielectric layer 216, the first high thermal conductive layer 218, and the top low-k dielectric layer 220, the first multilayer 230 can effectively dissipate heat horizontally while maintaining a relatively low dielectric constant.

[0046] refer to Fig. 20 and Fig.25, the method 400 includes block 410, where the second dielectric layer 208 is deposited over the top low-k dielectric layer 220. The operations at block 410 are similar to the operations described above with respect to block 110. For the sake of brevity, a detailed description of the operations at block 410 is omitted.

[0047] refer to Fig. 20 and Fig.26 , method 400 includes block 412, where contact opening 210 is formed through bottom low-k dielectric layer 216, first high thermal conductive layer 218, top low-k dielectric layer 220, and ESL 204. The operations at block 412 are similar to the operations described above with respect to block 112. For the sake of brevity, a detailed description of the operations at block 412 is omitted. Fig.26 As shown, the contact opening 210 extends through the second dielectric layer 208 , the top low-k dielectric layer 220 , the first high thermal conductive layer 218 , and the bottom low-k dielectric layer 216 .

[0048] refer to Fig. 20 , Fig. 27 and Fig.28 , the method 400 includes a block 414, in which the contact feature 212 is formed in the contact opening 210. The operations at block 414 are similar to the operations described above with respect to block 114. For the sake of brevity, a detailed description of the operations at block 414 is omitted. Fig.28 As shown, the contact feature 212 extends through the top low-k dielectric layer 220 , the first high thermal conductive layer 218 , and the bottom low-k dielectric layer 216 .

[0049] Fig.29 An alternative embodiment is shown in which the operations at blocks 406 and 408 are performed multiple times to form the second multilayer 232. Fig.29 In the illustrated embodiment, the second multilayer 232 includes low-k dielectric layers 216, 2202, 2204, and 2206 interleaved with high thermal conductivity layers 2182, 2184, and 2186. Due to the presence of the low-k dielectric layers and the high thermal conductivity layers, the second multilayer 232 can effectively dissipate heat horizontally while maintaining a relatively low dielectric constant.

[0050] Fig.31 and Fig.32A schematic diagram of implementing the low-k and high thermal conductivity structure of the present disclosure into a semiconductor device 500 is included. The semiconductor device 500 includes a substrate 502, a device layer 504 above the substrate 502, and an interconnect layer 520 above the device layer 504. The substrate 502 can be a silicon (Si) substrate. In some other embodiments, the substrate 502 can include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. The substrate 502 can also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure. The device layer 504 includes a front-end-of-line (FEOL) structure manufactured above the substrate 502. The device layer 504 can include transistors, such as planar transistors, fin field effect transistors (FinFETs), full-all-around gate (GAA) transistors, or complementary field effect transistors. The interconnect structure 520 includes multiple metallization layers. In some embodiments, the interconnect structure 520 includes about 10 to about 20 metallization layers. In Fig.31 and Fig.32 In the illustrated embodiment, the interconnect structure 520 includes a first metallization layer 506, a second metallization layer 508, a third metallization layer 510, a fourth metallization layer 512, and a fifth metallization layer 514. Additional metallization layers above the fifth metallization layer 514 are represented by dots. Each metallization layer includes contact features embedded in an inter-metal dielectric (IMD) layer. For example, the second metallization layer 508 is disposed above the etch stop layer 527 and includes a contact feature 528 disposed in the IMD layer 529.

[0051] First reference Fig.31 .like Fig. 9 and Fig.18 As shown, nanotubes 40 may be fabricated in each IMD layer in interconnect structure 520. In the illustrated embodiment, contact features 526 in first metallization layer 506 may correspond to conductive features 502 (eg, Fig. 9 and Fig.18 ), the etch stop layer 527 may correspond to the ESL 204 (as shown in Figure 8 and Fig. 9 ). IMD layer 528 may correspond to first dielectric layer 2060. Although the IMD layer in interconnect structure 520 has a low dielectric constant to reduce parasitic capacitance, nanotubes 40 in the IMD layer provide a vertical heat conduction path to dissipate heat generated at device layer 504 upward and away from device layer 504.

[0052] First reference Fig.32 .like Fig.19 As shown, dumbbell-shaped nanotubes 50 can be fabricated in each IMD layer in the interconnect structure 520. In the illustrated embodiment, the contact features 526 in the first metallization layer 506 can correspond to the conductive features 502 (eg, Fig.19), the etch stop layer 527 may correspond to the ESL 204 (as shown in Fig.18 506). The IMD layer 528 may correspond to the first dielectric layer 2060. Although the IMD layer in the interconnect structure 520 has a low dielectric constant to reduce parasitic capacitance, the dumbbell-shaped nanotubes 50 in the IMD layer provide a horizontal heat conduction path to evenly distribute heat along a horizontal plane (XY plane). The contact components in the interconnect structure 520 are connected to different devices in the device layer 504. Depending on whether the individual devices generate heat, the contact components may not be heated evenly. In addition, some contact components may be pseudo contact components to reduce the load effect and do not provide any circuit function. These pseudo contact components may never heat up due to the heat generated at the device layer 504. The horizontal heat conduction path helps to evenly distribute heat between the contact components in each metallization layer. Fig.32 The IMD layer and dumbbell-shaped nanotubes 50 shown may also be formed by Fig.28 The first multilayer 230 or Fig.29 The first multilayer 230 and the second multilayer 232 both provide a horizontal heat conduction path through the high thermal conductivity layer.

[0053] Therefore, one embodiment of the present invention provides a contact structure. The contact structure includes a conductive component, an etch stop layer (ESL) above the conductive component, a dielectric layer above the ESL, and a contact component extending through the dielectric layer and the ESL to contact the conductive component. The dielectric layer includes a low-k dielectric substrate and nanotubes disposed in the low-k dielectric substrate and configured to reduce the thermal resistance of the dielectric layer.

[0054] In some embodiments, each nanotube comprises an elongated shape. In some embodiments, the nanotubes are arranged along a vertical direction. In some embodiments, each nanotube comprises diamond, boron nitride, silicon carbide, beryllium oxide, boron phosphide, aluminum nitride, beryllium sulfide, boron arsenide, gallium nitride, aluminum phosphide, gallium phosphide, aluminum oxide, or graphene. In some embodiments, the low-k dielectric substrate comprises carbon-doped quartz glass.

[0055] In another embodiment, a method is provided. The method includes depositing an etch stop layer (ESL) over a metal feature, depositing a solution comprising a solvent, a low-k dielectric precursor, and at least one high thermal conductivity particle over the ESL, treating the solution to self-aggregate the at least one high thermal conductivity particle, curing the solution to form a low-k dielectric layer over the ESL, forming an opening through the low-k dielectric layer and the ESL, depositing a conductive material in the opening, and performing planarization to expose a top surface of the low-k dielectric layer.

[0056] In some embodiments, according to the method of claim 1, wherein the at least one high thermal conductivity particle comprises diamond, boron nitride, silicon carbide, beryllium oxide, boron phosphide, aluminum nitride, beryllium sulfide, boron arsenide, gallium nitride, aluminum phosphide, gallium phosphide, aluminum oxide or graphene. In some embodiments, after treatment, at least one high thermal conductivity particle is arranged into a nanotube. In some embodiments, the deposition of the solution comprises spin coating or flowable chemical vapor deposition (FCVD). In some cases, the treatment comprises a first annealing process. In some embodiments, the treatment further comprises applying an electric field or a magnetic field. In some embodiments, the curing comprises a second annealing process. The first annealing process comprises a first annealing temperature, and the second annealing process comprises a second annealing temperature greater than the first annealing temperature. In some embodiments, the method further comprises depositing a hard mask dielectric layer over the low-k dielectric layer before forming the opening. The hard mask dielectric layer comprises silicon oxide.

[0057] In another embodiment, a method is provided. The method includes depositing an etch stop layer (ESL) over a metal feature, forming a low-k dielectric layer over the ESL, wherein the low-k dielectric layer includes nanotubes aligned in a direction, forming an opening through the low-k dielectric layer and the ESL, depositing a conductive material in the opening, and performing planarization to expose a top surface of the low-k dielectric layer.

[0058] In some embodiments, the formation of the low-k dielectric layer includes depositing a solution comprising a low-k dielectric precursor and at least one high thermal conductivity particle above the ESL, treating the solution to self-aggregate the at least one high thermal conductivity particle to form nanotubes, and curing the solution to form a low-k dielectric layer above the ESL. In some cases, the at least one high thermal conductivity particle includes diamond, boron nitride, silicon carbide, beryllium oxide, boron phosphide, aluminum nitride, beryllium sulfide, boron arsenide, gallium nitride, aluminum phosphide, gallium phosphide, aluminum oxide, or graphene. In some embodiments, the deposition of the solution includes spin coating or flowable chemical vapor deposition (FCVD). In some embodiments, the formation of the low-k dielectric layer includes depositing a solution comprising a low-k dielectric precursor and at least one high thermal conductivity particle on the ESL, injecting nanotubes into the low-k dielectric precursor, and curing the low-k dielectric precursor. In some embodiments, the formation of the low-k dielectric layer includes depositing a solution including a low-k dielectric precursor and at least one high thermal conductivity particle over the ESL, injecting nanoparticles into the low-k precursor through a nozzle to form the at least one high thermal conductivity particle into nanotubes, and curing the low-k dielectric precursor. In some embodiments, the direction is perpendicular to the top surface of the metal component.

[0059] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can be subjected to various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

Claims

1. A contact structure comprising: Conductive parts; an etch stop layer (ESL) disposed above the conductive feature; a dielectric layer located above the etch stop layer; as well as a contact feature extending through the dielectric layer and the etch stop layer to contact the conductive feature, Wherein, the dielectric layer comprises: low-k dielectric substrates, and Nanotubes are disposed in the low-k dielectric substrate and are configured to reduce thermal resistance of the dielectric layer.

2. The contact structure according to claim 1, wherein: Each of the nanotubes includes an elongated shape.

3. The contact structure according to claim 2, wherein: The nanotubes are arranged in a vertical direction.

4. A method for forming a contact structure, comprising: depositing an etch stop layer (ESL) over the metal features; depositing a solution over the etch stop layer, the solution comprising: Solvents, low-k dielectric precursors, and at least one type of high thermal conductivity particle; treating the solution to cause self-aggregation of the at least one highly thermally conductive particle; curing the solution to form a low-k dielectric layer on the etch stop layer; forming an opening through the low-k dielectric layer and the etch stop layer; depositing a conductive material in the opening; and Planarization is performed to expose a top surface of the low-k dielectric layer.

5. The method according to claim 4, wherein: The at least one high thermal conductivity particle includes diamond, boron nitride, silicon carbide, beryllium oxide, boron phosphide, aluminum nitride, beryllium sulfide, boron arsenide, gallium nitride, aluminum phosphide, gallium phosphide, aluminum oxide or graphene.

6. The method according to claim 4, wherein: After said treatment, said at least one highly thermally conductive particle is aligned to form nanotubes.

7. The method according to claim 4, wherein: Deposition of the solution includes spin coating or flowable chemical vapor deposition (FCVD).

8. A method for forming a contact structure, comprising: depositing an etch stop layer (ESL) over the metal features; forming a low-k dielectric layer over the etch stop layer, wherein the low-k dielectric layer comprises nanotubes aligned in a direction; forming an opening through the low-k dielectric layer and the etch stop layer; depositing a conductive material in the opening; and Planarization is performed to expose a top surface of the low-k dielectric layer.

9. The method according to claim 8, wherein: The forming of the low-k dielectric layer comprises: depositing a solution over the etch stop layer, the solution comprising: low-k dielectric precursors, and at least one type of high thermal conductivity particle; treating the solution to cause the at least one highly thermally conductive particle to self-aggregate to form the nanotubes; and The solution is cured to form a low-k dielectric layer over the etch stop layer.

10. The method according to claim 9, wherein: The at least one high thermal conductivity particle includes diamond, boron nitride, silicon carbide, beryllium oxide, boron phosphide, aluminum nitride, beryllium sulfide, boron arsenide, gallium nitride, aluminum phosphide, gallium phosphide, aluminum oxide or graphene.

Images