Semiconductor device backside power distribution network structure and manufacturing method thereof

Abstract

The invention relates to a semiconductor device backside power distribution network structure and a manufacturing method thereof. Novel tools and techniques are provided for implementing semiconductor or chip packages, and more particularly, methods, systems, and apparatus are provided for implementing semiconductor or chip packages including a backside power distribution network. In various embodiments, an apparatus includes a first substrate including a device configured to receive a voltage and a first side positioned on a front side of the first substrate and a second side disposed on a back side of the first substrate; a second substrate, the second substrate being configured to support the first substrate; and a power distribution network positioned at an interface between the second side of the first substrate and the second substrate.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0003] The present disclosure generally relates to methods, systems, and apparatus for implementing semiconductor packaging or chip packaging. Background Art

[0004] In existing semiconductor devices, a power distribution network (e.g., a front-side power distribution network) is typically positioned on the front side of a substrate on a top metal layer. Then, power is transmitted from the power distribution network positioned on the top metal layer to the front-end process active device positioned below the metal layer. However, this power transmission path to the front-end process active device has several problems. The top metal layer that the current must travel through before reaching the front-end process active device causes a significant voltage drop, also known as an IR drop. As the IR drop increases, a large amount of power is wasted along the current path through the top metal layer. In addition, it is difficult to maintain power integrity with a long transmission path through the top metal layer. In addition, the power rails and / or power lines must be placed side by side with the signal lines within the top metal layer. Placing the power rails and / or power lines side by side with the signal lines limits the size that the semiconductor can be reduced, because the reduction in unit size is limited by the size of the power rails and / or power lines within each unit. In some cases, placing the power lines side by side with the signal lines further causes interference within the signal lines.

[0005] Therefore, there is a need for more robust and scalable solutions to implement semiconductor packaging and chip packaging.Accordingly, methods, systems, and apparatus for implementing semiconductor packaging or chip packaging including a backside power distribution network in a semiconductor device are provided. Summary of the invention

[0006] In one aspect, the present disclosure relates to an apparatus comprising: a first substrate comprising a first device configured to receive a voltage, a first side disposed on a front face of the first substrate, and a second side disposed on a back face of the first substrate; a second substrate configured to support the first substrate; and a power distribution network disposed at an interface between the second side of the first substrate and the second substrate.

[0007] In another aspect, the present disclosure relates to a method of manufacturing a backside power distribution network of a semiconductor device, the method comprising: forming at least one of a first substrate or a second substrate including a device configured to receive a voltage, wherein the second substrate is configured to support the first substrate; and forming a power distribution network, the power distribution network being configured to be disposed at an interface between the first substrate and the second substrate.

[0008] In another aspect, the present disclosure relates to a semiconductor device comprising: a first substrate comprising a device configured to receive a voltage; a metal layer coupled to a first side of the first substrate; a second substrate coupled to a second side of the first substrate opposite to the metal layer and the first side, the second substrate being configured to support the first substrate; and a power distribution network disposed between the second side of the first substrate and the second substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A further understanding of the nature and advantages of certain embodiments may be achieved by reference to the remainder of the specification and the accompanying drawings, in which like reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to indicate one of multiple similar components. When reference is made to a reference numeral without specifying an existing sub-label, it is intended to refer to all such multiple similar components.

[0010] Figure 1 is a schematic cross-sectional view of a semiconductor device having a backside power distribution network according to various embodiments;

[0011] Figure 2 is a schematic cross-sectional view of a semiconductor device having a backside power distribution network according to various embodiments;

[0012] Figure 3 is a schematic cross-sectional view of a semiconductor device having a backside power distribution network according to various embodiments;

[0013] Figure 4 is a schematic cross-sectional view of a semiconductor device having a backside power distribution network according to various embodiments;

[0014] Figure 5 is a schematic cross-sectional view of a memory device according to various embodiments;

[0015] Figure 6 is a schematic cross-sectional view of a semiconductor device having a backside power distribution network according to various embodiments;

[0016] Figure 7 is a flow chart of a method of manufacturing a semiconductor device having a backside power distribution network according to various embodiments;

[0017] Figure 8is a flow chart of a method of manufacturing a semiconductor device having a backside power distribution network according to various embodiments;

[0018] Fig. 9 is a flow chart of a method of manufacturing a semiconductor device having a backside power distribution network according to various embodiments; and

[0019] Fig.10 is a flow chart of a method of manufacturing a semiconductor device having a backside power distribution network according to various embodiments. DETAILED DESCRIPTION

[0020] Various embodiments provide tools and techniques for implementing a semiconductor package or chip package that includes a backside power distribution network.

[0021] In a first aspect, an apparatus comprises: a first substrate comprising a first device configured to receive a voltage, a first side disposed on a front surface of the first substrate, and a second side disposed on a back surface of the first substrate; a second substrate configured to support the first substrate; and a power distribution network disposed at an interface between the second side of the first substrate and the second substrate.

[0022] In some embodiments, the first substrate includes single crystal silicon, and the second substrate includes single crystal silicon, polycrystalline silicon, silicon carbide, glass, sapphire, or gallium arsenide.

[0023] In some cases, the first device configured to receive the voltage includes a transistor.

[0024] In various cases, the power distribution network is directly coupled to the second side of the first substrate and to the second substrate.

[0025] In various embodiments, the first substrate further includes a first connector coupled to a power source and a power distribution network and a second connector coupled to the power distribution network and the first device of the first substrate. A ratio of a first diameter of the first connector to a second diameter of the second connector may be between about 3:1 and 20:1. In some cases, at least one of the first connector or the second connector includes a through hole or a groove.

[0026] In some cases, a ratio of the first thickness of the first substrate to the second thickness of the second substrate is between about 1:200 and 1:10.

[0027] In some cases, the apparatus further includes a third substrate between the power distribution network and the first substrate, and the third substrate couples the power distribution network to the first substrate. The third substrate may further include a first connector coupled to a power source and the power distribution network and a second connector coupled to the power distribution network and the first device of the first substrate.

[0028] In various cases, the second substrate further includes a second device configured to provide non-volatile memory. The first substrate may further include circuitry toward the second side of the first substrate. The circuitry may be configured to control current.

[0029] In another aspect, a method of manufacturing a backside power distribution network of a semiconductor device includes: forming at least one of a first substrate or a second substrate, the first substrate including a device configured to receive a voltage, wherein the second substrate is configured to support the first substrate; and forming a power distribution network configured to be disposed at an interface between the first substrate and the second substrate.

[0030] In some cases, forming a power distribution network disposed at an interface between the first substrate and the second substrate includes forming the power distribution network on a back side of the first substrate.Once the power distribution network is formed on the first substrate, the method further includes bonding the first substrate to the second substrate.

[0031] In various embodiments, forming a power distribution network disposed at an interface between the first substrate and the second substrate includes forming the power distribution network on the second substrate.Once the power distribution network is formed on the second substrate, the method further includes bonding the first substrate to the second substrate.

[0032] In some examples, forming a power distribution network disposed at an interface between a first substrate and a second substrate includes forming a third substrate and forming a power distribution network on the third substrate. The third substrate further includes a connector configured to couple the device of the first substrate with the power distribution network. Once the power distribution network is formed on the third substrate, the method further includes bonding the first substrate to the third substrate and bonding the second substrate to the third substrate. The power distribution network may be between the second substrate and the third substrate.

[0033] In yet another aspect, a semiconductor device includes: a first substrate comprising a device configured to receive a voltage; a metal layer coupled to a first side of the first substrate; a second substrate coupled to a second side of the first substrate opposite to the metal layer and the first side, the second substrate configured to support the first substrate; and a power distribution network disposed between the second side of the first substrate and the second substrate.

[0034] In the following description, for the purpose of explanation, many details are set forth in order to provide a thorough understanding of the described embodiments. However, it will be appreciated by those skilled in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, and although various features are attributed to different embodiments, it will be appreciated that features described with respect to one embodiment may also be combined with other embodiments. However, for the same reason, any single feature or multiple features of any described embodiment should not be considered as necessary for each embodiment of the present invention, as other embodiments of the present invention may omit such features.

[0035] When an element is referred to herein as being "connected," "coupled," or "attached" to another element, it is understood that the element may be directly connected to the other element, or there may be an intervening element between the elements. In contrast, when an element is referred to as being "directly connected," "directly coupled," or "directly attached" to another element, it is understood that there are no intervening elements in a "direct" connection between the elements. However, the presence of a direct connection does not exclude other connections in which there may be intervening elements.

[0036] When an element is referred to herein as being "positioned" or "located" in some manner relative to another element (e.g., positioned on, between, below, adjacent, or in some other relative manner), it is understood that the element may be directly positioned or located relative to the other element (e.g., directly on the other element) or that there may be intervening elements between the elements. In contrast, when an element is referred to as being "directly positioned" or "directly located" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct placement does not exclude other instances in which there may be intervening elements.

[0037] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include intervening elements that exist between the coupled or connected layers. In contrast, when an element is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intervening elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections in which intervening elements may exist.

[0038] In addition, the terms left, right, front, back, top, bottom, forward, backward, clockwise, and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0039] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context dictates otherwise, intervening processes may occur before and / or after any portion of the described processes, and various additional processes may be reordered, added, and / or omitted according to various embodiments.

[0040] Unless otherwise indicated, all numbers used herein to express quantities, dimensions, etc., should be understood as being modified in all instances by the term "approximately." As used herein, the term "substantially" or "approximately" refers to a variation of ±10% or less (e.g., ±10%, ±5%, etc.) relative to a reference value or ratio, including the endpoints of the range.

[0041] In this application, unless specifically stated otherwise, the use of the singular includes the plural, and the use of the terms "and" and "or" means "and / or" unless otherwise indicated. Furthermore, the use of the terms "including" and "having" and other forms (such as "includes / included", "has / have and had") should be taken as non-exclusive. Also, unless specifically stated otherwise, terms such as "element" or "component" encompass both elements and components comprising one unit and elements and components comprising more than one unit.

[0042] As used herein, the phrase "at least one of..." preceding a series of items (where the terms "and" or "or" are used to separate any of the items) modifies the entire list, rather than each member of the list (i.e., each item). The phrase "at least one of..." does not require selection of at least one of each item listed; rather, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of items. For example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In instances where it is desired to select "at least one of each of A, B, and C," or, alternatively, "at least one of A, at least one of B, and at least one of C," it is explicitly described as such.

[0043] In existing semiconductor or chip packages, a power distribution network ("PDN") that powers one or more front-end-of-line ("FEOL") active devices is typically located on the front side of a semiconductor substrate on a top metal layer. However, this power delivery path to the front-end active devices has several problems. The top metal layer that the current must travel through before reaching the front end of the FEOL active devices can cause a significant voltage drop, also known as IR drop. As the IR drop increases, a large amount of power is wasted along the current path through the top metal layer. Furthermore, as semiconductor packages become more complex, power rails and / or power lines compete for space and limit the size to which semiconductor devices can be reduced, because cell size reduction can be limited by the size of the power rails and / or power lines within each cell.

[0044] The present technology includes a semiconductor or chip device (e.g., an integrated circuit (IC), chip, or other semiconductor device or module) that provides a backside power distribution network ("PDN") at the interface of a first substrate and a second substrate. By implementing a backside PDN at the interface of the first substrate and the second substrate, the power transmission path to the FEOL active device can be shorter, thereby achieving a reduction in IR drop. In addition, the size of the semiconductor device can be reduced because the power rail does not need to be as large as the PDN located on the front side of the semiconductor device.

[0045] Figures 1 to 4 6 are schematic cross-sectional views of different embodiments of the semiconductor device 100 according to various embodiments. It should be noted that the various components of the semiconductor device 100 are shown in FIG. Figures 1 to 4 Modifications to various components, orientations, and other arrangements of semiconductor device 100 are possible and are in accordance with various embodiments, as schematically illustrated in FIGS. Figures 1 to 4 6 only show some components and / or layers of the semiconductor device 100. According to various embodiments, there may be more or fewer components and / or layers, and the semiconductor device 100 is not intended to be limited to only the components and / or layers shown. Figures 1 to 4 6 are described as separate embodiments, but one of ordinary skill in the art will appreciate that various modifications to each embodiment may be applied to the other embodiments.

[0046] In various embodiments, semiconductor device 100 includes a first substrate (or wafer) 105. First substrate 105 includes a support material (e.g., single crystal silicon and / or any other semiconductor material or combination of materials) on which elements or components (e.g., connectors, passive devices, active devices, or the like) of semiconductor device 100 are fabricated or coupled. In some cases, first substrate 105 is single crystal silicon. In various examples, first substrate 105 may be doped with p-type dopants (e.g., boron or the like) and / or n-type dopants (e.g., phosphorus, arsenic, or the like). In various cases, first substrate 105 may be formed of one or more layers. One or more layers may include, but are not limited to, one or more dielectric layers, one or more device layers, one or more conductive layers, one or more insulating layers, one or more redistribution layers, and / or the like.

[0047] In some cases, first substrate 105 may include one or more passive or active devices 110. The one or more passive devices may be one or more circuit components (e.g., conductors, resistors, capacitors, inductors, etc.) that can transmit, absorb and / or dissipate power. The one or more active devices may be one or more circuit components (e.g., transistors or the like) that can control the flow of power. In various examples, first substrate 105 may be an active substrate (e.g., a substrate having one or more active devices such as transistors).

[0048] The one or more passive or active devices 110 may include, but are not limited to, one or more capacitors, one or more inductors, one or more transistors, one or more field programmable gate arrays (FPGAs), one or more memory devices, one or more micro-electromechanical systems (MEMS), or the like. The passive or active devices 110 may be arranged as complementary metal oxide semiconductor ("CMOS") circuits, radio frequency ("RF") circuits, logic circuits, peripheral circuits, or other types of circuits, and / or the like. In some embodiments, the passive or active devices 110 may include fin field effect transistors (finFETs), metal oxide semiconductor field effect transistors (MOSFETs), or planar transistor devices having gate terminals and source / drain terminals, and the like.

[0049] In various cases, the first substrate 105 includes a first side 115 (e.g., a front side) and a second side 120 (e.g., a back side) opposite the first side 115. In various examples, the first side 115 is the top or front side of the first substrate (where front end of line (FEOL) fabrication ends), and the second side 120 is the bottom or back side of the first substrate 105. FEOL fabrication is the first part of integrated circuit fabrication, where one or more passive or active devices 110 are patterned in the first substrate 105 of the semiconductor device 100.

[0050] In some cases, the first side 115 of the first substrate 105 may be coupled to or include one or more metal layers 125. The one or more metal layers 125 may be formed using one or more back end of line (“BEOL”) processes. BEOL is the second part of integrated circuit fabrication where one or more wiring or metal layers are deposited to form one or more interconnects between passive or active devices 110 and / or between the passive or active devices 110 and a circuit board (e.g., a printed circuit board) of the semiconductor device 100. The one or more metal layers 125 may include one or more signal lines coupled to the one or more passive or active devices 110. The top layer 130 of the one or more metal layers 125 or a connector on the top layer 130 may be configured to couple to a circuit board, a printed circuit board (“PCB”), or the like.

[0051] In some cases, semiconductor device 100 further includes a second substrate or wafer 135. In various cases, second substrate 135 can be formed of one or more layers. The one or more layers can include, but are not limited to, one or more dielectric layers, one or more device layers, one or more conductive layers, one or more insulating layers, one or more redistribution layers, and / or the like.

[0052] The second substrate 135 may be a carrier substrate or a support substrate configured to support the first substrate 105. As an example, the term "carrier" or "support" refers to a material or layer that holds, supports, protects and / or provides structural and mechanical rigidity to the first substrate 105 within the package. Depending on the packaging technology and application, there are different types of carriers or support substrates. For example, a carrier according to an embodiment of the present disclosure may include one or more materials, such as single crystal silicon, polycrystalline silicon, gallium arsenide, sapphire, silicon carbide, glass materials, organic materials, ceramic materials and / or other materials configured to carry or support the first substrate 105. In some cases, the second substrate 135 is polycrystalline silicon. Depending on the specific application, the carrier or support substrate may have properties such as heat dissipation capabilities or other features. For example, the second substrate 135 may be designed to provide structural and mechanical rigidity and support for the first substrate 105 within the package. In some cases, first substrate 105 may be an “active” substrate (eg, a substrate that includes one or more active devices 110 ), while second substrate 135 may be a support substrate that supports or carries first substrate 105 .

[0053] In various cases, the first thickness T1 of the first substrate 105 may be about 1.5 μm to about 50 μm, and the second thickness T2 of the second substrate may be about 100 μm to about 800 μm. Preferably, the ratio of the first thickness T1 of the first substrate 105 to the second thickness T2 of the second substrate 135 is between about 1:200 and 1:10.

[0054] The semiconductor device 100 may further include a power distribution network (“PDN”) 140 positioned between the second side 120 of the first substrate 105 and the second substrate 135. In some cases, the PDN 140 is a backside PDN. In other words, the PDN 140 is positioned on the second side 120 or backside of the first substrate 105 opposite the first side 115 of the first substrate 105 and opposite the one or more metal layers 125. In some cases, the PDN 140 may be manufactured together with the first substrate 105. Alternatively, in other cases, the PDN 140 may be manufactured together with the second substrate 135. As described below with respect to Figures 8 to 10 described.

[0055] In some cases, PDN 140 is at the interface between first substrate 105 and second substrate 135. In various cases, PDN 140 can directly contact first substrate 105 and / or second substrate 135.

[0056] The PDN 140 is configured to deliver power to one or more passive or active devices 110 of the first substrate 105. The PDN 140 may be configured to provide power in one or more voltage domains. For example, the PDN 140 may be configured to provide a positive power supply voltage (e.g., VDD) and / or a negative power supply voltage (e.g., VSS, ground (GND) = 0V) to one or more passive or active devices 110 of the first substrate 105. The PDN 140 may include one or more layers (e.g., one or more metal layers, conductive layers, insulating layers, redistribution layers, or other layers). In some cases, the PDN 140 may include one or more components or connectors configured to distribute power to the one or more passive or active devices 110. The one or more components may include, but are not limited to, one or more power lines, one or more redistribution layers (e.g., to reroute connections to desired locations), one or more connectors or interconnects, one or more power rails, and / or the like.

[0057] The one or more connectors may include, but are not limited to, one or more conductive pads, conductive traces, conductive vias, conductive microbumps, conductive solder balls, conductive posts or pillars, and / or other suitable connectors or interconnects. The one or more vias may extend completely through the liner PDN 140 (e.g., a "through" via), may extend through the PDN 140 from an external surface (e.g., a "blind" via), or may extend through a portion of the PDN 140 and be completely hidden from external view (e.g., a "buried" via), and / or the like. The conductive material of the connector may include a metal or a combination of metals / alloys such as copper, tungsten, aluminum, gold, silver, tin, nickel, lead, or may be formed of other conductive materials or combinations of conductive materials. The one or more connectors may be configured to form an electrical connection for passing power to or from the PDN 140.

[0058] In some cases, semiconductor device 100 further includes one or more power rails 145. One or more power rails 145 may include one or more front-end-of-line (“FEOL”) or back-end-of-line (“BEOL”) power rails 145. In other words, power rails 145 may be positioned at an interface between first side 115 of first substrate 105 and a bottom of one or more metal layers 125, positioned within or on top of one or more metal layers 125, and / or positioned within first substrate 105. Although Figure 1 Only one power rail 145 is shown in FIG. 1 , but more power rails 145 may be present.

[0059] The power rail 145 may be configured to receive a voltage (e.g., VDD or VSS) or power from a power source (e.g., a circuit board, a printed circuit board, or another power source configured to provide power) positioned above the one or more metal layers 125. The power rail 145 may then transmit the voltage or power to one or more first connectors or global power posts (“GPPs”) 150. The one or more global power posts 150 may be configured as a global power post array. The one or more GPPs 150 may include, but are not limited to, one or more vias, one or more deep metal trenches, and / or one or more other connectors or interconnects configured to connect the power rail 145 to the PDN 140, or one or more components configured to distribute power through the PDN 140. The one or more vias, one or more deep metal trenches, and / or one or more other interconnects or connectors may be formed of a metal or combination of metals / alloys such as copper, tungsten, titanium, aluminum, gold, silver, tin, nickel, lead, or may be formed of other conductive materials or combinations of conductive materials. One or more GPPs 150 may extend completely through the first substrate 105 and / or the metal layer 125 (e.g., a “through” via), may extend through the first substrate 105 from an exterior surface (e.g., a “blind” via), or may extend through a portion of the first substrate 105 and be completely hidden from external view (e.g., a “buried” via), and / or the like.

[0060] In some cases, the first substrate 105 of the semiconductor device 100 includes one or more second connectors or second power posts 155. The one or more second power posts 155 may be configured as a power post array. The one or more second power posts 155 may include, but are not limited to, one or more through-holes, deep metal trenches, and / or one or more other interconnects or connectors configured to connect the PDN 140 and / or one or more components of the PDN 140 to one or more passive or active devices 110. The one or more through-holes, the one or more deep metal trenches, and / or the one or more other interconnects or connectors may be formed of a metal or a combination of metals / alloys such as copper, tungsten, titanium, aluminum, gold, silver, tin, nickel, lead, or may be formed of other conductive materials or combinations of conductive materials. One or more second power posts 155 may extend completely through the first substrate 105 (e.g., a “through” via), may extend through the first substrate 105 from an exterior surface (e.g., a “blind” via), or may extend through a portion of the first substrate 105 and be completely hidden from external view (e.g., a “buried” via), and / or the like.

[0061] In various cases, the diameter of the GPP 150 may be larger than the diameter of the second power column 155 in order to more efficiently transmit power or current. In a non-limiting example, the diameter of the GPP 150 may be about 30 nm to about 20 μm, while the diameter of the second power column 155 may be about 50 nm to about 5 μm. Preferably, the ratio of the first diameter of the GPP 150 to the second diameter of the second power column 155 is between about 3:1 and 20:1.

[0062] In some cases, power or voltage may be transmitted through semiconductor device 100 from a power source to power rail 145 to GPP 150 to PDN 140 to second power column 155 to one or more active devices 110 .

[0063] In another embodiment, if Figure 2As shown, the first substrate 105 may include one or more buried power connectors 160. The one or more buried power connectors 160 may be coupled to one or more GPPs 150, PDN 140, one or more second power pillars 155, one or more connectors of the first substrate 105, one or more passive or active devices 110, or the like. The one or more buried power connectors 160 may include, but are not limited to, one or more through-holes, one or more trenches (e.g., one or more insulating trenches), and / or one or more other interconnects capable of transmitting voltage from the PDN 140 to the one or more passive or active devices 110, or the like. The one or more buried power connectors 160 may be formed of a metal or combination of metals / alloys such as copper, tungsten, titanium, aluminum, gold, silver, tin, nickel, lead, or may be formed of other conductive materials or combinations of conductive materials. In some cases, the one or more buried power connectors 160 may be coupled to the one or more second power posts 155 at an interface between the PDN 140 and the first substrate 105, as shown by buried power connector 160a, at an interface between one or more passive or active devices 110 and the second power posts 155, as shown by buried power connector 160b, and / or at an interface between the second power posts 155 and an interconnect 162 (e.g., a through-hole) of the first substrate 105, as shown by buried power connector 160c. In some cases, the one or more buried power connectors 160 may be directly coupled to the one or more passive or active devices 110, as shown by buried power connector 160d. In some cases, the width of buried power connector 160 is between about 0.02 μm and about 2 μm, and the height of buried power connector 160 is between about 0.1 μm and about 10 μm.

[0064] In another embodiment, if Figure 3 As shown, one or more GPPs 150 and / or second power pillars 155 can be integrated within a third substrate or layer 165. The third substrate 165 can be an intervening substrate or layer (e.g., a substrate or layer configured to provide one or more connections or interconnections (e.g., electrical connections or the like) between the PDN 140 and the first substrate 105 and / or one or more passive or active devices 110 of the first substrate 105).

[0065] The third substrate 165 may be formed of single crystal silicon, polycrystalline silicon, organic materials, glass materials, ceramic materials, and / or other materials. In some cases, the third substrate 165 may be formed of polycrystalline silicon. In various cases, the third substrate 165 may be formed of one or more layers. The one or more layers may include, but are not limited to, one or more dielectric layers, one or more device layers, one or more conductive layers, one or more insulating layers, one or more redistribution layers, and / or the like.

[0066] In some cases, PDN 140 is at the interface between third substrate 165 and second substrate 135. PDN 140 can directly contact third substrate 165 and / or second substrate 135. In various cases, PDN 140 can be manufactured with second substrate 135 or with third substrate 165.

[0067] In various cases, the first thickness T1 of the first substrate 105 may be about 1.5 μm to about 50 μm, the second thickness T2 of the second substrate 135 may be about 100 μm to about 800 μm, and the third thickness T3 of the third substrate 165 may be about 10 μm to about 50 μm. Preferably, the ratio of the first thickness T1 of the first substrate 105 to the third thickness T3 of the third substrate 165 is between about 1:20 and 1:5. Preferably, the ratio of the second thickness T2 of the second substrate 135 to the third thickness T3 of the third substrate 165 is between about 80:1 and 10:1.

[0068] When one or more GPPs 150 and / or one or more second power posts 155 are integrated within the third substrate 165, one or more buried power connectors 160 may be exposed on the first substrate 105 to engage with the one or more GPPs 150 and / or one or more second power posts 155 of the third substrate 165. In some cases, the one or more buried power connectors 160 are directly coupled to one or more passive or active devices 110, as shown by buried power connector 160a. Alternatively, in other cases, the one or more buried power connectors 160 are indirectly coupled to one or more passive or active devices 110, as shown by buried power connector 160b.

[0069] In some cases, one or more active or passive devices 170 may be integrated into the second substrate 135, such as Figure 4 The one or more active or passive devices 170 may include, but are not limited to, nonvolatile memory such as flash memory. For example, when the second substrate 135 is formed of polysilicon, the second substrate 135 may be used to form a Figure 5 Flash memory 500 is shown. Flash memory 500 may include a metal gate 502 configured to be coupled to PDN 140, source and / or drain regions 504, and a gate stack 506. Gate stack 506 may be disposed within the polysilicon of second substrate 135 and formed of a first silicon dioxide layer 508, a silicon nitride layer 510, and a second silicon dioxide layer 512.

[0070] In some embodiments, Figure 6As shown, the back side of the first substrate 105 can be used to form one or more current control circuits 175 on or toward the second side 120 of the first substrate 105. The one or more current control circuits 175 can control the voltage when the voltage is transmitted through the PDN 140, the GPP 150, the second power column 155, and / or the like. In some cases, the interconnect layer on the first side 115 of the first substrate 105 can be formed using a 16nm, 7nm, 5nm or lower node manufacturing or lithography process, while the interconnect layer on the second side 120 of the first substrate 105 can be formed using a 40nm, 130nm, 180nm or higher node manufacturing or lithography process. The one or more current control circuits 175 can be formed using a 40nm, 130nm, 180nm or higher node manufacturing or lithography process.

[0071] Figures 7 to 10 is a flow chart of a method of manufacturing the semiconductor device 100 according to various embodiments. Figure 7 is a flow chart of a method of manufacturing a semiconductor device 100 having a PDN 140 formed on a second side of a first substrate 105 . Figure 8 is a flow chart of a method of manufacturing a semiconductor device 100 having a PDN 140 formed on a second substrate 135 . Fig. 9 is a flow chart of a method of manufacturing a semiconductor device 100 having a PDN 140 formed on a second substrate 135 and a GPP and / or one or more power pillars formed in a third substrate 165 . Fig.10 is a flow chart of a method of manufacturing the semiconductor device 100 having the PDN 140 formed on the third substrate 165 .

[0072] Go to Figure 7 , method 700 may begin at block 705 by providing or forming a first substrate (e.g., first substrate 105 or the like). Forming the first substrate may include, but is not limited to, various additive and / or subtractive manufacturing processes known to those skilled in the art. In further examples, the substrate may be formed using manufacturing technologies that are being developed and / or have not yet been developed. Therefore, it should be understood that method 700 is not limited to any particular method of manufacturing the first substrate.

[0073] In some cases, forming the first substrate may include forming one or more GPPs (e.g., GPP 150 or the like) and / or one or more power pillars (e.g., second power pillar 155 or the like) in the back side of the first substrate at block 710. In a non-limiting example, the one or more GPPs and / or the one or more power pillars may be formed by drilling one or more openings in the back side of the first substrate and filling the one or more openings with a conductive material (e.g., copper, tungsten, or other conductive material).

[0074] Next, at optional block 715, one or more buried power connectors (e.g., buried power connector 160) may optionally be formed in the first substrate. In a non-limiting example, the one or more buried power connectors may be formed by drilling one or more openings in the back side of the first substrate and filling the one or more openings with a conductive material (e.g., copper, tungsten, or other conductive material). In some cases, the one or more buried power connectors may be coupled to one or more GPPs, one or more power columns, and / or one or more passive or active devices (e.g., passive or active device 110).

[0075] Next, at block 720, the first substrate 105 may be fabricated or processed with one or more front-end-of-line (FEOL) processes. The FEOL process is the first portion of semiconductor device fabrication in which one or more passive or active devices (e.g., passive or active device 110) are patterned in the first substrate. The FEOL typically covers everything up to (but not including) the deposition of a metal interconnect layer (e.g., metal layer 125 or the like). The FEOL process may include, but is not limited to, trench isolation, well formation, gate formation, source and drain formation, and / or the like.

[0076] In some embodiments, once the first substrate has been processed with one or more FEOL processes, then at block 725, one or more back-end-of-line (BEOL) manufacturing processes may occur. The one or more BEOL processes are the second portion of semiconductor device fabrication in which one or more passive or active devices are interconnected with wiring. The BEOL typically begins when a first metal layer (e.g., metal layer 125) is deposited on the first substrate. The BEOL includes, but is not limited to, forming contacts, insulating layers (dielectrics), metal layers, vias, and bonding sites for chip-to-package connections, and / or the like.

[0077] In some cases, one or more current control circuits (e.g., current control circuit 175 or the like) can be formed on the back side of the first substrate. In some cases, the first side of the first substrate can be formed using 16 nm, 7 nm, 5 nm, or lower node manufacturing or lithography processes, while the second side 120 of the first substrate 105 can be formed using 40 nm, 130 nm, 180 nm, or higher node manufacturing or lithography processes. The one or more current control circuits can be formed using 40 nm, 130 nm, 180 nm, or higher node manufacturing or lithography processes.

[0078] The method 700 continues at block 730 by thinning the first substrate 105 to expose one or more GPPs and / or one or more power pillars and / or to expose one or more buried power connectors to couple to the PDN.

[0079] Then, a second substrate may be formed. In some cases, the second substrate may be formed in parallel (e.g., simultaneously) with the first substrate. In some cases, the second substrate may be formed at a different location or at a different time than the first substrate. Method 700 may include providing or forming a second substrate at block 735. Forming the second substrate may include, but is not limited to, various additive and / or subtractive manufacturing processes known to those skilled in the art. In further examples, the substrate may be formed using manufacturing technologies that are being developed and / or have not yet been developed. Therefore, it should be understood that method 700 is not limited to any particular method of manufacturing the second substrate.

[0080] In some cases, one or more active or passive devices (e.g., active or passive device 170) may be formed in the second substrate before the PDN is fabricated on the second substrate. For example, the one or more active or passive devices may include a memory device (e.g., flash memory). By fabricating the one or more active or passive devices within the second substrate, the second substrate may be used and free up space for other active or passive devices on the first substrate.

[0081] In some cases, forming the second substrate may include forming a PDN (e.g., PDN 140 or the like) on the second substrate at block 740. By forming the PDN on the second substrate, the first substrate including one or more active and passive devices does not need to undergo as many manufacturing steps, which reduces the likelihood that the first substrate will be damaged or destroyed.

[0082] Next, at optional block 745, the second substrate may optionally be thinned.

[0083] Finally, once the first and second substrates are fabricated, the first and second substrates may be bonded together using a wafer or substrate bonding technique at step 750, wherein the PDN is located at the interface between the first and second substrates. The PDN may be coupled to the back side of the first substrate and to one or more GPPs, one or more power posts, and / or one or more buried power connectors of the first substrate. The one or more wafer or substrate bonding techniques may include, but are not limited to, direct bonding, surface activated bonding, plasma activated bonding, anodic bonding, eutectic bonding, glass frit bonding, adhesive bonding, thermocompression bonding, reaction bonding, transient liquid phase diffusion bonding, atomic diffusion bonding, and / or the like.

[0084] Go to Figure 8 , method 800 may begin at block 805 by providing or forming a first substrate. This step may be similar to Figure 7 In some cases, forming the first substrate may include forming one or more GPPs and / or one or more power columns in the back side of the first substrate at block 810. This step may be similar to Figure 7Next, at optional block 815, one or more buried power connectors may be formed in the first substrate, similar to Figure 7 At block 820, the first substrate may be fabricated using one or more FEOL processes. This step may be similar to Figure 7 In some embodiments, once the first substrate is fabricated using one or more FEOL processes, then at block 825, one or more BEOL processes may occur. This step may be similar to Figure 7 The method 800 continues at block 830 by thinning the first substrate to expose one or more GPPs, one or more power posts, and / or one or more buried power connectors. This step may be similar to Figure 7 Step 730.

[0085] The method 800 may include forming or fabricating a PDN on the back side of the first substrate at block 835 , and coupling the PDN to one or more GPPs, one or more power columns, and / or one or more buried power connectors of the first substrate.

[0086] Then, a second substrate may be formed. In some cases, the second substrate may be formed in parallel with the first substrate. In some cases, the second substrate may be formed at a different location or time than the first substrate. Method 800 may include providing or forming a second substrate at block 840. This step may be similar to Figure 7 Next, in step 845 (similar to Figure 7 Step 745) optionally thins the second substrate.

[0087] Finally, once the first and second substrates are formed, the first and second substrates may be bonded together using wafer or substrate bonding techniques at step 850, wherein the PDN is located at the interface between the first and second substrates. This step may be similar to Figure 7 Step 750.

[0088] Go to Fig. 9 , method 900 may begin at block 905 by providing or forming a first substrate. This step may be similar to Figure 7 Step 705 or Figure 8 In some cases, forming the first substrate may include forming one or more buried power connectors at block 910, similar to Figure 7 Optional box 715 or Figure 8 At block 915, the first substrate may then be manufactured using one or more FEOL processes. This step may be similar to Figure 7 Step 720 or Figure 8In some embodiments, once the first substrate is fabricated using one or more FEOL processes, then at block 920, one or more BEOL processes may occur. This step may be similar to Figure 7 Step 725 or Figure 8 Step 825. Method 900 continues at block 925 by thinning the first substrate to expose one or more buried power connectors. This step may be similar to Figure 7 Step 730 or Figure 8 Step 830.

[0089] Then, a second substrate may be formed. In some cases, the second substrate may be formed in parallel with the first substrate. In some cases, the second substrate may be formed at a different location or time than the first substrate. Method 900 may include providing or forming a second substrate at block 930. This step may be similar to Figure 7 Step 735 or Figure 8 In some cases, forming the second substrate may include forming a PDN on the second substrate at block 935. This step may be similar to Figure 7 Next, the second substrate (similar to Figure 7 Step 745 or Figure 8 Step 845).

[0090] In some cases, a third substrate (e.g., third substrate 165 or the like) may be formed. In some cases, the third substrate may be formed in parallel with the first substrate and / or the second substrate. In some cases, the second substrate may be formed at a different location or time than the first substrate and / or the second substrate. Method 900 may include providing or forming a third substrate at block 945. Forming the third substrate may include, but is not limited to, various additive and / or subtractive manufacturing processes known to those skilled in the art. In further examples, the third substrate may be formed using manufacturing technologies that are being developed and / or have not yet been developed. Therefore, it should be understood that method 900 is not limited to any particular method of manufacturing the third substrate.

[0091] In some cases, forming the third substrate may include forming one or more GPPs (e.g., GPP 150 or the like) and / or one or more power pillars (e.g., second power pillar 155 or the like) extending through the third substrate at block 940. In a non-limiting example, the one or more GPPs and / or the one or more power pillars may be formed by drilling one or more openings in the third substrate and filling the one or more openings with a conductive material (e.g., copper, tungsten, or other conductive material). Next, the third substrate may be thinned at step 945 to expose the one or more GPPs and / or power pillars.

[0092] Finally, once the first, second, and third substrates are formed, the first and third substrates may be bonded together using a wafer or substrate bonding technique, and the second and third substrates may be bonded together using a wafer or substrate bonding technique at step 960. When the first, third, and second substrates are bonded together, the PDN is located at the interface between the second and third substrates and is coupled to one or more GPPs and / or power columns.

[0093] Go to Fig.10 , method 1000 may begin at block 1005 by providing or forming a first substrate. This step may be similar to Figure 7 Step 705, Figure 8 Step 805 or Fig. 9 In some cases, forming the first substrate may include forming one or more buried power connectors at block 1010, similar to Figure 7 Optional box 715, Figure 8 Optional box 815 or Fig. 9 At block 1015, the first substrate may then be fabricated using one or more FEOL processes. This step may be similar to Figure 7 Step 720, Figure 8 Step 820 or Fig. 9 In some embodiments, once the first substrate is fabricated using one or more FEOL processes, then at block 1020, one or more BEOL processes may occur. This step may be similar to Figure 7 Step 725, Figure 8 Step 825 or Fig. 9 Step 920. The method 1000 continues at block 1025 by thinning the first substrate to expose one or more buried power connectors. This step may be similar to Figure 7 Step 730, Figure 8 Step 830 or Fig. 9 Step 1025.

[0094] Then, a second substrate may be formed. In some cases, the second substrate may be formed in parallel with the first substrate. In some cases, the second substrate may be formed at a different location or time than the first substrate. Method 1000 may include providing or forming a second substrate at block 1030. This step may be similar to Figure 7 Step 735, Figure 8 Step 840 or Fig. 9 Next, the second substrate (similar to Figure 7 Step 745, Figure 8 Step 845 or Fig. 9 Step 940).

[0095] Additionally, a third substrate may be formed. In some cases, the third substrate may be formed in parallel with the first substrate and / or the second substrate. In some cases, the second substrate may be formed at a different location or time than the first substrate and / or the second substrate. Method 1000 may include providing or forming a third substrate (similar to Fig. 9 In some cases, forming the third substrate may include forming one or more GPPs and / or one or more power pillars extending through the third substrate at block 1045 (similar to Fig. 9 Next, the third substrate may be thinned at step 1050 to expose one or more GPPs and / or power pillars (similar to Fig. 9 In addition, the method 1000 may further include forming a PDN on the third substrate at block 1055. The PDN may be coupled to one or more GPPs and / or power columns of the third substrate.

[0096] Finally, once the first, second, and third substrates are formed, the first and third substrates may be bonded together using a wafer or substrate bonding technique, and the second and third substrates may be bonded together using a wafer or substrate bonding technique at step 1060. When the first, third, and second substrates are bonded together, the PDN is located at the interface between the second and third substrates.

[0097] As described herein, the techniques and processes described above with respect to various embodiments may be used to manufacture Figures 1 to 6 A semiconductor device 100 and / or its components.

[0098] Although some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that many modifications are possible. For example, the methods and processes described herein may be implemented using hardware components, custom integrated circuits (ICs), programmable logic, and / or any combination thereof. In addition, although the various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by the various embodiments are not limited to any specific structural and / or functional architecture, but may be implemented in any suitable hardware configuration. Similarly, although some functionality is attributed to one or more system components, unless the context dictates otherwise, according to several embodiments, this functionality may be distributed among various other system components.

[0099] In addition, although the processes of the methods and processes described herein are described in a particular order for ease of description, the various processes may be reordered, added, and / or omitted according to various embodiments unless the context dictates otherwise. In addition, the processes described with respect to one method or process may be incorporated into other described methods or processes; similarly, system components described according to a particular structural architecture and / or with respect to one system may be organized in an alternative structural architecture and / or incorporated into other described systems. Therefore, although these embodiments with or without some features are described for ease of description and explanation of aspects of various embodiments, the various components and / or features described herein with respect to specific embodiments may be replaced, added, and / or subtracted from other described embodiments unless the context dictates otherwise. Therefore, although several embodiments are described above, it should be understood that the present invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A device comprising: a first substrate comprising a first device configured to receive a voltage, a first side disposed on a front surface of the first substrate, and a second side disposed on a back surface of the first substrate; a second substrate configured to support the first substrate; and A power distribution network is disposed at an interface between the second side of the first substrate and the second substrate. 2 . The apparatus of claim 1 , wherein the first substrate comprises single crystal silicon, and the second substrate comprises single crystal silicon, polycrystalline silicon, silicon carbide, glass, sapphire, or gallium arsenide.

3. The apparatus of claim 1, wherein the first device configured to receive the voltage comprises a transistor. 4 . The apparatus of claim 1 , wherein the power distribution network is directly coupled to the second side of the first substrate and the second substrate.

5. The apparatus of claim 1 , wherein the first substrate further comprises: a first connector coupled to a power source and to the power distribution network; and A second connector is coupled to the power distribution network and the first device of the first substrate.

6. The apparatus of claim 5, wherein a ratio of a first diameter of the first connector to a second diameter of the second connector is between about 3:1 and 20:

1.

7. The apparatus of claim 5, wherein at least one of the first connector or the second connector comprises a through hole or a groove.

8. The apparatus of claim 1, wherein a ratio of a first thickness of the first substrate to a second thickness of the second substrate is between approximately 1:200 and 1:

10.

9. The apparatus of claim 1, further comprising: a third substrate between the power distribution network and the first substrate; and The third substrate couples the power distribution network to the first substrate.

10. The device of claim 9, wherein the third substrate further comprises: a first connector coupled to a power source and to the power distribution network; and A second connector is coupled to the power distribution network and the first device of the first substrate.

11. The apparatus of claim 1, wherein the second substrate further comprises a second device configured to provide non-volatile memory.

12. The apparatus of claim 1, wherein the first substrate further comprises circuitry toward the second side of the first substrate, wherein the circuitry is configured to control current.

13. A method for manufacturing a backside power distribution network of a semiconductor device, the method comprising: forming at least one of a first substrate or a second substrate including a device configured to receive a voltage, wherein the second substrate is configured to support the first substrate; and A power distribution network is formed that is configured to be disposed at an interface between the first substrate and the second substrate.

14. The method of claim 13, wherein forming the power distribution network disposed at the interface between the first substrate and the second substrate comprises forming the power distribution network on a back side of the first substrate.

15. The method of claim 14, wherein once the power distribution network is formed on the first substrate, the method further comprises bonding the first substrate to the second substrate. 16 . The method of claim 13 , wherein forming the power distribution network disposed at an interface between the first substrate and the second substrate comprises forming the power distribution network on the second substrate.

17. The method of claim 16, wherein once the power distribution network is formed on the second substrate, the method further comprises bonding the first substrate to the second substrate.

18. The method of claim 13, wherein forming the power distribution network disposed at an interface between the first substrate and the second substrate comprises forming a third substrate and forming the power distribution network on the third substrate, wherein the third substrate further comprises a connector configured to couple the device of the first substrate with the power distribution network.

19. The method of claim 18, wherein once the power distribution network is formed on the third substrate, the method further comprises bonding the first substrate to the third substrate and bonding the second substrate to the third substrate, wherein the power distribution network is between the second substrate and the third substrate.

20. A semiconductor device comprising: a first substrate comprising a device configured to receive a voltage; a metal layer coupled to the first side of the first substrate; a second substrate coupled to a second side of the first substrate opposite the metal layer and the first side, the second substrate being configured to support the first substrate; and A power distribution network is disposed between the second side of the first substrate and the second substrate.

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