Semiconductor device and method for manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a manufacturing method of the semiconductor device. Provided is a semiconductor device in which deterioration of a gate insulating layer is suppressed. A semiconductor device (100a) includes a semiconductor substrate (1), a gate insulating film (2a), a gate electrode (2b), a first electrical wiring (5a), and a semiconductive insulating layer (3). The gate insulating film (2a) is formed on the semiconductor substrate (1). The gate electrode (2b) is formed on the semiconductor substrate (1) via the gate insulating film (2a). The first electrical wiring (5a) is connected to the gate electrode (2b). The semi-conductive insulating layer (3) is connected to the gate electrode (2b) and / or the first electrical wiring (5a).

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] In the manufacturing process of semiconductor devices, in order to suppress the charging of the gate insulating layer, an amorphous carbon film is formed to allow the charge to escape to the semiconductor substrate (for example, refer to Japanese Patent Application Laid-Open No. 7-245390). By forming such an amorphous carbon film, charging is suppressed during ion implantation in the manufacturing process of semiconductor devices.

[0003] However, the amorphous carbon film described above is removed after the ion implantation. Therefore, in the process after the ion implantation, there is a concern that the gate insulating layer may be charged and degraded. Summary of the invention

[0004] The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device in which degradation of a gate insulating layer is suppressed.

[0005] The semiconductor device of the present invention comprises a semiconductor substrate, a gate insulating film, a gate electrode, a first electrical wiring and a semi-conductive insulating layer. The gate insulating film is formed on the semiconductor substrate. The gate electrode is formed on the semiconductor substrate via the gate insulating film. The first electrical wiring is connected to the gate electrode. The semi-conductive insulating layer is connected to at least one of the gate electrode and the first electrical wiring.

[0006] The method for manufacturing a semiconductor device according to the present invention comprises the steps of: preparing a semiconductor substrate; forming a first semiconductive insulating layer on the semiconductor substrate; and rotating the semiconductor substrate after the step of forming the first semiconductive insulating layer.

[0007] The above and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 This is a schematic cross-sectional view of the semiconductor device according to the first embodiment.

[0009] Figure 2 This is a schematic plan view of the semiconductor device according to the first embodiment.

[0010] Figure 3 This is a flowchart of the method for manufacturing the semiconductor device according to the first embodiment.

[0011] Figure 4 This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0012] Figure 5 This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0013] Figure 6 This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0014] Figure 7 This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0015] Figure 8 This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0016] Fig. 9 This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0017] Fig.10 This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0018] Fig.11 This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0019] Fig.12 This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0020] Fig.13 This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0021] Fig.14 This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0022] Fig.15 This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0023] Fig.16 This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device according to the first embodiment.

[0024] Fig.17 This is a schematic cross-sectional view of a semiconductor device according to a second embodiment.

[0025] Fig.18 This is a flowchart of a method for manufacturing a semiconductor device according to the second embodiment.

[0026] Fig.19 This is a schematic cross-sectional view showing one step of the method for manufacturing a semiconductor device according to the second embodiment.

[0027] Fig. 20 This is a schematic cross-sectional view of a semiconductor device according to a third embodiment.

[0028] Fig.21 This is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION

[0029] Hereinafter, embodiments of the present invention will be described. In addition, unless otherwise specified, the same reference numerals are given to the same or corresponding parts in the following drawings, and the description thereof will not be repeated.

[0030] Implementation Method 1

[0031] <Structure of semiconductor device>

[0032] Figure 1 It is a schematic cross-sectional view of the semiconductor device 100 a according to the first embodiment. Figure 2 It is a schematic plan view of the semiconductor device 100 a according to the first embodiment.

[0033] Figure 1 The semiconductor device 100a shown is, for example, a semiconductor device 100a for an integrated circuit (IC), and mainly includes a semiconductor substrate 1, a gate insulating film 2a, a gate electrode 2b, a semiconductive insulating layer 3, an interlayer insulating layer 4, and an electrical wiring 5. In addition, the electrical wiring 5 is Figure 2 The illustration is omitted. Figure 2 In FIG. 1 , the outer shape of the semiconductive insulating layer 3 is shown by a dotted line.

[0034] like Figure 1 As shown, the semiconductor substrate 1 has a first main surface 11 and a second main surface 12. The second main surface 12 is a surface located on the opposite side of the first main surface 11. The first main surface 11 and the second main surface 12 extend in the x direction and the y direction perpendicular to the x direction respectively. The z direction is the thickness direction of the semiconductor substrate 1. The normal direction of the first main surface 11 is the z direction perpendicular to the x direction and the y direction. The first main surface 11 faces the +z direction. The second main surface 12 faces the -z direction. The material constituting the semiconductor substrate 1 is, for example, silicon. The material constituting the semiconductor substrate 1 may also be, for example, a wide bandgap semiconductor substrate of any one of silicon carbide (SiC), gallium nitride (GaN), and gallium oxide (Ga2O3).

[0035] The concentration of impurities contained in the semiconductor substrate 1 may be adjusted to match the withstand voltage of the semiconductor device 100a. The conductivity type of the semiconductor substrate 1 may be either n-type or p-type. A plurality of diffusion layers 13 are formed on the first main surface 11. When the conductivity type of the semiconductor substrate 1 is n-type, the conductivity type of the diffusion layer 13 may be p-type. When the conductivity type of the semiconductor substrate 1 is p-type, the conductivity type of the diffusion layer 13 may be n-type. Figure 1 As shown, a plurality of diffusion layers 13 are formed on the first main surface 11 so as to be separated from each other.

[0036] like Figure 1 As shown, the gate insulating film 2a is formed on the first main surface 11 of the semiconductor substrate 1. When the first main surface 11 is viewed from above, the gate insulating film 2a is arranged at a position sandwiched by a pair of diffusion layers 13. When the first main surface 11 is viewed from above, a portion of the gate insulating film 2a overlaps with the diffusion layer 13. The material constituting the gate insulating film 2a is, for example, silicon dioxide (SiO2).

[0037] like Figure 1 As shown, the gate electrode 2b is formed on the gate insulating film 2a. From a different point of view, the gate electrode 2b is formed on the semiconductor substrate 1 via the gate insulating film 2a. The material constituting the gate electrode 2b may be, for example, polysilicon.

[0038] like Figure 1 As shown, the semiconductive insulating layer 3 is formed on the semiconductor substrate 1 in a manner that covers the first main surface 11 and the gate electrode 2b when the first main surface 11 is viewed from above. The semiconductive insulating layer 3 may not be directly connected to the gate electrode 2b. As described later, the semiconductive insulating layer 3 may also be formed on the surface 41 of the interlayer insulating layer 4, and arranged between the surface 41 and the first electrical wiring 5a in the z direction. The semiconductive insulating layer 3 may also be formed in a manner that covers the surface 41 and the first electrical wiring 5a when the surface 41 of the interlayer insulating layer 4 is viewed from above.

[0039] The material constituting the semi-conductive insulating layer 3 is, for example, a material containing at least one of semi-conductive silicon nitride (SInSiN: Semi-Insulating Silicon Nitride) and silicon dioxide (SiO2). As described later, the semi-conductive insulating layer 3 is formed by plasma CVD (Chemical Vapor Deposition).

[0040] The semiconductive insulating layer 3 composed of the above-mentioned material has high insulation at low temperatures and high conductivity at high temperatures. From a different point of view, the resistivity of the semiconductive insulating layer 3 when the temperature of the semiconductive insulating layer 3 is 27° C. (room temperature) is greater than the resistivity of the semiconductive insulating layer 3 when the temperature of the semiconductive insulating layer 3 is 150° C. Specifically, the resistivity of the semiconductive insulating layer 3 at room temperature (27° C.) may be approximately 1×10 12 The resistivity of the semiconductive insulating layer 3 at 150° C. can be changed to less than or equal to one thousandth of the resistivity at room temperature (27° C.).

[0041] The resistivity of the semiconductive insulating layer 3 when the temperature of the semiconductive insulating layer 3 is 27° C. may be greater than or equal to 1×10 11 Ωcm and less than or equal to 1×10 13 Ωcm. The resistivity of the semiconductive insulating layer 3 when the temperature of the semiconductive insulating layer 3 is 150°C may be less than or equal to 1×10 10 As described above, the resistivity of the semiconductive insulating layer 3 has temperature dependence and changes reversibly according to the temperature of the semiconductive insulating layer 3. That is, by adjusting the temperature of the semiconductive insulating layer 3, the resistivity of the semiconductive insulating layer 3 can be adjusted.

[0042] like Figure 1 As shown, the interlayer insulating layer 4 is arranged on the semiconductor substrate 1. The interlayer insulating layer 4 has a surface 41 and a back surface 42. The back surface 42 is opposite to the semiconductor substrate 1 and the gate electrode 2b. In the present embodiment 1, the back surface 42 of the interlayer insulating layer 4 is connected to the semiconductive insulating layer 3. The surface 41 is a surface located on the opposite side of the back surface 42. The material constituting the interlayer insulating layer 4 can be, for example, any one of silicon dioxide (SiO2) and tetraethoxysilane (TEOS).

[0043] like Figure 1 and Figure 2 As shown in FIG. 4 , a plurality of contact holes H are formed in the interlayer insulating layer 4. Figure 2 As shown, the contact holes H include a plurality of first contact holes h1 and a plurality of second contact holes h2. The first contact holes h1 extend from the surface 41 to the gate electrode 2b. The second contact holes h2 extend from the surface 41 to the first main surface 11 of the semiconductor substrate 1. Figure 2 As shown, the first contact hole h1 and the second contact hole h2 are arranged separately from each other. From a different point of view, the first contact hole h1 is arranged at a position overlapping with the gate electrode 2b on the surface 41 of the interlayer insulating layer 4. The second contact hole h2 is arranged at a position not overlapping with the gate electrode 2b.

[0044] like Figure 1As shown, the electrical wiring 5 is formed by filling the contact hole H. The electrical wiring 5 includes a first electrical wiring 5a and a second electrical wiring 5b (not shown). The first electrical wiring 5a is electrically connected to the gate electrode 2b. The second electrical wiring 5b is electrically connected to the semiconductor substrate 1. The first electrical wiring 5a is connected to the gate electrode 2b, the inner peripheral surface hs1 of the first contact hole h1, and the surface 41 of the interlayer insulating layer 4 via the barrier metal 6. The second electrical wiring 5b is connected to the first main surface 11 of the semiconductor substrate 1 and the inner peripheral surface hs2 of the second contact hole h2 (see Fig. 20 ) and the surface 41 of the interlayer insulating layer 4 is connected.

[0045] By forming the second contact hole h2 reaching the first main surface 11 of the semiconductor substrate 1 from the surface 41, it is possible to form the second electrical wiring 5b that is conductive with the semiconductor substrate 1. By so doing, it is possible to further allow charges to flow to the semiconductor substrate 1. As a result, as will be described later, it is possible to further suppress degradation of the gate insulating film 2a.

[0046] The material constituting the electrical wiring 5 can be, for example, any metal. The electrical wiring 5 can be a single layer or a structure in which multiple layers are stacked in the z direction. Specifically, the electrical wiring 5 is formed by depositing an aluminum alloy (for example, an Al-Si alloy) on the surface 41 of the interlayer insulating layer 4 and the inner peripheral surface of the contact hole H using PVD (Physical Vapor Deposition) such as sputtering and evaporation. A nickel alloy (Ni alloy) can also be formed on the aluminum alloy using chemical plating or electrolytic plating. As shown above, the electrical wiring 5 can also be formed by stacking an aluminum alloy and a nickel alloy.

[0047] The electrical wiring 5 is formed on the barrier metal 6. That is, the barrier metal 6 is formed on the contact interface between the electrical wiring 5 and the interlayer insulating layer 4, on the contact interface between the electrical wiring 5 and the gate electrode 2b, and on the contact interface between the electrical wiring 5 and the semiconductor substrate 1. The material constituting the barrier metal 6 is, for example, any one of titanium (Ti) and titanium nitride (TiN).

[0048] Here, the features of the semiconductor device 100a according to the first embodiment are as follows: Figure 1 The semiconductor device 100a is shown to have a semiconductive insulating layer 3. By forming the semiconductive insulating layer 3, the charges generated in the manufacturing process of the semiconductor device 100a can flow to the outer periphery (not shown) of the semiconductor substrate 1 through the semiconductive insulating layer 3. As a result, the charges are not accumulated in the gate insulating film 2a, and the degradation of the gate insulating film 2a can be suppressed.

[0049] In addition, the resistivity of the semiconductive insulating layer 3 is temperature-dependent. Therefore, in a high temperature state such as an etching process and an ion implantation process, the semiconductive insulating layer 3 has high conductivity. Therefore, the charge generated in the manufacturing process of the semiconductor device 100a can flow to the semiconductor substrate 1. On the other hand, at room temperature or the temperature at which the semiconductor device 100a is operated, the semiconductive insulating layer 3 has high insulation. Therefore, the semiconductive insulating layer 3 does not need to be removed in the manufacturing process of the semiconductor device 100a, and the semiconductive insulating layer 3 can be left after the manufacturing of the semiconductor device 100a is completed. That is, the semiconductive insulating layer 3 is not removed but left until the manufacturing of the semiconductor device 100a is completed, so that even after the ion implantation process is completed, when a process that becomes a high temperature is implemented, etc., it is possible to make the charge flow to the semiconductor substrate 1. As a result, no charge is retained in the gate insulating film 2a, and the degradation of the gate insulating film 2a can be suppressed.

[0050] The film formation range of the semiconductive insulating layer 3 is not particularly limited, and the semiconductive insulating layer 3 may be formed on the entire first main surface 11 of the semiconductor substrate 1. However, the semiconductive insulating layer 3 has a high dielectric constant. Therefore, if the semiconductive insulating layer 3 is formed on the entire first main surface 11 of the semiconductor substrate 1, the load capacitance of the semiconductor device 100a may increase.

[0051] You can also Figure 2 As shown, the semiconductive insulating layer 3 is formed in a strip shape. The semiconductive insulating layer 3 has multiple layers. When viewed from above the first main surface 11, the multiple layers are arranged separately from each other in the y direction. Specifically, the semiconductive insulating layer 3 may also have a first layer 31 and a second layer 32. When viewed from above the first main surface 11, the first layer 31 and the second layer 32 may also be arranged separately from each other in the y direction. By setting it in this way, it is possible to suppress the increase of the load capacitance of the semiconductor device 100a while allowing charges to flow to the semiconductor substrate 1. In addition, when the semiconductive insulating layer 3 is formed in a strip shape, the stress applied to the semiconductor substrate 1 is smaller than the stress applied to the semiconductor substrate 1 when the semiconductive insulating layer 3 is formed on the entire first main surface 11. As a result, the warping of the semiconductor substrate 1 can be suppressed.

[0052] The semiconductive insulating layer 3 may be formed so as to extend to an end face (not shown) connecting the first main face 11 and the second main face 12 of the semiconductor substrate 1 when viewed from above. In this way, charges can flow from the end face of the semiconductor substrate 1. As a result, charges are not retained in the gate insulating film 2a, and degradation of the gate insulating film 2a can be further suppressed.

[0053] As described above, the semiconductive insulating layer 3 may be formed on the semiconductor substrate 1 in a manner that covers the first main surface 11 and the gate electrode 2b when viewed from above the first main surface 11. By setting it in this way, the contact area between the semiconductive insulating layer 3 and the semiconductor substrate 1 is increased, and the charge can be further flowed to the semiconductor substrate 1. As a result, the charge is not retained in the gate insulating film 2a, and the degradation of the gate insulating film 2a can be suppressed.

[0054] The thickness t of the semiconductive insulating layer 3 in the z direction may be greater than or equal to 50 nm. In this way, the thickness of the semiconductive insulating layer 3 can be stably controlled in the manufacturing process of the semiconductor device 100a.

[0055] The thickness t of the semiconductive insulating layer 3 in the z direction may be less than or equal to 100 nm. By setting in this way, the increase of the load capacitance of the semiconductor device 100a can be suppressed. In addition, the stress applied to the base layer of the semiconductive insulating layer 3 can be reduced, and the generation of cracks in the base layer can be suppressed. In addition, the stress applied to the semiconductor substrate 1 can be reduced, and the warping of the semiconductor substrate 1 can be suppressed. As a result, the semiconductor device 100a can be stably manufactured.

[0056] <Method for manufacturing semiconductor device>

[0057] Hereinafter, a method for manufacturing the semiconductor device 100 a according to the present embodiment will be described. Figure 3 This is a flowchart of a method for manufacturing the semiconductor device 100 a according to the first embodiment. Figures 4 to 16 This is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device 100 a according to the first embodiment.

[0058] First, a step (S1a) of preparing a semiconductor substrate 1 is performed. In this step (S1a), Figure 4 As shown, a semiconductor substrate 1 is prepared as a silicon wafer, which is a semiconductor material. The conductivity type of the semiconductor substrate 1 can be either n-type or p-type. In the method for manufacturing the semiconductor device 100a according to the first embodiment, the conductivity type of the semiconductor substrate 1 is set to n-type.

[0059] Next, a step (S2a) of forming the first semi-conductive insulating layer 3a is performed. In this step (S2a), Figure 5 As shown, a first semiconductive insulating layer 3a is formed on a semiconductor substrate 1. The first semiconductive insulating layer 3a is formed by plasma CVD. The material constituting the first semiconductive insulating layer 3a may be any material including at least one of semiconductive silicon nitride (SInSiN) and silicon dioxide (SiO2).

[0060] Next, a step (S3a) of rotating the semiconductor substrate 1 is performed. In this step (S3a), Figure 6 As shown, the semiconductor substrate 1 is rotated while either gas or water is flowed, so that the semiconductor substrate 1 is cleaned. The first semi-conductive insulating layer 3a is charged by friction between the surface of the semiconductor substrate 1 on which the first semi-conductive insulating layer 3a is formed and either gas, water or coating film. Conventionally, carbon dioxide (CO2) is added to increase the conductivity of the gas and suppress the charge caused by the electric charge, but in the method for manufacturing the semiconductor device 100a according to the first embodiment, it is not necessary to add carbon dioxide (CO2) in this step (S3a). That is, even if carbon dioxide (CO2) is not flowed, the charge of the first semi-conductive insulating layer 3a can be suppressed.

[0061] Next, a step (S4a) of injecting impurities into the semiconductor substrate 1 is performed. In this step (S4a), Figure 7 As shown in FIG. 1 , a resist layer 71 is formed on the first semi-conductive insulating layer 3a. Then, impurities are implanted into the semiconductor substrate 1. By setting it in this way, Figure 8 As shown in FIG. 1 , a diffusion layer 13 is formed on the first main surface 11 of the semiconductor substrate 1. Figure 8 As shown, when the first main surface 11 is viewed from above, the diffusion layer 13 is formed in a region where the resist layer 71 is not formed. When the conductivity type of the semiconductor substrate 1 is n-type, the conductivity type of the diffusion layer 13 may be p-type. When the conductivity type of the semiconductor substrate 1 is p-type, the conductivity type of the diffusion layer 13 may be n-type. In this process, the charge caused by the impurity injection process can also be removed via the first semi-conductive insulating layer 3a.

[0062] Next, a step (S5a) of removing the first semi-conductive insulating layer 3a is performed. In this step (S5a), Fig. 9 As shown in FIG. 5 , the resist layer 71 and the first semiconductive insulating layer 3a are removed by etching. In addition, in this step (S5a), as described later, only the resist layer 71 may be removed without removing the first semiconductive insulating layer 3a (not shown). When the first semiconductive insulating layer 3a is not removed in this step (S5a), the first semiconductive insulating layer 3a constitutes the semiconductive insulating layer 3.

[0063] Next, a step (S6a) of forming a gate insulating film 2a is performed. In this step (S6a), Fig.10As shown, by heating the semiconductor substrate 1 in an atmosphere containing oxygen, a gate insulating film 2a is formed on the first main surface 11. The material constituting the gate insulating film 2a is, for example, silicon dioxide (SiO2). In addition, in order to ensure the insulation of the gate insulating film 2a, in the step (S5a) of removing the first semi-conductive insulating layer 3a, the first semi-conductive insulating layer 3a located between the gate insulating film 2a and the first main surface 11 of the semiconductor substrate 1 can also be removed.

[0064] Next, a step (S7a) of forming the gate electrode 2b is performed. In this step (S7a), Fig.11 As shown in FIG. 1 , polysilicon is stacked on the gate insulating film 2a by CVD, thereby forming the gate electrode 2b. The polysilicon is doped with n-type or p-type impurities.

[0065] Next, a step (S8a) of forming the second semiconductive insulating layer 3b is performed. In this step (S8a), Fig.12 As shown, a second semiconductive insulating layer 3b is formed on the semiconductor substrate 1. The second semiconductive insulating layer 3b is formed by plasma CVD. The material constituting the second semiconductive insulating layer 3b may be the same as the material constituting the first semiconductive insulating layer 3a, or may be different from the material constituting the first semiconductive insulating layer 3a.

[0066] The second semiconductive insulating layer 3b constitutes the semiconductive insulating layer 3. When the step (S5a) of removing the first semiconductive insulating layer 3a is not performed, the semiconductive insulating layer 3 arranged between the first main surface 11 of the semiconductor substrate 1 and the interlayer insulating layer 4 becomes a two-layer structure of the first semiconductive insulating layer 3a and the second semiconductive insulating layer 3b.

[0067] If the material constituting the second semiconductive insulating layer 3b is the same as the material constituting the first semiconductive insulating layer 3a, it is difficult to confirm the boundary between the first semiconductive insulating layer 3a and the second semiconductive insulating layer 3b. As a result, the semiconductive insulating layer 3 is regarded as a single-layer structure. However, the thickness t2 of the semiconductive insulating layer 3 arranged between the first main surface 11 of the semiconductor substrate 1 and the interlayer insulating layer 4 in the z direction is thicker than the thickness t1 of the semiconductive insulating layer 3 arranged between the gate electrode 2b and the interlayer insulating layer 4 in the z direction. Therefore, by comparing the thickness t2 of the semiconductive insulating layer 3 arranged between the first main surface 11 of the semiconductor substrate 1 and the interlayer insulating layer 4 with the thickness t1 of the semiconductive insulating layer 3 arranged between the gate electrode 2b and the interlayer insulating layer 4 in the z direction, it is possible to determine whether the semiconductive insulating layer 3 is a two-layer structure of the first semiconductive insulating layer 3a and the second semiconductive insulating layer 3b.

[0068] The thickness ( t1 and t2 ) of the semiconductive insulating layer 3 in the z direction may be, for example, greater than or equal to 50 nm and less than or equal to 100 nm.

[0069] Next, a step (S9a) of forming the interlayer insulating layer 4 is performed. In this step (S9a), Fig.13 As shown, an interlayer insulating layer 4 is formed on the semiconductive insulating layer 3. The material constituting the interlayer insulating layer 4 may be, for example, silicon dioxide (SiO2) or tetraethoxysilane (TEOS).

[0070] Next, a step (S10a) of forming a contact hole H is performed. In this step (S10a), Fig.14 As shown in FIG. 1 , an anti-etching layer 72 is formed on the surface 41 of the interlayer insulating layer 4. The anti-etching layer 72 has an opening 72a. When the surface 41 is viewed from above, the opening 72a is arranged at a position overlapping with the gate electrode 2b. The interlayer insulating layer 4 and the semi-conductive insulating layer 3 are etched by using the anti-etching layer 72 as a mask, thereby Fig.15 As shown in FIG. 1 , a first contact hole h1 is formed. The first contact hole h1 reaches the gate electrode 2 b from the surface 41 .

[0071] Although not shown, the resist layer 72 may also have an opening 72b (not shown). When viewed from above the surface 41, the opening 72b is arranged at a position different from the opening 72a. The interlayer insulating layer 4 and the semiconductive insulating layer 3 are etched using the resist layer 72 as a mask, thereby forming a second contact hole h2 (not shown). The second contact hole h2 reaches the first main surface 11 of the semiconductor substrate 1 from the surface 41. Then, the resist layer 72 is removed.

[0072] Next, a step (S11a) of forming the electrical wiring 5 is performed. In this step (S11a), Fig.16 As shown, the electrical wiring 5 is formed in a manner of filling the contact hole H. The first electrical wiring 5a is connected to the gate electrode 2b, the inner peripheral surface hs1 of the first contact hole h1, and the surface 41 of the interlayer insulating layer 4 via the barrier metal 6. Although not shown, the second electrical wiring 5b is connected to the first main surface 11 of the semiconductor substrate 1, the inner peripheral surface hs2 of the second contact hole h2, and the surface 41 of the interlayer insulating layer 4 via the barrier metal 6.

[0073] The material constituting the electrical wiring 5 can be, for example, any metal. The electrical wiring 5 can be a single layer or a structure in which multiple layers are stacked in the z direction. Specifically, the electrical wiring 5 is formed by stacking an aluminum alloy (for example, an Al-Si alloy) on the surface 41 of the interlayer insulating layer 4 and the inner peripheral surface of the contact hole H using PVD (Physical Vapor Deposition) such as sputtering and evaporation. A nickel alloy (Ni alloy) can also be formed on the aluminum alloy by chemical plating or electrolytic plating. In this way, the electrical wiring 5 can also be formed by stacking an aluminum alloy and a nickel alloy.

[0074] By using the plating process, it is easy to form thick electric wiring 5. Therefore, by forming thick electric wiring 5, the heat capacity of the electric wiring 5 increases, and thus the heat resistance of the semiconductor device 100a is improved.

[0075] The electrical wiring 5 is formed on the barrier metal 6. That is, the barrier metal 6 is formed on the contact interface between the electrical wiring 5 and the interlayer insulating layer 4, on the contact interface between the electrical wiring 5 and the gate electrode 2b, and on the contact interface between the electrical wiring 5 and the semiconductor substrate 1. The material constituting the barrier metal 6 may be, for example, titanium (Ti) or titanium nitride (TiN).

[0076] The thickness t of the semiconductive insulating layer 3 in the z direction may be less than or equal to 100 nm.

[0077] Next, a dicing step (S12a) is performed. In this step (S12a), the semiconductor substrate 1 is cut into pieces by either laser dicing or knife dicing, thereby manufacturing Figure 1 A semiconductor device 100a is shown. A plurality of semiconductor devices 100a are manufactured by cutting the semiconductor substrate 1 into a matrix.

[0078] By setting in this way, the electric charge generated in the manufacturing process of the semiconductor device 100a can flow to the outer periphery of the semiconductor substrate 1 through the semiconductive insulating layer 3. Specifically, in the manufacturing process of the semiconductor device 100a, the charging of the first semiconductive insulating layer 3a caused by the friction between the first main surface 11 of the semiconductor substrate 1 and any one of the gas, water and coating film in the step (S3a) of rotating the semiconductor substrate 1, and the charging caused by the ion beam in the step (S4a) of injecting impurities into the semiconductor substrate 1, that is, the charging caused by the positive electric charge generated by the transmission of positive ions from the ion beam to the semiconductor substrate 1. In addition, it is not necessary to add carbon dioxide (CO2) in the step (S3a) of rotating the semiconductor substrate 1.

[0079] As a result, charges are not accumulated in the gate insulating film 2 a , and the semiconductor device 100 a in which degradation of the gate insulating film 2 a is suppressed can be obtained.

[0080] In addition, the resistivity of the semiconductive insulating layer 3 has temperature dependence. Therefore, in a high temperature state such as an etching process and an ion implantation process, the semiconductive insulating layer 3 has high conductivity. Therefore, the charge generated in the manufacturing process of the semiconductor device 100a can flow to the semiconductor substrate 1. On the other hand, in a relatively low temperature state such as room temperature or the temperature during the operation of the semiconductor device 100a, the semiconductive insulating layer 3 has high insulation. Therefore, the semiconductive insulating layer 3 does not need to be removed in the manufacturing process of the semiconductor device 100a, and the semiconductive insulating layer 3 can be left after the manufacturing of the semiconductor device 100a is completed.

[0081] <Effects>

[0082] The semiconductor device 100a according to the present invention comprises a semiconductor substrate 1, a gate insulating film 2a, a gate electrode 2b, a first electrical wiring 5a and a semi-conductive insulating layer 3. The gate insulating film 2a is formed on the semiconductor substrate 1. The gate electrode 2b is formed on the semiconductor substrate 1 via the gate insulating film 2a. The first electrical wiring 5a is connected to the gate electrode 2b. The semi-conductive insulating layer 3 is connected to at least one of the gate electrode 2b and the first electrical wiring 5a.

[0083] By setting in this way, the electric charge generated in the manufacturing process of the semiconductor device 100a can flow to the outer periphery of the semiconductor substrate 1 through the semiconductive insulating layer 3. Specifically, in the manufacturing process of the semiconductor device 100a, the charging of the first semiconductive insulating layer 3a caused by the friction between the first main surface 11 of the semiconductor substrate 1 and any one of the gas, water and coating film in the step (S3a) of rotating the semiconductor substrate 1, the charging caused by the ion beam in the step (S4a) of injecting impurities into the semiconductor substrate 1, etc. are suppressed. In addition, it is not necessary to add carbon dioxide (CO2) in the step (S3a) of rotating the semiconductor substrate 1. As a result, no electric charge is retained in the gate insulating film 2a, and the semiconductor device 100a in which the degradation of the gate insulating film 2a is suppressed can be obtained.

[0084] In addition, the resistivity of the semiconductive insulating layer 3 has temperature dependence. Therefore, in a high temperature state such as an etching process and an ion implantation process, the semiconductive insulating layer 3 has high conductivity. Therefore, the charge generated in the manufacturing process of the semiconductor device 100a can flow to the semiconductor substrate 1. On the other hand, in a low temperature state such as room temperature or during the operation of the semiconductor device 100a, the semiconductive insulating layer 3 has high insulation. Therefore, the semiconductive insulating layer 3 does not need to be removed in the manufacturing process of the semiconductor device 100a, and the semiconductive insulating layer 3 can remain after the manufacturing of the semiconductor device 100a is completed.

[0085] In the semiconductor device 100a, the resistivity of the semiconductive insulating layer 3 when the temperature of the semiconductive insulating layer 3 is 27°C is greater than the resistivity of the semiconductive insulating layer 3 when the temperature of the semiconductive insulating layer 3 is 150°C.

[0086] By setting it in this way, the semiconductive insulating layer 3 has high conductivity in the manufacturing process of the semiconductor device 100a. Therefore, the charge generated in the manufacturing process of the semiconductor device 100a can flow to the semiconductor substrate 1. On the other hand, in a low temperature state such as when the semiconductor device 100a is in operation, the semiconductive insulating layer 3 has high insulation. Therefore, it is not necessary to remove the semiconductive insulating layer 3 in the manufacturing process of the semiconductor device 100a, and the semiconductive insulating layer 3 can remain after the manufacturing of the semiconductor device 100a is completed.

[0087] In the semiconductor device 100a, the resistivity of the semiconductive insulating layer 3 when the temperature of the semiconductive insulating layer 3 is 27° C. is greater than or equal to 1×10 11 Ωcm and less than or equal to 1×10 13 Ωcm.

[0088] Thus, the semiconductive insulating layer 3 has high insulating properties at room temperature when the semiconductor device 100a is in operation. Therefore, the semiconductive insulating layer 3 does not need to be removed during the manufacturing process of the semiconductor device 100a, and the semiconductive insulating layer 3 may remain after the semiconductor device 100a is manufactured.

[0089] In the semiconductor device 100a, the resistivity of the semiconductive insulating layer 3 when the temperature of the semiconductive insulating layer 3 is 150° C. is less than or equal to 1×10 10 Ωcm.

[0090] By doing so, the semiconductive insulating layer 3 can have high conductivity during the manufacturing process of the semiconductor device 100 a , so that charges generated during the manufacturing process of the semiconductor device 100 a can flow to the semiconductor substrate 1 .

[0091] In the semiconductor device 100 a described above, the material constituting the semi-conductive insulating layer 3 includes at least one of semi-conductive silicon nitride and silicon dioxide.

[0092] By setting it in this way, the semiconductive insulating layer 3 can have high conductivity in the manufacturing process of the semiconductor device 100a. Therefore, the charge generated in the manufacturing process of the semiconductor device 100a can flow to the semiconductor substrate 1. On the other hand, in a low temperature state such as when the semiconductor device 100a is in operation, the semiconductive insulating layer 3 has high insulation. Therefore, it is not necessary to remove the semiconductive insulating layer 3 in the manufacturing process of the semiconductor device 100a, and the semiconductive insulating layer 3 can remain after the manufacturing of the semiconductor device 100a is completed.

[0093] In the semiconductor device 100 a described above, the thickness t of the semiconductive insulating layer 3 is greater than or equal to 50 nm and less than or equal to 100 nm.

[0094] By setting in this way, in the manufacturing process of the semiconductor device 100a, the film thickness of the semiconductive insulating layer 3 can be stably controlled. In addition, the increase of the load capacitance of the semiconductor device 100a can be suppressed. In addition, the stress applied to the base layer of the semiconductive insulating layer 3 can be reduced, and the generation of cracks in the base layer can be suppressed. In addition, the stress applied to the semiconductor substrate 1 can be reduced, and the warping of the semiconductor substrate 1 can be suppressed. As a result, the semiconductor device 100a can be stably manufactured.

[0095] The semiconductor device 100a further includes an interlayer insulating layer 4. The interlayer insulating layer 4 is disposed on the semiconductor substrate 1. The interlayer insulating layer 4 has a surface 41. The surface 41 is located on the opposite side of the surface facing the semiconductor substrate 1 and the gate electrode 2b. A first contact hole h1 is formed in the interlayer insulating layer 4. The first contact hole h1 reaches the gate electrode 2b from the surface 41. The first electrical wiring 5a is connected to the inner peripheral surface hs1 of the first contact hole h1 and the surface 41.

[0096] This arrangement allows charges generated during the manufacturing process of the semiconductor device 100a to flow to the periphery of the semiconductor substrate 1 via the semiconductive insulating layer 3. As a result, charges are not accumulated in the gate insulating film 2a, and the semiconductor device 100a can be obtained with reduced degradation of the gate insulating film 2a.

[0097] In the semiconductor device 100a, the semiconductive insulating layer 3 includes a first layer 31 and a second layer 32. In a plan view of the semiconductor substrate 1, the first layer 31 and the second layer 32 are arranged to be separated from each other.

[0098] By setting in this way, it is possible to allow charges to flow to the semiconductor substrate 1 while suppressing an increase in the load capacitance of the semiconductor device 100a. In addition, the stress applied to the semiconductor substrate 1 when the semiconductive insulating layer 3 is formed in a strip shape is smaller than the stress applied to the semiconductor substrate 1 when the semiconductive insulating layer 3 is formed on the entire first main surface 11. As a result, warping of the semiconductor substrate 1 can be suppressed.

[0099] The manufacturing method of the semiconductor device 100a involved in the present invention includes: a step (S1a) of preparing a semiconductor substrate 1; a step (S2a) of forming a first semi-conductive insulating layer 3a on the semiconductor substrate 1; and a step (S3a) of rotating the semiconductor substrate 1 after the step (S2a) of forming the first semi-conductive insulating layer 3a.

[0100] By setting it in this way, the electric charge generated in the manufacturing process of the semiconductor device 100a can flow to the outer periphery of the semiconductor substrate 1 through the semiconductive insulating layer 3. Specifically, the charging of the first semiconductive insulating layer 3a caused by the friction between the surface of the semiconductor substrate 1 formed with the first semiconductive insulating layer 3a and any one of the gas, water and coating film in the step (S3a) of rotating the semiconductor substrate 1 is suppressed. In addition, in the step (S3a) of rotating the semiconductor substrate 1, it is not necessary to add carbon dioxide (CO2) to the gas. As a result, no electric charge is retained in the gate insulating film 2a, and the semiconductor device 100a in which the degradation of the gate insulating film 2a is suppressed can be obtained.

[0101] The manufacturing method of the above-mentioned semiconductor device 100a also includes: a step (S4a), after the step (S2a) of forming the first semiconductive insulating layer 3a, injecting impurities into the semiconductor substrate 1; a step (S5a), after the step (S4a) of injecting impurities, removing the first semiconductive insulating layer 3a; a step (S7a), after the step (S5a) of removing the first semiconductive insulating layer 3a, forming a gate electrode 2b on the semiconductor substrate 1; and a step (S8a), after the step (S7a) of forming the gate electrode 2b, forming the second semiconductive insulating layer 3b in a manner covering the gate electrode 2b.

[0102] By setting it in this way, the electric charge generated in the manufacturing process of the semiconductor device 100a can flow to the outer periphery of the semiconductor substrate 1 through the semiconductive insulating layer 3. Specifically, the charging caused by the ion beam in the step (S4a) of injecting impurities into the semiconductor substrate 1 is suppressed. As a result, no electric charge is accumulated in the gate insulating film 2a, and the semiconductor device 100a in which the degradation of the gate insulating film 2a is suppressed can be obtained.

[0103] Implementation Method 2

[0104] <Structure of semiconductor device>

[0105] Fig.17 It is a schematic cross-sectional view of a semiconductor device 100 b according to the second embodiment. Fig.17 and Figure 1 correspond. Fig.17 The semiconductor device 100b shown basically has the same Figure 1 The semiconductor device 100a shown in FIG. 1 is the same structure as the semiconductor device 100b, but is different in that it is a power semiconductor instead of the semiconductor device 100a for integrated circuits. When the semiconductor device 100b is a power semiconductor, a drain electrode 8 may be formed on the second main surface 12 of the semiconductor substrate 1 as needed.

[0106] The material constituting the drain electrode 8 may include, for example, at least one of an aluminum-silicon alloy, titanium, nickel, and gold. The drain electrode 8 may also be formed by stacking a plurality of metals such as an aluminum-silicon alloy, titanium, nickel, and gold. In addition, a metal film may be further formed on the metal film formed by PVD by chemical plating or electrolytic plating. As shown above, the drain electrode 8 may also be formed by stacking a metal film formed by PVD and a metal film formed by chemical plating or electrolytic plating.

[0107] The semiconductive insulating layer 3 may be formed on the surface 41 of the interlayer insulating layer 4. From a different point of view, Fig.17 As shown, the semiconductive insulating layer 3 is arranged at a position sandwiched between the first electric wiring 5 a and the interlayer insulating layer 4 in the z direction.

[0108] <Method for manufacturing semiconductor device>

[0109] Hereinafter, a method for manufacturing the semiconductor device 100 b according to the present embodiment will be described. Fig.18 This is a flowchart of a method for manufacturing the semiconductor device 100 b according to the second embodiment. Fig.19 1 is a schematic cross-sectional view showing one step of the method for manufacturing the semiconductor device 100b according to the second embodiment. First, the method for manufacturing the semiconductor device 100a according to the first embodiment is performed. Figures 4 to 11 That is, the steps from the step of preparing the semiconductor substrate 1 ( S1b ) to the step of forming the gate electrode 2b ( S7b ) are performed.

[0110] Then, a step of forming the interlayer insulating layer 4 is performed (S8b). Specifically, the interlayer insulating layer 4 is formed to cover the first main surface 11 and the gate electrode 2b of the semiconductor substrate 1. That is, the back surface 42 of the interlayer insulating layer 4 is connected to the first main surface 11 and the gate electrode 2b.

[0111] Then, a step of forming the second semiconductive insulating layer 3b is performed (S9b). Specifically, the second semiconductive insulating layer 3b is formed in a manner that covers the surface 41 of the interlayer insulating layer 4. The second semiconductive insulating layer 3b may also be formed on the end surface 45 connecting the surface 41 and the back surface 42 of the interlayer insulating layer 4 and on the end surface 15 connecting the first main surface 11 and the second main surface 12 of the semiconductor substrate 1 (see Fig.19 The shape of the semiconductive insulating layer 3 may be a strip shape in which multiple layers are arranged separately from each other in the y direction when viewed from above the surface 41. Each of the multiple layers may be formed on the end surface 45 of the interlayer insulating layer 4 and on the end surface 15 of the semiconductor substrate 1.

[0112] Next, a step (S10b) of forming a contact hole H is performed. In this step (S10b), a resist layer 72 is formed on the second semiconductive insulating layer 3b. The resist layer 72 has an opening 72a. When the surface 41 is viewed from above, the opening 72a is arranged at a position overlapping with the gate electrode 2b. The interlayer insulating layer 4 and the semiconductive insulating layer 3 are etched using the resist layer 72 as a mask, thereby forming a first contact hole h1. The first contact hole h1 reaches the gate electrode 2b from the surface 41.

[0113] In the step (S9b) of forming the second semiconductive insulating layer 3b, the second semiconductive insulating layer 3b is formed as follows: Fig.19 When formed on the end surface 45 of the interlayer insulating layer 4 and the end surface 15 of the semiconductor substrate 1 as shown, the second contact hole h2 reaching the first main surface 11 of the semiconductor substrate 1 from the upper surface of the semiconductive insulating layer 3 may not be formed as described later.

[0114] Next, a step (S11b) of forming the electric wiring 5 is performed. In this step (S11b), the electric wiring 5 is formed to fill the contact hole H. The first electric wiring 5a is connected to the gate electrode 2b, the inner peripheral surface hs1 of the first contact hole h1, and the upper surface of the second semiconductive insulating layer 3b via the barrier metal 6.

[0115] The material constituting the electrical wiring 5 can be any metal, for example. The electrical wiring 5 can be a single layer or a structure in which multiple layers are stacked in the z direction. Specifically, the electrical wiring 5 is formed by depositing an aluminum alloy (for example, an Al-Si alloy) on the surface 41 of the interlayer insulating layer 4 and the inner peripheral surface of the contact hole H using PVD (Physical Vapor Deposition) such as sputtering and evaporation. A nickel alloy (Ni alloy) can also be formed on the aluminum alloy by chemical plating or electrolytic plating. In this way, the electrical wiring 5 can also be formed by stacking an aluminum alloy and a nickel alloy.

[0116] By using the plating process, it is easy to form thick electric wiring 5. Therefore, by forming thick electric wiring 5, the heat capacity of the electric wiring 5 increases, and thus the heat resistance of semiconductor device 100b is improved.

[0117] The formation of the nickel alloy using the plating process may be performed after the step ( S12 b ) of forming the drain electrode 8 described later.

[0118] Next, a step (S12b) of forming the drain electrode 8 is performed. In this step (S12b), Fig.19 As shown, a drain electrode 8 is formed on the second main surface 12 of the semiconductor substrate 1. When the semiconductor device 100b is manufactured as a power semiconductor, this step (S12b) is performed. The drain electrode 8 is formed, for example, by depositing an aluminum silicon alloy or titanium on the second main surface 12 by PVD such as sputtering or evaporation.

[0119] The second semiconductive insulating layer 3b is connected to the drain electrode 8. With this arrangement, even in the semiconductor device 100b in which the second contact hole h2 connected to the semiconductor substrate 1 is not formed, it is possible to allow charges to flow to the drain electrode 8.

[0120] The material constituting the drain electrode 8 may include, for example, at least one of an aluminum-silicon alloy, titanium, nickel, and gold. The drain electrode 8 may also be formed by stacking a plurality of metals such as an aluminum-silicon alloy, titanium, nickel, and gold. In addition, a metal film may be further formed on the metal film formed by PVD by chemical plating or electrolytic plating. As shown above, the drain electrode 8 may also be formed by stacking a metal film formed by PVD and a metal film formed by chemical plating or electrolytic plating.

[0121] Next, a cutting process (S13b) is performed. Fig.17 Such a semiconductor device 100b according to the second embodiment is shown.

[0122] Implementation 3

[0123] <Structure of semiconductor device>

[0124] Fig. 20 It is a schematic cross-sectional view of a semiconductor device 100 c according to the third embodiment. Fig. 20 and Figure 1 correspond. Fig. 20 The semiconductor device 100c shown basically has the same Figure 1The semiconductor device 100a shown in FIG. 1 is similar in structure to the semiconductor device 100a shown in FIG. 1 , but is different in that the semiconductive insulating layer 3 is formed on the surface 41 of the interlayer insulating layer 4. The semiconductive insulating layer 3 is not directly connected to the semiconductor substrate 1. Therefore, a second contact hole h2 is formed from the upper surface of the semiconductive insulating layer 3 to the first main surface 11 of the semiconductor substrate 1. Specifically, Fig. 20 As shown, the first contact hole h1 and the second contact hole h2 are arranged to be separated from each other.

[0125] The second electric wiring 5b is electrically connected to the semiconductor substrate 1. The second electric wiring 5b is connected to the first main surface 11 of the semiconductor substrate 1, the inner peripheral surface hs2 of the second contact hole h2, and the upper surface of the semiconductive insulating layer 3 via the barrier metal 6.

[0126] When the semiconductive insulating layer 3 is formed on the surface 41 of the interlayer insulating layer 4, by forming the second contact hole h2 reaching the first main surface 11 of the semiconductor substrate 1 from the upper surface of the semiconductive insulating layer 3, the second electrical wiring 5b that is conductive with the semiconductor substrate 1 can be formed. By setting it in this way, the charge can flow to the semiconductor substrate 1. As a result, the degradation of the gate insulating film 2a can be further suppressed.

[0127] <Effects>

[0128] In the semiconductor device 100 c described above, the semiconductive insulating layer 3 is connected to the first electric wiring 5 a and the surface 41 .

[0129] This arrangement allows charges generated during the manufacturing process of semiconductor device 100c to flow to the periphery of semiconductor substrate 1 via semiconductive insulating layer 3. As a result, charges are not accumulated in gate insulating film 2a, and semiconductor device 100c can be obtained with reduced degradation of gate insulating film 2a.

[0130] The semiconductor device 100c further includes a second electrical wiring 5b. The second electrical wiring 5b is connected to the semiconductive insulating layer 3. A second contact hole h2 is formed in the interlayer insulating layer 4. The second contact hole h2 reaches the semiconductor substrate 1 from the surface 41. The second electrical wiring 5b is connected to the inner peripheral surface hs2 of the second contact hole h2 and the surface 41.

[0131] This arrangement allows charges generated during the manufacturing process of semiconductor device 100c to flow to the periphery of semiconductor substrate 1 via semiconductive insulating layer 3. As a result, charges are not accumulated in gate insulating film 2a, and semiconductor device 100c can be obtained with reduced degradation of gate insulating film 2a.

[0132] Implementation 4

[0133] <Structure of semiconductor device>

[0134] Fig.21 It is a schematic cross-sectional view of a semiconductor device 100d according to a fourth embodiment. Fig.21 and Figure 1 correspond. Fig.21 The semiconductor device 100d shown basically has the same Figure 1 The semiconductor device 100a shown in FIG. 1 is similar in structure to the semiconductor device 100a shown in FIG. 1 , but is different in that the semiconductive insulating layer 3 is formed so as to cover the surface 41 and the first electrical wiring 5a when viewed from above the surface 41 of the interlayer insulating layer 4. By so doing, a part of the charge can flow from the upper surface of the first electrical wiring 5a to the outside. As a result, the degradation of the gate insulating film 2a can be further suppressed.

[0135] It should be considered that the entire contents of the embodiments disclosed this time are only illustrative and not restrictive. At least two of the embodiments disclosed this time can be combined without causing any contradiction. The basic scope of the present invention is not shown by the above description, but by the claims, and is intended to include all changes within the meaning and scope equivalent to the claims.

Claims

1. A semiconductor device comprising: Semiconductor substrates; a gate insulating film formed on the semiconductor substrate; a gate electrode formed on the semiconductor substrate via the gate insulating film; a first electrical wiring connected to the gate electrode; as well as A semiconductive insulating layer is connected to at least one of the gate electrode and the first electrical wiring.

2. The semiconductor device according to claim 1, wherein The resistivity of the semiconductive insulating layer when the temperature of the semiconductive insulating layer is 27° C. is greater than the resistivity of the semiconductive insulating layer when the temperature of the semiconductive insulating layer is 150° C.

3. The semiconductor device according to claim 1 or 2, wherein: The resistivity of the semiconductive insulating layer when the temperature of the semiconductive insulating layer is 27° C. is greater than or equal to 1×10 11 Ωcm and less than or equal to 1×10 13 Ωcm.

4. The semiconductor device according to any one of claims 1 to 3, wherein: The resistivity of the semiconductive insulating layer when the temperature of the semiconductive insulating layer is 150° C. is less than or equal to 1×10 10 Ωcm.

5. The semiconductor device according to any one of claims 1 to 4, wherein: The material constituting the semi-conductive insulating layer includes at least one of semi-conductive silicon nitride and silicon dioxide.

6. The semiconductor device according to any one of claims 1 to 5, wherein: The thickness of the semiconductive insulating layer is greater than or equal to 50 nm and less than or equal to 100 nm.

7. The semiconductor device according to any one of claims 1 to 6, wherein: It also has an interlayer insulating layer, which is arranged on the semiconductor substrate. The interlayer insulating layer has a surface located on the opposite side to the surface facing the semiconductor substrate and the gate electrode. A first contact hole is formed in the interlayer insulating layer, the contact hole extending from the surface to the gate electrode. The first electrical wiring is connected to the inner peripheral surface of the first contact hole and the surface.

8. The semiconductor device according to claim 7, wherein: The semiconductive insulating layer is connected to the first electrical wiring and the surface.

9. The semiconductor device according to claim 7 or 8, wherein: further comprising a second electrical wiring connected to the semiconductive insulating layer, A second contact hole is formed in the interlayer insulating layer and reaches the semiconductor substrate from the surface. The second electrical wiring is connected to the inner peripheral surface of the second contact hole and the surface.

10. The semiconductor device according to any one of claims 1 to 9, wherein: The semiconductive insulating layer comprises a first layer and a second layer, The first layer and the second layer are arranged to be separated from each other in a plan view of the semiconductor substrate.

11. A method for manufacturing a semiconductor device, comprising the following steps: preparing a semiconductor substrate; forming a first semiconductive insulating layer on the semiconductor substrate; and After the step of forming the first semiconductive insulating layer, the semiconductor substrate is rotated.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: It also has the following processes: After forming the first semiconductive insulating layer, injecting impurities into the semiconductor substrate; After the step of injecting the impurities, removing the first semiconductive insulating layer; After the step of removing the first semiconductive insulating layer, forming a gate electrode on the semiconductor substrate; as well as After the step of forming the gate electrode, a second semiconductive insulating layer is formed so as to cover the gate electrode.

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