Semiconductor device

Abstract

A semiconductor device may include a via pattern connected to a conductive pattern on a substrate and including a lower via pattern and an upper via pattern stacked on the lower via pattern; and a wiring line connected to the upper via pattern and extending in the second direction. The routing line may include the same metal as the upper via pattern. The bottom width of the routing line may be greater than the top width of the routing line. A width of a top surface of the lower via pattern may be equal to a width of a bottom surface of the upper via pattern.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices. Background Art

[0002] As one of scaling technologies for increasing the density of semiconductor devices, a multi-gate transistor has been proposed in which a multi-channel active pattern (or a silicon body) in a fin or nanowire shape is formed on a substrate and a gate is formed on a surface of the multi-channel active pattern.

[0003] Since such a multi-gate transistor utilizes a three-dimensional channel, scaling can be easily performed. In addition, even if the gate length of the multi-gate transistor is not increased, the current control capability can be improved. In addition, the short channel effect (SCE) in which the potential of the channel region is affected by the drain voltage can be effectively limited and / or suppressed. Summary of the invention

[0004] Aspects of the present disclosure provide a semiconductor device that can improve element performance and reliability.

[0005] However, aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0006] According to an embodiment of the present disclosure, a semiconductor device may include: a conductive pattern located on a substrate; a via pattern connected to the conductive pattern and including a lower via pattern and an upper via pattern, the lower via pattern and the upper via pattern being stacked in a first direction, the top surface of the lower via pattern being in contact with the bottom surface of the upper via pattern; and a wiring line located on the via pattern and extending in a second direction. The metal in the wiring line may be the same as the metal in the upper via pattern. The bottom surface of the wiring line and the top surface of the wiring line may be opposite to each other in the first direction. The bottom surface of the wiring line may be connected to the upper via pattern. The width of the bottom surface of the wiring line in the third direction may be greater than the width of the top surface of the wiring line in the third direction. The width of the top surface of the lower via pattern in the second direction may be equal to the width of the bottom surface of the upper via pattern in the second direction. The width of the top surface of the lower via pattern in the third direction may be equal to the width of the bottom surface of the upper via pattern in the third direction.

[0007] According to an embodiment of the present disclosure, a semiconductor device may include: a conductive pattern located on a substrate; an interlayer insulating film located on the conductive pattern and including a via hole; a lower via pattern connected to the conductive pattern and filling a portion of the via hole; and a wiring line pattern filling the remaining portion of the via hole. The wiring line pattern may be in contact with the top surface of the interlayer insulating film. The wiring line pattern may include an upper via pattern and a wiring extension line. The wiring line pattern may be located in the via hole and in contact with the entire top surface of the lower via pattern. The wiring extension line may extend in a first direction along the top surface of the interlayer insulating film. The upper via pattern may include an upper via filling film and an upper via barrier film extending along the sidewall of the upper via filling film. The wiring extension line and the upper via filling film may have an integral structure. The width of the wiring extension line in the second direction may decrease as the wiring extension line moves away from the lower via pattern.

[0008] According to an embodiment of the present disclosure, a semiconductor device may include: a gate electrode, the gate electrode is located on a substrate; a source / drain pattern, the source / drain pattern is located on one side of the gate electrode; a source / drain contact, the source / drain contact is located on the source / drain pattern and connected to the source / drain pattern; a via pattern, the via pattern is connected to the source / drain contact and includes a lower via pattern and an upper via pattern stacked in a first direction, and the entire top surface of the lower via pattern is in contact with the upper via pattern; a gate contact, the gate contact is connected to the gate electrode and includes a lower gate contact and an upper gate contact stacked in the first direction, and the entire top surface of the lower gate contact is in contact with the upper gate contact; a first wiring extension line, the first wiring extension line is located on the via pattern and extends in a second direction; and a second wiring extension line, the second wiring extension line is located on the gate contact. The upper via pattern may include an upper via filling film and an upper via barrier film. The upper via filling film may be directly connected to the first wiring extension line, and the upper via barrier film may extend along the sidewall of the upper via filling film. The upper gate contact may include an upper gate contact filling film and an upper gate contact barrier film. The upper gate contact filling film may be directly connected to the second wiring extension line. The upper gate contact barrier film may extend along the sidewall of the upper gate contact filling film. The width of the first wiring extension line in the third direction may decrease as the first wiring extension line moves away from the source / drain contact. The width of the second wiring extension line in the third direction may decrease as the second wiring extension line moves away from the gate electrode. The first wiring extension line, the second wiring extension line, the upper path filling film, and the upper gate contact filling film may each include ruthenium (Ru). BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 is an example layout diagram for illustrating a semiconductor device according to some embodiments.

[0010] Figure 2 It is along Figure 1 A cross-sectional view taken along line AA.

[0011] Figure 3 It is along Figure 1 A cross-sectional view taken along line BB.

[0012] Figure 4 It is along Figure 1 Cross-sectional view taken along line CC.

[0013] Figure 5 It is along Figure 1 A cross-sectional view taken along line DD.

[0014] Figure 6 yes Figure 2 An enlarged view of part P.

[0015] Figure 7 yes Figure 3 A magnified view of part Q.

[0016] Figure 8 yes Figure 4 An enlarged view of part R.

[0017] Fig. 9 yes Figure 5 An enlarged view of part S.

[0018] Figures 10 to 13 Each of them is a diagram for explaining a semiconductor device according to some embodiments.

[0019] Figures 14 to 16 is a diagram for explaining a semiconductor device according to some embodiments.

[0020] Figures 17 to 20 is a diagram for explaining a semiconductor device according to some embodiments.

[0021] Fig.21 and Fig. 22 Each of them is a diagram for explaining a semiconductor device according to some embodiments.

[0022] Fig.23 is a diagram for explaining a semiconductor device according to some embodiments.

[0023] Fig.24 and Fig.25 is a diagram for explaining a semiconductor device according to some embodiments.

[0024] Fig.26 is a diagram for explaining a semiconductor device according to some embodiments.

[0025] Figure 27 to Figure 29is a diagram for explaining a semiconductor device according to some embodiments.

[0026] Figures 30 to 37 is a diagram for explaining an intermediate stage of a method for manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0027] Although terms such as first and second are used in this specification to describe various elements or components, it goes without saying that these elements or components are not limited by these terms. These terms are only used to distinguish a single element or component from other elements or components. Therefore, it goes without saying that within the technical concept of the present disclosure, the first element or component mentioned below may be a second element or component.

[0028] Expressions such as "at least one of...", when preceding a list of elements, modify the entire list of elements, rather than the individual elements of the list. For example, "at least one of A, B, and C" and similar language (e.g., "at least one selected from the group consisting of A, B, and C" and "at least one of A, B, or C") may be interpreted as any combination of only A, only B, only C, or two or more of A, B, and C, such as, for example, ABC, AB, BC, and AC.

[0029] Although the term "equal to" is used in the description of the example embodiments, it should be understood that some imprecision may exist. Therefore, when an element is referred to as "equal to" another element, it should be understood that the element or value can be "equal to" the other element within a desired manufacturing or operating tolerance range (e.g., ±10%).

[0030] The semiconductor device according to some embodiments may include a tunnel transistor (tunnel FET) or a transistor based on two-dimensional materials (FET based on 2D materials) and a heterostructure thereof. In addition, the semiconductor device according to some embodiments may include a bipolar junction transistor, a lateral diffused metal oxide semiconductor (LDMOS), etc.

[0031] Reference Figures 1 to 9 A semiconductor device according to some embodiments is described.

[0032] Figure 1 is an example layout diagram for illustrating a semiconductor device according to some embodiments. Figure 2 It is along Figure 1 A cross-sectional view taken along line AA. Figure 3 It is along Figure 1 A cross-sectional view taken along line BB. Figure 4 It is along Figure 1 Cross-sectional view taken along line CC. Figure 5 It is along Figure 1 A cross-sectional view taken along line DD. Figure 6 yes Figure 2 An enlarged view of part P. Figure 7 yes Figure 3 A magnified view of part Q. Figure 8 yes Figure 4 An enlarged view of part R. Fig. 9 yes Figure 5 An enlarged view of part S.

[0033] refer to Figures 1 to 9 According to some embodiments, the semiconductor device may include a first active pattern AP1, a second active pattern AP2, a plurality of first gate electrodes 120, a first source / drain pattern 150, a first source / drain contact 170, a second source / drain contact 270, a first gate contact 175, a source / drain path pattern 180, a first wiring line 190, and a second wiring line 195.

[0034] The substrate 100 may be bulk silicon or silicon on insulator (SOI). In contrast, the substrate 100 may be a silicon substrate or may include other materials such as, but not limited to, silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or aluminum antimonide.

[0035] The first active pattern AP1 and the second active pattern AP2 may be respectively disposed on the substrate 100. The first active pattern AP1 and the second active pattern AP2 may each longitudinally extend in the first direction D1.

[0036] The first active pattern AP1 and the second active pattern AP2 may be positioned to be spaced apart from each other in the second direction D2. The first active pattern AP1 and the second active pattern AP2 may be adjacent to each other in the second direction D2.

[0037] As an example, one of the first active pattern AP1 and the second active pattern AP2 may be a region in which a p-type transistor is formed, and the other may be a region in which an n-type transistor is formed. As another example, the first active pattern AP1 and the second active pattern AP2 may be a region in which a p-type transistor is formed. As yet another example, the first active pattern AP1 and the second active pattern AP2 may be a region in which an n-type transistor is formed.

[0038] Each of the first active pattern AP1 and the second active pattern AP2 may be a multi-channel active pattern. For example, the first active pattern AP1 may include a first lower pattern BP1 and a plurality of first sheet patterns NS1. The second active pattern AP2 may include a second lower pattern BP2 and a plurality of second sheet patterns NS2. In the semiconductor device according to some embodiments, each of the first active pattern AP1 and the second active pattern AP2 may be an active pattern including nanosheets or nanowires.

[0039] Each of the first and second lower patterns BP1 and BP2 may protrude from the substrate 100. Each of the first and second lower patterns BP1 and BP2 may have a fin pattern shape.

[0040] The first lower pattern BP1 and the second lower pattern BP2 may each extend longitudinally in the first direction D1. The first lower pattern BP1 may be spaced apart from the second lower pattern BP2 in the second direction D2. The first lower pattern BP1 and the second lower pattern BP2 may be separated by a fin trench FT extending in the first direction D1. For example, a bottom surface of the fin trench FT may be a top surface of the substrate 100.

[0041] Each of the first lower pattern BP1 and the second lower pattern BP2 includes a sidewall extending in the first direction D1. The sidewalls of the first lower pattern BP1 and the second lower pattern BP2 may be defined by the fin trench FT.

[0042] A plurality of first sheet patterns NS1 may be disposed on the first lower pattern BP1. The plurality of first sheet patterns NS1 may be spaced apart from a top surface of the first lower pattern BP1 in the third direction D3.

[0043] A plurality of second sheet patterns NS2 may be disposed on the second lower pattern BP2. The plurality of second sheet patterns NS2 may be spaced apart from a top surface of the second lower pattern BP2 in the third direction D3.

[0044] Here, the first direction D1 may intersect the second direction D2 and the third direction D3. In addition, the second direction D2 may intersect the third direction D3. The third direction D3 may be a thickness direction of the substrate 100.

[0045] The first sheet pattern NS1 and the second sheet pattern NS2 may each include a top surface and a bottom surface opposite to each other in the third direction D3. The bottom surface of the first sheet pattern NS1 and the bottom surface of the second sheet pattern NS2 may look at the substrate 100. Although the three first sheet patterns NS1 and the three second sheet patterns NS2 are shown as being arranged along the third direction D3, this is only for convenience of explanation, and the embodiment is not limited thereto.

[0046] Each of the first lower pattern BP1 and the second lower pattern BP2 may be formed by etching a portion of the substrate 100, or may include an epitaxial layer grown from the substrate 100. Each of the first lower pattern BP1 and the second lower pattern BP2 may include silicon or germanium as an elemental semiconductor material. In addition, each of the first lower pattern BP1 and the second lower pattern BP2 may include a compound semiconductor, and may include, for example, a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0047] Group IV-IV compound semiconductors may include, for example, binary or ternary compounds having at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or compounds obtained by doping these elements with Group IV elements.

[0048] The III-V compound semiconductor may be, for example, at least one of a binary compound, a ternary compound, or a quaternary compound formed by combining at least one of aluminum (Al), gallium (Ga), and indium (In) as III-group elements with one of phosphorus (P), arsenic (As), and antimony (Sb) as V-group elements.

[0049] Each of the first sheet pattern NS1 and the second sheet pattern NS2 may include one of silicon or germanium as an elemental semiconductor material, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. The width of the first sheet pattern NS1 in the second direction D2 may increase or decrease in proportion to the width of the first lower pattern BP1 in the second direction D2. The width of the second sheet pattern NS2 in the second direction D2 may increase or decrease in proportion to the width of the second lower pattern BP2 in the second direction D2.

[0050] Taking the first sheet pattern NS1 as an example, although the width of each of the first sheet patterns NS1 disposed on the first lower pattern BP1 in the second direction D2 is shown to be the same, the embodiment is not limited thereto.

[0051] The field insulating film 105 is disposed on the substrate 100. The field insulating film 105 may fill at least a portion of the fin trench FT separating the first lower pattern BP1 and the second lower pattern BP2.

[0052] The field insulating film 105 may be disposed on the substrate 100 between the first lower pattern BP1 and the second lower pattern BP2. As an example, the field insulating film 105 may cover the entire sidewall of the first lower pattern BP1 and the entire sidewall of the second lower pattern BP2.

[0053] Unlike the illustrated example, as another example, the field insulating film 105 may cover a portion of the sidewall of the first lower pattern BP1 and / or a portion of the sidewall of the second lower pattern BP2. For example, a portion of the first lower pattern BP1 and / or a portion of the second lower pattern BP2 may protrude beyond the top surface of the field insulating film 105 in the third direction D3.

[0054] The field insulating film 105 does not cover top surfaces of the first and second lower patterns BP1 and BP2 . Each of the first and second sheet patterns NS1 and NS2 is disposed higher than a top surface of the field insulating film 105 based on a top surface of the substrate 100 .

[0055] Although the top surface of the field insulating film 105 is shown as being concave, this is only for convenience of description, and the embodiment is not limited thereto. The field insulating film 105 may include, for example, an oxide film, a nitride film, an oxynitride film, or a combination thereof. Although the field insulating film 105 is shown as a single film, this is only for convenience of description, and the embodiment is not limited thereto.

[0056] A plurality of gate structures GS may be disposed on the substrate 100. Each gate structure GS may extend in the second direction D2. The gate structures GS may be spaced apart from each other in the first direction D1. The gate structures GS may be adjacent to each other in the first direction D1.

[0057] The gate structure GS may be disposed on the first active pattern AP1 and the second active pattern AP2. The gate structure GS may intersect the first active pattern AP1 and the second active pattern AP2.

[0058] The gate structure GS may intersect the first lower pattern BP1 and the second lower pattern BP2. The gate structure GS may surround each of the first sheet patterns NS1. The gate structure GS may surround each of the second sheet patterns NS2.

[0059] Although the gate structure GS is shown as being disposed above the first active pattern AP1 and the second active pattern AP2, this is only for convenience of explanation, and the embodiment is not limited thereto. That is, although not shown, a portion of the gate structure GS may be divided into two portions by a gate separation structure disposed on the field insulating film 105, and may be disposed on the first active pattern AP1 and the second active pattern AP2.

[0060] The gate structure GS may include, for example, a first gate electrode 120 , a first gate insulating film 130 , a first gate spacer 140 , and a gate capping pattern 145 .

[0061] The gate structure GS may include a plurality of inner gate structures GS_INT disposed between first sheet patterns NS1 adjacent to each other in the third direction D3 and between the first lower pattern BP1 and the first sheet pattern NS1. The inner gate structure GS_INT may be disposed between a top surface of the first lower pattern BP1 and a bottom surface of the first sheet pattern NS1, and between a top surface of the first sheet pattern NS1 facing each other in the third direction D3 and a bottom surface of the first sheet pattern NS1.

[0062] The number of the inner gate structures GS_INT may be the same as the number of the first sheet patterns NS1. The inner gate structure GS_INT contacts the top surface of the first lower pattern BP1, the top surface of the first sheet pattern NS1, and the bottom surface of the first sheet pattern NS1. In the semiconductor device according to some embodiments, the inner gate structure GS_INT may contact the first source / drain pattern 150 which will be described later.

[0063] The inner gate structure GS_INT includes a first gate electrode 120 and a first gate insulating film 130 disposed between adjacent first sheet patterns NS1 and between the first lower pattern BP1 and the first sheet pattern NS1. Although not shown, the inner gate structure GS_INT may be disposed between second sheet patterns NS2 adjacent to each other in the third direction D3 and between the second lower pattern BP2 and the second sheet pattern NS2.

[0064] The first gate electrode 120 may be disposed on the first and second lower patterns BP1 and BP2. The first gate electrode 120 may intersect the first and second lower patterns BP1 and BP2. The first gate electrode 120 may surround the first and second sheet patterns NS1 and NS2.

[0065] In such Figure 2 In the cross-sectional view of FIG. 1 , the top surface of the first gate electrode 120 is shown as a concave curved surface, but the embodiment is not limited thereto. Needless to say, the top surface of the first gate electrode 120 may be a flat surface.

[0066] The first gate electrode 120 may include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. The first gate electrode 120 may include, but is not limited to, for example, at least one of titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlCN), titanium aluminum carbide (TiAlC), titanium carbide (TiC), carbonitride (CNT), titanium aluminum nitride (TiAlN), titanium aluminum nitride (TiAlCN), titanium aluminum nitride (TiAlC), titanium carbide (TiC), titanium aluminum nitride (TiAlN), titanium aluminum nitride (TiAlCN), titanium aluminum nitride (TiAlCN), titanium aluminum nitride (TiAlCN), titanium aluminum nitride (TiAlCN), titanium aluminum nitride (TiC), titanium aluminum nitride (TiN), titanium aluminum nitride (TiAlN), titanium aluminum nitride (TiAlCN), titanium aluminum nitride (TiAlCN), titanium aluminum nitride (TiC), titanium aluminum nitride (TiN ... Tantalum (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (NiPt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V) and combinations thereof. Conductive metal oxides and conductive metal oxynitrides may include, but are not limited to, oxidized forms of the foregoing materials.

[0067] The first gate insulating film 130 may extend along the top surface of the field insulating film 105, the top surface of the first lower pattern BP1, and the top surface of the second lower pattern BP2. The first gate insulating film 130 may cover the plurality of first sheet patterns NS1. The first gate insulating film 130 may cover the plurality of second sheet patterns NS2. The first gate insulating film 130 may be disposed along the periphery of the first sheet pattern NS1 and along the periphery of the second sheet pattern NS2. The first gate electrode 120 is disposed on the first gate insulating film 130.

[0068] The first gate insulating film 130 is disposed between the first gate electrode 120 and the first sheet pattern NS1 and between the first gate electrode 120 and the second sheet pattern NS2. In the semiconductor device according to some embodiments, the first gate insulating film 130 included in the inner gate structure GS_INT may contact the first source / drain pattern 150 to be described below.

[0069] The first gate insulating film 130 may include silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide. The high dielectric constant material may include, for example, one or more of boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0070] Although the first gate insulating film 130 is shown as a single film, this example is only for convenience of explanation and is not limited thereto. The first gate insulating film 130 may include a plurality of films. The first gate insulating film 130 may include an interface layer and a high dielectric constant insulating film placed between the first active pattern AP1 and the first gate electrode 120 and between the second active pattern AP2 and the first gate electrode 120. For example, the interface layer may not be formed along the contour of the top surface of the field insulating film 105.

[0071] The semiconductor device according to some embodiments may include a negative capacitance (NC) FET using a negative capacitor.For example, the first gate insulating film 130 may include a ferroelectric material film having a ferroelectric property and a paraelectric material film having a paraelectric property.

[0072] A ferroelectric material film may have a negative capacitance, while a paraelectric material film may have a positive capacitance. For example, if two or more capacitors are connected in series and the capacitance of each capacitor has a positive value, the total capacitance is reduced compared to the capacitance of each individual capacitor. On the other hand, if at least one of the capacitances of two or more capacitors connected in series has a negative value, the total capacitance may be greater than the absolute value of each individual capacitance while having a positive value.

[0073] When a ferroelectric material film having negative capacitance and a paraelectric material film having positive capacitance are connected in series, the total capacitance value of the ferroelectric material film and the paraelectric material film connected in series may increase. By using the increased total capacitance value, a transistor including the ferroelectric material film can have a subthreshold swing (SS) below 60mV / decade at room temperature.

[0074] The ferroelectric material film may have ferroelectric properties. The ferroelectric material film may include, for example, at least one of hafnium oxide, hafnium zirconium oxide, barium strontium titanium oxide, barium titanium oxide, and lead zirconium titanium oxide. Here, as an example, hafnium zirconium oxide may be a material obtained by doping hafnium oxide with zirconium (Zr). As another example, hafnium zirconium oxide may be a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0075] The ferroelectric material film may also include doped dopants. For example, the dopant may include at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr) and tin (Sn). The type of dopant included in the ferroelectric material film may vary depending on the type of ferroelectric material included in the ferroelectric material film.

[0076] When the ferroelectric material film includes hafnium oxide, the dopant included in the ferroelectric material film may include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0077] When the dopant is aluminum (Al), the ferroelectric material film may include 3 to 8 at% (atomic %) of aluminum. Here, the ratio of the dopant may be a ratio of aluminum to the sum of hafnium and aluminum.

[0078] When the dopant is silicon (Si), the ferroelectric material film may include 2at% to 10at% silicon. When the dopant is yttrium (Y), the ferroelectric material film may include 2at% to 10at% yttrium. When the dopant is gadolinium (Gd), the ferroelectric material film may include 1at% to 7at% gadolinium. When the dopant is zirconium (Zr), the ferroelectric material film may include 50at% to 80at% zirconium.

[0079] The paraelectric material film may have paraelectric properties. The paraelectric material film may include, for example, at least one of silicon oxide and a metal oxide with a high dielectric constant. The metal oxide included in the paraelectric material film may include, for example but not limited to, at least one of hafnium oxide, zirconium oxide, and aluminum oxide.

[0080] The ferroelectric material film and the paraelectric material film may include the same material. The ferroelectric material film has ferroelectric properties, but the paraelectric material film may not have ferroelectric properties. For example, when the ferroelectric material film and the paraelectric material film include hafnium oxide, the crystal structure of the hafnium oxide included in the ferroelectric material film is different from the crystal structure of the hafnium oxide included in the paraelectric material film.

[0081] The ferroelectric material film may have a thickness that exhibits ferroelectric properties. The thickness of the ferroelectric material film may be, for example but not limited to, 0.5 nm to 10 nm. Since the critical thickness that exhibits ferroelectric properties may vary for each ferroelectric material, the thickness of the ferroelectric material film may vary depending on the ferroelectric material.

[0082] As an example, the first gate insulating film 130 may include one ferroelectric material film. As another example, the first gate insulating film 130 may include a plurality of ferroelectric material films spaced apart from each other. The first gate insulating film 130 may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0083] The first gate spacer 140 may be placed on the sidewall of the first gate electrode 120. The first gate spacer 140 may not be placed between the first lower pattern BP1 and the first sheet pattern NS1, and may not be placed between first sheet patterns NS1 adjacent in the third direction D3.

[0084] The first gate spacer 140 may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. Although the first gate spacer 140 is shown as a single film, this example is only for ease of explanation and is not limited thereto.

[0085] The gate capping pattern 145 may be placed on the top surface of the first gate electrode 120. The top surface of the gate capping pattern 145 may be the top surface of the gate structure GS. Figure 2 In the cross-sectional view of FIG. 1 , the gate capping pattern 145 may cover the top surface of the first gate spacer 140. Unlike the illustrated example, the gate capping pattern 145 may be placed between the first gate spacers 140.

[0086] The gate capping pattern 145 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and combinations thereof. The gate capping pattern 145 may include a material having an etching selectivity with respect to the lower interlayer insulating film 191 .

[0087] The first source / drain pattern 150 may be placed on the first active pattern AP1. The first source / drain pattern 150 may be placed on the first lower pattern BP1. The first source / drain pattern 150 is connected to the first sheet pattern NS1.

[0088] The first source / drain pattern 150 may be disposed on the side of the gate structure GS. The first source / drain pattern 150 may be disposed between the gate structures GS adjacent to each other along the first direction D1. For example, the first source / drain pattern 150 may be disposed on both sides of the gate structure GS. Different from the illustrated example, the first source / drain pattern 150 may be disposed on one side of the gate structure GS, but may not be disposed on the other side of the gate structure GS.

[0089] The first source / drain pattern 150 may be included in a source / drain of a transistor using the first sheet pattern NS1 as a channel region.

[0090] The first source / drain pattern 150 may contact the first sheet pattern NS1 and the first lower pattern BP1 . For example, the first gate insulating film 130 included in the inner gate structure GS_INT may contact the first source / drain pattern 150 .

[0091] Although not shown, the second source / drain pattern may be disposed on the second active pattern AP2. The second source / drain pattern may be connected to the second sheet pattern NS2.

[0092] The first source / drain pattern 150 may include an epitaxial pattern. The first source / drain pattern 150 includes a semiconductor material.

[0093] The first source / drain pattern 150 may include, for example, silicon or germanium as an elemental semiconductor material. Likewise, the first source / drain pattern 150 may include a binary compound or a ternary compound having at least two or more of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), or a compound obtained by doping these elements with a group IV element. For example, the first source / drain pattern 150 may include, but is not limited to, silicon, silicon germanium, silicon carbide, and the like.

[0094] The first source / drain pattern 150 may include impurities doped in the semiconductor material. The first source / drain pattern 150 may include a p-type dopant or an n-type dopant. The p-type dopant may include, but is not limited to, at least one of boron (B) and gallium (Ga). The n-type dopant may include, but is not limited to, at least one of phosphorus (P), arsenic (As), antimony (Sb), and bismuth (Bi).

[0095] Although the first source / drain pattern 150 is illustrated as a single film, this is only for convenience of explanation, and embodiments are not limited thereto.

[0096] The source / drain etch stop film 156 may extend along sidewalls of the gate structure GS, a top surface of the first source / drain pattern 150 , sidewalls of the first source / drain pattern 150 , and a top surface of the field insulating film 105 .

[0097] The source / drain etch stop film 156 may not extend along the sidewall of the gate capping pattern 145. Unlike the illustrated example, the source / drain etch stop film 156 may extend along the sidewall of the gate capping pattern 145.

[0098] The source / drain etch stop film 156 may include a material having an etch selectivity relative to the lower interlayer insulating film 191. The source / drain etch stop film 156 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. Unlike the illustrated example, the source / drain etch stop film 156 may not be formed.

[0099] The lower interlayer insulating film 191 may be disposed on the substrate 100. The lower interlayer insulating film 191 may be disposed on the source / drain etch stop film 156. The lower interlayer insulating film 191 may not cover the top surface of the gate capping pattern 145. For example, the top surface of the lower interlayer insulating film 191 may be disposed on the same plane as the top surface of the gate capping pattern 145.

[0100] The lower interlayer insulating film 191 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The dielectric constant of the low dielectric constant material may have a value less than 3.9 which is the dielectric constant of silicon oxide.

[0101] The contact separation structure CSS may be provided in the lower interlayer insulating film 191. The contact separation structure CSS may not extend to the field insulating film 105.

[0102] The contact separation structure CSS may not separate the source / drain etch stop film 156. A portion of the lower interlayer insulating film 191 may be disposed between the contact separation structure CSS and the field insulating film 105. The width of the contact separation structure CSS in the second direction D2 may increase as it moves away from the field insulating film 105.

[0103] The contact separation structure CSS may be disposed on both sides of the first source / drain pattern 150. In other words, the first source / drain pattern 150 may be disposed between the contact separation structures CSS adjacent to each other along the second direction D2. Although not shown, the contact separation structure CSS may be disposed on both sides of the second source / drain pattern.

[0104] The contact separation structure CSS includes an insulating material. The contact separation structure CSS may include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO 2 ), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon oxyboron nitride (SiOBN), silicon oxycarbide (SiOC), aluminum oxide (AlO), and combinations thereof. Although the contact separation structure CSS is shown as a single film, this is only for ease of explanation and the embodiment is not limited thereto.

[0105] The first source / drain contact 170 is disposed on the first source / drain pattern 150. The first source / drain contact 170 is electrically connected to the first source / drain pattern 150.

[0106] The first source / drain contact 170 may be placed between the contact separation structures CSS. The first source / drain contact 170 may be in contact with the contact separation structures CSS.

[0107] The first source / drain contact 170 may be disposed on the lower interlayer insulating film 191. Although the top surface 170US of the first source / drain contact may be placed on the same plane as the top surface of the gate capping pattern 145, the embodiment is not limited thereto.

[0108] A contact silicide film 155 may be disposed between the first source / drain contact 170 and the first source / drain pattern 150 .

[0109] Although the first source / drain contact 170 is shown as having a single conductive film structure, the embodiment is not limited thereto. Unlike the illustrated example, the first source / drain contact 170 may have a multi-conductive film structure including a barrier film and a plug film. The first source / drain contact 170 may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material (2D material). The contact silicide film 155 may include a metal silicide material.

[0110] The 2D material may include a 2D allotrope or a 2D compound, and may include, for example, but not limited to, at least one of graphene, boron nitride (BN), molybdenum sulfide, molybdenum selenide, tungsten sulfide, tungsten selenide, and tantalum sulfide. That is, since the above-mentioned 2D materials are listed only by way of example, the 2D materials that may be included in the semiconductor device of the present disclosure are not limited to the above-mentioned materials.

[0111] Although not shown, the second source / drain contact 270 may be disposed on the second active pattern AP2. The second source / drain contact 270 may be connected to the second source / drain pattern. A cross section of the second source / drain contact 270 taken along the second direction D2 may be similar to Figure 4 Needless to say, the description of the first source / drain contact 170 also applies to the second source / drain contact 270 .

[0112] The first gate electrode 120 and the first source / drain contact 170 may be conductive patterns disposed on the substrate 100. The first gate electrode 120 and the first source / drain contact 170 may be conductive patterns connected to the first wiring line 190 and the second wiring line 195. For example, the first source / drain contact 170 may be a first conductive pattern connected to the first wiring line 190. The first gate electrode 120 may be a second conductive pattern connected to the second wiring line 195.

[0113] A first upper interlayer insulating film 192 may be disposed on the gate capping pattern 145 and the first and second source / drain contacts 170 and 270. The first upper interlayer insulating film 192 may cover top surfaces 170US of the first source / drain contacts.

[0114] The first upper interlayer insulating film 192 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The dielectric constant of the low dielectric constant material may have a value less than 3.9 which is the dielectric constant of silicon oxide.

[0115] Although not shown, a contact etch stopper film may be disposed between the first upper interlayer insulating film 192 and the gate capping pattern 145 and between the first upper interlayer insulating film 192 and the first source / drain contact 170. The contact etch stopper film may include a material having an etch selectivity with respect to the first upper interlayer insulating film 192.

[0116] The first gate contact 175 may be disposed in the first upper interlayer insulating film 192 and the gate capping pattern 145. The first gate contact 175 may penetrate the first upper interlayer insulating film 192 and the gate capping pattern 145.

[0117] The first gate contact 175 may be disposed in the gate contact hole 175H. The gate contact hole 175H extends from the top surface 192US of the first upper interlayer insulating film to the top surface of the first gate electrode 120.

[0118] The first gate contact 175 is disposed on the first gate electrode 120. The first gate contact 175 may be connected to the first gate electrode 120. Although the first gate electrode 120 is illustrated as being disposed between the first lower pattern BP1 and the second lower pattern BP2, the embodiment is not limited thereto.

[0119] The source / drain via pattern 180 may be disposed in the first upper interlayer insulating film 192. The source / drain via pattern 180 may penetrate the first upper interlayer insulating film 192.

[0120] The source / drain via pattern 180 may be disposed in the source / drain via hole 180H. The first upper interlayer insulating film 192 includes the source / drain via hole 180H.

[0121] The source / drain via pattern 180 may be connected to the first source / drain contact 170. The source / drain via pattern 180 may be disposed on the top surface 170US of the first source / drain contact. Although not shown, the source / drain via pattern 180 may be disposed on the second source / drain contact 280.

[0122] The first gate contact 175 may be a first via pattern connected to the first gate electrode 120. The source / drain via pattern 180 may be a second via pattern connected to the first source / drain contact 170. In other words, the first gate contact 175 and the source / drain via pattern 180 may be via patterns connected to a conductive pattern on the substrate 100.

[0123] The source / drain via pattern 180 may include a lower via pattern 181 and an upper via pattern 182 stacked along the third direction D3. The lower via pattern 181 and the upper via pattern 182 may be disposed in the first upper interlayer insulating film 192. The lower via pattern 181 is disposed between the first source / drain contact 170 and the upper via pattern 182.

[0124] The lower via pattern 181 may partially fill the source / drain via hole 180H. The upper via pattern 182 may fill the remaining portion of the source / drain via hole 180H.

[0125] The lower via pattern 181 may include a top surface 181US looking at the upper via pattern 182. The lower via pattern 181 may include a bottom surface opposite to the top surface 181US of the lower via pattern in the third direction D3. The upper via pattern 182 may include a bottom surface 182BS looking at the lower via pattern 181. The bottom surface 182BS of the upper via pattern looks at the first source / drain contact 170. In the semiconductor device according to some embodiments, the top surface 181US of the lower via pattern may be a plane from a cross-sectional perspective.

[0126] exist Figure 2 and Figure 6 In the embodiment, the width W21 of the top surface 181US of the lower via pattern in the first direction D1 is the same as the width W22 of the bottom surface 182BS of the upper via pattern in the first direction D1. Figure 4 and Figure 8 , a width W31 of a top surface 181US of the lower via pattern in the second direction D2 is the same as a width W32 of a bottom surface 182BS of the upper via pattern in the second direction D2.

[0127] The top surface 181US of the lower via pattern may contact the bottom surface 182BS of the upper via pattern. For example, the entire top surface 181US of the lower via pattern may contact the upper via pattern 182. The entire bottom surface 182BS of the upper via pattern may contact the lower via pattern 181.

[0128] In the semiconductor device according to some embodiments, the lower via pattern 181 may have a single film structure. The lower via pattern 181 may be formed of a single conductive material. The lower via pattern 181 may have a single conductive film structure.

[0129] The lower path pattern 181 may include a metal. The lower path pattern 181 may include, for example, one of tungsten (W), molybdenum (Mo), and cobalt (Co). For example, when the lower path pattern 181 includes molybdenum (Mo), the lower path pattern 181 may have a single film structure formed of molybdenum. Here, the single film structure formed of molybdenum does not mean a structure formed only of molybdenum. When the lower path pattern 181 including molybdenum is being formed, various impurities may flow into the lower path pattern 181. That is, the lower path pattern 181 as a single film structure made of molybdenum may contain impurities contained in the molybdenum film.

[0130] The upper via pattern 182 may include an upper via barrier film 182A and an upper via filling film 182B. For example, the upper via pattern 182 may be a multi-film structure including conductive materials different from each other.

[0131] The upper via barrier film 182A may extend along the sidewall of the upper via filling film 182B. The upper via barrier film 182A may not extend along the bottom surface of the upper via filling film 182B.

[0132] The bottom surface 182BS of the upper via pattern may be defined by the upper via barrier film 182A and the upper via filling film 182B. For example, the upper via barrier film 182A and the upper via filling film 182B may contact the top surface 181US of the lower via pattern. The upper via filling film 182B may be directly connected to the lower via pattern 181.

[0133] The upper via barrier film 182A may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material (2D material). For example, the upper via barrier film 182A may include, but is not limited to, tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), nickel (Ni), nickel boron (NiB), tungsten (W), tungsten nitride (WN), tungsten carbonitride (WCN), zirconium (Zr), zirconium nitride (ZrN), vanadium (V), vanadium nitride (VN), niobium (Nb), niobium nitride (NbN), platinum (Pt), iridium (Ir), rhodium (Rh), and at least one of a two-dimensional material.

[0134] The upper via fill film 182B may include a metal. The upper via fill film 182B may include a metal different from that of the lower via pattern 181. For example, the upper via fill film 182B may include ruthenium (Ru).

[0135] The first gate contact 175 may include a lower gate contact 176 and an upper gate contact 177 stacked along the third direction D3. The lower gate contact 176 is disposed between the first gate electrode 120 and the upper gate contact 177. The lower gate contact 176 may partially fill the gate contact hole 175H. The upper gate contact 177 may fill the rest of the gate contact hole 175H.

[0136] The lower gate contact 176 may be disposed in the first upper interlayer insulating film 192 and the gate capping pattern 145. The upper gate contact 177 may be disposed in the first upper interlayer insulating film 192.

[0137] The lower gate contact 176 may include a top surface 176US looking at the upper gate contact 177. The lower gate contact 176 may include a bottom surface opposite to the top surface 176US of the lower gate contact in the third direction D3. The upper gate contact 177 may include a bottom surface 177BS looking at the lower gate contact 176. The bottom surface 177BS of the upper gate contact looks at the first gate electrode 120. In the semiconductor device according to some embodiments, the top surface 176US of the lower gate contact may be a plane from a cross-sectional perspective.

[0138] A portion of the lower gate contact 176 may protrude beyond a top surface of the gate capping pattern 145. A top surface 176US of the lower gate contact is higher than a top surface of the gate capping pattern 145 based on a top surface of the first gate electrode 120.

[0139] exist Figure 3 and Figure 7 In the embodiment, the width of the top surface 176US of the lower gate contact in the second direction D2 is the same as the width of the bottom surface 177BS of the upper gate contact in the second direction D2. Figure 5 and Fig. 9 , a width of a top surface 176US of the lower gate contact in the first direction D1 is the same as a width of a bottom surface 177BS of the upper gate contact in the first direction D1.

[0140] The top surface 176US of the lower gate contact may contact the bottom surface 177BS of the upper gate contact. For example, the entire top surface 176US of the lower gate contact may contact the upper gate contact 177. The entire bottom surface 177BS of the upper gate contact may contact the lower gate contact 176.

[0141] In the semiconductor device according to some embodiments, the lower gate contact 176 may have a single film structure. The lower gate contact 176 may be formed of a single conductive material. The lower gate contact 176 may have a single conductive film structure.

[0142] The lower gate contact 176 may include a metal. The lower gate contact 176 may include, for example, one of tungsten (W), molybdenum (Mo), and cobalt (Co). As an example, the lower gate contact 176 may include the same metal as the lower via pattern 181. When the lower via pattern 181 includes molybdenum, the lower gate contact 176 may include molybdenum. As another example, the lower gate contact 176 may include a different metal from the lower via pattern 181.

[0143] The upper gate contact 177 may include an upper gate barrier film 177A and an upper gate filling film 177B. For example, the upper gate contact 177 may be a multi-film structure including conductive materials different from each other.

[0144] The upper gate blocking film 177A may extend along the sidewall of the upper gate filling film 177B. The upper gate blocking film 177A may not extend along the bottom surface of the upper gate filling film 177B.

[0145] The bottom surface 177BS of the upper gate contact may be defined by the upper gate barrier film 177A and the upper gate filling film 177B. For example, the upper gate barrier film 177A and the upper gate filling film 177B may contact the top surface 176US of the lower gate contact. The upper gate filling film 177B may be directly connected to the lower gate contact 176.

[0146] The upper gate barrier film 177A may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional (2D) material. The upper gate filling film 177B may include a metal. The upper gate filling film 177B may include a metal different from the lower gate contact 176. The upper gate filling film 177B may include the same metal as the upper via filling film 182B. For example, the upper gate filling film 177B may include ruthenium (Ru).

[0147] In the following description of the slope of the sidewall, the bottom surface of the lower via pattern 181 and the bottom surface of the lower gate contact 176 will be described as a plane including the first direction D1 and the second direction D2. In other words, the bottom surface of the lower via pattern 181 and the bottom surface of the lower gate contact 176 will be described as being perpendicular to the third direction D3.

[0148] exist Figure 2 and Figure 6, the lower via pattern 181 may include a first sidewall 181S1 and a second sidewall 181S2 opposite to each other in the first direction D1. The upper via pattern 182 may include a first sidewall 182S1 and a second sidewall 182S2 opposite to each other in the first direction D1. The first sidewall 182S1 of the upper via pattern and the second sidewall 182S2 of the upper via pattern may be defined by an upper via barrier film 182A.

[0149] A first sidewall 181S1 of the lower via pattern is connected to a first sidewall 182S1 of the upper via pattern. A second sidewall 181S2 of the lower via pattern is connected to a second sidewall 182S2 of the upper via pattern.

[0150] For example, the first sidewall 181S1 of the lower via pattern forms an obtuse angle with respect to the bottom surface of the lower via pattern 181. The second sidewall 181S2 of the lower via pattern forms an obtuse angle with respect to the bottom surface of the lower via pattern 181. The first sidewall 182S1 of the upper via pattern forms an obtuse angle with respect to the bottom surface 182BS of the upper via pattern. The second sidewall 182S2 of the upper via pattern forms an obtuse angle with respect to the bottom surface 182BS of the upper via pattern.

[0151] Hereinafter, when the sidewall forms an obtuse angle with respect to the bottom surface, the slope of the sidewall will be described as having a positive value. Alternatively, when the sidewall forms an obtuse angle with respect to the bottom surface, the sidewall may have a positive slope value. In contrast, when the sidewall forms an acute angle with respect to the bottom surface, the slope of the sidewall will be described as having a negative value. Alternatively, when the sidewall forms an acute angle with respect to the bottom surface, the sidewall may have a negative slope value.

[0152] The slope of the first sidewall 181S1 of the lower via pattern may have a positive value. The slope of the second sidewall 181S2 of the lower via pattern may have a positive value. The slope of the first sidewall 182S1 of the upper via pattern may have a positive value. The slope of the second sidewall 182S2 of the upper via pattern may have a positive value.

[0153] The slope of the first sidewall 181S1 of the lower via pattern has the same sign as the slope of the second sidewall 181S2 of the lower via pattern. The slope of the first sidewall 182S1 of the upper via pattern has the same sign as the slope of the second sidewall 182S2 of the upper via pattern.

[0154] The slope of the first sidewall 181S1 of the lower via pattern has the same sign as the slope of the first sidewall 182S1 of the upper via pattern. The slope of the second sidewall 181S2 of the lower via pattern has the same sign as the slope of the second sidewall 182S2 of the upper via pattern.

[0155] exist Figure 4 and Figure 8, the lower via pattern 181 may include a third sidewall 181S3 and a fourth sidewall 181S4 opposite to each other in the second direction D2. The upper via pattern 182 may include a third sidewall 182S3 and a fourth sidewall 182S4 opposite to each other in the second direction D2. The third sidewall 182S3 of the upper via pattern and the fourth sidewall 182S4 of the upper via pattern may be defined by an upper via barrier film 182A.

[0156] The third sidewall 181S3 of the lower via pattern is connected to the third sidewall 182S3 of the upper via pattern. The fourth sidewall 181S4 of the lower via pattern is connected to the fourth sidewall 182S4 of the upper via pattern.

[0157] The slope of the third sidewall 181S3 of the lower via pattern may have a positive value. The slope of the fourth sidewall 181S4 of the lower via pattern may have a positive value. The slope of the third sidewall 182S3 of the upper via pattern may have a positive value. The slope of the fourth sidewall 182S4 of the upper via pattern may have a positive value.

[0158] The slope of the third sidewall 181S3 of the lower via pattern has the same sign as the slope of the fourth sidewall 181S4 of the lower via pattern. The slope of the third sidewall 182S3 of the upper via pattern has the same sign as the slope of the fourth sidewall 182S4 of the upper via pattern.

[0159] The slope of the third sidewall 181S3 of the lower via pattern has the same sign as the slope of the third sidewall 182S3 of the upper via pattern. The slope of the fourth sidewall 181S4 of the lower via pattern has the same sign as the slope of the fourth sidewall 182S4 of the upper via pattern.

[0160] exist Figure 5 and Fig. 9 , the lower gate contact 176 may include a first sidewall 176S1 and a second sidewall 176S2 opposite to each other in the first direction D1. The upper gate contact 177 may include a first sidewall 177S1 and a second sidewall 177S2 opposite to each other in the first direction D1. The first sidewall 177S1 of the upper gate contact and the second sidewall 177S2 of the upper gate contact may be defined by the upper gate blocking film 177A.

[0161] The first sidewall 176S1 of the lower gate contact is connected to the first sidewall 177S1 of the upper gate contact. The second sidewall 176S2 of the lower gate contact is connected to the second sidewall 177S2 of the upper gate contact.

[0162] The slope of the first sidewall 176S1 of the lower gate contact has the same sign as the slope of the second sidewall 176S2 of the lower gate contact. The slope of the first sidewall 177S1 of the upper gate contact has the same sign as the slope of the second sidewall 177S2 of the upper gate contact.

[0163] The sign of the slope of the first sidewall 176S1 of the lower gate contact is the same as the sign of the slope of the first sidewall 177S1 of the upper gate contact. The sign of the slope of the second sidewall 176S2 of the lower gate contact is the same as the sign of the slope of the second sidewall 177S2 of the upper gate contact.

[0164] exist Figure 3 and Figure 7 , the lower gate contact 176 may include a third sidewall 176S3 and a fourth sidewall 176S4 opposite to each other in the second direction D2. The upper gate contact 177 may include a third sidewall 177S3 and a fourth sidewall 177S4 opposite to each other in the second direction D2. The third sidewall 177S3 of the upper gate contact and the fourth sidewall 177S4 of the upper gate contact may be defined by the upper gate blocking film 177A.

[0165] The third sidewall 176S3 of the lower gate contact is connected to the third sidewall 177S3 of the upper gate contact. The fourth sidewall 176S4 of the lower gate contact is connected to the fourth sidewall 177S4 of the upper gate contact.

[0166] The sign of the slope of the third sidewall 176S3 of the lower gate contact is the same as the sign of the slope of the fourth sidewall 176S4 of the lower gate contact. The sign of the slope of the third sidewall 177S3 of the upper gate contact is the same as the sign of the slope of the fourth sidewall 177S4 of the upper gate contact.

[0167] The sign of the slope of the third sidewall 176S3 of the lower gate contact is the same as the sign of the slope of the third sidewall 177S3 of the upper gate contact. The sign of the slope of the fourth sidewall 176S4 of the lower gate contact is the same as the sign of the slope of the fourth sidewall 177S4 of the upper gate contact.

[0168] The first wiring line 190 may be disposed on the source / drain via pattern 180. The first wiring line 190 is connected to the source / drain via pattern 180.

[0169] The second wiring line 195 may be disposed on the first gate contact 175. The second wiring line 195 is connected to the first gate contact 175.

[0170] The first wiring line 190 and the second wiring line 195 may each extend in the first direction D1. The first wiring line 190 may be spaced apart from the second wiring line 195 in the second direction D2. The first wiring line 190 and the second wiring line 195 may extend along the top surface 192US of the first upper interlayer insulating film. Each of the first wiring line 190 and the second wiring line 195 may contact the top surface 192US of the first upper interlayer insulating film.

[0171] The first wiring line 190 may include a top surface 190US and a bottom surface 190BS opposite to each other in the third direction D3. The bottom surface 190BS of the first wiring line looks at the first upper interlayer insulating film 192. The bottom surface 190BS of the first wiring line contacts the top surface 192US of the first upper interlayer insulating film. The bottom surface 190BS of the first wiring line is connected to the upper via pattern 182.

[0172] The second wiring line 195 may include a top surface 195US and a bottom surface 195BS opposite to each other in the third direction D3. The bottom surface 195BS of the second wiring line looks at the first upper interlayer insulating film 192. The bottom surface 195BS of the second wiring line contacts the top surface 192US of the first upper interlayer insulating film. The bottom surface 195BS of the second wiring line is connected to the upper gate contact 177.

[0173] The first wiring line 190 will be described as an example. The width of the first wiring line 190 in the second direction D2 may decrease as it moves away from the first upper interlayer insulating film 192. The width of the first wiring line 190 in the second direction D2 may decrease as it moves away from the lower via pattern 181. The width W12 of the bottom surface 190BS of the first wiring line in the second direction D2 may be greater than the width W11 of the top surface 190US of the first wiring line in the second direction D2.

[0174] The top surface 192US of the first upper interlayer insulating film can be confirmed by the bottom surface 190BS of the first wiring line and the bottom surface 195BS of the second wiring line. For example, the source / drain path pattern 180 and the first wiring line 190 can be divided based on the top surface 192US of the first upper interlayer insulating film. The first gate contact 175 and the second wiring line 195 can be divided based on the top surface 192US of the first upper interlayer insulating film.

[0175] In the semiconductor device according to some embodiments, each of the first wiring line 190 and the second wiring line 195 may have a single film structure. Each of the first wiring line 190 and the second wiring line 195 may have a single conductive film structure.

[0176] Each of the first wiring line 190 and the second wiring line 195 may include a metal. For example, each of the first wiring line 190 and the second wiring line 195 may be formed of a single metal conductive film. The first wiring line 190 and the second wiring line 195 may include ruthenium (Ru).

[0177] The first wiring line 190 may include the same material as the upper via filling film 182B. The metal included in the first wiring line 190 may be the same as the metal included in the upper via filling film 182B. The second wiring line 195 may include the same material as the upper gate filling film 177B.

[0178] The first wiring line 190 may include a first wiring extension line 190B extending in the first direction D1. The first wiring extension line 190B may include a first wiring line top surface 190US and a first wiring line bottom surface 190BS. The first wiring extension line 190B may contact a top surface 192US of the first upper interlayer insulating film.

[0179] The second wiring line 195 may include a second wiring extension line 195B extending in the first direction D1. The second wiring extension line 195B may include a second wiring line top surface 195US and a second wiring line bottom surface 195BS. The second wiring extension line 195B may contact the top surface 192US of the first upper interlayer insulating film.

[0180] The width of the first wiring extension line 190B in the second direction D2 may decrease as it moves away from the lower via pattern 181. The width of the first wiring extension line 190B in the second direction D2 may decrease as it moves away from the first source / drain contact 170. The width of the second wiring extension line 195B in the second direction D2 may decrease as it moves away from the lower gate contact 176. The width of the second wiring extension line 195B in the second direction D2 may decrease as it moves away from the first gate electrode 120.

[0181] The first wiring extension line 190B and the second wiring extension line 195B may include ruthenium (Ru). The first wiring extension line 190B and the second wiring extension line 195B may be a metal conductive film formed of ruthenium.

[0182] The first wiring extension line 190B and the upper via filling film 182B may include ruthenium. Each of the first wiring extension line 190B and the upper via filling film 182B may be formed of ruthenium. The first wiring extension line 190B may be directly connected to the upper via filling film 182B. For example, the boundary between the first wiring extension line 190B and the upper via filling film 182B may not be distinguished. The first wiring extension line 190B and the upper via filling film 182B may have an integral structure or an integrated structure.

[0183] Each of the second wiring extension line 195B and the upper gate filling film 177B may be formed of ruthenium. The second wiring extension line 195B may be directly connected to the upper gate filling film 177B. The second wiring extension line 195B and the upper gate filling film 177B may have an integral structure.

[0184] The first wiring line pattern 190WP may be placed on the lower via pattern 181. The first wiring line pattern 190WP may include an upper via pattern 182 and a first wiring line 190.

[0185] The first wiring line pattern 190WP may fill the remaining portion of the source / drain via hole 180H that is left after providing the lower via pattern 181. The first wiring line pattern 190WP may be in contact with a top surface 192US of the first upper interlayer insulating film.

[0186] The second wiring line pattern 195WP may be disposed on the lower gate contact 176. The second wiring line pattern 195WP may include an upper gate contact 177 and a second wiring line 195.

[0187] The second wiring line pattern 195WP may fill the remaining portion of the gate contact hole 175H that remains after providing the lower gate contact 176. The second wiring line pattern 195WP may be in contact with the top surface 192US of the first upper interlayer insulating film.

[0188] Since the first wiring line 190 and the second wiring line 195 are formed by subtractive etching, the separation distance between the first wiring line 190 and the second wiring line 195 can be easily ensured.

[0189] The source / drain via pattern 180 will be described as an example. The sidewalls 181S1, 181S2, 181S3, and 181S4 of the lower via pattern 181 are covered by the first upper interlayer insulating film 192. When the lower via pattern 181 includes molybdenum, the molybdenum can be easily oxidized. In addition, it is not easy to reduce the oxidized molybdenum.

[0190] The manufacturing process for forming the first wiring line 190 and the second wiring line 195 is performed in a state where the first upper interlayer insulating film 192 covers the sidewall of the lower via pattern 181. That is, when the etching process for forming the first wiring line 190 and the second wiring line 195 is being performed, the lower via pattern 181 is not exposed to the etching environment. This can limit and / or prevent the lower via pattern 181 from being oxidized.

[0191] The second upper interlayer insulating film 193 may be disposed on the first upper interlayer insulating film 192. The second upper interlayer insulating film 193 may cover the sidewalls of the first wiring line 190.

[0192] The second upper interlayer insulating film 193 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a low dielectric constant material. The dielectric constant of the low dielectric constant material may have a value less than 3.9 which is the dielectric constant of silicon oxide.

[0193] The boundary between the first upper interlayer insulating film 192 and the second upper interlayer insulating film 193 may include a recessed portion toward the substrate 100. Unlike the illustrated example, depending on materials included in the first upper interlayer insulating film 192 and the second upper interlayer insulating film 193, the boundary between the first upper interlayer insulating film 192 and the second upper interlayer insulating film 193 may not be distinguished.

[0194] Figures 10 to 13 are diagrams for illustrating semiconductor devices according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 9 The points that are explained are different.

[0195] For reference, Figures 10 to 12 It shows Figure 4 This is an enlarged view of part R. Even if Figure 4 Enlarged image of part R Figures 10 to 12 The same changes, Figure 2 Part P and Figure 5 The enlarged view of the portion S may also not be changed. Figure 3 The enlarged view of the partial Q can be similar to Figures 10 to 12 one of them.

[0196] refer to Figures 10 to 12 , in the semiconductor device according to some embodiments, the fourth sidewall 182S4 of the upper via pattern may include the third portion SL_R3 and the fourth portion SL_R4 having slope signs different from each other.

[0197] The fourth portion SL_R4 of the fourth sidewall 182S4 of the upper via pattern may be disposed between the third portion SL_R3 of the fourth sidewall 182S4 of the upper via pattern and the fourth sidewall 181S4 of the lower via pattern.

[0198] A fourth portion SL_R4 of the fourth sidewall 182S4 of the upper via pattern may be defined by the upper via barrier film 182A. A third portion SL_R3 of the fourth sidewall 182S4 of the upper via pattern may be defined by the upper via barrier film 182A and the upper via filling film 182B.

[0199] The fourth portion SL_R4 of the fourth sidewall 182S4 of the upper via pattern may have a positive slope value. The third portion SL_R3 of the fourth sidewall 182S4 of the upper via pattern may have a negative slope value.

[0200] In the following description, the sign of the slope of the fourth sidewall 182S4 of the upper via pattern will be described as the sign of the slope of the third portion SL_R3 of the fourth sidewall 182S4 of the upper via pattern close to the first wiring line 190. That is, the slope of the fourth sidewall 182S4 of the upper via pattern may have a negative value.

[0201] Since the slope of the fourth sidewall 181S4 of the lower via pattern has a positive value, the sign of the slope of the fourth sidewall 182S4 of the upper via pattern may be different from the sign of the slope of the fourth sidewall 181S4 of the lower via pattern.

[0202] Unlike the illustrated example, the fourth sidewall 182S4 of the upper via pattern may not include the fourth portion SL_R4 of the fourth sidewall 182S4 of the upper via pattern having a positive slope value.

[0203] exist Fig.10 The third sidewall 182S3 of the upper via pattern may include a first portion SL_R1 and a second portion SL_R2 having different slope signs from each other. The second portion SL_R2 of the third sidewall 182S3 of the upper via pattern may be disposed between the first portion SL_R1 of the third sidewall 182S3 of the upper via pattern and the third sidewall 181S3 of the lower via pattern.

[0204] The second portion SL_R2 of the third sidewall 182S3 of the upper via pattern may be defined by the upper via barrier film 182A. The first portion SL_R1 of the third sidewall 182S3 of the upper via pattern may be defined by the upper via barrier film 182A and the upper via filling film 182B.

[0205] The second portion SL_R2 of the third sidewall 182S3 of the upper via pattern may have a positive slope value. The first portion SL_R1 of the third sidewall 182S3 of the upper via pattern may have a negative slope value.

[0206] The slope of the third sidewall 182S3 of the upper via pattern may have a negative value. Since the slope of the third sidewall 181S3 of the lower via pattern has a positive value, the sign of the slope of the third sidewall 182S3 of the upper via pattern may be different from the sign of the slope of the third sidewall 181S3 of the lower via pattern. On the other hand, the sign of the slope of the third sidewall 182S3 of the upper via pattern may be the same as the sign of the slope of the fourth sidewall 182S4 of the upper via pattern.

[0207] Unlike the illustrated example, the third sidewall 182S3 of the upper via pattern may not include the second portion SL_R2 of the third sidewall 182S3 of the upper via pattern having a positive slope value.

[0208] exist Fig.11 and Fig.12 , the third sidewall 182S3 of the upper via pattern may not include portions having slope signs different from each other. The slope of the third sidewall 182S3 of the upper via pattern may have a positive value.

[0209] Since the fourth sidewall 182S4 of the upper via pattern may have a negative slope value, the sign of the slope of the third sidewall 182S3 of the upper via pattern may be different from the sign of the slope of the fourth sidewall 182S4 of the upper via pattern.

[0210] exist Fig.11 In the embodiment, from a cross-sectional perspective, a sidewall of the first wiring line 190 may be directly connected to the third sidewall 182S3 of the upper via pattern.

[0211] exist Fig.12 In the embodiment, from a cross-sectional perspective, a top surface 192US of the first upper interlayer insulating film may connect a side wall of the first wiring line 190 and a third side wall 182S3 of the upper via pattern.

[0212] refer to Fig.13 , in the semiconductor device according to some embodiments, the top surface 181US of the lower via pattern may include a concave curved surface.

[0213] Although not shown, the top surface of the lower gate contact ( Figure 3 176US) may include a concave surface.

[0214] Figures 14 to 16 is a diagram for illustrating a semiconductor device according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 9 The points that are explained are different.

[0215] refer to Figures 14 to 16 In the semiconductor device according to some embodiments, the first wiring line 190 may include a first wiring barrier film 190A and a first wiring extension line 190B.

[0216] The first wiring barrier film 190A may extend along the bottom surface of the first wiring extension line 190B. The first wiring extension line 190B may include a top surface 190US of the first wiring line. The first wiring barrier film 190A may include a bottom surface 190BS of the first wiring line. The first wiring barrier film 190A may contact a top surface 192US of the first upper interlayer insulating film.

[0217] The first wiring barrier film 190A may be directly connected to the upper via barrier film 182A. The first wiring barrier film 190A includes the same conductive material as the upper via barrier film 182A.

[0218] The second wiring line 195 may include a second wiring barrier film 195A and a second wiring extension line 195B.

[0219] The second wiring barrier film 195A may extend along the bottom surface of the second wiring extension line 195B. The second wiring extension line 195B may include a top surface 195US of the second wiring line. The second wiring barrier film 195A may include a bottom surface 195BS of the second wiring line. The second wiring barrier film 195A may contact the top surface 192US of the first upper interlayer insulating film.

[0220] The second wiring barrier film 195A may be directly connected to the upper gate barrier film 177A. The second wiring barrier film 195A includes the same conductive material as the upper gate barrier film 177A.

[0221] Figures 17 to 20 is a diagram for illustrating a semiconductor device according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 9 as well as Figures 14 to 16 The points that are explained are different.

[0222] refer to Figures 17 to 20 In the semiconductor device according to some embodiments, the upper via barrier film 182A may extend along the sidewalls of the upper via filling film 182B and the bottom surface of the upper via filling film 182B.

[0223] The bottom surface 182BS of the upper via pattern may be defined by the upper via barrier film 182A. The upper via filling film 182B and the lower via pattern 181 may be separated by the upper via barrier film 182A. The upper via filling film 182B does not contact the top surface 181US of the lower via pattern.

[0224] The upper gate blocking film 177A may extend along the sidewalls of the upper gate filling film 177B and the bottom surface of the upper gate filling film 177B.

[0225] The bottom surface 177BS of the upper gate contact may be defined by the upper gate barrier film 177 A. The upper gate filling film 177B and the lower gate contact 176 may be separated by the upper gate barrier film 177 A. The upper gate filling film 177B does not contact the top surface 176US of the lower gate contact.

[0226] Fig.21 and Fig. 22 are diagrams for illustrating semiconductor devices according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 9 The points that are explained are different.

[0227] refer to Fig.21 , in the semiconductor device according to some embodiments, the lower via pattern 181 may include a lower via barrier film 181A and a lower via filling film 181B.

[0228] The lower via pattern 181 may have a multi-film structure including conductive materials different from each other. The lower via barrier film 181A may extend along the sidewall of the lower via filling film 181B and the bottom surface of the lower via filling film 181B. The top surface 181US of the lower via pattern may be defined by the lower via barrier film 181A and the lower via filling film 181B.

[0229] The lower via blocking film 181A may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material (2D material). The lower via filling film 181B may include a metal. The lower via filling film 181B may include a metal different from that of the upper via filling film 182B.

[0230] refer to Fig. 22 In the semiconductor device according to some embodiments, the lower gate contact 176 may include a lower gate barrier film 176A and a lower gate filling film 176B. For example, the lower gate contact 176 may be a multi-film structure including conductive materials different from each other.

[0231] The lower gate barrier film 176A may extend along the sidewalls of the lower gate filling film 176B and the bottom surface of the lower gate filling film 176B. A top surface 176US of the lower gate contact may be defined by the lower gate barrier film 176A and the lower gate filling film 176B.

[0232] The lower gate barrier film 176A may include, for example, at least one of a metal, a conductive metal nitride, a conductive metal carbide, a conductive metal oxide, a conductive metal carbonitride, and a two-dimensional material (2D material). The lower gate filling film 176B may include a metal. The lower gate filling film 176B may include a metal different from the upper gate filling film 177B.

[0233] Fig.23 is a diagram for explaining a semiconductor device according to some embodiments. Fig.24 and Fig.25 is a diagram for illustrating a semiconductor device according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 9 The points that are explained are different.

[0234] refer to Fig.23 In the semiconductor device according to some embodiments, the gate structure GS may further include a plurality of inner spacers 140IN.

[0235] The inner spacer 140IN may be disposed between the first sheet patterns NS1 adjacent to each other in the third direction D3 and between the first lower pattern BP1 and the first sheet pattern NS1 . The inner spacer 140IN may be disposed between the inner gate structure GS_INT and the first source / drain pattern 150 .

[0236] The inner gate structure GS_INT may not contact the first source / drain pattern 150. For example, the first source / drain pattern 150 may include an n-type dopant.

[0237] refer to Fig.24 and Fig.25 In the semiconductor device according to some embodiments, the first active pattern AP1 and the second active pattern AP2 may not include a sheet pattern ( Figure 3 NS1, NS2).

[0238] No inner gate structure is provided between the first source / drain patterns 150 ( Figure 2 of GS_INT).

[0239] Fig.26 is a diagram for illustrating a semiconductor device according to some embodiments. For ease of explanation, the description will focus on the use of Figures 1 to 9 The points that are explained are different.

[0240] refer to Fig.26 , in the semiconductor device according to some embodiments, the first active pattern AP1 may include a first lower pattern BP1 , a first lower sheet pattern NS1_BP, and a first upper sheet pattern NS1_UP.

[0241] The first lower sheet pattern NS1_BP may be spaced apart from the first lower pattern BP1 in the third direction D3. The first upper sheet pattern NS1_UP may be disposed on the first lower sheet pattern NS1_BP. The first upper sheet pattern NS1_UP may be spaced apart from the first lower sheet pattern NS1_BP in the third direction D3.

[0242] Although each of the three first lower sheet patterns NS1_BP and the three first upper sheet patterns NS1_UP is illustrated as being disposed along the third direction D3 , this is only for convenience of explanation, and the embodiment is not limited thereto.

[0243] The first lower sheet pattern NS1_BP and the first upper sheet pattern NS1_UP may each include one of silicon or germanium as an elemental semiconductor material, a group IV-IV compound semiconductor, or a group III-V compound semiconductor. The first lower sheet pattern NS1_BP and the first upper sheet pattern NS1_UP may include the same material or may include different materials.

[0244] As an example, one of the first lower pattern NS1_BP and the first upper pattern NS1_UP may be a channel region of a PMOS, and the other may be a channel region of an NMOS. As another example, the first lower pattern NS1_BP and the first upper pattern NS1_UP may be a channel region of a PMOS. As yet another example, the first lower pattern NS1_BP and the first upper pattern NS1_UP may be a channel region of an NMOS.

[0245] like Figure 3 As shown, the first gate insulating film 130 may surround the periphery of the first lower sheet pattern NS1_BP and the periphery of the first upper sheet pattern NS1_UP. Figure 3 As shown, the first gate electrode 120 may surround a circumference of the first lower sheet pattern NS1_BP and a circumference of the first upper sheet pattern NS1_UP.

[0246] The first lower source / drain pattern 150_LP may be disposed on the first lower pattern BP1. The first lower source / drain pattern 150_LP may be connected to the first lower sheet pattern NS1_BP.

[0247] The first upper source / drain pattern 150_UP may be disposed on the first lower source / drain pattern 150_LP. The first upper source / drain pattern 150_UP may be connected to the first upper sheet pattern NS1_UP. The first upper source / drain pattern 150_UP is spaced apart from the first lower source / drain pattern 150_LP in the third direction D3.

[0248] For example, the first upper source / drain pattern 150_UP and the first lower source / drain pattern 150_LP may contact the first gate insulating film 130. Unlike the illustrated example, at least one of the first upper source / drain pattern 150_UP and the first lower source / drain pattern 150_LP may not contact the first gate insulating film 130.

[0249] An interlayer insulating film 153 may be interposed between the first upper source / drain pattern 150_UP and the first lower source / drain pattern 150_LP.

[0250] The interlayer insulating film 153 may include an insulating material. The inserted interlayer insulating film 153 may include, for example but not limited to, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbon oxynitride, silicon carbon nitride, and a low dielectric constant material.

[0251] The first source / drain contact 170 may be connected to the first upper source / drain pattern 150_UP. Although not shown, the first source / drain contact 170 may be connected to the first lower source / drain pattern 150_LP.

[0252] A portion of the first source / drain contact 170 may be connected to the first lower source / drain pattern 150_LP, and the remaining portion of the first source / drain contact 170 may be connected to the first upper source / drain pattern 150_UP.

[0253] Although not shown, a cross-sectional view taken along the second active pattern AP2 in the first direction D1 may be similar to Fig.26 .

[0254] Figure 27 to Figure 29 is a diagram for explaining a semiconductor device according to some embodiments. For reference, Fig. 27 is a plan view for explaining a semiconductor device according to some embodiments. Fig.28 It is along Fig. 27 A cross-sectional view taken along lines EE and FF. Fig.29 It is along Fig. 27 A cross-sectional view taken along line GG.

[0255] refer to Figure 27 to Figure 29 , the logic cell LC may be disposed on the substrate 100. The logic cell LC may refer to a logic element (eg, an inverter, a flip-flop, etc.) that performs a specific function. The logic cell LC may include vertical transistors (vertical FETs) constituting the logic element and wiring that connects the vertical transistors to each other.

[0256] The logic cell LC on the substrate 100 may include a first active region RX1 and a second active region RX2. For example, the first active region RX1 may be a PMOSFET region, and the second active region RX2 may be an NMOSFET region. The first active region RX1 and the second active region RX2 may be defined by a trench T_CH formed on the top of the substrate 100. The first active region RX1 and the second active region RX2 may be spaced apart from each other in the first direction D1.

[0257] The first lower epitaxial pattern SPO1 may be disposed on the first active region RX1, and the second lower epitaxial pattern SPO2 may be disposed on the second active region RX2. From a plane perspective, the first lower epitaxial pattern SPO1 may overlap with the first active region RX1, and the second lower epitaxial pattern SPO2 may overlap with the second active region RX2. The first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2 may be epitaxial patterns formed by a selective epitaxial growth process. The first lower epitaxial pattern SPO1 may be disposed in a first recessed region RS1 of the substrate 100, and the second lower epitaxial pattern SPO2 may be disposed in a second recessed region RS2 of the substrate 100.

[0258] The third active pattern AP3 may be disposed on the first active region RX1, and the fourth active pattern AP4 may be disposed on the second active region RX2. Each of the third active pattern AP3 and the fourth active pattern AP4 may be in a fin shape protruding vertically. From a plane perspective, each of the third active pattern AP3 and the fourth active pattern AP4 may be in a strip shape extending in the first direction D1. The third active pattern AP3 may be arranged along the second direction D2, and the fourth active pattern AP4 may be arranged along the second direction D2.

[0259] Each third active pattern AP3 may include a first channel pattern CHP1 vertically protruding from the first lower epitaxial pattern SPO1 and a first upper epitaxial pattern DOP1 on the first channel pattern CHP1. Each fourth active pattern AP4 may include a second channel pattern CHP2 vertically protruding from the second lower epitaxial pattern SPO2 and a second upper epitaxial pattern DOP2 on the second channel pattern CHP2.

[0260] An element separation film ST may be disposed on the substrate 100 to fill the trench T_CH. The element separation film ST may cover top surfaces of the first and second lower epitaxial patterns SPO1 and SPO2. The third and fourth active patterns AP3 and AP4 may protrude vertically over the element separation film ST.

[0261] A plurality of second gate electrodes 420 extending parallel to each other in the first direction D1 may be disposed on the element separation film ST. The second gate electrodes 420 may be arranged along the second direction D2. The second gate electrode 420 may surround the first channel pattern CHP1 of the third active pattern AP3, and may surround the second channel pattern CHP2 of the fourth active pattern AP4. For example, the first channel pattern CHP1 of the third active pattern AP3 may have first to fourth side walls SW1 to SW4. The first side wall SW1 and the second side wall SW2 may be opposite to each other in the second direction D2, and the third side wall SW3 and the fourth side wall SW4 may be opposite to each other in the first direction D1. The second gate electrode 420 may be disposed on the first to fourth side walls SW1 to SW4. In other words, the second gate electrode 420 may surround the first to fourth side walls SW1 to SW4.

[0262] The second gate insulating film 430 may be interposed between the second gate electrode 420 and each of the first and second channel patterns CHP1 and CHP2. The second gate insulating film 430 may cover the bottom surface of the second gate electrode 420 and the inner wall of the second gate electrode 420. For example, the second gate insulating film 430 may directly cover the first to fourth side walls SW1 to SW4 of the third active pattern AP3.

[0263] The first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2 may protrude vertically above the second gate electrode 420. A top surface of the second gate electrode 420 may be lower than a bottom surface of each of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. In other words, each of the first active pattern AP1 and the second active pattern AP2 may have a structure protruding vertically from the substrate 100 and penetrating the second gate electrode 420.

[0264] A semiconductor device according to some embodiments may include a vertical transistor in which carriers move in a third direction D3. For example, when a voltage is applied to the second gate electrode 420 and the transistor is "turned on", carriers may move from lower epitaxial patterns SPO1 and SPO2 to upper epitaxial patterns DOP1 and DOP2 through channel patterns CHP1 and CHP2. In a semiconductor device according to some embodiments, the second gate electrode 420 may completely surround the sidewalls SW1 to SW4 of the channel patterns CHP1 and CHP2. The transistor according to the present disclosure may be a three-dimensional field effect transistor (e.g., VFET) having a fully surrounding gate structure. Since the gate surrounds the channel, the semiconductor device according to the present disclosure may have excellent electrical properties.

[0265] The spacer 440 covering the second gate electrode 420, the third active pattern AP3, and the fourth active pattern AP4 may be disposed on the element separation film ST. The spacer 440 may include a silicon nitride film or a silicon oxynitride film. The spacer 440 may include a lower spacer 440LS, an upper spacer 440US, and a second gate spacer 440GS located between the lower spacer 440LS and the upper spacer 440US.

[0266] The lower spacer 440LS may directly cover the top surface of the element separation film ST. The second gate electrode 420 may be spaced apart from the element separation film ST in the third direction D3 by the lower spacer 440LS. The second gate spacer 440GS may cover the top surface and the outer wall of each second gate electrode 420. The upper spacer 440 may cover the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. However, the upper spacer 440US may not cover the top surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2, but may expose the top surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2.

[0267] The first portion 191BP of the lower interlayer insulating film may be disposed on the spacer 440. The top surface of the first portion 191BP of the lower interlayer insulating film may be substantially coplanar with the top surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2. The second portion 191UP of the lower interlayer insulating film and the first upper interlayer insulating film 192 and the second upper interlayer insulating film 193 may be sequentially stacked on the first portion 191BP of the lower interlayer insulating film. The first portion 191BP of the lower interlayer insulating film and the second portion 191UP of the lower interlayer insulating film may be included in the lower interlayer insulating film 191. The second portion 191UP of the lower interlayer insulating film may cover the top surfaces of the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2.

[0268] At least one third source / drain contact 470 penetrating the second portion 191UP of the lower interlayer insulating film and connected to the first upper epitaxial pattern DOP1 and the second upper epitaxial pattern DOP2 may be provided. At least one fourth source / drain contact 570 penetrating the lower interlayer insulating film 191, the lower spacer 440LS, and the element separation film ST in sequence and connected to the first lower epitaxial pattern SPO1 and the second lower epitaxial pattern SPO2 may be provided. A second lower gate contact 480 penetrating the second portion 191UP of the lower interlayer insulating film, the first portion 191BP of the lower interlayer insulating film, and the second gate spacer 440GS in sequence and connected to the second gate electrode 420 may be provided.

[0269] Although not shown, an etch stopper film 155 may be additionally disposed between the second portion 191UP of the lower interlayer insulating film and the first upper interlayer insulating film 192 .

[0270] The source / drain via pattern 180, the first gate contact 175, the first wiring line 190, and the second wiring line 195 may be disposed on the third source / drain contact 470, the fourth source / drain contact 570, and the second lower gate contact 480. The source / drain via pattern 180 may be connected to the third source / drain contact 470 and the fourth source / drain contact 570. The first gate contact 175 may be connected to the second lower gate contact 480.

[0271] The detailed description of the source / drain via pattern 180, the first gate contact 175, the first wiring line 190 and the second wiring line 195 can be referred to above. Figures 1 to 22 The detailed description is basically the same.

[0272] Figures 30 to 37 is a diagram for explaining an intermediate stage of a method for manufacturing a semiconductor device according to some embodiments.

[0273] refer to Fig.30 and Fig.31, a first source / drain pattern 150 is formed on the first lower pattern BP1.

[0274] Although not shown, a source / drain pattern may be formed on the second lower pattern BP2 Before forming the first source / drain pattern 150 , a first gate spacer 140 may be formed on the first and second lower patterns BP1 and BP2 .

[0275] A first gate insulating film 130 and a first gate electrode 120 surrounding the first and second sheet patterns NS1 and NS2 may be formed on the first and second lower patterns BP1 and BP2. A gate capping pattern 145 may be formed on the first gate electrode 120. A gate structure GS may be formed on the first and second active patterns AP1 and AP2, respectively.

[0276] A first source / drain contact 170 may then be formed on the first source / drain pattern 150. The first source / drain contact 170 is electrically connected to the first source / drain pattern 150.

[0277] Subsequently, a first upper interlayer insulating film 192 may be formed on the first source / drain contacts 170 and the gate capping pattern 145 .

[0278] A source / drain via hole 180H may be formed in the first upper interlayer insulating film 192. The source / drain via hole 180H exposes the first source / drain contact 170. A pre-source / drain via pattern 180P is formed in the source / drain via hole 180H. The pre-source / drain via pattern 180P is connected to the first source / drain contact 170.

[0279] A gate contact hole 175H may be formed in the first upper interlayer insulating film 192 and the gate capping pattern 145. The gate contact hole 175H exposes the first gate electrode 120. A pre-gate contact 175P is formed in the gate contact hole 175H. The pre-gate contact 175P is connected to the first gate electrode 120.

[0280] As an example, after forming the pre-source / drain path pattern 180P, the pre-gate contact 175P may be formed. As another example, the pre-gate contact 175P may be formed before forming the pre-source / drain path pattern 180P. As yet another example, the pre-source / drain path pattern 180P and the pre-gate contact 175P may be formed simultaneously.

[0281] refer to Figure 30 to Figure 33 , the lower via pattern 181 may be formed by removing a portion of the pre-source / drain via pattern 180P.

[0282] Therefore, the top surface 181US of the lower via pattern becomes lower than the top surface 192US of the first upper interlayer insulating film.

[0283] A portion of the pre-gate contact 175P may be removed to form a lower gate contact 176. A top surface 176US of the lower gate contact accordingly becomes lower than a top surface 192US of the first upper interlayer insulating film.

[0284] refer to Figure 32 to Figure 35 , the upper via barrier film 182A may be formed along a portion of the sidewall of the source / drain via hole 180H.

[0285] The upper gate blocking film 177A may be formed along a portion of a sidewall of the gate contact hole 175H. The upper gate blocking film 177A and the upper via blocking film 182A may be formed simultaneously.

[0286] Different from the illustrated example, as an example, each of the upper gate barrier film 177A and the upper via barrier film 182A may extend along the top surface 192US of the first upper interlayer insulating film. As another example, the upper gate barrier film 177A may extend along the top surface 176US of the lower gate contact. The upper via barrier film 182A may extend along the top surface 181US of the lower via pattern.

[0287] Subsequently, a wiring conductive film 190P may be formed on the first upper interlayer insulating film 192. The wiring conductive film 190P may cover the top surface 192US of the first upper interlayer insulating film. The wiring conductive film 190P may fill the source / drain via hole 180H left after forming the lower via pattern 181. The wiring conductive film 190P may fill the gate contact hole 175H left after forming the lower gate contact 176. The wiring conductive film 190P contains ruthenium (Ru).

[0288] refer to Figure 34 to Figure 37 , the first wiring line 190 and the second wiring line 195 can be formed on the first upper interlayer insulating film 192 by patterning the wiring conductive film 190P.

[0289] When the first wiring line 190 is being formed, an upper via filling film 182B may be formed in the source / drain via hole 180H. An upper via pattern 182 may be formed in the source / drain via hole 180H accordingly.

[0290] When the second wiring line 195 is being formed, the upper gate filling film 177B may be formed in the gate contact hole 175H. The upper gate contact 177 may be formed in the gate contact hole 175H accordingly.

[0291] For example, ruthenium (Ru) can be etched using a gas containing oxygen. In other words, the first wiring line 190 and the second wiring line 195 can be etched in an environment including oxygen. The lower path pattern 181 and / or the lower gate contact 176 may include molybdenum (Mo). When the lower path pattern 181 and / or the lower gate contact 176 are exposed during the formation of the first wiring line 190 and the second wiring line 195, the lower path pattern 181 and / or the lower gate contact 176 can be easily oxidized. When molybdenum is oxidized, the reliability and performance of the semiconductor device may decrease. On the other hand, when a portion of the lower path pattern 181 and the lower gate contact 176 is removed before forming the wiring conductive film 190P, during the formation of the first wiring line 190 and the second wiring line 195, the lower path pattern 181 and the lower gate contact 176 can be limited and / or prevented from being exposed.

[0292] When the first wiring line 190 and the second wiring line 195 are being formed, the upper gate filling film 177B and / or the upper via filling film 182B may be formed as shown in FIG. Figures 10 to 12 Shown is over-etched.

[0293] Misalignment may occur between the first wiring line 190 and the source / drain path pattern 180. Misalignment may occur between the second wiring line 195 and the first gate contact 175. Even if misalignment occurs, overetching of the upper gate filling film 177B and the upper path filling film 182B can be performed. Therefore, a sufficient space margin between the first wiring line 190 and the first gate contact 175 can be ensured. In addition, a sufficient space margin between the second wiring line 195 and the source / drain path pattern 180 can be ensured.

[0294] Subsequently, a second upper interlayer insulating film 193 may be formed on the first wiring line 190 and the second wiring line 195 .

[0295] Although the embodiments of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to the above-described embodiments and can be implemented in various different forms. A person of ordinary skill in the technical field to which the present disclosure belongs will be able to understand that the present disclosure can be implemented in other specific forms without changing the technical concept or essential characteristics of the present disclosure. Therefore, it should be understood that the embodiments described above are not restrictive in all aspects, but illustrative.

Claims

1. A semiconductor device, comprising: A conductive pattern, wherein the conductive pattern is located on a substrate; a via pattern connected to the conductive pattern and comprising a lower via pattern and an upper via pattern, the lower via pattern and the upper via pattern being stacked in a first direction, a top surface of the lower via pattern being in contact with a bottom surface of the upper via pattern; as well as a wiring line located on the via pattern and extending in a second direction, wherein The metal in the wiring line is the same as the metal in the upper via pattern, The bottom surface of the wiring line and the top surface of the wiring line are opposite to each other in the first direction, The bottom surface of the wiring line is connected to the upper via pattern, The width of the bottom surface of the wiring line in the third direction is greater than the width of the top surface of the wiring line in the third direction, The width of the top surface of the lower via pattern in the second direction is equal to the width of the bottom surface of the upper via pattern in the second direction, and A width of a top surface of the lower via pattern in the third direction is equal to a width of a bottom surface of the upper via pattern in the third direction.

2. The semiconductor device according to claim 1, wherein The upper via pattern and the lower via pattern each include a first side wall and a second side wall opposite to each other in the third direction, The sign of the slope of the first sidewall of the lower via pattern is the same as the sign of the slope of the second sidewall of the lower via pattern, The sign of the slope of the first sidewall of the upper via pattern is the same as the sign of the slope of the second sidewall of the upper via pattern, and A sign of a slope of the first sidewall of the lower via pattern is different from a sign of a slope of the first sidewall of the upper via pattern.

3. The semiconductor device according to claim 2, wherein: the upper via pattern includes a third side wall and a fourth side wall opposite to each other in the second direction, The sign of the slope of the third sidewall of the upper via pattern is the same as the sign of the slope of the fourth sidewall of the upper via pattern, and A sign of the slope of the first sidewall of the lower via pattern is the same as a sign of the slope of the third sidewall of the upper via pattern.

4. The semiconductor device according to claim 1, wherein: The upper via pattern and the lower via pattern each include a first side wall and a second side wall opposite to each other in the third direction, The sign of the slope of the first sidewall of the lower via pattern is the same as the sign of the slope of the second sidewall of the lower via pattern, The sign of the slope of the first sidewall of the upper via pattern is the same as the sign of the slope of the second sidewall of the upper via pattern, and A sign of the slope of the first sidewall of the lower via pattern is the same as a sign of the slope of the first sidewall of the upper via pattern.

5. The semiconductor device according to claim 1, wherein The upper via pattern includes a first side wall and a second side wall opposite to each other in the third direction, and A sign of a slope of the first sidewall of the upper via pattern is different from a sign of a slope of the second sidewall of the upper via pattern.

6. The semiconductor device according to claim 1, wherein The upper via pattern includes an upper via filling film and an upper via blocking film, The upper via filling film contacts a top surface of the lower via pattern, and the upper via barrier film extends along a side wall of the upper via filling film. The wiring line is a single metal conductive film, and The metal included in the wiring line is the same as the metal included in the upper via filling film.

7. The semiconductor device according to claim 1, wherein The upper via pattern includes an upper via filling film and an upper via barrier film, the upper via barrier film extending along a sidewall of the upper via filling film, The wiring line includes a wiring extension line and a wiring barrier film extending along the bottom surface of the wiring extension line. The wiring barrier film and the upper via barrier film include the same conductive material, and The metal included in the wiring extension line is the same as the metal included in the upper via filling film.

8. The semiconductor device according to claim 7, wherein: The upper via filling film contacts a top surface of the lower via pattern.

9. The semiconductor device according to claim 7, wherein: The upper via barrier film extends along a bottom surface of the upper via filling film.

10. The semiconductor device according to claim 1, wherein The lower via pattern includes molybdenum, and The upper via pattern includes ruthenium.

11. The semiconductor device according to claim 1, further comprising: A gate electrode and a source / drain pattern, wherein the gate electrode and the source / drain pattern are located on the substrate; as well as a source / drain contact connected to the source / drain pattern, wherein The conductive pattern is one of the gate electrode and the source / drain contact.

12. A semiconductor device, comprising: A conductive pattern, wherein the conductive pattern is located on a substrate; an interlayer insulating film located on the conductive pattern and including a via hole; a lower via pattern connected to the conductive pattern and filling a portion of the via hole; A wiring line pattern filling the remaining portion of the via hole, wherein The wiring line pattern is in contact with the top surface of the interlayer insulating film, The wiring line pattern includes an upper via pattern and a wiring extension line, The wiring line pattern is located in the via hole and contacts the entire top surface of the lower via pattern, The wiring extension line extends in a first direction along the top surface of the interlayer insulating film, The upper via pattern includes an upper via filling film and an upper via barrier film extending along a sidewall of the upper via filling film, The wiring extension line and the upper via filling film have an integral structure, and The width of the wiring extension line in the second direction decreases as the wiring extension line moves away from the lower via pattern.

13. The semiconductor device according to claim 12, wherein: The wiring extension line is in contact with a top surface of the interlayer insulating film.

14. The semiconductor device according to claim 12, wherein: The upper via barrier film extends along a top surface of the lower via pattern, and The lower via pattern and the upper via filling film are separated by the upper via barrier film.

15. The semiconductor device according to claim 12, wherein: The wiring line pattern further includes a wiring barrier film, The wiring barrier film extends along the bottom surface of the wiring extension line and contacts the top surface of the interlayer insulating film. The wiring barrier film is directly connected to the upper via barrier film, and The wiring barrier film includes the same conductive material as the upper via barrier film.

16. The semiconductor device according to claim 12, wherein: The upper via filling film is directly connected to the lower via pattern.

17. A semiconductor device, comprising: A gate electrode, the gate electrode being located on the substrate; a source / drain pattern, wherein the source / drain pattern is located on one side of the gate electrode; a source / drain contact located on the source / drain pattern and connected to the source / drain pattern; a via pattern connected to the source / drain contacts, The via pattern includes a lower via pattern and an upper via pattern stacked in a first direction, and The entire top surface of the lower via pattern is in contact with the upper via pattern; a gate contact connected to the gate electrode, The gate contact includes a lower gate contact and an upper gate contact stacked in the first direction, and The entire top surface of the lower gate contact is in contact with the upper gate contact; a first wiring extension line, the first wiring extension line being located on the via pattern and extending in a second direction; as well as a second wiring extension line, the second wiring extension line is located on the gate contact, wherein: The upper via pattern includes an upper via filling film and an upper via blocking film, the upper via filling film is directly connected to the first wiring extension line, and the upper via barrier film extends along a side wall of the upper via filling film, The upper gate contact comprises an upper gate contact filling film and an upper gate contact barrier film, The upper gate contact filling film is directly connected to the second wiring extension line, The upper gate contact barrier film extends along the sidewall of the upper gate contact filling film, The width of the first wiring extension line in the third direction decreases as the first wiring extension line moves away from the source / drain contact. The width of the second wiring extension line in the third direction decreases as the second wiring extension line moves away from the gate electrode, and The first wiring extension line, the second wiring extension line, the upper via fill film, and the upper gate contact fill film each include ruthenium.

18. The semiconductor device according to claim 17, wherein: The upper via filling film is directly connected to the lower via pattern, and The upper gate contact filling film is directly connected to the lower gate contact.

19. The semiconductor device according to claim 17, wherein: The lower via pattern and the lower gate contact include molybdenum.

20. The semiconductor device according to claim 17, further comprising: A plurality of sheet patterns, the plurality of sheet patterns being located on the substrate, wherein The gate electrode surrounds a sheet pattern among the plurality of sheet patterns.

Images