Semiconductor device

Abstract

In a semiconductor device, the positional accuracy of a control lead frame is improved. The semiconductor device includes: a semiconductor chip; a main current lead frame having a main chip pad on which the semiconductor chip is disposed; a control element connected to the semiconductor chip via a first control wiring; and a control lead frame having a control chip pad on which the control element is disposed. The control lead frame includes: a first frame having a control chip pad; and a second frame connected to the control element via a second control wiring. The first frame further has a curved portion that is curved so that the control chip pad is positioned below the second frame in the thickness direction (Z direction) of the semiconductor chip.

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a main current lead frame and a control lead frame. The main current lead frame has a main chip pad on which a semiconductor chip is arranged, and the control lead frame has a control chip pad on which a control element is arranged. Background Art

[0002] As a semiconductor device used for a power conversion device, there is a semiconductor device in which a control chip pad of a control lead frame on which a control element is arranged is located above a main chip pad of a main current lead frame on which a semiconductor chip is arranged. In such a semiconductor device, a semiconductor chip, a control element, a lead frame, etc. are connected to each other by wiring and sealed by a sealing resin (for example, refer to Patent Documents 1 to 5).

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2014-99547

[0006] Patent Document 2: Japanese Patent Application Publication No. 2016-129257

[0007] Patent Document 3: Japanese Patent Application Publication No. 2019-87565

[0008] Patent Document 4: Japanese Patent Application Publication No. 2008-186889

[0009] Patent Document 5: Japanese Patent Application Publication No. 2000-196002 Summary of the invention

[0010] Problem that the invention aims to solve

[0011] For example, in order to reduce the height difference between the control chip pad and the main chip pad and suppress the deformation of the control wiring during resin molding, it is preferable that the control lead frame is provided with a bent portion that makes the height of the control chip pad lower than the height of the portion extending from the sealing resin. However, in the control lead frame, since the width of each separated frame is narrow, if the control lead frame is bent, the position accuracy of each frame is deteriorated.

[0012] An object of the present invention is to provide a semiconductor device capable of improving the positional accuracy of a lead frame.

[0013] Solutions for solving problems

[0014] A semiconductor device of a technical solution comprises: a semiconductor chip; a main current lead frame having a main chip pad on which the semiconductor chip is configured; a control element connected to the semiconductor chip via a first control wiring; and a control lead frame having a control chip pad on which the control element is configured, the control lead frame comprising: a first frame having the control chip pad; and a second frame connected to the control element via a second control wiring, the first frame also having a bent portion, the bent portion being bent in such a manner that the control chip pad is located below the second frame in the thickness direction of the semiconductor chip.

[0015] Effects of the Invention

[0016] According to the above aspect, it is possible to improve the position accuracy of the lead frame. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a top view showing a semiconductor device according to one embodiment.

[0018] Figure 2 This is a right side view showing the internal structure of the semiconductor device according to one embodiment.

[0019] Figure 3 yes Figure 1 III-III sectional view.

[0020] Figure 4 It is a plan view for explaining the flow rate (s / L) corresponding to the loop height of the first control wiring in one embodiment.

[0021] Figure 5 This is a graph showing the relationship between the loop height and the flow rate (deformation rate) of the control wiring in one embodiment.

[0022] Description of Reference Numerals

[0023] 1. semiconductor device; 11, 12, 13, 14. semiconductor chip; 21, 22. control element; 30 (31-37) main current lead frame; 34a, 35a, 36a, 37a. main chip pad; 34b, 35b, 36b, 37b. bent portion; 40. control lead frame; 41. first frame; 41a, 41b. control chip pad; 41c, 41d, 41e. bent portion; 42. second frame; 43. third frame; 43a. component chip pad; 51, 52, 53. electronic component; 60. sealing resin; 61. recess; 70. insulating sheet; D. resin injection direction; D1, D2. flow direction; W1. first control wiring; W1a. first control wiring (after deformation); W2. second control wiring; W3. third control wiring; W4. main current wiring. DETAILED DESCRIPTION

[0024] Hereinafter, a semiconductor device according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings. In addition, the X, Y, and Z axes in the referenced figures are shown for the purpose of defining directions in the illustrated semiconductor device 1. The X, Y, and Z axes are orthogonal to each other and form a right-hand system. In the following description, the thickness direction of the semiconductor chips 11 to 14, that is, the Z direction, is set as the up-down direction. These directions are terms used for the convenience of description, and the corresponding relationship with the XYZ directions may change depending on the different mounting postures of the semiconductor device 1, etc. For example, in this specification, the surface facing the positive side (+Z direction) of the Z direction in the member constituting the semiconductor device 1 is called the upper surface, the surface facing the negative side (-Z direction) of the Z direction is called the lower surface, the surface facing the negative side (-Y direction) of the Y direction is called the front surface, and the four surfaces facing both sides of the X direction and both sides of the Y direction including the front surface are called the side surfaces. In addition, in this specification, the top view refers to the situation where the upper surface of the semiconductor device 1 is observed from the negative side of the Z direction.

[0025] The aspect ratios and size relationships of the components in the drawings are schematic and do not necessarily correspond to the relationships in the actually manufactured semiconductor device 1 etc. The shapes of the same components may differ between the drawings.

[0026] In the following description, as an example of the semiconductor device 1 of this embodiment, a device applied to a power conversion device such as an inverter device for an industrial or vehicle-mounted motor is listed. Therefore, in the following description, detailed descriptions of the structure, function, operation, assembly method, etc. that are the same or similar to those of a known semiconductor device are omitted.

[0027] Figure 1 It is a plan view showing the semiconductor device 1 . Figure 2 It is a right side view showing the internal structure of the semiconductor device 1 . Figure 3 yes Figure 1 In addition, in Figure 1 In FIG. 1 , the sealing resin 60 is indicated by a two-dot chain line (imaginary line).

[0028] like Figure 1 As shown, the semiconductor device 1 includes a plurality of semiconductor chips 11 to 14, a plurality of control elements 21 and 22, a main current lead frame 30, a control lead frame 40, a plurality of electronic components 51 to 53, a sealing resin 60, and an insulating sheet 70. In addition, the semiconductor device 1 includes a plurality of first control wirings W1, a plurality of second control wirings W2, a plurality of third control wirings W3, and a plurality of main current wirings W4.

[0029] The semiconductor chips 11 to 14 are composed of, for example, RC (Reverse Conducting)-IGBT elements that integrate IGBT (Insulated Gate Bipolar Transistor) elements as switching elements and diode elements such as FWD (Free Wheeling Diode) elements that are connected in reverse parallel to the switching elements. Instead of the individual semiconductor chips 11 to 14, semiconductor chips having switching elements and semiconductor chips having diode elements may be separately provided.

[0030] A first main electrode (not shown) is provided on the lower surface of the semiconductor chips 11 to 14. A second main electrode (not shown) and a control electrode (gate) are provided on the upper surface of the semiconductor chips 11 to 14. When the switching element of the semiconductor chips 11 to 14 is an IGBT element, the first main electrode on the lower surface is called a collector, and the second main electrode on the upper surface is called an emitter.

[0031] For example, six semiconductor chips 11 to 14 are arranged in the X direction in the form of three semiconductor chips 11 and semiconductor chips 12 to 14. The three semiconductor chips 11 constituting the upper arm are all arranged on a single main chip pad 37a of the main current lead frame 37 described later. The three semiconductor chips 12 to 14 constituting the lower arm are respectively arranged on main chip pads 34a, 35a, and 36a of different main current lead frames 34 to 36. It is preferred that the first main electrode on the lower surface of the semiconductor chips 11 to 14 is bonded to the main chip pads 34a, 35a, 36a, and 37a using a conductive bonding material such as solder.

[0032] The second main electrodes and control electrodes on the upper surfaces of the three semiconductor chips 11 constituting the upper arm are connected to the common control element 21 via the first control wiring W1, respectively. In addition, the three semiconductor chips 11 are connected on the upper surface via the main current wiring W4 to the main current lead frames 34 to 36 which are different from the main current lead frame 37 having the main chip pad 37a on which these semiconductor chips 11 are arranged. In addition, the connection in this specification includes electrical connection, and therefore includes indirect connection (fixing) via other components in addition to direct bonding (fixing).

[0033] Control electrodes on the upper surfaces of semiconductor chips 12 to 14 constituting the lower arm are connected to a common control element 22 via a first control wiring W1. Also, semiconductor chips 12 to 14 are connected to main current lead frames 31 to 33 on their upper surfaces via a main current wiring W4.

[0034] The control element 21 is, for example, a HVIC (High Voltage Integrated Circuit), and the control element 22 is, for example, a LVIC (Low Voltage Integrated Circuit). The control elements 21 and 22 preferably have a sensor function for detecting environmental information such as temperature and a protection circuit function for operating based on the detection result of the environmental information.

[0035] The control elements 21 and 22 are arranged in the X direction on the control die pads 41a and 41b provided on the single first frame 41 of the control lead frame 40. The lower surfaces of the control elements 21 and 22 are preferably bonded to the control die pads 41a and 41b using a conductive bonding material such as solder.

[0036] As described above, the control element 21 is connected to each of the three semiconductor chips 11 via two first control wirings W1, and the control element 22 is connected to each of the semiconductor chips 12 to 14 via one first control wiring W1. Furthermore, as an example, the electrode on the upper surface of the control element 21 is connected to the component die pads 43a of the seven second frames 42 and the three third frames 43 of the control lead frame 40 via the second control wiring W2. In addition, the electrode on the upper surface of the control element 22 is connected to the seven second frames 42 via the second control wiring W2.

[0037] The main current lead frame 30 has seven frames (also referred to as main current lead frames 31 to 37). The main current lead frames 31 to 37 function as output circuit parts. The main current lead frames 31 to 37 are arranged in the X direction in the order of the reference numerals 31 to 37, from the main current lead frame 31 located at the most negative side in the X direction to the main current lead frame 37 located at the most positive side in the X direction.

[0038] The main current lead frames 34 to 37 having the main chip pads 34a, 35a, 36a, and 37a extend from the main chip pads 34a to 37a toward the negative side of the Y direction (an example of the first direction) away from the control chip pads 41a and 41b, thereby extending from the sealing resin 60 and functioning as the main current terminal. In addition, the main current lead frames 34 to 37 extend toward the negative side of the Y direction while bending toward the positive side of the X direction from the main chip pads 34a to 37a, but this case can also be referred to as extending toward the negative side of the Y direction. The main current lead frames 31 to 33 also extend toward the negative side of the Y direction, extend from the sealing resin 60, and function as the main current terminal.

[0039] like Figure 2 As shown, the main current lead frames 34 to 37 ( Figure 2Only the main current lead frame 37 is shown in the figure, and has bent portions 34b, 35b, 36b, and 37b bent downward in the Z direction (the thickness direction of the semiconductor chip 11) so that the main chip pads 34a~37a are in contact with the upper surface of the insulating sheet 70 described later.

[0040] As mentioned above, Figure 1 The control lead frame 40 shown has a first frame 41, a plurality of second frames 42, and three third frames 43. Each frame 41 to 43 functions as a control circuit unit. The first frame 41 has control chip pads 41a and 41b arranged at a distance from each other in the X direction, and extends from the control chip pads 41a and 41b to both sides of the X direction in a manner away from each other, and then extends to the positive side of the Y direction away from the main chip pads 34a to 37a (an example of a second direction opposite to the first direction). The three third frames 43 have component chip pads 43a on which electronic components 51, 52, and 53 are arranged.

[0041] The first frame 41 has three bent portions 41c, 41d, and 41e, which are bent so that the control chip pads 41a and 41b are located below the second frame 42 and the third frame 43 (component chip pads 43a) in the Z direction. The two bent portions 41c and 41d are provided on both sides of the control chip pads 41a and 41b in the first frame 41 (an example of the third direction side and the fourth direction side that are orthogonal to the first direction and the second direction and opposite to each other) in the X direction. The control chip pads 41a and 41b are sandwiched by the bent portions 41c and 41d, so as to be located at the same height in the Z direction. In addition, in this case, the bent portions 41c and 41d may be located at a position offset to the positive side of the Y direction from the control chip pads 41a and 41b. In addition, the bent portion 41e is provided at a position on the positive side of the Y direction from the control chip pads 41a and 41b. Furthermore, the height of the control chip pads 41 a and 41 b lower than the portion of the first frame 41 extending from the sealing resin 60 by the bent portions 41 c , 41 d , and 41 e may be equal to or less than the plate thickness of the first frame 41 .

[0042] The control lead frame 40 (the first frame 41, the second frame 42, and the third frame 43) extends from the sealing resin 60 toward the positive side in the Y direction and functions as a control terminal. Figure 2As shown, it is desirable that the height H2 of the control lead frame 40 extending from the sealing resin 60 and the height H1 of the main current lead frame 30 (main current lead frames 31 to 37) extending from the sealing resin 60 are the same height in the Z direction with respect to the lower surface of the sealing resin 60 as a reference. In addition, due to the influence of tolerances, etc., even if the same height is intended, the height may slightly vary, so, for example, even if the height H1 and H2 have a difference of the thickness of the main current lead frame 30 or the control lead frame 40, they can be regarded as the same height.

[0043] The main current lead frame 30 and the control lead frame 40 are formed by, for example, etching or punching a metal plate having a wiring pattern. The main current lead frame 30 and the control lead frame 40 are made of, for example, a copper material, a copper alloy material, an aluminum alloy material, an iron alloy material, or other metal material.

[0044] The bent portions 34b to 37b of the main current lead frame 30 and the bent portions 41c to 41e of the control lead frame 40 are formed by, for example, press working. The bent portions 34b to 37b and the bent portions 41c to 41e only need to be bent to change the extending direction and can be bent without edges.

[0045] The electronic components 51 to 53 are, for example, bootstrap diodes. The electronic components 51 to 53 may also be other components such as passive components such as thermistors, capacitors, resistors, etc. The electronic components 51 to 53 are preferably bonded to the component chip pads 43a of the third frame 43 using conductive bonding materials such as solder. The electronic components 51 to 53 are connected to the second frame 42 via the third control wiring W3.

[0046] The sealing resin 60 is, for example, a rectangular parallelepiped shape that is longer in the X direction and the Y direction than in the Z direction, and seals the semiconductor chips 11 to 14, the control elements 21 and 22, the electronic components 51 to 53, the first control wirings W1 to the third control wirings W3, the main current wiring W4, etc. Figure 1 As shown, a concave portion 61 having a U-shaped shape (semicircular shape) in a top view is provided on the side surface of the sealing resin 60 on the positive side in the X direction and the side surface on the negative side in the X direction. These concave portions 61 can be called grooves that penetrate the sealing resin 60 in the Z direction. For example, the concave portions 61 are used to insert bolts that mount the semiconductor device 1 on a cooler such as a heat sink disposed at the bottom of the semiconductor device 1. In addition, the sealing resin 60 is a thermosetting resin such as an epoxy resin, and is preferably formed by transfer molding.

[0047] As described above, the main current lead frame 30 extends from the sealing resin 60 to the negative side in the Y direction, and the control lead frame 40 extends from the sealing resin 60 to the positive side in the Y direction. The sealing resin 60 is injected from the injection gate into the space between the upper and lower molds (not shown) at the same height in the Z direction as the height at which the main current lead frames 31 to 37 extend. Figure 1 As shown by the arrows in the figure, the sealing resin 60 is injected from 6 locations between the main current lead frames 31 to 37. That is, the sealing resin 60 is injected from the side surfaces (front surfaces) extending from the main current lead frames 31 to 37. The side surfaces are the surfaces of the sealing resin 60 on the negative side in the Y direction, but may be composed of multiple planes or curved surfaces instead of a single plane.

[0048] In addition, the injected portion of the sealing resin 60 is cut off after the injected sealing resin 60 is cured, so that it can be identified as the injected portion. In addition, the portion inserted into the mold is the entire portion of the semiconductor device 1 except the sealing resin 60, and it is preferably set to a state where the main current lead frame 30 and the control lead frame 40 extend from the sealing resin 60. That is, before the sealing resin 60 is injected (before the mold is inserted), the semiconductor chips 11 to 14, the control elements 21, 22, and the electronic components 51 to 53 are arranged on the main current lead frame 30 or the control lead frame 40, and the first control wiring W1 to the third control wiring W3 and the main current wiring W4 are wired, and the insulating sheet 70 is preferably attached to the lower surface of the main chip pads 34a to 37a of the main current lead frames 34 to 37. In addition, the insulating sheet 70 can also be thermally cured together with the sealing resin 60 in a semi-cured state before the sealing resin 60 is injected, so as to be attached to the lower surface of the main chip pads 34a to 37a.

[0049] like Figure 2 As shown, the lower surface of the insulating sheet 70 and the lower surface of the sealing resin 60 form the same plane, and the insulating sheet 70 is exposed to the outside of the sealing resin 60 on the lower surface. The insulating sheet 70 is preferably formed into a rectangular shape in a top view that is larger on both sides of the X direction and the Y direction than the four main chip pads 34a to 37a to which it is attached. In addition, the control chip pad 41a (control lead frame 40) is located above the main chip pads 34a to 37a in the Z direction, so the insulating sheet 70 does not contact the control lead frame 40.

[0050] The insulating sheet 70 is preferably formed of a material that has excellent insulation properties for the main chip pads 34a to 37a and excellent heat dissipation properties, so as to conduct the heat generated from the semiconductor chips 11 to 14 to the cooler disposed below the insulating sheet 70. Therefore, the insulating sheet 70 can also be called a heat sink. In addition, the insulating sheet 70 can also be called an insulating plate, an insulating substrate, a heat sink, a heat dissipation substrate, etc. The insulating sheet 70 is made of, for example, epoxy resin, etc.

[0051] In addition, the wire diameter of the first control wiring W1 to the third control wiring W3 is, for example, about 15 μm to 50 μm, which is thinner than the wire diameter of the main current wiring W4, for example, about one tenth. Therefore, the rigidity of the first control wiring W1 to the third control wiring W3 is much lower than that of the main current wiring W4, and is easily deformed by the flow of resin during transfer molding of the sealing resin 60. If the first control wiring W1 to the third control wiring W3 are deformed in this way, short circuits between different potentials, reduction in bonding strength due to deformation (open circuit), etc. may occur.

[0052] In particular, Figure 3 As shown in FIG. 1 , for the first control wiring W1 connecting the semiconductor chip 11 and the control element 21 (the same applies to the semiconductor chips 12 to 14 and the control element 22), since the semiconductor chip 11 is located below the control element 21 in the Z direction and separated in the height direction (Z direction), the line loop height H3 of the first control wiring W1 becomes higher and the effective wiring length becomes longer. Therefore, the first control wiring W1 is subjected to a strong load and is particularly easy to deform, which is easy to cause a decrease in manufacturability and quality. In particular, the sealing resin 60 injected along the resin injection direction D during transfer molding branches into the flow direction D1 above the control element 21 in the Z direction and the flow direction D2 below the control element 21 in the Z direction. Therefore, the higher the height of the control element 21 in the Z direction and the higher the line loop height H3, the easier it is for the sealing resin 60 to flow in the downward flow direction D2. Therefore, the first control wiring W1 extending in a manner intersecting the flow direction D2 is easy to deform.

[0053] Here, if Figure 4 As shown in FIG. 1 , the first control wiring W1 having a length L when viewed from above and deformed by flowing to the positive side in the Y direction due to the resin flow during transfer molding of the sealing resin 60 is referred to as the deformed first control wiring W1a (illustrated by a dotted line). Furthermore, the flow rate s, which is the maximum length between the first control wiring W1 and the first control wiring W1a in the direction orthogonal to the first control wiring W1 when viewed from above, and the length L are expressed according to the flow rate s / L [%] Figure 3 The loop height H3 of the first control wiring W1 shown in FIG.

[0054] like Figure 5 As shown, the flow rate s / L, which is about 37[%] on average when the line arc height H3 is 1960[μm], is reduced to about 27[%] on average when the line arc height H3 is 1830[μm]. In this way, the lower the line arc height H3, the more the deformation of the first control wiring W1 can be suppressed. Therefore, as described above, the first frame 41 of the control lead frame 40 has bent portions 41c, 41d, and 41e, so that the control chip pads 41a and 41b are located at a lower position in the Z direction in a manner close to the height of the main chip pads 34a to 37a of the main current lead frame 30, which is effective from the perspective of reducing the line arc height H3 and suppressing the deformation of the first control wiring W1. In addition, by suppressing the wiring deformation of the first control wiring W1 and the like, the thickening of the wiring can be avoided, thereby preventing the semiconductor chip 11 having a large number of bonding pads, the control elements 21 and 22 from being enlarged, the cost from being increased, and the reliability of the semiconductor device 1 from being reduced (for example, peeling caused by the stress increase of the sealing resin 60). In addition, if the control chip pads 41a and 41b are lowered to the height in the Z direction of the main chip pads 34a to 37a, the cost will increase due to the enlargement of the insulating sheet 70, the wiring of the first control wiring W1 to the third control wiring W3 (for example, ultrasonic bonding) will become difficult, and the bending process of the control lead frame 40 will become difficult.

[0055] The control lead frame 40 is an example, and is composed of a plurality of frames 41 to 43 separated from each other, for example, one first frame 41, 14 second frames 42, and three third frames 43. Therefore, the width of each frame 41 to 43 perpendicular to the extension direction when viewed from above is relatively narrow. Therefore, if all the frames 41 to 43 are bent, the positional accuracy of each frame 41 to 43 is deteriorated, for example, the distance between each frame becomes close to short-circuit, or the frame 41 to 43 is enlarged to ensure the distance between each frame.

[0056] Therefore, it is desirable that the first frame 41 has the bent portions 41 c , 41 d , and 41 e , whereas the second frame 42 and the third frame 43 do not have a bent portion at least inside the sealing resin 60 .

[0057] In addition, the control elements 21 and 22 arranged on the control chip pads 41a and 41b of the first frame 41 are connected to the second frame 42 and the third frame 43 via the second control wiring W2. Therefore, by reducing the height of the control chip pads 41a and 41b of the first frame 41 in the Z direction, the height of the upper surface of the control elements 21 and 22 is made close to the height of the upper surface of the second frame 42 and the third frame 43, so that the line loop height of the second control wiring W2 can be reduced in the same manner as the line loop height H3 of the first control wiring W1 described above, and deformation of the second control wiring W2 can also be suppressed. In this way, it is effective to reduce the height of the control chip pads 41a and 41b in the Z direction in the control lead frame 40.

[0058] In the present embodiment described above, the semiconductor device 1 includes: semiconductor chips 11 to 14; main current lead frames 34 to 37 having main die pads 34a to 37a on which the semiconductor chips 11 to 14 are arranged; control elements 21 and 22 connected to the semiconductor chips 11 to 14 via the first control wiring W1; and a control lead frame 40 having control die pads 41a and 41b on which the control elements 21 and 22 are arranged. The control lead frame 40 includes: a first frame 41 having control die pads 41a and 41b; and a second frame 42 connected to the control elements 21 and 22 via the second control wiring W2. The first frame 41 further includes bent portions 41c, 41d, and 41e, which are bent so that the control die pads 41a and 41b are located below the second frame 42 in the thickness direction (Z direction) of the semiconductor chips 11 to 14.

[0059] In this way, the bent portions 41c to 41e are provided so that the control chip pads 41a and 41b of the first frame 41 are located below the second frame 42 in the Z direction, thereby reducing the number of bent frames compared to a configuration in which not only the control chip pads 41a but also the second frame 42 are bent downward in the Z direction. In particular, the number of second frames 42 connected to the control elements 21 and 22 via the second control wiring W2 is large, and each of the second frames 42 has a narrow width and is densely arranged. Therefore, if these second frames 42 are also bent downward in the Z direction, the position accuracy of the second frames 42 is degraded, and the position accuracy of the control lead frame 40 is further degraded. Therefore, according to the present embodiment, the position accuracy of the control lead frame 40 can be improved. Furthermore, by improving the position accuracy of the control lead frame 40, it is possible to prevent the distance between two adjacent second frames 42, between the second frame 42 and the first frame 41, etc. from becoming short and thus causing a short circuit, or to prevent the control lead frame 40 and the semiconductor device 1 from being enlarged to ensure the distance.

[0060] Furthermore, the control chip pads 41a and 41b are located below the second frame 42 in the Z direction, so that the height of the upper surface of the control elements 21 and 22 is close to the height of the upper surface of the second frame 42, thereby reducing the line height of the second control wiring W2 connecting the control elements 21 and 22 and the second frame 42. As a result, during the transfer molding of the sealing resin 60, the deformation of the second control wiring W2 caused by the flow of the resin can be suppressed with a simple structure. In addition, the height of the control elements 21 and 22 can be close to the semiconductor chips 11 to 14, so the detection accuracy of environmental information such as temperature detected by the control elements 21 and 22 can also be improved.

[0061] In the present embodiment, the control die pads 41 a and 41 b of the control lead frame 40 are located above the main die pads 34 a to 37 a of the main current lead frame 30 in the Z direction.

[0062] Therefore, as described above, by bending the first frame 41 so that the control chip pads 41a and 41b are located below the second frame 42 in the Z direction, the height difference between the control elements 21 and 22 and the semiconductor chips 11 to 14 can be reduced, and the line loop height H3 of the first control wiring W1 connecting the control elements 21 and 22 and the semiconductor chips 11 to 14 can be reduced. In addition, during transfer molding of the sealing resin 60, the sealing resin 60 is less likely to flow downwardly of the first frame 41 (the flow rate of the sealing resin 60 is reduced), and deformation of the first control wiring W1 caused by resin flow can be suppressed with a simple structure.

[0063] In addition, in the present embodiment, the main current lead frames 34 to 37 extend from the main chip pad 34a to the negative side of the Y direction (an example of the first direction) away from the control chip pads 41a and 41b. The first frame 41 extends from the control chip pads 41a and 41b to the positive side of the Y direction (an example of the second direction opposite to the first direction). The bent portions 41c and 41d are provided on both sides of the control chip pads 41a and 41b in the first frame 41 in the X direction (an example of the third direction side and the fourth direction side that are orthogonal to the first direction and the second direction and opposite to each other).

[0064] Thus, the region extending in the X direction between the control chip pads 41a, 41b and the bent portions 41c, 41d is also located below the second frame 42, so that the sealing resin 60 is unlikely to flow downwardly toward the first frame 41. Therefore, deformation of the first control wire W1 can be suppressed with a simple structure.

[0065] In the present embodiment, the semiconductor device 1 further includes a sealing resin 60 that seals at least the semiconductor chips 11 to 14 and the control elements 21 and 22 , and the main current lead frame 30 and the control lead frame 40 extend from the sealing resin 60 at the same heights H1 and H2 in the Z direction.

[0066] This facilitates processing of the main current lead frame 30 and the control lead frame 40 from a single metal plate, and improves usability of the control terminals of the main current lead frame 30 and the control lead frame 40 extending from the sealing resin 60 .

[0067] In addition, in the present embodiment, the sealing resin 60 is injected from the side surface (for example, the front surface on the negative side in the Y direction) from which the main current lead frame 30 extends.

[0068] Thus, the first to third control wirings W1 to W3 having lower rigidity than the main current wiring W4 are located downstream in the resin injection direction D of the sealing resin 60 , and thus deformation of the first to third control wirings W1 to W3 can be suppressed.

[0069] In the present embodiment, the semiconductor device 1 includes a plurality of control elements 21 and 22 , and the first frame 41 includes a plurality of control die pads 41 a and 41 b on which the control elements 21 and 22 are respectively arranged. The plurality of control die pads 41 a and 41 b are located at the same height in the Z direction.

[0070] Therefore, compared with a configuration in which only one of the control chip pads 41a, 41b is located below the second frame 42 in the Z direction, the sealing resin 60 is less likely to flow in the flow direction D2 that intersects the first control wiring W1 connecting the semiconductor chips 11 to 14 and the control elements 21, 22, thereby suppressing deformation of the first control wiring W1 with a simple structure.

[0071] In the present embodiment, in the control lead frame 40, the electronic components 51, 52, 53 connected to the second frame 42 via the third control wiring W3 are arranged on the component die pads 43a of the third frame 43. The control die pads 41a, 41b are located below the second frame 42 and the component die pads 43a in the Z direction.

[0072] Thus, compared with the configuration in which the third frame 43 is bent downward in the Z direction, the number of frames for controlling the bending of the lead frame 40 can be reduced. Therefore, the position accuracy of the third frame 43 can be improved, and the position accuracy of the lead frame 40 can be further improved. In addition, it is also possible to prevent the second frame 42 and the third frame 43 from becoming too close to each other and causing a short circuit, or to prevent the semiconductor device 1 from being enlarged in order to ensure the distance.

[0073] The semiconductor device of the present invention is not limited to the semiconductor device 1 of this embodiment, and various changes, substitutions, and deformations can be made within the scope of the main idea of ​​the technology. Moreover, if the technology idea can be realized in other ways due to technological progress or other derived technologies, the method can also be used for implementation. Therefore, the claims cover all embodiments that can be included in the scope of the technology idea.

[0074] For example, the control chip pads 41a and 41b of the control lead frame 40 may be located at the same height as or below the main chip pads 34a to 37a of the main current lead frame 30 in the Z direction. In addition, the positions of the bent portions 41c to 41e of the control lead frame 40 may be other positions as long as they can be bent in such a way that at least one control chip pad 41a or 41b is located below the second frame 42 in the Z direction. In addition, the height H1 of the main current lead frame 30 extending from the sealing resin 60 and the height H2 of the control lead frame 40 extending from the sealing resin 60 may be different heights. In addition, the position where the sealing resin 60 is injected is not limited to the side surface (front surface) from which the main current lead frames 31 to 37 of the sealing resin 60 extend. In addition, the plurality of control chip pads 41a and 41b of the control lead frame 40 may be set at different heights in the Z direction. In addition, the control chip pads 41a and 41b only need to be located below the second frame 42 in the Z direction, and may also be located at the same height as or above the third frame 43 in the Z direction (for example, the third frame 43 has a curved portion so that the component chip pad 43a is located below the second frame 42 in the Z direction).

[0075] Hereinafter, a part of the invention described in the specification and drawings of this application will be supplemented.

[0076] <Additional Note 1>

[0077] A semiconductor device, characterized in that

[0078] The semiconductor device has:

[0079] Semiconductor chips;

[0080] a main current lead frame having a main chip pad configured with the semiconductor chip;

[0081] a control element connected to the semiconductor chip via a first control wiring; and

[0082] a control lead frame having a control chip pad provided with the control element,

[0083] The control lead frame includes: a first frame having the control chip pad; and a second frame connected to the control element via a second control wiring.

[0084] The first frame further includes a bent portion that is bent so that the control chip pad is located below the second frame in the thickness direction of the semiconductor chip.

[0085] <Note 2>

[0086] The semiconductor device according to Supplementary Note 1 is characterized in that

[0087] The control die pad is located above the main die pad in the thickness direction.

[0088] <Addendum 3>

[0089] The semiconductor device according to Supplementary Note 1 or 2, characterized in that

[0090] The main current lead frame extends from the main chip pad in a first direction away from the control chip pad.

[0091] The first frame extends from the control chip pad in a second direction opposite to the first direction.

[0092] The bent portion is provided on the first frame at a third direction side and a fourth direction side, respectively, which are orthogonal to the first direction and the second direction and are opposite to each other, with respect to the control chip pad.

[0093] <Note 4>

[0094] The semiconductor device according to any one of Supplementary Notes 1 to 3, characterized in that

[0095] The semiconductor device further includes a sealing resin that seals at least the semiconductor chip and the control element.

[0096] The main current lead frame and the control lead frame extend from the sealing resin at the same height in the thickness direction.

[0097] <Addendum 5>

[0098] The semiconductor device according to any one of Supplementary Notes 1 to 3, characterized in that

[0099] The semiconductor device further includes a sealing resin that seals at least the semiconductor chip and the control element.

[0100] The sealing resin is injected from the side surface extending from the main current lead frame.

[0101] <Addendum 6>

[0102] The semiconductor device according to any one of Supplementary Notes 1 to 5, characterized in that

[0103] The semiconductor device comprises a plurality of the control elements.

[0104] The first frame has a plurality of control chip pads on which the control elements are respectively arranged.

[0105] The plurality of control chip pads are located at the same height in the thickness direction.

[0106] <Addendum 7>

[0107] The semiconductor device according to any one of Supplementary Notes 1 to 6, characterized in that:

[0108] The control lead frame further includes a third frame having a component die pad, and the component die pad is provided with an electronic component connected to the second frame via a third control wiring.

[0109] The control die pad is located below the second frame and the component die pad in the thickness direction.

[0110] Industrial Applicability

[0111] As described above, the present invention has an effect of improving the positional accuracy of the lead frame, and is particularly useful for inverter devices for industrial or electrical equipment.

Claims

1. A semiconductor device, characterized in that: The semiconductor device has: Semiconductor chips; a main current lead frame having a main chip pad configured with the semiconductor chip; a control element connected to the semiconductor chip via a first control wiring; as well as a control lead frame having a control chip pad provided with the control element, The control lead frame includes: a first frame having the control chip pad; and a second frame connected to the control element via a second control wiring. The first frame further includes a bent portion that is bent so that the control chip pad is located below the second frame in the thickness direction of the semiconductor chip.

2. The semiconductor device according to claim 1, wherein: The control die pad is located above the main die pad in the thickness direction.

3. The semiconductor device according to claim 1 or 2, characterized in that: The main current lead frame extends from the main chip pad in a first direction away from the control chip pad. The first frame extends from the control chip pad in a second direction opposite to the first direction. The bent portion is provided on the first frame at a third direction side and a fourth direction side, respectively, which are orthogonal to the first direction and the second direction and are opposite to each other, with respect to the control chip pad.

4. The semiconductor device according to claim 1 or 2, characterized in that: The semiconductor device further includes a sealing resin that seals at least the semiconductor chip and the control element. The main current lead frame and the control lead frame extend from the sealing resin at the same height in the thickness direction.

5. The semiconductor device according to claim 1 or 2, characterized in that: The semiconductor device further includes a sealing resin that seals at least the semiconductor chip and the control element. The sealing resin is injected from the side surface extending from the main current lead frame.

6. The semiconductor device according to claim 1 or 2, characterized in that: The semiconductor device comprises a plurality of the control elements. The first frame has a plurality of control chip pads on which the control elements are respectively arranged. The plurality of control chip pads are located at the same height in the thickness direction.

7. The semiconductor device according to claim 1 or 2, characterized in that: The control lead frame further includes a third frame having a component die pad, and the component die pad is provided with an electronic component connected to the second frame via a third control wiring. The control die pad is located below the second frame and the component die pad in the thickness direction.

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