Substrate structure and method of manufacturing the same

Abstract

A substrate structure and a method of fabricating the same, including: a core layer having a plurality of conductive structures; a first build-up structure disposed on the core layer and having a plurality of first conductive pillars; and a second build-up structure disposed on the first build-up structure and having a plurality of second conductive pillars; wherein the first conductive pillars are misaligned with the conductive structures, and the second conductive pillars are aligned with the conductive structures and misaligned with the first conductive pillars.

Description

Technical Field

[0001] This disclosure relates to a substrate structure and its manufacturing method, and particularly to a substrate structure and its manufacturing method that can improve substrate utilization. Background Technology

[0002] FIG. 1A and FIG. 1B These are cross-sectional and top views of the existing substrate structure 1, respectively. FIG. 1A As shown, the substrate structure 1 includes a core layer 10, first add-on structures 13 disposed on opposite sides of the core layer 10, a second add-on structure 14 disposed on the first add-on structure 13, and a third add-on structure 15 disposed on the second add-on structure 14. The core layer 10 has a plurality of conductive structures 12, the first add-on structure 13 has a first dielectric layer 130 and a plurality of first conductive pillars 132, the second add-on structure 14 has a second dielectric layer 140 and a plurality of second conductive pillars 142, and the third add-on structure 15 has a third dielectric layer 150 and a plurality of third conductive pillars 152.

[0003] However, the conductive structure 12, the first conductive post 132, the second conductive post 142 and the third conductive post 152 are arranged on the edge B of the substrate structure 1 in a staggered and progressive manner, which means that the edge B needs to reserve a certain width, thereby limiting the number of circuit areas A in the substrate structure 1.

[0004] Therefore, overcoming the various problems of the existing technologies has become an urgent issue to be addressed. Summary of the Invention

[0005] This disclosure provides a substrate structure, including: a core layer having a plurality of conductive structures; a first add-on structure disposed on the core layer and having a first dielectric layer and a plurality of first conductive pillars formed in the first dielectric layer; and a second add-on structure disposed on the first add-on structure and having a second dielectric layer and a plurality of second conductive pillars formed in the second dielectric layer; wherein the first conductive pillars are offset from the conductive structures, and the second conductive pillars are correspondingly aligned with the conductive structures and offset from the first conductive pillars.

[0006] The substrate structure described above also includes a third add-on structure, which is disposed on the second add-on structure and has a third dielectric layer and a plurality of third conductive pillars formed in the third dielectric layer.

[0007] As described above in the substrate structure, the third conductive post is aligned with the first conductive post and is offset from the second conductive post and the conductive structure.

[0008] As described above in the substrate structure, the conductive structure, the first conductive pillar, the second conductive pillar, and the third conductive pillar are adjacent to the edge of the substrate structure.

[0009] The core layer has opposite first and second surfaces, and the first build-up structure is formed on the first and second surfaces.

[0010] The present disclosure also provides a method of manufacturing a substrate structure, comprising: providing a core layer having a plurality of conductive structures; forming a first build-up structure on the core layer, wherein the first build-up structure has a first dielectric layer and a plurality of first conductive pillars formed in the first dielectric layer; forming a second build-up structure on the first build-up structure, wherein the second build-up structure has a second dielectric layer and a plurality of second conductive pillars formed in the second dielectric layer; wherein the first conductive pillars are misaligned with the conductive structures, and the second conductive pillars are aligned with the conductive structures and misaligned with the first conductive pillars.

[0011] The method of manufacturing a substrate structure as claimed in the preceding paragraph, further comprising forming a third build-up structure on the second build-up structure, wherein the third build-up structure has a third dielectric layer and a plurality of third conductive pillars formed in the third dielectric layer.

[0012] The method of manufacturing a substrate structure as claimed in the preceding paragraph, wherein the third conductive pillars are aligned with the first conductive pillars, and misaligned with the second conductive pillars and the conductive structures.

[0013] The method of manufacturing a substrate structure as claimed in the preceding paragraph, wherein the conductive structures, the first conductive pillars, the second conductive pillars and the third conductive pillars are adjacent to a board edge of the substrate structure.

[0014] The method of manufacturing a substrate structure as claimed in the preceding paragraph, wherein the core layer has opposite first and second surfaces, and the first build-up structure is formed on the first and second surfaces.

[0015] In summary, the substrate structure and the method of manufacturing the substrate structure of the present disclosure utilize the design that the conductive pillars of adjacent layers are misaligned with each other, and the conductive pillars of spaced layers are aligned with each other, so as to reduce the width of the board edge and improve the substrate utilization rate. The difference in substrate utilization rate will be greater when the number of carrier layers is greater. BRIEF DESCRIPTION OF DRAWINGS

[0016] FIG. 1A FIG. 1 is a cross-sectional view of a conventional substrate structure.

[0017] FIG. 1B FIG. 2 is a top view of the conventional substrate structure.

[0018] FIG. 2A to FIG. 2G FIG. 5 is a cross-sectional view of a method of manufacturing a substrate structure of the present disclosure.

[0019] FIG. 3 FIG. 6 is a top view of the substrate structure manufactured by the method of the present disclosure.

[0020] Wherein, the reference signs are explained as follows:

[0021] 1, 2 substrate structure

[0022] 10, 20 core layer

[0023] 20a first surface

[0024] 20b second surface

[0025] 200 via

[0026] 21 wiring layer

[0027] 12, 22 conductive structure

[0028] 13, 23 first build-up structure

[0029] 130, 230 first dielectric layer

[0030] 231 first via

[0031] 132, 232 first conductive pillar

[0032] 233 first wiring layer

[0033] 14, 24 second build-up structure

[0034] 140, 240 second dielectric layer

[0035] 241 second via

[0036] 142, 242 second conductive pillar

[0037] 243 second wiring layer

[0038] 15, 25 third build-up structure

[0039] 150, 250 third dielectric layer

[0040] 251 third via

[0041] 152, 252 third conductive pillar

[0042] 253 third wiring layer

[0043] A wiring region

[0044] B board edge DETAILED DESCRIPTION

[0045] The embodiments of the present disclosure will be described in detail by the specific embodiments below, and other advantages and technical effects of the present disclosure can be easily understood by those skilled in the art from the content disclosed in the specification.

[0046] It is to be understood that the structures, proportions, sizes, etc. shown in the drawings accompanying the present disclosure are merely intended to facilitate the understanding of the disclosed content for the understanding and reading of those skilled in the art, and are not intended to limit the conditions for implementing the present disclosure, and therefore do not have technical significance. Any modification of the structure, change of the proportional relationship, or adjustment of the size, without affecting the technical effects that can be produced by the present disclosure and the purposes that can be achieved, should still fall within the scope of the technical content disclosed by the present disclosure. At the same time, the terms such as "upper", "first", "second", "third", etc. cited in the present specification are only for the convenience of clear description, and are not intended to limit the scope of the present disclosure, and the change or adjustment of the relative relationship, without substantially changing the technical content, is also considered as the scope of the present disclosure.

[0047] FIG. 2A to FIG. 2G Cross-sectional schematic view of the method for manufacturing the substrate structure 2 of the present disclosure.

[0048] As shown in FIG. 2A , a core layer 20 having a circuit layer 21 and a plurality of conductive structures 22 is provided.

[0049] In the present embodiment, the core layer 20 has opposite first and second surfaces 20a and 20b. For example, the material of the core layer 20 can be a substrate containing glass fibers and organic resin, such as BT (Bismaleimide Triazine), FR4 or FR5, etc., without particular limitation.

[0050] In an embodiment, a plurality of through holes 200 can be formed in the core layer 20 by mechanical, laser, etching or other appropriate means, and a plurality of columnar conductive structures 22 can be formed in the plurality of through holes 200 by plating through hole (PTH) and patterning processes (such as inner layer development etching stripping line (DES)), etc. processes, and then a circuit layer 21 can be formed on the plurality of conductive structures 22 and the core layer 20.

[0051] As shown in FIG. 2B , a first dielectric layer 230 is formed on the first and second surfaces 20a and 20b of the core layer 20 by lamination. Then, a plurality of first through holes 231 are formed in the first dielectric layer 230 by mechanical, laser, etching or other appropriate means, wherein the first through holes 231 do not penetrate the first dielectric layer 230 and do not expose the core layer 20.

[0052] As shown in FIG. 2C , a plurality of first conductive pillars 232, for example, copper, are formed in the plurality of first through holes 231 by plating in the circuit redistribution layer (RDL) specification, and a first circuit layer 233, for example, copper, is formed on the plurality of first conductive pillars 232 and the first dielectric layer 230.

[0053] In this embodiment, the first conductive pillars 232 are misaligned with the conductive structures 22, and the conductive structures 22 and the first conductive pillars 232 on different sides of the core layer 20 correspond to each other.

[0054] As shown in FIG. 2B, a second dielectric layer 240 is formed on the first dielectric layer 230 in a lamination manner. Then, a plurality of second through holes 241 are formed in the second dielectric layer 240 by mechanical, laser, etching or other appropriate means, wherein the second through holes 241 do not penetrate the second dielectric layer 240 and do not expose the first dielectric layer 230. FIG. 2D

[0055] As shown in FIG. 2C, a plurality of second conductive pillars 242, for example, copper, are formed in the plurality of second through holes 241 by electroplating in RDL specifications, and a second wiring layer 243, for example, copper, is formed on the plurality of second conductive pillars 242 and the second dielectric layer 240. FIG. 2E

[0056] In this embodiment, the second conductive pillars 242 are misaligned with the conductive structures 22 and the first conductive pillars 232, and the conductive structures 22 and the second conductive pillars 242 on different sides of the core layer 20 correspond to each other.

[0057] As shown in FIG. 2D, a third dielectric layer 250 is formed on the second dielectric layer 240 in a lamination manner. Then, a plurality of third through holes 251 are formed in the third dielectric layer 250 by mechanical, laser, etching or other appropriate means, wherein the third through holes 251 do not penetrate the third dielectric layer 250 and do not expose the second dielectric layer 240. FIG. 2F

[0058] As shown in FIG. 2E, a plurality of third conductive pillars 252, for example, copper, are formed in the plurality of third through holes 251 by electroplating in RDL specifications, and a third wiring layer 253, for example, copper, is formed on the plurality of third conductive pillars 252 and the third dielectric layer 250, so as to obtain the substrate structure 2 of the present disclosure. FIG. 2G

[0059] In this embodiment, the third conductive pillars 252 are misaligned with the conductive structures 22 and the second conductive pillars 242, and the first conductive pillars 232 and the third conductive pillars 252 on different sides of the core layer 20 correspond to each other.

[0060] ​​​​In this embodiment, the material of the first dielectric layer 230, the second dielectric layer 240 and the third dielectric layer 250 can be, for example, Ajinomoto build-up film (ABF), polybenzoxazole (PBO), polyimide (PI), prepreg (PP) or other dielectric materials. The materials of the first dielectric layer 230, the second dielectric layer 240 and the third dielectric layer 250 can be the same or different. The present disclosure is not limited in this regard.

[0061] In the substrate structure 2 of the present disclosure, the first conductive pillar 232 is aligned with the third conductive pillar 252 (or the first via 231 is aligned with the third via 251), the second conductive pillar 242 is aligned with the conductive structure 22 (or the second via 241 is aligned with the via 200), and the first conductive pillar 232 and the second conductive pillar 242 / conductive structure 22 are staggered with each other (or the first via 231 and the second via 241 / via 200 are staggered with each other), and the third conductive pillar 252 and the second conductive pillar 242 / conductive structure 22 are staggered with each other (or the third via 251 and the second via 241 / via 200 are staggered with each other), as shown in FIG. 3 Compared with the prior art, the board edge B of the substrate structure 2 of the present disclosure can be reduced, thereby increasing the circuit area A, for example FIG. 1B In the prior art, only 12 lines can be arranged in the circuit area A, while in the present disclosure, 14 lines can be arranged. The substrate utilization rate is effectively improved.

[0062] In summary, the substrate structure and the manufacturing method of the present disclosure use the design that the conductive pillars of adjacent layers are staggered with each other and the conductive pillars of the layers in between are aligned with each other, which can reduce the width of the board edge and improve the substrate utilization rate. The difference in substrate utilization rate will be greater when the number of carrier board layers is greater.

[0063] The above embodiments are used to illustrate the principles and technical effects of the present disclosure, but are not used to limit the present disclosure. Those skilled in the art can modify the above embodiments without departing from the concept and scope of the present disclosure. Therefore, the protection scope of the present disclosure should be as stated in the claims.

Claims

1. A substrate structure, comprising: The core layer has opposing first and second surfaces and multiple conductive structures; The first layer structure is disposed on the first surface and the second surface of the core layer, and has a first dielectric layer and a plurality of first conductive pillars formed in the first dielectric layer; as well as The second add-in structure is disposed on the first add-in structure and has a second dielectric layer and a plurality of second conductive pillars formed in the second dielectric layer; The first conductive post is misaligned with the conductive structure, and the second conductive post is aligned with the conductive structure and misaligned with the first conductive post. The second conductive posts located on different sides of the core layer are aligned with each other.

2. The substrate structure as described in claim 1, characterized in that, The substrate structure also includes a third add-on structure disposed on the second add-on structure, and has a third dielectric layer and a plurality of third conductive pillars formed in the third dielectric layer.

3. The substrate structure as described in claim 2, characterized in that, The third conductive post is aligned with the first conductive post and is misaligned with the second conductive post and the conductive structure.

4. The substrate structure as described in claim 2, characterized in that, The conductive structure, the first conductive post, the second conductive post, and the third conductive post are adjacent to the edge of the substrate structure.

5. A method for manufacturing a substrate structure, comprising: A core layer is provided having opposing first and second surfaces and multiple conductive structures; A first add-on structure is formed on the first surface and the second surface of the core layer, wherein the first add-on structure has a first dielectric layer and a plurality of first conductive pillars formed in the first dielectric layer; and A second layer structure is formed on the first layer structure, wherein the second layer structure has a second dielectric layer and a plurality of second conductive pillars formed in the second dielectric layer; The first conductive post is misaligned with the conductive structure, and the second conductive post is aligned with the conductive structure and misaligned with the first conductive post. The second conductive posts located on different sides of the core layer are aligned with each other.

6. The method for manufacturing the substrate structure as described in claim 5, characterized in that, The method further includes forming a third layer structure on the second layer structure, wherein the third layer structure has a third dielectric layer and a plurality of third conductive pillars formed in the third dielectric layer.

7. The method for manufacturing the substrate structure as described in claim 6, characterized in that, The third conductive post is aligned with the first conductive post and is misaligned with the second conductive post and the conductive structure.

8. The method for manufacturing the substrate structure as described in claim 6, characterized in that, The conductive structure, the first conductive post, the second conductive post, and the third conductive post are adjacent to the edge of the substrate structure.

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