Back-end metal interconnection layer structure and manufacturing method

Abstract

The invention discloses a back-end metal interconnection layer structure and a manufacturing method thereof. The back-end metal interconnection layer structure comprises a plurality of protruding metal connecting wires which are arranged on a substrate and located on the same layer; the dielectric protection shell layer is arranged between any two adjacent metal connecting wires, a cavity is formed in the protection shell layer, the cavity is filled with an aerogel layer, and the aerogel layer and the protection shell layer jointly form a dielectric layer between the metal connecting wires. According to the invention, the aerogel layer of which the dielectric constant is close to that of air is used as the isolation dielectric layer between the metal connecting wires, so that the capacitance between the metal connecting wires of the subsequent metal interconnection layer can be effectively reduced by using the extremely low dielectric constant of the aerogel layer; and meanwhile, sufficient mechanical strength can be provided by utilizing the extremely high pressure resistance of the aerogel layer, so that the whole metal interconnection layer structure is prevented from collapsing.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit process technology, and in particular to a back-end metal interconnection layer structure and a manufacturing method. Background Art

[0002] As semiconductor process nodes shrink, the spacing between back-end metal connections gradually decreases, and their parasitic capacitance gradually increases, gradually becoming the main reason for the reduction in chip speed. To solve this problem, the industry generally adopts lower dielectric constant (Low-k) dielectrics to reduce the capacitance between copper interconnects. Although the ultra-low dielectric constant dielectrics of the existing technology have reduced the k value to around 2.0, it still cannot meet the technical requirements for further reduction of metal line width. Since the dielectric constant of air is about 1.001, which is almost close to the dielectric constant of a vacuum, the industry began to consider using air as the interconnect medium, that is, air gap.

[0003] There are two main approaches to forming air gaps. One involves using easily decomposable materials as the interconnect dielectric throughout the entire process. This material is then decomposed, typically by heating, to release gaseous matter, ultimately forming the air gap. Another approach involves using conventional materials (such as silicon dioxide or low-k materials) as a sacrificial dielectric for the interconnect layer on the substrate. After completing the current metal connection, the sacrificial dielectric is etched away, and a layer of dielectric with poorer filling capacity is deposited to form the air gap.

[0004] Both of the above solutions have obvious shortcomings. For solution one, on the one hand, the introduction of new easily decomposable materials is incompatible with existing processes, resulting in additional risks; on the other hand, the large amount of gas released during decomposition will destroy the existing structure. For solution two, on the one hand, the dielectric material used for filling is generally porous materials with a low dielectric constant. These materials themselves have low mechanical strength, and after the air gap is formed, the overall mechanical strength is insufficient, which may cause the structure to collapse. On the other hand, although the pore-filling ability of the dielectric material is poor, it still has a certain pore-filling ability. As a result, a portion of the dielectric material will still be deposited on the sidewalls and bottom of the air gap, resulting in a porosity much lower than expected, making it difficult to achieve a final dielectric constant less than 2. Summary of the Invention

[0005] The purpose of the present invention is to overcome the above-mentioned defects in the prior art and provide a back-end metal interconnection layer structure and a manufacturing method.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] The present invention provides a back-end metal interconnection layer structure, comprising:

[0008] A plurality of protruding metal wirings provided on the substrate and located on the same layer;

[0009] A dielectric protective shell layer is provided between any two adjacent metal lines, wherein the protective shell layer has a cavity therein, the cavity is filled with an aerogel layer, and the aerogel layer and the protective shell layer together form a dielectric layer between the metal lines.

[0010] Furthermore, the side of the protective shell layer facing the substrate is open, and the aerogel layer is covered on the substrate.

[0011] Furthermore, a low dielectric constant material layer is provided on the surface of the substrate, the metal connection, the protective shell layer, the cavity and the aerogel layer are located on the surface of the low dielectric constant material layer, and the low dielectric constant material layer is provided with metal through holes corresponding to the metal connection.

[0012] Furthermore, the aerogel layer includes a silicon aerogel layer.

[0013] The present invention also provides a method for manufacturing a back-end metal interconnection layer structure, comprising:

[0014] providing a substrate;

[0015] forming an aerogel layer on the surface of the substrate;

[0016] forming a first dielectric layer on the surface of the aerogel layer;

[0017] forming a groove on the surface of the first dielectric layer, stopping on the surface of the substrate;

[0018] forming a second dielectric layer on the surface of the first dielectric layer, and making the second dielectric layer cover the inner wall of the trench;

[0019] removing the second dielectric layer on the bottom of the groove, and retaining the second dielectric layer on the sidewall of the groove and the first dielectric layer on the surface of the aerogel layer, so as to form a protective shell layer covering the aerogel layer by the first dielectric layer and the second dielectric layer;

[0020] Metal wiring is formed in the trench.

[0021] Furthermore, a silica aerogel layer is obtained by spin coating silica sol on the surface of the substrate and performing low-temperature vacuum drying.

[0022] Furthermore, the thickness of the silica sol is adjusted by adjusting the composition of the silica sol precursor and / or adjusting the rotation speed when spin-coating the silica sol; and the thickness of the silica aerogel layer is adjusted by adjusting the low-temperature vacuum drying process.

[0023] Further, atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition or chemical vapor deposition process below atmospheric pressure is used to form a layer with a thickness of The first dielectric layer and the second dielectric layer are formed; and / or, the groove is formed by an ion beam etching process.

[0024] The present invention also provides a method for manufacturing a back-end metal interconnection layer structure, comprising:

[0025] providing a substrate;

[0026] forming a low dielectric constant material layer and an aerogel layer in sequence on the surface of the substrate;

[0027] forming a first dielectric layer and a hard mask layer in sequence on the surface of the aerogel layer;

[0028] forming a first intermediate trench on the surface of the hard mask layer, stopping on the surface of the first dielectric layer;

[0029] forming a first middle through hole on the surface of the first dielectric layer at the bottom of the first middle trench, stopping in the low dielectric constant material layer;

[0030] forming a second intermediate trench downwardly along the first intermediate trench and stopping on the surface of the low dielectric constant material layer, and forming a second intermediate via downwardly along the first intermediate via and stopping on the surface of the substrate, forming a metal wiring trench formed by the first intermediate trench and the second intermediate trench, and forming an interlayer via formed by the first intermediate via and the second intermediate via located below the metal wiring trench;

[0031] forming a second dielectric layer on the surface of the hard mask layer, and making the second dielectric layer cover the inner walls of the metal wiring trench and the interlayer via hole;

[0032] removing the second dielectric layer on the bottom of the metal wiring trench and the bottom of the interlayer via hole, and retaining the second dielectric layer on the sidewalls of the metal wiring trench and the sidewalls of the interlayer via hole;

[0033] Metal is filled in the metal connection trench and the interlayer through hole to form metal connection and metal through hole, and the hard mask layer is removed. A protective shell layer covering the aerogel layer is formed through the first dielectric layer and the second dielectric layer.

[0034] Furthermore, the hard mask layer includes a metal hard mask layer; when forming the first intermediate through hole, a certain distance is maintained between the bottom of the first intermediate through hole and the surface of the substrate; when forming the metal connection trench, in the absence of photoresist, the first dielectric layer and the aerogel layer below the first intermediate trench, and the low dielectric constant material layer on the bottom of the first intermediate through hole are simultaneously etched directly through the hard mask layer, and the surface of the low dielectric constant material layer and the surface of the substrate are simultaneously exposed at the etching end point.

[0035] As can be seen from the above technical solution, the present invention utilizes an aerogel layer with a dielectric constant close to that of air as the isolation dielectric layer between metal interconnects. This not only effectively reduces the capacitance between metal interconnects in the downstream metal interconnect layer by leveraging the aerogel layer's extremely low dielectric constant, but also simultaneously leverages the aerogel layer's extremely high voltage resistance to provide sufficient mechanical strength, preventing collapse of the entire metal interconnect layer structure. Furthermore, by employing specialized processes (including forming the dielectric protective shell layer using a thermally-independent, non-plasma-enhanced CVD process, and patterning the aerogel layer using a pure inert gas bombardment and highly collimated ion beam etching process), damage to the aerogel layer during device manufacturing can be effectively prevented, thereby ensuring the stability of the aerogel layer's properties and eliminating conventional cleaning processes, saving costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1-Figure 2 Schematic diagram of a back-end metal interconnection layer structure according to a preferred embodiment of the present invention.

[0037] Figure 3-Figure 8 Schematic diagram of the process steps of a method for manufacturing a back-end metal interconnection layer structure according to a preferred embodiment of the present invention.

[0038] Figures 9-15 Schematic diagram of the process steps of a method for manufacturing a back-end metal interconnection layer structure according to a second preferred embodiment of the present invention. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. Unless otherwise defined, the technical terms or scientific terms used herein should be the common meanings understood by people with ordinary skills in the field to which the invention belongs. The words "including" and similar words used in this article mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0040] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings.

[0041] refer to Figure 1 A back-end metal interconnection layer structure of the present invention includes a substrate 21 , a plurality of metal lines 24 disposed on the substrate 21 , and a dielectric isolation structure 27 disposed between the metal lines 24 .

[0042] The substrate 21 is a general term for the front layers of the back-end metal interconnection layer, which generally includes one or more layers. Figure 1 The back-end metal interconnection layer structure shown is a first metal interconnection layer structure built on a substrate 21 ; the first metal interconnection layer is composed of a plurality of metal lines 24 and does not have metal through-holes.

[0043] A plurality of metal wirings 24 located in the same layer of the first metal interconnection layer are disposed separately from each other on the substrate 21 , thereby forming a protruding metal wiring 24 structure on the surface of the substrate 21 .

[0044] Dielectric isolation structure 27 is disposed between any two adjacent metal lines 24 and contacts the sidewalls of the metal lines 24. Dielectric isolation structure 27 includes a dielectric protective shell 26; protective shell 26 contacts the sidewalls of the metal lines 24 through its sides. Protective shell 26 has a cavity within it, which is filled with aerogel layer 22. Aerogel layer 22 and protective shell 26 together form dielectric isolation structure 27 and a dielectric layer between metal lines 24.

[0045] refer to Figure 1 In some embodiments, the side of the protective shell layer 26 facing the substrate 21 is open, that is, the cavity has an opening facing the substrate 21 , thereby covering the aerogel layer 22 on the substrate 21 .

[0046] In some embodiments, the upper surface of the protective shell layer 26 is flush with the top surface of the metal connection 24 .

[0047] In some embodiments, aerogel layer 22 comprises a silica aerogel layer.

[0048] The dielectric protective shell layer 26 is made of silicon dioxide or other silicon materials.

[0049] The metal connection 24 is made of copper.

[0050] In some embodiments, the thickness of the dielectric protective shell 26 is

[0051] In some embodiments, the dielectric protection shell 26 includes a first dielectric layer 23 located on the top surface of the cavity and a second dielectric layer 25 located on the side surface of the cavity. The first dielectric layer 23 and the second dielectric layer 25 are connected as a whole and together form a cavity.

[0052] Furthermore, the second dielectric layer 25 also extends onto the top surface of the first dielectric layer 23 , so that the thickness of the top surface of the cavity is greater than the thickness of the side surface of the cavity.

[0053] Furthermore, the thickness of the second dielectric layer 25 is greater than the thickness of the first dielectric layer 23 .

[0054] refer to Figure 2 The back-end metal interconnect structure of the present invention includes a substrate 31, a low-k dielectric constant material layer 32 disposed on the substrate 31, a plurality of metal lines 36 disposed on the low-k dielectric constant material layer 32, and a dielectric isolation structure 39 disposed between the metal lines 36. The low-k dielectric constant material layer 32 includes metal vias 37 connected to the metal lines 36.

[0055] Figure 2 The back-end metal interconnection layer structure shown is a metal interconnection layer structure above the first metal interconnection layer (for example, it can be the second metal interconnection layer, the third metal interconnection layer, etc., until the top metal interconnection layer, for the convenience of description, it is represented by the current metal interconnection layer below) built on the substrate 31. Therefore, in addition to multiple metal connections 36, it also has metal through holes 37. The substrate 31 in this embodiment can be regarded as a metal interconnection layer for each previous layer (including Figure 1 A general term for the first metal interconnect layer and substrate 21 in the system.

[0056] A plurality of metal lines 36 located in the same layer of the current metal interconnect layer are disposed separately from each other on the low-k material layer 32 , thereby forming a protruding metal line 36 structure on the surface of the low-k material layer 32 .

[0057] Dielectric isolation structure 39 is disposed between any two adjacent metal lines 36 and contacts the sidewalls of the metal lines 36. Dielectric isolation structure 39 includes a dielectric protective shell 38; protective shell 38 contacts the sidewalls of the metal lines 36 through its sides. Protective shell 38 has a cavity within it, which is filled with aerogel layer 33. Aerogel layer 33 and protective shell 38 together form dielectric isolation structure 39 and a dielectric layer between metal lines 36.

[0058] In this embodiment, a low-k material layer 32 constituting a current metal interconnect layer is provided on the surface of the substrate 31; the metal connection 36 of the current metal interconnect layer, the protective shell 38 of the dielectric isolation structure 39, the cavity, and the aerogel layer 33 are all located on the surface of the low-k material layer 32; a metal through hole 37 is provided through the low-k material layer 32, the upper end of the metal through hole 37 is connected to the corresponding metal connection 36, and the lower end of the metal through hole 37 is exposed from the bottom surface of the low-k material layer 32 for connecting to the previous metal interconnect layer, for example Figure 1 The metal wiring 24 on the first metal interconnect layer in the embodiment is connected to the substrate 21 ( Figure 2 The substrate 31 can be regarded as Figure 1 The metal connection line 36 located at the uppermost metal interconnection layer is used to connect to the lead-out structure (such as a pad) to be led out to the outside.

[0059] refer to Figure 2 In some embodiments, the side of the protective shell layer 38 facing the low dielectric constant material layer 32 is open, that is, the cavity has an opening facing the low dielectric constant material layer 32 , thereby covering the aerogel layer 33 on the low dielectric constant material layer 32 .

[0060] In some embodiments, the upper surface of the protective shell layer 38 is flush with the top surface of the metal connection 36 .

[0061] In some embodiments, aerogel layer 33 comprises a silica aerogel layer.

[0062] The dielectric protective shell layer 38 is made of silicon dioxide or other silicon materials.

[0063] In some embodiments, the thickness of the dielectric protective shell 38 is

[0064] In some embodiments, the low-k material layer 32 is made of a conventional low-k material (eg, BDI, BDII, etc.).

[0065] The metal connection lines 36 and the metal vias 37 are made of copper.

[0066] In some embodiments, the dielectric protection shell 38 includes a first dielectric layer 34 located on the top surface of the cavity and a second dielectric layer 35 located on the side surface of the cavity. The first dielectric layer 34 and the second dielectric layer 35 are connected as a whole and together form a cavity.

[0067] The following further describes in detail a method for manufacturing a back-end metal interconnection layer structure of the present invention through specific embodiments and in conjunction with the accompanying drawings.

[0068] refer to Figure 3-Figure 8 The back-end metal interconnection layer structure manufacturing method of the present invention can be used to manufacture, for example Figure 1 A back-end metal interconnection layer structure is shown, and includes the following steps:

[0069] Step S11 : forming an aerogel layer 22 on the surface of the substrate 21 .

[0070] like Figure 3 As shown, a silica sol of a certain thickness is spin-coated on the surface of a substrate 21 by spin coating, and then dried in a vacuum at low temperature to obtain a silica aerogel layer 22.

[0071] The silica sol's thickness can be adjusted by adjusting the silica sol's viscosity and other physical and chemical properties by adjusting the silica sol's precursor composition and / or by finding appropriate coordinate points on the spin-coating curve and adjusting the spin-coating speed. The thickness of the silica aerogel layer 22 can also be adjusted by adjusting the silica sol's thickness and the low-temperature vacuum drying process. The thickness of the resulting silica aerogel layer 22 is determined by the thickness of the spin-coated silica sol and the low-temperature drying process, eliminating the need for additional chemical mechanical polishing or etching processes to adjust the thickness of the silica aerogel layer 22.

[0072] Step S12 : forming a first dielectric layer 23 on the surface of the aerogel layer 22 .

[0073] like Figure 4 As shown, a first dielectric layer 23, such as silicon dioxide or other silicon materials, is deposited on the surface of the silicon aerogel layer 22 using a CVD process to serve as a barrier layer for subsequent electroplating, cleaning, and other steps, thereby preventing the silicon aerogel layer 22 from being damaged in subsequent steps or causing process materials to penetrate into the porous silicon aerogel layer 22.

[0074] Furthermore, in order to avoid plasma damage to the silicon aerogel layer 22, the deposition method of the first dielectric layer 23 is a thermal process related CVD process, such as atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), and sub-atmospheric pressure chemical vapor deposition (SACVD) process, instead of using a plasma enhanced CVD process. The thickness of the deposited first dielectric layer 23 of silicon dioxide or other silicon material is relatively thin.

[0075] Step S13 : forming a trench 28 on the surface of the first dielectric layer 23 , stopping on the surface of the substrate 21 .

[0076] like Figure 5 As shown, by photolithography and etching the film layers (first dielectric layer 23 and silicon aerogel layer 22 ) on the substrate 21 , a trench 28 filled with metal wiring is formed, and the bottom of the trench 28 is located on the surface of the substrate 21 .

[0077] Furthermore, since the silicon aerogel layer 22 located on the sidewalls of the trench 28 will be exposed during the etching process, in order to avoid damage to the silicon aerogel layer 22, the etching process uses pure inert gas bombardment and better collimation ion beam etching (IBE) instead of traditional reactive ion etching (RIE) using F-containing gas.

[0078] Furthermore, since the density of the silicon aerogel layer 22 is very low, the polymer content after ion beam etching is also relatively small. Therefore, in order to avoid unnecessary damage to the silicon aerogel layer 22 , conventional cleaning is not performed after etching.

[0079] Step S14 : forming a second dielectric layer 25 on the surface of the first dielectric layer 23 , and making the second dielectric layer 25 cover the inner wall of the trench 28 .

[0080] like Figure 6 As shown, a second dielectric layer 25 such as silicon dioxide or other silicon material is deposited on the surface of the first dielectric layer 23 using a CVD process. The second dielectric layer 25 covers the inner wall of the groove 28 and serves as a barrier layer for subsequent electroplating, cleaning and other steps to prevent the subsequent steps from damaging the silicon aerogel layer 22 or causing process materials to penetrate into the porous silicon aerogel layer 22.

[0081] Furthermore, in order to avoid plasma damage to the silicon aerogel layer 22, the second dielectric layer 25 is deposited by a thermal process-related CVD process, such as atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), and sub-atmospheric pressure chemical vapor deposition (SACVD), rather than a plasma-enhanced CVD process. The thickness of the deposited second dielectric layer 25 of silicon dioxide or other silicon material is also relatively thin.

[0082] Step S15: removing the second dielectric layer 25 on the bottom of the groove 28 and retaining the second dielectric layer 25 on the sidewall of the groove 28 and the first dielectric layer 23 on the surface of the aerogel layer 22 to form a protective shell layer 26 covering the aerogel layer 22 by the first dielectric layer 23 and the second dielectric layer 25.

[0083] like Figure 7As shown, a maskless full-surface etching is used, for example, the second dielectric layer 25 is etched back to remove the silicon dioxide or other silicon material of the second dielectric layer 25 at the bottom of the trench 28, thereby opening the bottom of the trench 28. At the same time, due to the directional nature of the etching, the second dielectric layer 25 on the sidewall of the trench 28 is retained, and the first dielectric layer 23 on the top of the aerogel layer 22 is also retained, enclosing the entire silicon aerogel layer 22 for protection. Thus, a silicon aerogel layer 22 is formed by the first dielectric layer 23 and the second dielectric layer 25. Figure 1 The protective shell layer 26 covers the aerogel layer 22 (the silicon aerogel layer 22 pattern defined by the grooves 28).

[0084] In this embodiment, there are no special requirements for the etching process, and either reactive ion etching or ion beam etching can be used for maskless full-sheet surface etching. Since the protective shell layer 26 covering the aerogel layer 22 has been formed, conventional cleaning can be performed after etching.

[0085] Step S16 : forming metal wiring 24 in the trench 28 .

[0086] like Figure 8 As shown, subsequent metal electroplating and chemical mechanical polishing processes are performed to form metal lines 24 in the grooves 28. This forms a back-end first-layer metal interconnect structure built on the substrate 21, using the silicon aerogel layer 22 as an isolation medium between the metal lines 24.

[0087] refer to Figures 9-15 The back-end metal interconnection layer structure manufacturing method of the present invention can be used to manufacture, for example Figure 2 A back-end metal interconnection layer structure is shown, and includes the following steps:

[0088] Step S21 : forming a low dielectric constant material layer 32 and an aerogel layer 33 in sequence on the surface of the substrate 31 .

[0089] like Figure 9 As shown, a conventional low dielectric constant material (such as BDI, BDII, etc.) is deposited on the surface of the substrate 31 to form a low dielectric constant material layer 32 .

[0090] Subsequently, a silica sol having a certain thickness is spin-coated on the surface of the low dielectric constant material layer 32 by spin coating, and then dried in a vacuum at low temperature to obtain a silica aerogel layer 33 .

[0091] Furthermore, the thickness of the obtained silica aerogel layer 33 is determined by the thickness of the spin-coated silica sol and the low-temperature drying process, and there is no need to adjust the thickness through additional chemical mechanical polishing or etching processes.

[0092] If the thickness of the silica sol needs to be adjusted, this can be achieved by finding a suitable coordinate point on the spin coating curve, adjusting the rotation speed when spin coating the silica sol, or by adjusting the composition of the silica sol precursor to change the viscosity and other physical and chemical properties of the silica sol.

[0093] Step S22 : forming a first dielectric layer 34 and a hard mask layer 40 in sequence on the surface of the aerogel layer 33 .

[0094] like Figure 9 As shown, a first dielectric layer 34 of silicon dioxide or other silicon material is further deposited on the surface of the silicon aerogel layer 33 to serve as a barrier layer for subsequent electroplating, cleaning and other steps, thereby preventing the silicon aerogel layer 33 from being damaged in subsequent steps or causing the process materials to penetrate into the porous silicon aerogel layer 33.

[0095] Furthermore, the thickness of the deposited first dielectric layer 34 is relatively thin. Furthermore, to prevent plasma from damaging the silicon aerogel layer 33 , the deposition method is a thermal process-related CVD process, such as atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, and chemical vapor deposition below atmospheric pressure, without using a plasma-enhanced CVD process.

[0096] Afterwards, a metal hard mask layer 40 is deposited on the surface of the first dielectric layer 34 to serve as a hard mask for forming trenches and through holes in a subsequent one-step etching process.

[0097] Step S23 : forming a first middle trench on the surface of the hard mask layer 40 , stopping on the surface of the first dielectric layer 34 .

[0098] like Figure 10 As shown, through the first photolithography and etching process, the pattern of the metal connection is transferred to the hard mask layer 40 to form a hard mask pattern, thereby forming a first intermediate trench 41 on the surface of the hard mask layer 40 (i.e., between the hard mask patterns), and the bottom of the first intermediate trench 41 stops on the surface of the first dielectric layer 34 and cannot be etched through, so as to retain the first dielectric layer 34 as a protective layer for the silicon aerogel layer 33 and prevent the photoresist in the subsequent photolithography steps from contacting the silicon aerogel layer 33.

[0099] Step S24 : forming a first middle through hole 42 on the surface of the first dielectric layer 34 at the bottom of the first middle trench 41 , stopping in the low dielectric constant material layer 32 .

[0100] like Figure 11As shown, a second photolithography and etching process is performed to form a first intermediate via 42 on the surface of the first dielectric layer 34 at the bottom of the first intermediate trench 41, thereby forming a metal via pattern. This etching step removes a portion of the low-k dielectric layer 32, but does not completely penetrate it, maintaining a certain distance between the bottom of the first intermediate via 42 and the surface of the substrate 31. The specific thickness of the distance to be retained is adjusted based on the selectivity of the subsequent etching step.

[0101] Step S25: A second intermediate trench 43 is formed downward along the first intermediate trench 41, stopping on the surface of the low dielectric constant material layer 32, and a second intermediate through hole 44 is formed downward along the first intermediate through hole 42, stopping on the surface of the substrate 31, forming a metal connection trench 45 formed by the first intermediate trench 41 and the second intermediate trench 43, and forming an interlayer through hole 46 formed by the first intermediate through hole 42 and the second intermediate through hole 44 located below the metal connection trench 45.

[0102] like Figure 12 As shown, in the absence of a photoresist, etching of the metal wiring pattern is performed. Specifically, etching is performed directly through the metal hard mask layer 40, using the metal hard mask pattern as a mask, simultaneously etching the first dielectric layer 34 and aerogel layer 33 below the first intermediate trench 41, as well as a certain distance of the low-k material layer 32 at the bottom of the first intermediate via 42, which is retained based on the etching selectivity. Specifically, etching is performed downward along the first intermediate trench 41, penetrating the first dielectric layer 34 and aerogel layer 33, stopping on the surface of the low-k material layer 32, and forming a second intermediate trench 43 below the first intermediate trench 41. Simultaneously, etching is performed downward along the first intermediate via 42, penetrating the remaining portion of the low-k material layer 32, stopping on the surface of the substrate 31, and forming a second intermediate via 44 below the first intermediate via 42. This allows the surfaces of the low-k material layer 32 and the substrate 31 within the trench and via regions to be simultaneously exposed at the etching endpoint. That is, this etching step simultaneously removes the first dielectric layer 34 and aerogel layer 33 below the first intermediate trench 41, as well as a certain thickness of the low-k dielectric constant material layer 32 at the bottom of the first intermediate via 42, which is retained based on the etch selectivity. The portion of the first intermediate via 42 that was originally located within the first dielectric layer 34 and the silica aerogel layer 33 no longer exists, having been replaced by the second intermediate trench 43. This forms a metal connection trench 45 formed by the first intermediate trench 41 and the second intermediate trench 43, and an interlayer via 46 between adjacent metal layers formed by the first intermediate via 42 and the second intermediate via 44 below the metal connection trench 45.

[0103] Step S26 : forming a second dielectric layer 35 on the surface of the hard mask layer 40 , and making the second dielectric layer 35 cover the inner walls of the metal wiring trench 45 and the interlayer via 46 .

[0104] like Figure 13 As shown, a second dielectric layer 35, such as silicon dioxide or other silicon materials, is deposited on the surface of the hard mask layer 40 using a CVD process. The second dielectric layer 35 covers the inner walls of the metal connection trenches 45 and the interlayer vias 46, serving as a barrier layer for subsequent electroplating, cleaning, and other steps, thereby preventing the subsequent steps from damaging the silicon aerogel layer 33 or causing process materials to penetrate into the porous silicon aerogel layer 33.

[0105] Furthermore, in order to avoid plasma damage to the silicon aerogel layer 33, the deposition method of the second dielectric layer 35 is a thermal process related CVD process, such as atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition, chemical vapor deposition process below atmospheric pressure, rather than using a plasma enhanced CVD process. The thickness of the deposited second dielectric layer 35 of silicon dioxide or other silicon material is also relatively thin.

[0106] Step S27 : removing the second dielectric layer 35 on the bottom of the metal wiring trench 45 and the bottom of the interlayer via 46 , and retaining the second dielectric layer 35 on the sidewalls of the metal wiring trench 45 and the sidewalls of the interlayer via 46 .

[0107] like Figure 14 As shown, a maskless full-wafer etching process is employed, for example, etching back the second dielectric layer 35 to remove the second dielectric layer 35 at the bottom of the metal connection trench 45 and the bottom of the interlayer via 46, thereby opening the bottom of the metal connection trench 45 and the bottom of the interlayer via 46. At the same time, due to the directional nature of the etching, the second dielectric layer 35 located on the sidewalls of the metal connection trench 45 and the sidewalls of the interlayer via 46 is retained, thereby encapsulating and protecting the entire silica aerogel layer 33.

[0108] In this embodiment, there are no special requirements for the etching process, and either reactive ion etching or ion beam etching can be used for maskless full-surface etching. The aerogel layer 33 is completely covered, so conventional cleaning can be performed after etching.

[0109] Step S28: Filling the metal connection trenches 45 and the interlayer vias 46 with metal to form metal connections 36 and metal vias 37 , removing the hard mask layer 40 , and forming a protective shell layer 38 covering the aerogel layer 33 through the first dielectric layer 34 and the second dielectric layer 35 .

[0110] like Figure 15As shown, subsequent metal electroplating is performed to fill the metal connection trench 45 and the interlayer via 46 with metal, forming a metal connection 36 in the metal connection trench 45, and forming a metal through-hole 37 connected to the metal connection 36 in the interlayer via 46. Finally, through a chemical mechanical polishing process, the excess metal outside the metal connection trench 45 and the hard mask layer 40 remaining after the previous process steps are removed to expose the flat surface of the first dielectric layer 34. Thus, a low dielectric constant material layer 32 is formed by the first dielectric layer 34 and the second dielectric layer 35. Figure 2 A protective shell 38 is shown enclosing the aerogel layer 33 .

[0111] In summary, the present invention uses an aerogel layer 22 (33) with a dielectric constant close to that of air as an isolation dielectric layer between metal interconnects 24 (36), which can not only effectively reduce the capacitance between metal interconnects by utilizing the extremely low dielectric constant of the aerogel layer, but also simultaneously utilize the extremely high voltage resistance of the aerogel layer to provide sufficient mechanical strength to prevent the collapse of the entire metal interconnection layer structure. In addition, by using a CVD process that is only related to a thermal process without plasma enhancement to form the dielectric protective shell layer 26 (38), and using a pure inert gas bombardment and better collimation ion beam etching process to pattern the aerogel layer, special processes such as can effectively prevent the aerogel layer from being damaged during the device manufacturing process, thereby ensuring the stability of the properties of the aerogel layer, and thus eliminating the conventional cleaning process and saving costs.

[0112] While the embodiments of the present invention have been described in detail above, it will be apparent to those skilled in the art that various modifications and variations of these embodiments are possible. However, it should be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the claims. Furthermore, the invention described herein is susceptible to other embodiments and may be practiced or implemented in a variety of ways.

Claims

1. A back-end metal interconnection layer structure, characterized in that: include: A plurality of protruding metal wirings disposed on the substrate and located on the same layer; A dielectric protective shell layer is arranged between any two adjacent metal wires, wherein the protective shell layer has a cavity therein, the cavity is filled with an aerogel layer, and the aerogel layer and the protective shell layer together form a dielectric layer between the metal wires.

2. The back-end metal interconnection layer structure according to claim 1, characterized in that: The side of the protective shell layer facing the substrate is open, and the aerogel layer is covered on the substrate.

3. The back-end metal interconnection layer structure according to claim 1, characterized in that: A low dielectric constant material layer is provided on the surface of the substrate, the metal wiring, the protective shell layer, the cavity and the aerogel layer are located on the surface of the low dielectric constant material layer, and a metal through hole corresponding to the metal wiring is provided in the low dielectric constant material layer.

4. The back-end metal interconnection layer structure according to claim 1, characterized in that: The aerogel layer includes a silicon aerogel layer.

5. A method for manufacturing a back-end metal interconnection layer structure, characterized in that: include: providing a substrate; forming an aerogel layer on the surface of the substrate; forming a first dielectric layer on the surface of the aerogel layer; forming a groove on the surface of the first dielectric layer, stopping on the surface of the substrate; forming a second dielectric layer on the surface of the first dielectric layer, and making the second dielectric layer cover the inner wall of the groove; removing the second dielectric layer on the bottom of the groove, and retaining the second dielectric layer on the sidewall of the groove and the first dielectric layer on the surface of the aerogel layer, so as to form a protective shell layer covering the aerogel layer by the first dielectric layer and the second dielectric layer; Metal wiring is formed in the trench.

6. The method for manufacturing a back-end metal interconnection layer structure according to claim 5, characterized in that: The silica aerogel layer is obtained by spin coating the silica sol on the surface of the substrate and drying it in a low-temperature vacuum.

7. The method for manufacturing a back-end metal interconnection layer structure according to claim 6, characterized in that: The thickness of the silica sol is adjusted by adjusting the composition of the silica sol precursor and / or adjusting the rotation speed when the silica sol is spin-coated; the thickness of the silica aerogel layer is adjusted by adjusting the low-temperature vacuum drying process.

8. The method for manufacturing a back-end metal interconnection layer structure according to claim 5, characterized in that: Using atmospheric pressure chemical vapor deposition, low pressure chemical vapor deposition or chemical vapor deposition process below atmospheric pressure, a layer with a thickness of The first dielectric layer and the second dielectric layer are formed; and / or, the groove is formed by an ion beam etching process.

9. A method for manufacturing a back-end metal interconnection layer structure, characterized in that: include: providing a substrate; forming a low dielectric constant material layer and an aerogel layer in sequence on the surface of the substrate; forming a first dielectric layer and a hard mask layer in sequence on the surface of the aerogel layer; forming a first intermediate trench on the surface of the hard mask layer, stopping on the surface of the first dielectric layer; forming a first intermediate through hole on the surface of the first dielectric layer at the bottom of the first intermediate trench, stopping in the low dielectric constant material layer; Forming a second intermediate trench downward along the first intermediate trench, stopping on the surface of the low dielectric constant material layer, and forming a second intermediate through hole downward along the first intermediate through hole, stopping on the surface of the substrate, forming a metal wiring trench formed by the first intermediate trench and the second intermediate trench, and forming an interlayer through hole formed by the first intermediate through hole and the second intermediate through hole located below the metal wiring trench; forming a second dielectric layer on the surface of the hard mask layer, and making the second dielectric layer cover the inner wall of the metal wiring trench and the interlayer through hole; Removing the second dielectric layer on the bottom of the metal wiring trench and the bottom of the interlayer via hole, and retaining the second dielectric layer on the sidewalls of the metal wiring trench and the sidewalls of the interlayer via hole; Metal is filled in the metal wiring trench and the interlayer through hole to form metal wiring and metal through hole, and the hard mask layer is removed, and a protective shell layer covering the aerogel layer is formed through the first dielectric layer and the second dielectric layer.

10. The method for manufacturing a back-end metal interconnection layer structure according to claim 9, characterized in that: The hard mask layer includes a metal hard mask layer; when forming the first intermediate through hole, a certain distance is maintained between the bottom of the first intermediate through hole and the surface of the substrate; when forming the metal wiring trench, in the absence of photoresist, the first dielectric layer and the aerogel layer below the first intermediate trench, and the low dielectric constant material layer on the bottom of the first intermediate through hole are simultaneously etched directly through the hard mask layer, and the surface of the low dielectric constant material layer and the surface of the substrate are simultaneously exposed at the etching end point.

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