Manufacturing method of suspension shielding layer

Abstract

The invention provides a manufacturing method of a suspension shielding layer, which comprises the following steps of: forming a top metal dielectric layer covering a top metal layer on a substrate, etching the top metal dielectric layer to form a shielding layer groove with a shielding layer pattern, and depositing a metal shielding layer in the shielding layer groove, and then carrying out passivation layer deposition, exposure and etching to obtain the required shielding layer structure. According to the manufacturing method of the suspension shielding layer provided by the invention, the arc discharge influence caused by etching of the metal shielding layer can be avoided, and the alignment problem during exposure can be solved. Furthermore, TiN is adopted as the metal shielding layer, so that the stress generated by the shielding layer can be reduced, and the performance of the semiconductor device is improved.

Description

Technical Field

[0001] The invention relates to the field of semiconductor technology, and in particular to a method for manufacturing a suspended shielding layer. Background Art

[0002] Currently, many encryption chips use metal shielding layers to cover and shield the chip. Most of these metal shielding layers directly use the top metal and the second top metal as active shielding layers, and judge whether the chip is damaged by comparing the difference between the input and output signals. However, this shielding layer has high requirements for the top metal wiring and occupies the top metal resources, such as Figure 1 There is also a passive shielding layer, which uses a single layer of metal to detect changes in electrical parameters within the shielding layer, mainly playing a shielding and covering role.

[0003] The manufacturing of the metal shielding layer of the chip mainly adopts the metal film preparation technology. In the process of chip preparation, a metal film layer will be made on the surface of the wafer, and then photolithography, wet etching and other manufacturing steps will be carried out to form a metal shielding layer. At present, a metal layer can be added above the top metal layer (MT) without interconnection, in order to save the mask, and then it is exposed and the topological structure is etched to form a metal shielding layer. However, this process has the following problems: because the etching of special metal patterns is added, byproducts such as polymers will be increased, and the metal shielding layer is suspended and has no connection with the bottom, which is more likely to cause arcing; after the metal shielding layer is deposited, since the metal needs a certain thickness to ensure that it is not transparent, the alignment mark required during exposure is difficult to find, resulting in inaccurate exposure. Summary of the invention

[0004] The object of the present invention is to provide a method for manufacturing a suspended shielding layer, so as to avoid the influence of arc discharge caused by etching of the metal shielding layer and solve the alignment problem during exposure.

[0005] To achieve the above object, the present invention provides a method for manufacturing a suspended shielding layer, comprising:

[0006] providing a substrate on which a top metal layer is formed;

[0007] forming a top metal dielectric layer on the substrate, wherein the top metal dielectric layer covers the top metal layer;

[0008] Etching the top metal dielectric layer to form a shielding layer groove having a shielding layer pattern, and depositing a metal shielding layer in the shielding layer groove;

[0009] A passivation layer is formed, wherein the passivation layer covers the metal shielding layer and the top metal dielectric layer.

[0010] Optionally, before etching the top metal dielectric layer to form the shielding layer groove, the method further includes: performing a planarization process on the top metal dielectric layer.

[0011] Optionally, after depositing the metal shielding layer in the shielding layer groove and before forming the passivation layer, the method further includes: performing a planarization process on the top metal dielectric layer deposited with the metal shielding layer.

[0012] Optionally, the passivation layer includes a first passivation layer and a second passivation layer, the first passivation layer includes a TEOS layer, and the second passivation layer includes a silicon nitride layer.

[0013] Optionally, after forming the passivation layer, the method further includes: etching the passivation layer and the top metal dielectric layer to form an opening exposing a portion of the top surface of the top metal layer.

[0014] Optionally, the shielding layer pattern includes an array having a topological structure.

[0015] Optionally, the metal shielding layer includes a titanium nitride layer.

[0016] Optionally, the top metal dielectric and the passivation layer are formed by plasma enhanced chemical vapor deposition.

[0017] Optionally, the planarization process is chemical mechanical polishing.

[0018] In summary, the present invention provides a method for manufacturing a suspended shielding layer, forming a top metal dielectric layer covering a top metal layer on a substrate, then etching the top metal dielectric layer to form a shielding layer groove having a shielding layer pattern and depositing a metal shielding layer in the shielding layer groove, and then performing passivation layer deposition, exposure and etching to obtain the desired shielding layer structure. The method for manufacturing a suspended shielding layer provided by the present invention can avoid the influence of arc discharge caused by etching of the metal shielding layer, and can solve the alignment problem during exposure. Furthermore, the use of TiN as a metal shielding layer in the present invention can reduce the stress generated by the shielding layer and improve the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A structural distribution diagram of a semiconductor device;

[0020] Figure 2 A schematic diagram of a process for manufacturing a suspended shielding layer provided in an embodiment of the present invention;

[0021] FIG. 3A to FIG. 3F It is a structural schematic diagram of each step corresponding to the manufacturing method of the suspended shielding layer in an embodiment of the present invention;

[0022] Figure 4 for Figure 3FThe corresponding top view of the structure;

[0023] FIG. 5A to FIG. 5D It is the shielding layer pattern.

[0024] The reference numerals are described as follows:

[0025] 100 - substrate; 101 - top metal layer; 102 - top metal dielectric layer; 103 - metal shielding layer; 104 - passivation layer; 105 - opening; 110 - shielding layer groove. DETAILED DESCRIPTION

[0026] To make the content of the present invention more clear and understandable, the content of the present invention is further described below in conjunction with the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general replacements known to those skilled in the art are also covered within the protection scope of the present invention.

[0027] Secondly, the present invention is described in detail using schematic diagrams. When describing the examples of the present invention in detail, for the sake of convenience, the schematic diagrams are not partially enlarged according to general proportions, and this should not be used as a limitation of the present invention.

[0028] For ease of description, some embodiments of the present invention may use spatially relative terms such as "above", "below", "top", "below", etc. to describe the relationship between one element or component and another (or other) elements or components as shown in the various figures of the embodiments. It should be understood that in addition to the orientations described in the drawings, the spatially relative terms are also intended to include different orientations of the device in use or operation. For example, if the device in the drawings is turned over, the elements or components described as being "below" or "beneath" other elements or components will subsequently be positioned as being "above" or "above" the other elements or components. The terms "first", "second", etc., hereinafter, are used to distinguish between similar elements and are not necessarily used to describe a specific order or time sequence.

[0029] Figure 2 A schematic diagram of a process for manufacturing a suspended shielding layer provided by an embodiment of the present invention is shown in FIG. Figure 2 As shown, the manufacturing method of the suspended shielding layer provided in this embodiment includes the following steps:

[0030] Step S01: providing a substrate, on which a top metal layer is formed;

[0031] Step S02: forming a top metal dielectric layer on the substrate, wherein the top metal dielectric layer covers the top metal layer;

[0032] Step S03: etching the top metal dielectric layer to form a shielding layer groove having a shielding layer pattern, and depositing a metal shielding layer in the shielding layer groove; and,

[0033] Step S04: forming a passivation layer, wherein the passivation layer covers the metal shielding layer and the top metal dielectric layer.

[0034] FIG. 3A to FIG. 3F This is a schematic diagram of the structure of each step corresponding to the method for manufacturing a suspended shielding layer in one embodiment of the present invention. Figure 2 As shown, combined with FIG. 3A to FIG. 3F , a method for manufacturing the suspended shielding layer provided by the present invention is described in detail.

[0035] First, refer to Figure 3A As shown, step S01 is performed to provide a substrate 100 , on which a top metal layer 101 is formed.

[0036] Specifically, a substrate 200 is provided, and the substrate 200 may be single crystal silicon (Si), single crystal germanium (Ge), silicon germanium (GeSi) or silicon carbide (SiC), or may be silicon on insulator (SOI) or germanium on insulator (GOI); or may be other materials, such as III-V compounds such as gallium arsenide. The substrate 200 described in this embodiment is only an example of a silicon substrate, which is only an example, and the present invention is not limited thereto.

[0037] The top metal layer 101 is used to form a metal interconnection structure, which can realize the electrical connection relationship of the subsequent device structure, that is, there are other metal layers for forming a metal interconnection structure between the top metal layer 101 and the substrate 100. A dielectric layer is formed on the substrate 100, and at least one metal layer is embedded in the dielectric layer. Exemplarily, the metal layer includes a first metal layer (M1), a second metal layer (M2), a third metal layer (M3) and a top metal layer (MT) 101 embedded from bottom to top. There is no limit to the number of metal layers embedded in the dielectric layer, and it is set according to actual conditions. Several metal layers are electrically connected through plugs. The plug is a conductive layer filled in the through hole in the dielectric layer between the upper and lower metal layers.

[0038] In this embodiment, the material of the top metal layer 101 can be metal aluminum. In other embodiments, the material of the top metal layer 101 can be one or a combination of at least two of aluminum, copper, titanium, nickel, aluminum nitride, titanium nitride and nickel nitride. The top metal layer 101 can be formed by sputtering.

[0039] Next, refer to Figure 3BAs shown, step S02 is performed to form a top metal dielectric layer 102 on the substrate 100, and the top metal dielectric layer 102 covers the top metal layer 101. Exemplarily, the top metal dielectric 102 can be formed by plasma enhanced chemical vapor deposition. After the top metal dielectric layer 102 is deposited on the substrate 100, a planarization process is also performed on the top metal dielectric layer 102 until the thickness uniformity of the top metal dielectric layer 102 is within a set range. In this process, the planarization process is, for example, CMP (chemical mechanical polishing).

[0040] Next, refer to Figure 3C and Figure 3D As shown, step S03 is performed to etch the top metal dielectric layer 102 to form a shielding layer groove 110 having a shielding layer pattern, and deposit a metal shielding layer 103 in the shielding layer groove 110 .

[0041] The shielding layer pattern includes an array with a topological structure, and the shielding layer pattern includes a spiral line type, a Hilbert curve type, a Peano curve type and a random Hamiltonian loop type, as shown in sequence. FIG. 5A to FIG. 5D As shown, the shielding layer pattern can be transferred to the top metal dielectric layer 102 by photolithography and etching process. FIG. 3A to FIG. 3F It is a schematic diagram of a cross-sectional structure, where only the shielding layer groove 110 is used to illustrate the shielding layer pattern.

[0042] In reference Figure 3D As shown, the metal shielding layer 103 is deposited in the shielding layer groove 110. Specifically, the shielding layer groove 110 is first filled with metal to cover the top metal dielectric layer 102, and then a planarization process is performed to expose the top metal dielectric layer 102. In this embodiment, the metal shielding layer 103 is a titanium nitride (TiN) layer, and the deposition thickness of the metal shielding layer 103 is 5um. Titanium nitride (TiN) is used as the material of the metal shielding layer 103. Compared with the original shielding layer metal (such as tungsten fluoride), the stress generated by the shielding layer can be reduced to avoid wafer warping and deformation.

[0043] Next, refer to Figure 3E As shown, step S04 is performed to form a passivation layer 104, and the passivation layer 104 covers the metal shielding layer 103 and the top metal dielectric layer 102. The passivation layer 104 includes a first passivation layer 1041 and a second passivation layer 1042. The first passivation layer 1041 includes a TEOS (tetraethoxysilane) layer, and the second passivation layer 1042 includes a silicon nitride layer, which can be formed by plasma enhanced chemical vapor deposition. The thickness of the first passivation layer 1041 is greater than the thickness of the second passivation layer 1042. The thickness of the first passivation layer 1041 is, for example, 15um, and the thickness of the second passivation layer 1042 is, for example, 6um.

[0044] refer to Figure 3F and Figure 4 As shown, after forming the passivation layer 104, the process also includes: etching the passivation layer 104 and the top metal dielectric layer 102 to form an opening 105 exposing a portion of the top surface of the top metal layer 101, and filling the opening with a conductive material to lead out the top metal layer 101 to form a pad structure.

[0045] In summary, the present invention provides a method for manufacturing a suspended shielding layer, forming a top metal dielectric layer covering a top metal layer on a substrate, then etching the top metal dielectric layer to form a shielding layer groove having a shielding layer pattern and depositing a metal shielding layer in the shielding layer groove, and then performing passivation layer deposition, exposure and etching to obtain the desired shielding layer structure. The method for manufacturing a suspended shielding layer provided by the present invention can avoid the influence of arc discharge caused by etching of the metal shielding layer, and can solve the alignment problem during exposure. Furthermore, the present invention uses TiN as a metal shielding layer, which can reduce the stress generated by the shielding layer and improve the performance of the semiconductor device.

[0046] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for manufacturing a suspended shielding layer, characterized in that: include: providing a substrate on which a top metal layer is formed; forming a top metal dielectric layer on the substrate, wherein the top metal dielectric layer covers the top metal layer; Etching the top metal dielectric layer to form a shielding layer groove having a shielding layer pattern, and depositing a metal shielding layer in the shielding layer groove; and, A passivation layer is formed, wherein the passivation layer covers the metal shielding layer and the top metal dielectric layer.

2. The method for manufacturing a suspended shielding layer according to claim 1, characterized in that: Before etching the top metal dielectric layer to form the shielding layer groove, the method further includes: performing a planarization process on the top metal dielectric layer.

3. The method for manufacturing a suspended shielding layer according to claim 2, characterized in that: After depositing the metal shielding layer in the shielding layer groove and before forming the passivation layer, the method further includes: performing a planarization process on the top metal dielectric layer deposited with the metal shielding layer.

4. The method for manufacturing a suspended shielding layer according to claim 3, characterized in that: The passivation layer includes a first passivation layer and a second passivation layer, the first passivation layer includes a TEOS layer, and the second passivation layer includes a silicon nitride layer.

5. The method for manufacturing a suspended shielding layer according to claim 1, characterized in that: After forming the passivation layer, the method further includes: etching the passivation layer and the top metal dielectric layer to form an opening exposing a portion of the top surface of the top metal layer.

6. The method for manufacturing a suspended shielding layer according to claim 1, characterized in that: The shielding layer pattern includes an array having a topological structure.

7. The method for manufacturing a suspended shielding layer according to claim 1, characterized in that: The metal shielding layer includes a titanium nitride layer.

8. The method for manufacturing a suspended shielding layer according to claim 1, characterized in that: The top metal dielectric and the passivation layer are formed by plasma enhanced chemical vapor deposition.

9. The method for manufacturing a suspended shielding layer according to claim 2 or 3, characterized in that: The planarization process is chemical mechanical polishing.

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