Control Method, Controller, Chip and Circuit of PFC Circuit

Abstract

The present invention relates to the field of switching power supply control, and particularly to a control method, a controller, a chip and a circuit for a PFC circuit. The control method of the PFC circuit includes setting the combined working mode of CRM and DCM within one power frequency sine half-wave of the PFC circuit, and adopting the maximum expected switching period and the minimum expected switching period corresponding to the basic conduction time of the switching device of the PFC circuit, where the maximum expected switching period is greater than the minimum expected switching period. Comparing the previous switching period of the switching device corresponding to the PFC circuit with the maximum expected switching period and the minimum expected switching period, and adjusting the time of the current switching period of the switching device corresponding to the PFC circuit by increasing or decreasing the number of troughs of the inductor current discontinuous time, so as to control the fluctuation range of the switching frequency and improve the system working efficiency. At the same time, when switching at the trough, adjust the conduction time of the current switching period of the switching device of the PFC circuit to enhance the THD performance of the system.

Description

Technical Field

[0001] The present invention relates to the field of switch power supply control, and particularly to a control method, a controller, a chip and a circuit for a PFC circuit. Background Art

[0002] With the rapid development of power electronics technology, switch power supplies are widely used in electronic devices due to their small size, light weight and high efficiency. They are an indispensable power supply method for the rapid development of today's electronic information industry. However, these advantages are also accompanied by some negative effects, especially the grid harmonic pollution and the increase of reactive power caused by the distortion of non-sinusoidal current waveforms. Currently, according to industry standards, capacitive load electrical equipment with a power greater than 75W must be equipped with a power factor correction (PFC) circuit to correct the power factor of the electrical equipment, make the alternating current line current track the instantaneous change trajectory of the voltage waveform, and make the current and voltage in the same phase so that the system exhibits a pure resistive characteristic, thereby reducing the harmonic pollution and reactive power of the grid caused by the distortion of non-sinusoidal current waveforms and improving the overall efficiency of the power system.

[0003] The BOOST PFC circuit is a commonly used topology for improving the power factor of a power supply and reducing harmonic distortion. Due to its simple structure and convenient control, it has been widely used in medium and small power applications. In particular, the constant on-time control method and the critical conduction mode (CRM) operating mode perform particularly well in medium and small power applications. However, within the power frequency half-wave, maintaining a single CRM operating mode in the BOOST PFC circuit will result in a large fluctuation range of the switching frequency, which in turn affects the system efficiency. Therefore, how to regulate the range of the switching frequency and improve its operating efficiency is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] In view of this, embodiments of the present invention provide a control method, a controller, a chip and a circuit for a PFC circuit.

[0005] The present application adopts the following technical solutions:

[0006] A control method for a PFC circuit, comprising:

[0007] Obtaining a maximum expected switching period and a minimum expected switching period based on the basic on-time of the switching device of the PFC circuit, wherein the maximum expected switching period is greater than the minimum expected switching period;

[0008] Obtaining the previous switching period of the PFC circuit and the number of troughs of the inductor current discontinuous time in the previous switching period, and comparing the size of the previous switching period with the maximum expected switching period and the minimum expected switching period;

[0009] When the previous switching period is greater than the maximum expected switching period, control the current switching period of the PFC circuit switching device to reduce the number of troughs of the discontinuous inductor current time;

[0010] When the previous switching period is less than the minimum expected switching period, control the current switching period of the PFC circuit switching device to increase the number of troughs of the discontinuous inductor current time, where when the number of troughs of the discontinuous inductor current time is one, the PFC circuit enters the CRM mode, and when the number of troughs of the discontinuous inductor current time is greater than one, the PFC circuit enters the DCM mode.

[0011] Optionally, obtaining the maximum expected switching period T ref_sub and the minimum expected switching period T ref_add includes the steps of:

[0012] Obtain the basic conduction time of the PFC circuit switching device;

[0013] Obtain the bus voltage value and the instantaneous input voltage value, and based on the basic conduction time of the PFC circuit switching device, the bus voltage value, and the instantaneous input voltage value, obtain the real-time switching period of the PFC circuit in the CRM mode. The expression for the real-time switching period of the PFC circuit in the CRM mode is:

[0014] ,

[0015] ,

[0016] where V ac is the instantaneous input voltage value, V bus is the bus voltage value, T on_base is the basic conduction time of the PFC circuit switching device, T dem is the inductor demagnetization time, T CRM is the real-time switching period of the PFC circuit in the CRM mode;

[0017] Based on the real-time switching period of the PFC circuit in the CRM mode, establish an inverse relationship between the minimum expected switching period and the real-time switching period of the PFC circuit in the CRM mode, and obtain the minimum expected switching period;

[0018] Obtain a first offset, and based on the first offset and the minimum expected switching period, add the minimum expected switching period and the first offset to obtain the maximum expected switching period.

[0019] Optionally, the expression for establishing the inverse relationship between the minimum expected switching period and the real-time switching period of the PFC circuit in the CRM mode is:

[0020] , T ref_add ≥T ref_min ,

[0021] where k is a negative number, b is a positive number, and T ref_min is the minimum switching period allowed by the system.

[0022] Optionally, it further includes further adjusting the minimum desired switching period and the maximum desired switching period. When the input voltage slope is less than 0, the second offset is added to both the minimum desired switching period and the maximum desired switching period to obtain the second minimum desired switching period and the second maximum desired switching period, which are respectively used as the minimum desired switching period of the PFC circuit switching device and the maximum desired switching period of the switching device.

[0023] Optionally, it further includes pre-compensating the conduction time of the PFC circuit switching device at the valley switching moment to obtain the conduction time of the PFC circuit switching device in the current switching period. The step of obtaining the conduction time of the PFC circuit switching device in the current switching period includes:

[0024] Obtaining the previous switching period corresponding to the PFC circuit switching device, the total time of inductor magnetization and demagnetization in the previous switching period of the PFC circuit, the valley period of the PFC circuit, and the basic conduction time of the PFC circuit switching device;

[0025] Calculating the conduction time of the PFC circuit switching device in the current switching period based on the number of valleys of the discontinuous inductor current in the current switching period that is reduced or increased.

[0026] Optionally, when the number of valleys of the discontinuous time in the current switching period is one, the expression for calculating the conduction time of the PFC circuit switching device in the current switching period is:

[0027] ,

[0028] where T on is the conduction time of the PFC circuit switching device in the current switching period, T on_base is the basic conduction time of the PFC circuit switching device, T sw is the previous switching period corresponding to the PFC circuit switching device, T power is the total time of inductor magnetization and demagnetization in the previous switching period of the PFC circuit, and T zcd is the valley period of the discontinuous inductor current of the PFC circuit;

[0029] When the number of valleys of the discontinuous time in the current switching period is one, the expression for calculating the conduction time of the PFC circuit switching device in the current switching period is:

[0030] ,

[0031] Among them, T on is the conduction time of the current switching cycle of the PFC circuit switching device, T on_base is the basic conduction time of the PFC circuit switching device, T sw is the previous switching cycle corresponding to the PFC circuit switching device, T power is the total time of inductance excitation and demagnetization in the previous switching cycle of the PFC circuit, T zcd is the trough period of the discontinuous time of the PFC circuit inductance current.

[0032] The present invention also provides a PFC circuit controller adopting the above PFC circuit control method, including:

[0033] An acquisition unit for acquiring a maximum expected switching cycle and a minimum expected switching cycle, the maximum expected switching cycle being greater than the minimum expected switching cycle, the maximum expected switching cycle and the minimum expected switching cycle being obtained based on the basic conduction time of the PFC circuit switching device; acquiring the previous switching cycle of the PFC circuit and the number of troughs of the discontinuous time of the inductance current in the previous switching cycle;

[0034] A comparison and adjustment unit for comparing the size of the previous switching cycle with the maximum expected switching cycle and the minimum expected switching cycle according to the information acquired by the acquisition unit; when the previous switching cycle is greater than the maximum expected switching cycle, controlling the current switching cycle corresponding to the PFC circuit switching device to reduce the number of troughs of the discontinuous time of the inductance current, wherein when the number of troughs of the discontinuous time of the inductance current is one, the PFC circuit enters the CRM mode, and when the number of troughs of the discontinuous time of the inductance current is greater than one, the PFC circuit enters the DCM mode; when the previous switching cycle is less than the minimum expected switching cycle, controlling the current switching cycle corresponding to the PFC circuit switching device to increase the number of troughs of the discontinuous time of the inductance current.

[0035] Optionally, the PFC circuit controller further includes:

[0036] A conduction time adjustment unit for pre-compensating the conduction time of the PFC circuit switching device at the trough switching moment to obtain the conduction time of the current switching cycle of the PFC circuit switching device.

[0037] The present invention also provides a chip including the above PFC circuit controller.

[0038] The present invention also provides a circuit including a PFC circuit and the above PFC circuit controller.

[0039] In summary, the advantages and beneficial effects of the present invention are as follows:

[0040] The present invention provides a control method, a controller, a chip and a circuit for a PFC circuit. The control method of the PFC circuit includes obtaining a maximum expected switching period and a minimum expected switching period based on the basic conduction time of the switching device of the PFC circuit, where the maximum expected switching period is greater than the minimum expected switching period; obtaining the previous switching period of the PFC circuit and the number of troughs of the inductor current discontinuous time in the previous switching period, and comparing the previous switching period with the maximum expected switching period and the minimum expected switching period; when the previous switching period is greater than the maximum expected switching period, controlling the current switching period corresponding to the switching device of the PFC circuit to reduce the number of troughs of the inductor current discontinuous time, where when the number of troughs of the inductor current discontinuous time is one, the PFC circuit enters the CRM mode, and when the number of troughs of the inductor current discontinuous time is greater than one, the PFC circuit enters the DCM mode; when the previous switching period is less than the minimum expected switching period, controlling the current switching period corresponding to the switching device of the PFC circuit to increase the number of troughs of the inductor current discontinuous time.

[0041] Set the PFC circuit to a combined working mode of CRM and DCM within a power frequency sine half-wave, obtain the maximum expected switching period and the minimum expected switching period, compare the previous switching period corresponding to the switching device of the PFC circuit with the maximum expected switching period and the minimum expected switching period, and adjust the time of the current switching period corresponding to the switching device of the PFC circuit by increasing or decreasing the number of troughs of the inductor current discontinuous time, so as to control the fluctuation range of the switching frequency and improve the system working efficiency.

[0042] In the DCM mode of the PFC circuit, the inductor current will have an inductor current discontinuous phenomenon within a switching period. This discontinuous characteristic will lead to a relatively high harmonic distortion; at the same time, when the number of troughs switches, the current waveform will also be distorted, resulting in an increase in the total harmonic distortion (THD). Therefore, when the trough switches, adjust the conduction time of the current switching period of the switching device of the PFC circuit to enhance the THD performance of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings, but they should fall within the protection scope of this application.

[0044] Figure 1Schematic diagram of a traditional BOOST PFC circuit;

[0045] Figure 2 Schematic diagram of the relationship among the instantaneous input voltage, the basic conduction time of the switching device, and the switching frequency of the switching device in the CRM mode of the BOOST PFC circuit;

[0046] Figure 3 Schematic diagram of the flow of a control method for a PFC circuit provided by an embodiment of the present invention;

[0047] Figures 4a - 4b Schematic diagram of the relationship between the instantaneous input voltage and the switching frequency of the switching device corresponding to the CRM operating mode and the DCM mode of a control method for a PFC circuit provided by an embodiment of the present invention;

[0048] Figure 5 Schematic diagram of obtaining the basic conduction time of the switching device in a control method for a PFC circuit provided by an embodiment of the present invention;

[0049] Figure 6 Schematic diagram of obtaining the maximum expected switching period and the minimum expected switching period in a control method for a PFC circuit provided by an embodiment of the present invention;

[0050] Figure 7 Schematic diagram of the linear relationship between the minimum expected switching period and the real-time switching period of the PFC circuit in the CRM mode in a control method for a PFC circuit provided by an embodiment of the present invention;

[0051] Figure 8 Schematic diagram of the relationship between the maximum expected switching period, the minimum expected switching period and the instantaneous input voltage in a control method for a PFC circuit provided by an embodiment of the present invention;

[0052] Figure 9 Schematic diagram of the relationship between the maximum expected switching period, the minimum expected switching period and the current switching period corresponding to the switching device of the PFC circuit in a control method for a PFC circuit provided by an embodiment of the present invention;

[0053] Figure 10 Schematic diagram of the relationship between the maximum expected switching period, the minimum expected switching period obtained by further adjustment and the current switching period corresponding to the switching device of the PFC circuit in a control method for a PFC circuit provided by an embodiment of the present invention;

[0054] Figure 11 Schematic diagram of the inductor current waveform after compensating the conduction time of the switching device of the PFC circuit in the previous switching period in a control method for a PFC circuit provided by an embodiment of the present invention;

[0055] Figure 12 Schematic diagram for obtaining the current switching cycle conduction time of the switching device of a PFC circuit, provided by an embodiment of the present invention;

[0056] Figure 13 Schematic diagram of valley detection for a control method of a PFC circuit, provided by an embodiment of the present invention;

[0057] Figure 14 Schematic diagram of the principle of a PFC circuit, provided by an embodiment of the present invention. Detailed implementation manners

[0058] As Figure 1 shown, it is a traditional BOOST PFC (boost power factor correction) circuit, including: a rectifier bridge composed of the first diode D1 to the fourth diode D4, the first inductor L1, the second inductor L2, the third inductor L3, the switching device Q, the fifth diode D5, the first capacitor C1, the second capacitor C2, the third capacitor C3, the resistor R, and the input voltage;

[0059] One end of the first capacitor C1 is connected to one end of the first inductor L1 and one end of the input voltage, the other end of the first capacitor C1 is connected to one end of the second inductor L2 and the other end of the input voltage, one end of the second capacitor C2 is connected to the anode of the first diode D1, the cathode of the fourth diode D4, and the other end of the first inductor L1, the other end of the second capacitor C2 is connected to the anode of the third diode D3, the cathode of the second diode D2, and the other end of the second inductor L2, the cathode of the first diode D1 is connected to the cathode of the third diode D3, one end of the third inductor L3, and one end of the third capacitor C3, the other end of the third inductor L3 is connected to the drain of the switching device Q and the anode of the fifth diode D5, the cathode of the fifth diode D5 is connected to one end of the fourth capacitor C4 and one end of the resistor R, and the anode of the fourth diode D4 is connected to the anode of the second diode D2, the other end of the third capacitor C3, the source of the switching device Q, the other end of the fourth capacitor, and the other end of the resistor R.

[0060] In the single CRM mode within the power frequency half-wave of the BOOST PFC circuit, as Figure 2 shown, since the conduction time T on of the switching device Q of the PFC circuit remains unchanged, when the input voltage V acWhen it is relatively small, the growth rate of the forward excitation current of the third inductor L3 will slow down accordingly, resulting in a relatively small forward excitation current of the third inductor L3. The energy stored in the third inductor L3 will decrease. Correspondingly, the energy that needs to be released during the demagnetization stage of the third inductor L3 will also decrease accordingly. The demagnetization time of the third inductor L3 becomes shorter, resulting in a shorter time for one switching cycle of the switching device Q of the PFC circuit, and ultimately leading to an increase in the switching frequency f of the switching device Q of the PFC circuit, that is, as Figure 2 shown, the switching frequency f of the switching device of the PFC circuit is inversely proportional to the input voltage V ac . When the input voltage V ac is relatively small, the switching frequency f of the switching device Q of the PFC circuit will increase, that is, when the waveform of the input voltage V ac descends, the waveform of the switching frequency f of the switching device Q of the PFC circuit will upturn, and the change range of the switching frequency f of the switching device Q of the PFC circuit will be relatively wide; moreover, the increase in the switching frequency f of the switching device Q of the PFC circuit will also lead to an increase in the switching loss of the switching device Q of the PFC circuit. And because the change range of the switching frequency f of the switching device Q of the PFC circuit is relatively wide, it will also make the design of magnetic components and EMI filters in the PFC circuit more difficult.

[0061] In order to regulate the width of the change range of the switching frequency f of the switching device Q of the PFC circuit, reduce the highest switching frequency f of the switching device Q of the PFC circuit, and improve the working efficiency of the system, the embodiments of the present application provide a control method, a controller, a chip and a circuit for the PFC circuit, to control the range of the switching frequency f of the switching device Q of the PFC circuit and improve the efficiency of the PFC circuit.

[0062] In order to better understand the technical solutions of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0063] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present invention.

[0064] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms of "a", "the" and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0065] The present invention provides a control method for a PFC circuit, as Figure 3 shown, including:

[0066] Step S10, obtaining a maximum expected switching period and a minimum expected switching period based on the basic conduction time of the switching device of the PFC circuit, where the maximum expected switching period is greater than the minimum expected switching period;

[0067] Step S20, obtaining the previous switching period of the PFC circuit and the number of troughs of the inductor current discontinuous time in the previous switching period, and comparing the size of the previous switching period with the maximum expected switching period and the minimum expected switching period;

[0068] Step S30, when the previous switching period is greater than the maximum expected switching period, controlling the corresponding current switching period of the switching device of the PFC circuit to reduce the number of troughs of the inductor current discontinuous time, where when the number of troughs of the inductor current discontinuous time is one, the PFC circuit enters the CRM mode, and when the number of troughs of the inductor current discontinuous time is greater than one, the PFC circuit enters the DCM mode;

[0069] Step S40, when the previous switching period is less than the minimum expected switching period, controlling the corresponding current switching period of the switching device of the PFC circuit to increase the number of troughs of the inductor current discontinuous time.

[0070] Specifically, in the embodiment of the present invention, the PFC circuit is set to a multi-mode operating state, and the multi-mode operating state includes a discontinuous conduction mode (DCM) and a critical conduction mode (CRM), avoiding the PFC circuit switching frequency being too high caused by a single operating mode.

[0071] In the embodiment of the present invention, when the number of troughs is one, the PFC circuit is set to the CRM operating mode; when the number of troughs is greater than one, the PFC circuit is set to the DCM operating mode.

[0072] Execute step S10 to obtain the maximum expected switching period T ref_sub and the minimum expected switching period T ref_add , where the maximum expected switching period T ref_sub is greater than the minimum expected switching period T ref_add .

[0073] In the embodiment of the present invention, based on the basic conduction time of the switching device of the PFC circuit, the maximum expected switching period T ref_sub and the minimum expected switching period T ref_add are obtained by calculation, and the maximum expected switching period T ref_sub and the minimum expected switching period Tref_add The steps include:

[0074] Step S11, obtaining the basic conduction time T of the PFC circuit switching device on_base ;

[0075] In the embodiments of the present invention, based on the bus voltage value V bus , the bus voltage reference value V bus_ref the basic conduction time T of the PFC circuit switching device is obtained through calculation on_base .

[0076] In the embodiments of the present invention, as Figure 5 shown, the steps of obtaining the basic conduction time T of the PFC circuit switching device on_base include:

[0077] Step S111, obtaining the bus voltage value V bus , the bus voltage reference value V bus_ref , based on the bus voltage value V bus , the bus voltage reference value V bus_ref performing voltage loop calculation to obtain the compensation amount u t ;

[0078] In the embodiments of the present invention, the bus voltage value V bus is the output voltage of the PFC circuit; the bus voltage reference value V bus_ref is the output target voltage of the PFC circuit.

[0079] In the embodiments of the present invention, the method of the voltage loop calculation includes one of a PI (Proportional Integral) controller and a PID (Proportional Integral Derivative) controller.

[0080] In other embodiments, the method of the voltage loop calculation adopts other suitable calculation methods.

[0081] Step S112, obtaining the input voltage peak value V of the PFC circuit acpk , based on the input voltage peak value V acpk , the compensation amount u t normalizing the compensation amount u t , obtaining the normalized compensation amount to eliminate the influence of the input voltage fluctuation of the PFC circuit on the compensation amount u t ;

[0082] Adopting the normalized compensation amount to ensure that the compensation amount u t is not affected by the input voltage fluctuation of the PFC circuit, thereby improving the stability and accuracy of the system.

[0083] In an embodiment of the present invention, based on the peak value V of the input voltage acpk and the compensation amount u t , the expression for obtaining the normalized compensation amount u' t is: the compensation amount u t is divided by the square of the peak value V of the input voltage acpk , that is: u' t =u t / V 2 acpk , where u' t is the normalized compensation amount, u t is the compensation amount, and V acpk is the peak value of the input voltage.

[0084] Step S113: Multiply the normalized compensation amount by the coefficient K to obtain the basic conduction time T of the switching device of the PFC circuit on_base , where K is a constant.

[0085] The coefficient K is used to eliminate the influence of proportional conversion such as the sampling circuit ratio and digital quantization.

[0086] Step S12: Obtain the bus voltage value V bus , the instantaneous value V of the input voltage ac , and based on the basic conduction time T of the switching device of the PFC circuit on_base , the bus voltage value V bus , and the instantaneous value V of the input voltage ac , obtain the maximum expected switching period T ref_sub and the minimum expected switching period T ref_add .

[0087] In an embodiment of the present invention, as Figure 6 shown, the steps of calculating the maximum expected switching period T ref_sub and the minimum expected switching period T ref_add include:

[0088] Step S121: Obtain the bus voltage value V bus , the instantaneous value V of the input voltage ac , and based on the basic conduction time T of the switching device of the PFC circuit on_base , and the inductor energy relationship, obtain the real-time switching period T of the PFC circuit in the CRM mode CRM ;

[0089] In an embodiment of the present invention, the expression for obtaining the real-time switching period T of the PFC circuit in the CRM mode CRM is:

[0090] ,

[0091] ,

[0092] wherein, V ac is the instantaneous value of the input voltage, V bus is the bus voltage value, T on_base is the basic conduction time of the switching device of the PFC circuit, T dem is the inductor demagnetization time, T CRM is the real-time switching period of the PFC circuit in the CRM mode.

[0093] As Figure 2 shown, when the PFC circuit adopts a fixed CRM mode, the switching frequency of the switching device of the PFC circuit increases as the instantaneous value of the input voltage decreases, that is, the real-time switching period T CRM decreases. In order to reduce the switching frequency of the switching device of the PFC circuit, the time of the switching period needs to be increased. When the input voltage is small, by increasing the time of the switching period, the switching frequency of the switching device of the PFC circuit is reduced. Therefore, based on the inverse ratio of the instantaneous value of the input voltage to the switching period, as the basis for calculating the maximum expected switching period T ref_sub and the minimum expected switching period T ref_add , adjusting the number of troughs of the inductor current discontinuous time realizes the purpose of reducing the switching frequency of the switching device of the PFC circuit when the instantaneous value of the input voltage decreases in a power frequency half-wave.

[0094] Step S122, establish the inverse ratio relationship between the minimum expected switching period T CRM and the real-time switching period T ref_add of the PFC circuit in the CRM mode, and obtain the minimum expected switching period T CRM . ref_add .

[0095] Since the minimum expected switching period T ref_add , the maximum expected switching period T ref_sub and the real-time switching period T CRM of the PFC circuit in the CRM mode are inversely proportional, therefore, by establishing the inverse ratio relationship between the minimum expected switching period T ref_add and the real-time switching period T CRM of the PFC circuit in the CRM mode, the reduction of the switching frequency of the switching device of the PFC circuit is realized.

[0096] In the embodiment of the present invention, as Figure 7 shown, establish the minimum expected switching period Tref_add and the real-time switching period T of the PFC circuit in the CRM mode CRM The expression of the inverse proportional relationship is as follows:

[0097] , T ref_add ≥T ref_min ,

[0098] where k is a negative number, b is a positive number, and T ref_min is the minimum allowable switching period of the system.

[0099] In the embodiment of the present invention, the value of b is 1.5 times, 2 times, 2.5 times or other suitable values of the minimum expected switching frequency of the system. The value range of the minimum expected switching frequency of the system is 22 kHz to 25 kHz to avoid audible noise that can be heard by the human ear;

[0100] The value of the constant k is -0.8, -1, -1.5 or other suitable values. Among them, when the absolute value of k is relatively large, as Figure 4b shown, the bending slope change of the minimum expected switching period T ref_add is relatively large, so that the switching frequency f of the switching device Q of the PFC circuit drops relatively fast. When the absolute value of k is relatively small, as Figure 4a shown, the bending slope change of the minimum expected switching period T ref_add is relatively small, so that the switching frequency f of the switching device Q of the PFC circuit drops relatively slowly;

[0101] The minimum allowable switching period T of the system ref_min is the highest frequency allowed by the system. The minimum expected switching period T ref_min is limited by the minimum allowable switching period T of the system (i.e., the highest frequency allowed by the system) for the minimum expected switching period T ref_add .

[0102] In other embodiments, the expression of the inverse proportional relationship between the minimum expected switching period and the real-time switching period of the PFC circuit in the CRM mode can be set according to actual requirements.

[0103] Step S123, obtain the first offset ΔT ref , and based on the first offset ΔT ref , the minimum expected switching period T ref_add , add the minimum expected switching period T ref_add and the first offset ΔT ref to obtain the maximum expected switching period T ref_sub .

[0104] In an embodiment of the present invention, the maximum expected switching period T is obtained. ref_sub The expression is:

[0105] ,

[0106] Among them, T ref_sub is the maximum expected switching period, T ref_add is the minimum expected switching period, ΔT ref is the first offset.

[0107] In the embodiment of the present invention, the first offset ΔT ref It can be 1.5us, 2us, 2.5us or other suitable values.

[0108] In the embodiment of the present invention, Figure 7 As shown, the minimum desired switching period T established ref_add and the real-time switching cycle T of the PFC circuit in the CRM mode CRM The inverse relationship between ) where k is a negative number. The larger the absolute value of k, the corresponding Figure 8 As shown, the minimum expected switching period T ref_add and the maximum expected switching period T ref_sub The higher the slope of the curve, the faster and more the number of valleys is inserted, and the faster the switching frequency of the PFC circuit switch device decreases, thereby achieving a decrease in the switching frequency of the PFC circuit switch device, achieving the purpose of regulating the fluctuation range of the PFC circuit switch device, and improving the system working efficiency. Among them, T ref is the current expected switching cycle.

[0109] The present invention sets the PFC circuit to a combined working mode of CRM and DCM within a power frequency sine half wave, obtains the maximum expected switching cycle and the minimum expected switching cycle, compares the previous switching cycle corresponding to the PFC circuit switch device with the maximum expected switching cycle and the minimum expected switching cycle, and adjusts the time of the current switching cycle corresponding to the PFC circuit switch device by increasing or decreasing the number of valleys of the inductor current discontinuous time, thereby regulating the fluctuation range of the switching frequency and reducing the maximum switching frequency f of the PFC circuit switch device Q, thereby solving the problem of Figure 2 The original input voltage V ac The waveform decreases, and the switching frequency f waveform of the PFC circuit switching device Q will rise (especially when the input voltage V ac The switching frequency is close to 0V, that is, the switching frequency is high, such as Figures 4a - 4bAs shown, the present invention adjusts the number of troughs continuously, so that the switching frequency of the switching device of the FC circuit decreases when it rises (is higher), thereby reducing the switching loss of the system and improving the working efficiency of the system. Taking the example that in the embodiment of the present invention, within one power frequency sine half-wave, the switching frequency of the switching device of the PFC circuit bends downward as the input voltage decreases.

[0110] In practical applications, as Figure 9 shown, when the instantaneous value V of the input voltage ac rises continuously, that is, when the slope of the input voltage is positive, the current switching period T decreases continuously, the number of troughs of the PFC circuit shows a continuous decreasing trend, and the frequency of the switching device of the PFC circuit increases. At this time, the maximum expected switching period T ref_sub is the main control line; when the instantaneous value V of the input voltage ac decreases continuously, that is, when the slope of the input voltage is negative, the current switching period T increases continuously, the number of troughs of the system shows a continuous increasing trend, and the frequency of the switching device of the PFC circuit decreases. At this time, the minimum expected switching period T ref_add is the main control line. The inventor found that as the slope of the input voltage changes, the switching frequency of the switching device of the PFC circuit will show an asymmetric state, resulting in the asymmetry of the inductor current, making the THD performance worse. Moreover, this state of inductor current asymmetry deteriorates further as the first offset ΔT ref increases. In order to improve the symmetry of the inductor current waveform, it is necessary to further adjust the minimum expected switching period T ref_add and the maximum expected switching period T ref_sub as the slope of the input voltage changes.

[0111] In the embodiment of the present invention, it further includes further adjusting the minimum expected switching period T ref_add and the maximum expected switching period T ref_sub , and the steps of further adjusting the minimum expected switching period T ref_add and the maximum expected switching period T ref_sub include:

[0112] Obtain the slope of the input voltage Slope V ac and the second offset ΔT ref_bias ,

[0113] Based on the slope of the input voltage Slope V ac and the second offset ΔT ref_bias regulate the maximum expected switching period T ref_sub and the minimum expected switching period T ref_add, the second minimum expected switching period and the second maximum expected switching period are obtained, where the second minimum expected switching period is used as the minimum expected switching period of the switching device, and the second maximum expected switching period is used as the maximum expected switching period of the switching device.

[0114] In an embodiment of the present invention, as Figure 10 shown, when the input voltage slope Slope V ac is less than 0, the minimum expected switching period T ref_add and the maximum expected switching period T ref_sub are both superimposed with the second offset ΔT ref_bias to obtain the second minimum expected switching period and the second maximum expected switching period, which are respectively used as the minimum expected switching period T ref_add of the switching device and the maximum expected switching period T ref_sub of the switching device, where T is the current switching period.

[0115] In an embodiment of the present invention, the value of the second offset ΔT ref_bias is one half of the value of the first offset ΔT ref .

[0116] In other embodiments, the value of the second offset ΔT ref_bias is determined according to the situation.

[0117] By further regulating the maximum expected switching period T ref_sub and the minimum expected switching period T ref_add , the system control is prevented from switching back and forth, and at the same time, the symmetry of the waveform is improved, so that the system obtains better THD performance.

[0118] In an embodiment of the present invention, the input voltage slope Slope V ac is obtained based on the half-wave after input rectification.

[0119] Execute step S20 to obtain the previous switching period of the next PFC circuit and the number of wave troughs of the discontinuous time of the inductor current in the previous switching period, and compare the previous switching period with the maximum expected switching period T ref_sub and the minimum expected switching period T ref_add .

[0120] In an embodiment of the present invention, a timer is used to measure the time of the previous switching period. In other embodiments, a counter or other method is used to measure the time of the previous switching period.

[0121] In an embodiment of the present invention, in the DCM mode, there are at least two troughs in each switching cycle. In a switching cycle, the position where the drain-source voltage V of the switching device of the PFC circuit reaches the lowest point is a trough, and one low point is recorded as one trough. DS The voltage waveform of reaches the lowest point is a trough, and one low point is recorded as one trough.

[0122] In an embodiment of the present invention, the number of troughs is determined by detecting the waveform of the drain-source voltage V of the switching device of the PFC circuit or by detecting the zero-crossing point ZCD of the auxiliary winding, and the switching device of the PFC circuit is a MOS transistor. DS The number of troughs is determined by detecting the waveform of the drain-source voltage V of the switching device of the PFC circuit or by detecting the zero-crossing point ZCD of the auxiliary winding, and the switching device of the PFC circuit is a MOS transistor.

[0123] Execute step S30. When the previous switching cycle is greater than the maximum expected switching cycle T ref_sub control the number of troughs of the inductor current discontinuous time in the current switching cycle corresponding to the switching device of the PFC circuit to be reduced. Among them, when the number of troughs of the inductor current discontinuous time is one, the PFC circuit enters the CRM mode, and when the number of troughs of the inductor current discontinuous time is greater than one, the PFC circuit enters the DCM mode.

[0124] In an embodiment of the present invention, by reducing the number of troughs of the inductor current discontinuous time in the current switching cycle, the time of the current switching cycle T becomes shorter, so that the switching cycle returns to the expected range. Correspondingly, within the same total time, the number of switching times of the PFC circuit is increased, thereby increasing the switching frequency of the switching device.

[0125] In an embodiment of the present invention, the number of troughs of the inductor current discontinuous time is reduced by one each time, so that the switching cycle returns to the expected range. In other embodiments, the number of troughs of the inductor current discontinuous time is reduced by two or other suitable numbers of troughs each time.

[0126] Execute step S40. When the previous switching cycle is less than the minimum expected switching cycle T ref_add control the number of troughs of the inductor current discontinuous time in the current switching cycle corresponding to the switching device of the PFC circuit to be increased.

[0127] In an embodiment of the present invention, by increasing the number of troughs of the inductor current discontinuous time in the current switching cycle, the time of the current switching cycle becomes longer, so that the switching cycle returns to the expected range. Correspondingly, within the same total time, the number of switching times of the PFC circuit is reduced, thereby reducing the switching frequency of the switching device.

[0128] In an embodiment of the present invention, the number of troughs of the inductor current discontinuous time is increased by one each time in the current switching cycle. In other embodiments, the number of troughs of the inductor current discontinuous time is increased by two or other suitable numbers of troughs each time in the current switching cycle.

[0129] By reducing the number of troughs of the inductor current discontinuous time in the current switching cycle, reducing the time of the current switching cycle, and increasing the switching frequency of the corresponding switching cycle; increasing the number of troughs of the discontinuous time in the current switching cycle, increasing the time of the current switching cycle, and reducing the switching frequency of the corresponding switching cycle, when the instantaneous value of the input voltage is small, that is, when the input instantaneous power is small, the corresponding switching frequency is reduced, thereby reducing the switching loss, and realizing the regulation of the fluctuation range of the switching frequency of the PFC circuit switching device, and improving the working efficiency of the PFC circuit.

[0130] In an embodiment of the present invention, as Figure 8 shown, based on the maximum switching frequency allowed by the system, the minimum value T of the minimum expected switching cycle is correspondingly obtained ref_min , and the minimum value T of the minimum expected switching cycle is used ref_min to limit the minimum expected switching cycle T ref_add to regulate the switching frequency of the PFC circuit switching device in the DCM mode to be less than or equal to the allowed maximum switching frequency, avoiding too low system frequency and generating audible noise for human ears.

[0131] In an embodiment of the present invention, when the number of troughs is one, the PFC circuit is set to the CRM working mode; when the number of troughs is greater than one, the PFC circuit is set to the DCM working mode.

[0132] Since, as Figure 11 shown, in the DCM mode of the PFC circuit, the inductor current will have an inductor current discontinuous phenomenon within one switching cycle, and this discontinuous characteristic will lead to higher harmonic distortion; at the same time, the current switching cycle corresponding to the PFC circuit switching device is based on the maximum expected switching cycle T ref_sub and the minimum expected switching cycle T ref_add to continuously adjust the number of troughs of the inductor current within each switching cycle, that is, when the troughs are switched, the current waveform will also be distorted, resulting in an increase in THD. Therefore, when the troughs are switched, it is necessary to adjust the conduction time of the current switching cycle of the PFC circuit switching device to enhance the THD performance of the system, where T off is the inductor current discontinuous time after adding or subtracting 1 trough in the previous switching cycle.

[0133] Therefore, in an embodiment of the present invention, the control method of the PFC circuit further includes pre-compensating the conduction time of the PFC circuit switching device at the trough switching moment to obtain the current switching cycle conduction time T on of the PFC circuit switching device.

[0134] In an embodiment of the present invention, as Figure 12As shown, the steps of obtaining the on-time of the current switching cycle of the PFC circuit switching device include:

[0135] Step S51, obtaining the previous switching cycle T corresponding to the lower PFC circuit switching device sw , the total time T of the previous switching cycle inductor excitation and demagnetization of the PFC circuit power , the trough period T of the discontinuous time of the PFC circuit inductor current zcd , the basic on-time T of the PFC circuit switching device on_base ;

[0136] Step S52, calculating the on-time T of the current switching cycle of the PFC circuit switching device based on the number of troughs of the discontinuous time of the inductor current reduced or increased in the current switching cycle on .

[0137] In the embodiment of the present invention, as Figure 13 shown, the steps of obtaining the trough period T of the discontinuous time of the PFC circuit inductor current include: zcd

[0138] Detecting the trough point to obtain the trough point signal ZCD;

[0139] Detecting the trough period, and taking the time interval between two adjacent trough point signals ZCD as the trough period T of the discontinuous time of the PFC circuit inductor current zcd .

[0140] In the embodiment of the present invention, when the drain-source voltage V of the PFC circuit switching device DS reaches the lowest point each time, a trough point signal ZCD is generated.

[0141] In the embodiment of the present invention, an auxiliary winding is added to the inductor of the PFC circuit, the induced voltage generated by the auxiliary winding is detected, and a trough point signal ZCD is generated when the drain-source voltage V of the PFC circuit switching device DS reaches the lowest point; or directly measuring the drain-source voltage V of the PFC circuit switching device DS , and generating a trough point signal ZCD when it reaches the lowest point.

[0142] In the embodiment of the present invention, obtaining the zero-crossing voltage signal and recording the time interval between two adjacent zero-crossing voltage signals as the trough period T of the discontinuous time of the PFC circuit inductor current zcd , and selecting the time interval between the second trough point signal and the third trough point signal as the trough period T of the discontinuous time of the PFC circuit inductor current zcd to reduce the possibility of false detection.

[0143] In the embodiment of the present invention, calculating the on-time T of the current switching cycle of the switching deviceon The steps include:

[0144] When the number of valleys of the inductor current increases in the current switching cycle of the PFC circuit switching device, increase the conduction time of the switching device;

[0145] When the number of valleys of the inductor current decreases in the current switching cycle of the PFC circuit switching device, decrease the conduction time of the switching device.

[0146] In the embodiment of the present invention, when the number of valleys of the current switching cycle increasing the discontinuous time is one, calculate the current switching cycle conduction time T of the PFC circuit switching device on The expression is:

[0147] ,

[0148] where, T on is the current switching cycle conduction time of the PFC circuit switching device, T on_base is the basic conduction time of the PFC circuit switching device, T sw is the previous switching cycle corresponding to the PFC circuit switching device, T power is the total time of inductor excitation and demagnetization in the previous switching cycle of the PFC circuit, T zcd is the valley period of the discontinuous inductor current in the PFC circuit;

[0149] When the number of valleys of the current switching cycle decreasing the discontinuous time is one, calculate the current switching cycle conduction time T of the PFC circuit switching device on The expression is:

[0150] ,

[0151] where, T on is the current switching cycle conduction time of the PFC circuit switching device, T on_base is the basic conduction time of the PFC circuit switching device, T sw is the previous switching cycle corresponding to the PFC circuit switching device, T power is the total time of inductor excitation and demagnetization in the previous switching cycle of the PFC circuit, T zcd is the valley period of the discontinuous inductor current in the PFC circuit.

[0152] In other embodiments, calculate the current switching cycle conduction time of the PFC circuit switching device according to actual requirements.

[0153] The present invention also provides a PFC circuit controller, including the above-mentioned control method of a PFC circuit, including:

[0154] A sampling unit for obtaining the instantaneous value Vac of the input voltage and the bus voltage value V bus and the reference value V of the bus voltage bus_ref ;

[0155] An acquisition unit for obtaining the maximum expected switching period and the minimum expected switching period, where the maximum expected switching period is greater than the minimum expected switching period, and the maximum expected switching period and the minimum expected switching period are obtained based on the basic conduction time of the switching device of the PFC circuit; obtaining the previous switching period of the PFC circuit in the DCM mode and the number of troughs of the inductor current discontinuous time in the previous switching period;

[0156] A comparison and adjustment unit for comparing the size of the previous switching period with the maximum expected switching period and the minimum expected switching period according to the information obtained by the acquisition unit; when the previous switching period is greater than the maximum expected switching period, controlling the current switching period of the switching device of the PFC circuit to reduce the number of troughs of the inductor current discontinuous time, where when the number of troughs of the inductor current discontinuous time is one, the PFC circuit enters the CRM mode, and when the number of troughs of the inductor current discontinuous time is greater than one, the PFC circuit enters the DCM mode; when the previous switching period is less than the minimum expected switching period, controlling the current switching period of the switching device of the PFC circuit to increase the number of troughs of the inductor current discontinuous time.

[0157] In an embodiment of the present invention, the PFC circuit controller further includes:

[0158] A conduction time adjustment unit for pre-compensating the conduction time of the switching device of the PFC circuit at the trough switching moment to obtain the current switching period conduction time of the switching device of the PFC circuit.

[0159] The present invention also provides a chip including a PFC circuit controller as described above.

[0160] Specifically, the functions of each pin of the chip are:

[0161] ZCD: Trough detection, obtaining the trough point and obtaining the trough point signal;

[0162] VAC: Obtaining the input voltage sampling value, and the input voltage sampling value is used as the instantaneous value of the input voltage;

[0163] VBUS: Obtaining the bus voltage value.

[0164] The control chip U receives the signals required in implementing the control method of the present application according to the above pins and controls the PFC circuit accordingly.

[0165] The present invention also provides a circuit, such as Figure 14As shown, it includes a PFC circuit and a PFC circuit controller as described above;

[0166] One end of the first capacitor C1 is connected to one end of the first inductor L1 and one end of the input voltage. The other end of the first capacitor C1 is connected to one end of the second inductor L2 and the other end of the input voltage V ac The other end. One end of the second capacitor C2 is connected to the anode of the first diode D1, the cathode of the fourth diode D4, the anode of the sixth diode D6, and the other end of the first inductor L1. The other end of the second capacitor C2 is connected to the anode of the third diode D3, the cathode of the second diode D2, the anode of the seventh diode D7, and the other end of the second inductor L2. The cathode of the first diode D1 is connected to the cathode of the third diode D3, the first end of the common-mode inductor L, and one end of the third capacitor C3. The third end of the common-mode inductor L is connected to the drain of the switching device Q and the anode of the fifth diode D5. The cathode of the fifth diode D5 is connected to one end of the fourth capacitor C4, one end of the resistor R load One end. The anode of the fourth diode D4 is connected to the anode of the second diode D2, the other end of the third capacitor C3, one end of the resistor R cs One end, the other end of the fourth capacitor C4, one end of the resistor R load The other end, one end of the second resistor R2, and the ground. The other end of the first resistor R1 is connected to the other end of the second resistor R2 and the VBU interface of the PFC circuit controller. One end of the resistor R cs The other end is connected to the source of the switching device Q and the VCS interface of the PFC circuit controller. The cathode of the seventh diode is connected to the cathode of the sixth diode and one end of the resistor R ac1 One end. The other end of the resistor R ac1 The other end is connected to one end of the resistor R ac2 One end and is connected to the VAC interface of the PFC circuit controller; One end of the resistor R ac2 The other end is grounded. The gate of the switching device Q is connected to the Q interface of the PFC circuit controller. The second end of the common-mode inductor L is connected to one end of the resistor R zcd1 One end. The fourth end of the common-mode inductor L is grounded. The other end of the resistor R zcd1 The other end is connected to one end of the resistor R zcd2 One end and the ZCD interface of the PFC circuit controller. The other end of the resistor R zcd2 The other end is grounded.

[0167] The technical features of the above embodiments can be combined arbitrarily. For the sake of concise description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0168] It should be understood that for those of ordinary skill in the art, improvements or changes can be made according to the above description, and all such improvements and changes should fall within the protection scope of the appended claims of this application.

Claims

1. A control method for a PFC circuit, characterized in that Including: Obtaining a maximum expected switching period and a minimum expected switching period based on the basic conduction time of the switching device of the PFC circuit, where the maximum expected switching period is greater than the minimum expected switching period; Obtaining the previous switching period of the PFC circuit and the number of troughs of the inductor current discontinuous time in the previous switching period, and comparing the size of the previous switching period with the maximum expected switching period and the minimum expected switching period; When the previous switching period is greater than the maximum expected switching period, controlling the current switching period of the switching device of the PFC circuit to reduce the number of troughs of the inductor current discontinuous time. Among them, when the number of troughs of the inductor current discontinuous time is one, the PFC circuit enters the CRM mode. When the number of troughs of the inductor current discontinuous time is greater than one, the PFC circuit enters the DCM mode; When the previous switching period is less than the minimum expected switching period, controlling the current switching period of the switching device of the PFC circuit to increase the number of troughs of the inductor current discontinuous time; wherein, the step of obtaining the maximum expected switching period T ref_sub and the minimum expected switching period T ref_add comprises: Obtaining the basic conduction time of the switching device of the PFC circuit; Obtaining the bus voltage value and the instantaneous input voltage value, and obtaining the real-time switching period of the PFC circuit in the CRM mode based on the basic conduction time of the switching device of the PFC circuit, the bus voltage value, and the instantaneous input voltage value. The expression of the real-time switching period of the PFC circuit in the CRM mode is: ， ， Among them, V ac is the instantaneous value of the input voltage, V bus is the bus voltage value, T on_base is the basic conduction time of the PFC circuit switching device, T dem is the inductor demagnetization time, T CRM is the real-time switching period of the PFC circuit in CRM mode; Establishing an inverse relationship between the minimum expected switching period and the real-time switching period of the PFC circuit in the CRM mode based on the real-time switching period of the PFC circuit in the CRM mode, and obtaining the minimum expected switching period; Obtaining a first offset, and adding the minimum expected switching period and the first offset based on the first offset and the minimum expected switching period to obtain the maximum expected switching period.

2. The control method of the PFC circuit according to claim 1, characterized in that It further includes further adjusting the minimum expected switching period and the maximum expected switching period. Among them, when the slope of the input voltage is less than 0, adding a second offset to both the minimum expected switching period and the maximum expected switching period to obtain a second minimum expected switching period and a second maximum expected switching period, which are respectively used as the minimum expected switching period of the switching device of the PFC circuit and the maximum expected switching period of the switching device.

3. The control method of the PFC circuit according to claim 1, characterized in that, It further includes pre-compensating the conduction time of the switching device of the PFC circuit at the trough switching moment to obtain the switching period conduction time of the switching device of the PFC circuit. The step of obtaining the current switching period conduction time of the switching device of the PFC circuit includes: Obtaining the previous switching period corresponding to the switching device of the PFC circuit, the total time of inductor excitation and demagnetization in the previous switching period of the PFC circuit, the trough period of the inductor current discontinuous time of the PFC circuit, and the basic conduction time of the switching device of the PFC circuit; Calculating the current switching period conduction time of the switching device of the PFC circuit based on the number of troughs of the inductor current discontinuous time reduced or increased in the current switching period.

4. The control method of the PFC circuit according to claim 3, wherein When the number of troughs of the discontinuous time reduced in the current switching period is one, the expression for calculating the current switching period conduction time of the switching device of the PFC circuit is: ， Among them, T on is the current on-time of the switching device in the PFC circuit during the current switching cycle, T on_base is the basic on-time of the switching device in the PFC circuit, T sw is the previous switching cycle corresponding to the switching device in the PFC circuit, T power is the total time of inductor magnetization and demagnetization during the previous switching cycle of the PFC circuit, T zcd is the trough period of the discontinuous time of the inductor current in the PFC circuit; When the number of valleys of the discontinuous time in the current switching period is one, the expression for calculating the conduction time of the switching device of the PFC circuit in the current switching period is as follows: ， Wherein, T on is the current switching cycle conduction time of the PFC circuit switching device, T on_base is the basic conduction time of the PFC circuit switching device, T sw is the previous switching cycle corresponding to the PFC circuit switching device, T power is the total time of inductor magnetization and demagnetization in the previous switching cycle of the PFC circuit, T zcd is the trough period of the inductor current discontinuous time of the PFC circuit.

5. A PFC circuit controller adopting the PFC circuit control method described in any one of claims 1 to 4, characterized in that, It includes: An acquisition unit, configured to acquire a maximum expected switching period and a minimum expected switching period, where the maximum expected switching period is greater than the minimum expected switching period, and the maximum expected switching period and the minimum expected switching period are obtained based on the basic conduction time of the switching device of the PFC circuit; acquire the previous switching period of the PFC circuit and the number of valleys of the discontinuous time of the inductor current in the previous switching period; A comparison and adjustment unit, configured to compare the magnitude of the previous switching period with the maximum expected switching period and the minimum expected switching period according to the information acquired by the acquisition unit; when the previous switching period is greater than the maximum expected switching period, control the corresponding current switching period of the switching device of the PFC circuit to reduce the number of valleys of the discontinuous time of the inductor current, where when the number of valleys of the discontinuous time of the inductor current is one, the PFC circuit enters the CRM mode, and when the number of valleys of the discontinuous time of the inductor current is greater than one, the PFC circuit enters the DCM mode; when the previous switching period is less than the minimum expected switching period, control the corresponding current switching period of the switching device of the PFC circuit to increase the number of valleys of the discontinuous time of the inductor current.

6. A PFC circuit controller according to claim 5, characterized in that, It further includes: A conduction time adjustment unit, which pre-compensates the conduction time of the switching device of the PFC circuit at the valley switching moment to obtain the conduction time of the switching device of the PFC circuit in the current switching period.

7. A chip, characterized in that, It includes a PFC circuit controller as described in claim 5.

8. A circuit, characterized in that, It includes a PFC circuit and a PFC circuit controller as described in claim 5.

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