Reverse BUCK driving power supply circuit
Through the driving power supply circuit of reverse BUCK, combined with the half-bridge circuit and the reverse BUCK circuit, the ground voltage is controlled by using the PWM control signal, which solves the complexity and large loss of power supply of the driver chip of the high-voltage DC-DC power module, and realizes an efficient and simple power supply circuit design.
Patent Information
- Application Number
- CN202411923720.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-25
- Publication Date
- 2025-04-29
AI Technical Summary
The driver chip power supply of existing high-voltage DC-DC power modules is difficult to effectively solve, especially when no additional isolation and bucking circuit is added, resulting in complex circuits, large space and large losses.
The driving power supply circuit of reverse BUCK is adopted, and the voltage of the ground is controlled by combining the half-bridge circuit and the reverse BUCK circuit by using the PWM control signal of the reverse BUCK circuit to replace the complex isolation and buck power supply circuit, reducing the number of components and circuit complexity.
It realizes rapid power supply to the driver chip without adding additional isolation and buck circuits, reduces the product's area of printed board, reduces the number of components and circuit complexity, improves power efficiency and saves costs.
Smart Images
Figure CN119906262A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of electronic technology, and in particular to a reverse BUCK driving power supply circuit. Background Art
[0002] With the continuous development of power electronics technology, the performance requirements for power supply technology are getting higher and higher, and switching power supplies are also developing towards miniaturization, low switching loss, high efficiency, low cost, etc. To achieve performance improvements in these aspects, a major way is to reduce the number of components and improve the utilization of components.
[0003] At present, the main control chip of the high-voltage DC-DC power module is not enough to stably drive the MOS tube to open and close, and a driver chip needs to be added to ensure the stable operation of the power module. However, the power supply of the driver chip has become a problem. Since the power supply voltage required by various circuits is different, most driver power supplies use isolation and step-down methods. This method not only has a complex circuit structure, uses more components, and occupies a larger space, but also generates a lot of losses in the process of reducing high voltage to low voltage. Summary of the invention
[0004] The purpose of the present invention is to provide a reverse BUCK driving power supply circuit to solve the power supply problem of the driving chip without adding an additional isolation step-down circuit, thereby reducing the design complexity of the driving power supply, reducing costs, saving space, and reducing losses.
[0005] In order to achieve the above object, the technical solution adopted by the present invention includes:
[0006] A reverse BUCK driving power supply circuit comprises a half-bridge circuit, a reverse BUCK circuit and a driving chip power supply circuit; wherein the input power supply is connected to the half-bridge circuit, the output end of the reverse BUCK circuit is respectively connected to the input end of the driving chip power supply circuit and the first input end of the half-bridge circuit, and the second input end and the third input end of the half-bridge circuit are both connected to the output end of the driving chip power supply circuit.
[0007] Further, the half-bridge circuit includes a resistor R1, a resistor R5, a resistor R6, a resistor R10, a resistor R15, a resistor R17, a resistor R20, a junction field effect transistor Q1, a junction field effect transistor Q2, a junction field effect transistor Q3, a junction field effect transistor Q5, a junction field effect transistor Q7, a junction field effect transistor Q9, a diode D1, a transformer B1, an inductor L1, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C6, a capacitor C9, a capacitor C10, a capacitor C12, a capacitor C17, a capacitor C21, a capacitor C22, an integrated circuit IC1, an integrated circuit IC2 and an integrated circuit IC3; wherein:
[0008] The 7th pin of the integrated circuit IC2 is connected to the 4th pin of the integrated circuit IC2 and one end of the capacitor C10, and the input voltage 5V is connected together; the 1st pin of the integrated circuit IC2 is connected to the input ground VI- and the other end of the capacitor C10; the 2nd pin of the integrated circuit IC2 is connected to the drive signal PUSH node; the 3rd pin of the integrated circuit IC2 is connected to the drive signal PULL node; the 6th pin of the integrated circuit IC2 is connected to one end of the resistor R17 and one end of the capacitor C22; the 5th pin of the integrated circuit IC2 is connected to the other end of the resistor R17, the other end of the capacitor C22, and the input ground VI-; the 8th pin of the integrated circuit IC2 is connected to one end of the capacitor C21, the source of the junction field effect transistor Q9, one end of the capacitor C6, and one end of the resistor R20, and the connection point is connected to the output end of the reverse BUCK circuit as the first input end of the half-bridge circuit; the 9th pin of the integrated circuit IC2 is connected to the other end of the resistor R20 and the gate of the junction field effect transistor Q9; the 10th pin of the integrated circuit IC2 is connected to the The other end of capacitor C21 is connected, and the connection point is connected to the power supply node of the driver chip power supply circuit as the second input end of the half-bridge circuit; the 12th pin of the integrated circuit IC2 is connected to one end of the capacitor C9, one end of the resistor R6, the source of the junction field effect transistor Q2, the drain of the junction field effect transistor Q9, and the 2nd pin of the transformer B1; the 13th pin of the integrated circuit IC2 is connected to the other end of the resistor R6 and the gate of the junction field effect transistor Q2; the 14th pin of the integrated circuit IC2 is connected to the other end of the capacitor C9 and the cathode of the diode D1; the anode of the diode D1 is connected to the output end of the driver chip power supply circuit as the third input end of the half-bridge circuit; one end of the inductor L1 is connected to the input VIN+, and the other end of the inductor L1 is connected to one end of the capacitor C2, the drain of the junction field effect transistor Q2, the VI+ power supply input node, and one end of the capacitor C4; the other end of the capacitor C2 is connected to the input ground VI-; the 1st pin of the transformer B1 is connected to the other end of the capacitor C4 and the other end of the capacitor C6;
[0009] Pin 1 of the integrated circuit IC1 is connected to the secondary power supply node SVC3 and one end of the capacitor C1; Pin 6 of the integrated circuit IC1 is connected to the pin 5 of the integrated circuit IC3 and the input control signal PWM1 node; Pin 5 of the integrated circuit IC1 is connected to the pin 6 of the integrated circuit IC3 and the input control signal PWM2 node; Pin 3 of the integrated circuit IC1 is connected to the gate of the junction field effect transistor Q3 and one end of the resistor R5; Pin 4 of the integrated circuit IC1 is connected to the other end of the resistor R5, one end of the capacitor C3, the drain of the junction field effect transistor Q1, the source of the junction field effect transistor Q3 and the pin 3 of the transformer B1; Pin 2 of the integrated circuit IC1 is connected to the other end of the capacitor C3; Pin 8 of the integrated circuit IC1 is connected to the gate of the junction field effect transistor Q1 and one end of the resistor R1; Pin 7 of the integrated circuit IC1 is connected to the other end of the resistor R1, the source of the junction field effect transistor Q1 and the secondary ground GND2; the other end of the capacitor C1, the integrated circuit IC1 The 9th pin of the integrated circuit is connected to the secondary ground GND2; the drain of the junction field effect transistor Q3 is connected to the drain of the junction field effect transistor Q5 and the VC8 node; the 3rd pin of the integrated circuit IC3 is connected to one end of the connection resistor R10 and the gate of the junction field effect transistor Q5; the 4th pin of the integrated circuit IC3 is connected to one end of the capacitor C12, the other end of the resistor R10, the source of the junction field effect transistor Q5, the drain of the junction field effect transistor Q7, and the 4th pin of the transformer B1; the 2nd pin of the integrated circuit IC3 is connected to the other end of the capacitor C12; the 8th pin of the integrated circuit IC3 is connected to one end of the resistor R15 and the gate of the junction field effect transistor Q7; the 7th pin of the integrated circuit IC3 is connected to the other end of the resistor R15, the source of the junction field effect transistor Q7, and the secondary ground GND2; the 1st pin of the integrated circuit IC3 is connected to the secondary chip power supply node SVC3 and one end of the capacitor C17; the 9th pin of the integrated circuit IC3 and the other end of the capacitor C17 are connected to the secondary ground GND2.
[0010] Further, the resistance of the resistor R1, the resistance of the resistor R5, the resistance of the resistor R10 and the resistance of the resistor R15 is 15KΩ, the resistance of the resistor R6 and the resistor R20 is 15KΩ, the resistance of the resistor R17 is 2KΩ, the capacitance of the capacitor C1 and the capacitor C17 is 4.7uF, the capacitance of the capacitor C2 is 330nF, the capacitance of the capacitor C3 and the capacitance of the capacitor C12 is 470nF, the capacitance of the capacitor C4 and the capacitor C6 is 4.7uF, the capacitance of the capacitor C9, the capacitor C10 and the capacitor C21 is 1uF, and the capacitance of the capacitor C The capacitance of 22 is 2.2nF, the inductance of inductor L1 is 0.47uH, the models of junction field effect transistor Q1, junction field effect transistor Q3, junction field effect transistor Q5 and junction field effect transistor Q7 are FDMS86300DC, the models of junction field effect transistor Q2 and junction field effect transistor Q9 are BSC320N20NS3G, the model of diode D1 is B16WS, the models of integrated circuit IC1 and integrated circuit IC3 are RMJ5101AD, and the model of integrated circuit IC2 is SI8233-AB-D-IM1.
[0011] Further, the reverse BUCK circuit includes a resistor R22, a transformer B2, a diode D3, a Schottky transistor D2, a junction field effect transistor Q10, a capacitor C24 and a capacitor C30; wherein the cathode of the Schottky transistor D2 is commonly connected to the VI+ power supply input node and one end of the capacitor C30; the anode of the Schottky transistor D2 is commonly connected to the drain of the junction field effect transistor Q10 and the 2nd pin of the transformer B2; the gate of the junction field effect transistor Q10 is connected to the input PWM signal; the source of the junction field effect transistor Q10 is connected to one end of the resistor R22 and the CS node; the other end of the resistor R22 is connected to the input ground VI-; the 1st pin of the transformer B2 is commonly connected to one end of the capacitor C24, the other end of the capacitor C30, and the 4th pin of the transformer B2, and the connection point is connected to the input end of the driver chip power supply circuit and the first input end of the half-bridge circuit as the output end of the reverse BUCK circuit; the 3rd pin of the transformer B2 is connected to the anode of the diode D3; the cathode of the diode D3 is commonly connected to the other end of the capacitor C24 and the node VDD0.
[0012] Furthermore, the resistance of the resistor R22 is 0.2R, the capacitance of the capacitor C24 and the capacitance of the capacitor C30 are 10uF / 35V, the inductance of the transformer B2 is 0.44uH, the model of the Schottky tube D2 is IDL06G65C5, the model of the diode D3 is B16WS, and the model of the junction field effect tube Q10 is IPL65R130C7.
[0013] Further, the chip power supply circuit includes a resistor R2, a resistor R3, a resistor R4, a resistor R12, a resistor R14, a junction field effect transistor Q4, a junction field effect transistor Q6, a junction field effect transistor Q8, a voltage regulator DZ1, a voltage regulator DZ2, a voltage regulator DZ3, a capacitor C8, a capacitor C14, a capacitor C16 and a capacitor C19; wherein one end of the resistor R2 is connected to the connection node VI+ and one end of the resistor R3; the other end of the resistor R3 is connected to one end of the resistor R4; the other end of the resistor R4 is connected to the drain of the junction field effect transistor Q6, one end of the capacitor C8, the cathode of the voltage regulator DZ1, and the gate of the junction field effect transistor Q4; the source of the junction field effect transistor Q6, the other end of the capacitor C8, and the anode of the voltage regulator DZ1 are connected to the output end of the reverse BUCK circuit; the source of the junction field effect transistor Q4 is connected to the junction field effect transistor Q6; the source of the junction field effect transistor Q4 is connected to the output end of the reverse BUCK circuit; the source of the junction field effect transistor Q4 is connected to the junction field effect transistor Q6; the source of the junction field effect transistor Q6 is connected to the output end of the reverse BUCK circuit; the source of the junction field effect transistor Q4 is connected to the junction field effect transistor Q6 ... The source of the junction transistor Q8 and one end of the capacitor C16 are connected together, and the connection point is connected to the second input end of the half-bridge circuit and the third input end of the half-bridge circuit as the power supply node of the driver chip circuit; the drain of the junction field effect transistor Q4 is connected to the other end of R2; the gate of the junction field effect transistor Q6 is connected to the anode of the voltage regulator tube DZ3 and one end of the resistor R12; the cathode of the voltage regulator tube DZ3 is connected to the node VDD0, one end of the capacitor C14, the drain of the junction field effect transistor Q8, and one end of the resistor R14; the gate of the junction field effect transistor Q8 is connected to the cathode of the voltage regulator tube DZ2, one end of the capacitor C19, and the other end of the resistor R14; the other end of the capacitor C16 is connected to the output end of the reverse BUCK circuit together with the anode of the voltage regulator tube DZ2, the other end of the capacitor C19, the other end of the capacitor C14, and the other end of the resistor R12.
[0014] Furthermore, the resistance of the resistor R2 is 300R, the resistance of the resistor R3 and the resistor R4 is 240KΩ, the resistance of the resistor R12 is 100KΩ, the resistance of the resistor R14 is 5.1KΩ, the capacitance of the capacitor C8 is 100nF, the capacitance of the capacitor C14 and the capacitor C16 is 10uF / 35V, the capacitance of the capacitor C19 is 10nF, the model of the junction field effect transistor Q4 is LG65N280J, the model of the junction field effect transistor Q6 is 2N7002KW, the model of the junction field effect transistor Q8 is JRZ10N018L, the model of the Zener diode DZ1 is MM3Z13VT1G, the model of the Zener diode DZ2 is MM3Z12VT1G, and the model of the Zener diode DZ3 is MM3Z12VT1G.
[0015] Compared with the prior art, the present invention has the following technical effects:
[0016] (1) By connecting the output end of the reverse buck circuit to the signal ground of the driving power supply, the voltage of the ground line is controlled by the PWM control signal of the reverse buck circuit, thereby reducing the voltage difference between the two ends of the Zener diode DZ1 and the Zener diode DZ2, reducing the power loss of the Zener diode DZ1 and the Zener diode DZ2, and improving the power supply efficiency.
[0017] (2) The half-bridge circuit uses four MOS tubes Q1, Q3, Q5, and Q7 to replace diodes for rectification and filtering, which reduces the conduction voltage drop and improves the working efficiency of the power supply.
[0018] (3) The driver chip power supply circuit controls the conversion of power supply from the startup phase to the operation phase by turning on and off the MOS tube Q6, replacing the complex isolation step-down power supply circuit and reducing the number of components and circuit complexity.
[0019] (4) The functions realized by combining the circuits of the three attached drawings meet the functional and technical requirements of the high-voltage DC-DC power module driver chip. The present invention can greatly reduce the area of the printed circuit board occupied by the product, reduce the number of components used, make the circuit simpler, reduce the loss, save costs, and has broad application prospects.
[0020] (5) All devices used are general-purpose devices with stable and reliable delivery and wide application. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] Figure 1 Schematic diagram of a half-bridge circuit, where (a) is the left half and (b) is the right half.
[0022] Figure 2 Schematic diagram of the reverse BUCK circuit.
[0023] Figure 3 Schematic diagram of the power supply circuit for the driver chip.
[0024] The present invention is further explained below in conjunction with the accompanying drawings and specific embodiments. DETAILED DESCRIPTION
[0025] The technical solution of the present invention will be clearly and completely described below in conjunction with the drawings and embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.
[0026] The reverse BUCK driving power supply circuit provided in this embodiment includes a half-bridge circuit 1, a reverse BUCK circuit 2 and a driving chip power supply circuit 3. The input power supply is connected to the half-bridge circuit 1, the output end of the reverse BUCK circuit 2 is respectively connected to the input end of the driving chip power supply circuit 3 and the first input end of the half-bridge circuit 1, and the second input end and the third input end of the half-bridge circuit 1 are both connected to the output end of the driving chip power supply circuit 3.
[0027] like Figure 1 As shown, the half-bridge circuit 1 includes a resistor R1, a resistor R5, a resistor R6, a resistor R10, a resistor R15, a resistor R17, a resistor R20, a junction field effect transistor Q1, a junction field effect transistor Q2, a junction field effect transistor Q3, a junction field effect transistor Q5, a junction field effect transistor Q7, a junction field effect transistor Q9, a diode D1, a transformer B1, an inductor L1, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C6, a capacitor C9, a capacitor C10, a capacitor C12, a capacitor C17, a capacitor C21, a capacitor C22, an integrated circuit IC1, an integrated circuit IC2 and an integrated circuit IC3; wherein:
[0028] Pin 7 of the integrated circuit IC2 is connected to the input voltage 5V with pin 4 of the integrated circuit IC2 and one end of the capacitor C10; pin 1 of the integrated circuit IC2 is connected to the input ground VI- and the other end of the capacitor C10; pin 2 of the integrated circuit IC2 is connected to the drive signal PUSH node; pin 3 of the integrated circuit IC2 is connected to the drive signal PULL node; pin 6 of the integrated circuit IC2 is connected to one end of the resistor R17 and one end of the capacitor C22; pin 5 of the integrated circuit IC2 is connected to the other end of the resistor R17, the other end of the capacitor C22, and the input ground VI-; pin 8 of the integrated circuit IC2 is connected to one end of the capacitor C21, the source of the junction field effect transistor Q9, one end of the capacitor C6, and one end of the resistor R20, and the connection point is connected to the output end (GNDF) of the reverse BUCK circuit 2 as the first input end of the half-bridge circuit 1; pin 9 of the integrated circuit IC2 is connected to the other end of the resistor R20 and the gate of the junction field effect transistor Q9; pin 10 of the integrated circuit IC2 is connected to the other end of the capacitor C21, This connection point is connected to the power supply node (VDD) of the driver chip power supply circuit 3 (i.e., the output end of the driver chip power supply circuit 3) as the second input end of the half-bridge circuit 1; the 12th pin of the integrated circuit IC2 is connected to one end of the capacitor C9, one end of the resistor R6, the source of the junction field effect transistor Q2, the drain of the junction field effect transistor Q9, and the 2nd pin of the transformer B1; the 13th pin of the integrated circuit IC2 is connected to the other end of the resistor R6 and the gate of the junction field effect transistor Q2; the 14th pin of the integrated circuit IC2 is connected to the other end of the capacitor C9 and the cathode of the diode D1; the anode of the diode D1 is connected to the output end (VDD) of the driver chip power supply circuit 3 as the third input end of the half-bridge circuit 1; one end of the inductor L1 is connected to the input VIN+, and the other end of the inductor L1 is connected to one end of the capacitor C2, the drain of the junction field effect transistor Q2, the VI+ power input node, and one end of the capacitor C4; the other end of the capacitor C2 is connected to the input ground VI-; the 1st pin of the transformer B1 is connected to the other end of the capacitor C4 and the other end of the capacitor C6;
[0029] Pin 1 of the integrated circuit IC1 is connected to the secondary power supply node SVC3 and one end of the capacitor C1; Pin 6 of the integrated circuit IC1 is connected to the pin 5 of the integrated circuit IC3 and the input control signal PWM1 node; Pin 5 of the integrated circuit IC1 is connected to the pin 6 of the integrated circuit IC3 and the input control signal PWM2 node; Pin 3 of the integrated circuit IC1 is connected to the gate of the junction field effect transistor Q3 and one end of the resistor R5; Pin 4 of the integrated circuit IC1 is connected to the other end of the resistor R5, one end of the capacitor C3, the drain of the junction field effect transistor Q1, the source of the junction field effect transistor Q3 and the pin 3 of the transformer B1; Pin 2 of the integrated circuit IC1 is connected to the other end of the capacitor C3; Pin 8 of the integrated circuit IC1 is connected to the gate of the junction field effect transistor Q1 and one end of the resistor R1; Pin 7 of the integrated circuit IC1 is connected to the other end of the resistor R1, the source of the junction field effect transistor Q1 and the secondary ground GND2; the other end of the capacitor C1 and Pin 9 of the integrated circuit IC1 are both connected to the secondary ground GND2; The drain of the field effect transistor Q3 is commonly connected with the drain of the junction field effect transistor Q5 and the VC8 node (i.e., the output node of the half-bridge circuit 1); the 3rd pin of the integrated circuit IC3 is commonly connected with one end of the resistor R10 and the gate of the junction field effect transistor Q5; the 4th pin of the integrated circuit IC3 is commonly connected with one end of the capacitor C12, the other end of the resistor R10, the source of the junction field effect transistor Q5, the drain of the junction field effect transistor Q7, and the 4th pin of the transformer B1; the 2nd pin of the integrated circuit IC3 is connected with the other end of the capacitor C12; Pin 8 of the integrated circuit IC3 is connected to one end of the resistor R15 and the gate of the junction field effect transistor Q7; pin 7 of the integrated circuit IC3 is connected to the other end of the resistor R15, the source of the junction field effect transistor Q7, and the secondary ground GND2; pin 1 of the integrated circuit IC3 is connected to the secondary chip power supply node SVC3 (this node is the power supply node of the IC1 chip and the IC3 chip) and one end of the capacitor C17; pin 9 of the integrated circuit IC3 and the other end of the capacitor C17 are both connected to the secondary ground GND2.
[0030] Under the above technical scheme, the ground wire of the half-bridge primary circuit is connected to the GNDF node at the output end of the reverse BUCK circuit, and a floating ground is established. The half-bridge primary circuit is divided into two upper and lower junction field effect transistors. During the startup phase, when the input pins 4 and 7 of IC2 are powered by 5V, and the output pins 14 and 10 of IC2 are connected to the 8.5V-11V power supply of the VDD node of the chip power supply circuit 3, the PUSH signal amplified by the 13th pin of IC2 drives the conduction and shutdown of the junction field effect transistor Q2, and the PULL signal amplified by the 9th pin of IC2 drives the conduction and shutdown of the junction field effect transistor Q9. The secondary controls the conduction and shutdown of the junction field effect transistor Q1, the junction field effect transistor Q3, the junction field effect transistor Q5, and the junction field effect transistor Q7 through the two signals PWM1 and PWM2, realizing the basic functions of buck and rectification of the half-bridge circuit.
[0031] Among them, the resistance value of resistor R1, the resistance value of resistor R5, the resistance value of resistor R10 and the resistance value of resistor R15 are 15KΩ, the resistance value of resistor R6 and resistor R20 are 15KΩ, the resistance value of resistor R17 is 2KΩ, the capacitance value of capacitor C1 and capacitor C17 is 4.7uF, the capacitance value of capacitor C2 is 330nF, the capacitance value of capacitor C3 and the capacitance value of capacitor C12 are 470nF, the capacitance value of capacitor C4 and capacitor C6 is 4.7uF, the capacitance value of capacitor C9, capacitor C10 and capacitor C21 is 1uF, and the capacitance value of capacitor C22 is The capacitance is 2.2nF, the inductance of inductor L1 is 0.47uH, the models of junction field effect transistor Q1, junction field effect transistor Q3, junction field effect transistor Q5 and junction field effect transistor Q7 are FDMS86300DC, the models of junction field effect transistor Q2 and junction field effect transistor Q9 are BSC320N20NS3G, the model of diode D1 is B16WS, the models of integrated circuit IC1 and integrated circuit IC3 are RMJ5101AD, and the model of integrated circuit IC2 is SI8233-AB-D-IM1.
[0032] like Figure 2 As shown, the reverse BUCK circuit 2 includes a resistor R22, a transformer B2, a diode D3, a Schottky transistor D2, a junction field effect transistor Q10, a capacitor C24 and a capacitor C30; wherein the cathode of the Schottky transistor D2 is connected to the VI+ power input node and one end of the capacitor C30; the anode of the Schottky transistor D2 is connected to the drain of the junction field effect transistor Q10 and the 2nd pin of the transformer B2; the gate of the junction field effect transistor Q10 is connected to the input PWM signal; the source of the junction field effect transistor Q10 is connected to one end of the resistor R22 and the CS node (the node is used for power supply overcurrent protection ); the other end of the resistor R22 is connected to the input ground VI-; the 1st pin of the transformer B2 is connected to one end of the capacitor C24, the other end of the capacitor C30, and the 4th pin of the transformer B2, and the connection point is connected to the input end of the driver chip power supply circuit 3 and the first input end of the half-bridge circuit 1 as the output end (GNDF) of the reverse BUCK circuit 2; the 3rd pin of the transformer B2 is connected to the anode of the diode D3; the cathode of the diode D3 is connected to the other end of the capacitor C24 and the node VDD0 (the node is connected to the VDD0 node of the driver chip power supply circuit 3 to provide voltage for it).
[0033] In the above technical solution, the output of the reverse BUCK circuit is connected to the signal ground GNDF of the half-bridge circuit and the driving power supply circuit, and the voltage value of the signal ground is changed by changing the duty cycle of the input PWM wave of the gate of Q10 in the reverse BUCK circuit. When the power supply works normally, the transformer B2 generates a power supply voltage to turn on the diode D3 to the VDD0 node, and the CS node on the resistor R22 is used to realize the overcurrent protection function.
[0034] Among them, the resistance of resistor R22 is 0.2R, the capacitance of capacitor C24 and capacitor C30 is 10uF / 35V, the inductance of transformer B2 is 0.44uH, the model of Schottky tube D2 is IDL06G65C5, the model of diode D3 is B16WS, and the model of junction field effect tube Q10 is IPL65R130C7.
[0035] like Figure 3 As shown, the chip power supply circuit 3 includes a resistor R2, a resistor R3, a resistor R4, a resistor R12, a resistor R14, a junction field effect transistor Q4, a junction field effect transistor Q6, a junction field effect transistor Q8, a voltage regulator DZ1, a voltage regulator DZ2, a voltage regulator DZ3, a capacitor C8, a capacitor C14, a capacitor C16 and a capacitor C19; wherein one end of the resistor R2 is commonly connected to the connection node VI+ and one end of the resistor R3; the other end of the resistor R3 is connected to one end of the resistor R4; the other end of the resistor R4 is commonly connected to the drain of the junction field effect transistor Q6, one end of the capacitor C8, the cathode of the voltage regulator DZ1, and the gate of the junction field effect transistor Q4; the source of the junction field effect transistor Q6, the other end of the capacitor C8, and the anode of the voltage regulator DZ1 are commonly connected to the output end (GNDF) of the reverse BUCK circuit 2; the source of the junction field effect transistor Q4 is commonly connected to the source of the junction field effect transistor Q8, the capacitor C1 6 are commonly connected, and the connection point is used as the power supply node (VDD) of the driving chip circuit 3 (that is, the output end of the driving chip circuit 3) to connect the second input end of the half-bridge circuit 1 and the third input end of the half-bridge circuit 1; the drain of the junction field effect transistor Q4 is connected to the other end of R2; the gate of the junction field effect transistor Q6 is commonly connected to the anode of the voltage regulator DZ3 and one end of the resistor R12; the cathode of the voltage regulator DZ3 is commonly connected to the node VDD0, one end of the capacitor C14, the drain of the junction field effect transistor Q8, and one end of the resistor R14; the gate of the junction field effect transistor Q8 is commonly connected to the cathode of the voltage regulator DZ2, one end of the capacitor C19, and the other end of the resistor R14; the other end of the capacitor C16 is commonly connected to the output end (GNDF) of the reverse BUCK circuit 2 with the anode of the voltage regulator DZ2, the other end of the capacitor C19, the other end of the capacitor C14, and the other end of the resistor R12.
[0036] Under the above technical solution, the input of the driver chip circuit is the VI+ node, and the ground line is connected to the output node GNDF of the reverse BUCK circuit 2. Therefore, during the startup phase, when the voltage difference between the VI+ node and the GNDF node reaches 13V, the voltage is stabilized by the voltage regulator DZ1, and the junction field effect transistor Q4 is turned on to flow into the power supply node VDD to supply power to the chip IC2 of the half-bridge circuit 1. When the power supply is working stably, the voltage difference between VI+ and the ground line GNDF is stabilized at 140V, and is stabilized to 14V by the voltage regulator DZ1, causing great loss, so the power supply method needs to be changed. Therefore, when the power supply is working stably, the input voltage of node VDD0 is 14V higher than the ground node GNDF. When the current flowing through the voltage regulator DZ3 and the resistor R12 is greater than 0.02mA, Ugs is greater than 2V, so that the junction field effect transistor Q6 is turned on, the gate of the junction field effect transistor Q4 is grounded, the junction field effect transistor Q4 is turned off, and the power supply is stopped. The voltage of VDD0 is stabilized at 12V through the voltage regulator DZ2, so that the junction field effect transistor Q8 is turned on and flows into the power supply node VDD to power the chip IC2 of the half-bridge circuit 1, thereby realizing the conversion of power supply from the startup stage to the operation stage.
[0037] Among them, the resistance value of resistor R2 is 300R, the resistance values of resistor R3 and resistor R4 are 240KΩ, the resistance value of resistor R12 is 100KΩ, the resistance value of resistor R14 is 5.1KΩ, the capacitance value of capacitor C8 is 100nF, the capacitance values of capacitor C14 and capacitor C16 are 10uF / 35V, the capacitance value of capacitor C19 is 10nF, the model of junction field effect transistor Q4 is LG65N280J, the model of junction field effect transistor Q6 is 2N7002KW, the model of junction field effect transistor Q8 is JRZ10N018L, the model of Zener tube DZ1 is MM3Z13VT1G, the model of Zener tube DZ2 is MM3Z12VT1G, and the model of Zener tube DZ3 is MM3Z12VT1G.
[0038] Following the technical solution of the present invention, the designed reverse BUCK driving power supply circuit meets the functional and technical requirements required by the high-voltage DCDC power module driver chip. The reverse BUCK circuit realizes the change of the ground terminal voltage, reduces the loss required for voltage reduction, and realizes the rapid power supply to the driver chip without adding an additional isolation buck circuit. The adoption of the present invention can greatly reduce the area of the printed circuit board occupied by the product, reduce the number of components used, make the circuit simpler, reduce the loss, and save costs.
[0039] The above description is only a specific implementation mode of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be thought of by any technician familiar with the field within the technical scope disclosed by the present invention without creative work should be covered within the protection scope of the present invention.
Claims
1. A reverse BUCK driving power supply circuit, characterized in that: It comprises a half-bridge circuit (1), a reverse buck circuit (2) and a driver chip power supply circuit (3); wherein the input power supply is connected to the half-bridge circuit (1), the output end of the reverse buck circuit (2) is respectively connected to the input end of the driver chip power supply circuit (3) and the first input end of the half-bridge circuit (1), and the second input end and the third input end of the half-bridge circuit (1) are both connected to the output end of the driver chip power supply circuit (3).
2. The reverse BUCK driving power supply circuit is characterized by: The half-bridge circuit (1) comprises a resistor R1, a resistor R5, a resistor R6, a resistor R10, a resistor R15, a resistor R17, a resistor R20, a junction field effect transistor Q1, a junction field effect transistor Q2, a junction field effect transistor Q3, a junction field effect transistor Q5, a junction field effect transistor Q7, a junction field effect transistor Q9, a diode D1, a transformer B1, an inductor L1, a capacitor C1, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C6, a capacitor C9, a capacitor C10, a capacitor C12, a capacitor C17, a capacitor C21, a capacitor C22, an integrated circuit IC1, an integrated circuit IC2 and an integrated circuit IC3; wherein: Pin 7 of the integrated circuit IC2 is connected to pin 4 of the integrated circuit IC2 and one end of the capacitor C10 to input voltage 5V; pin 1 of the integrated circuit IC2 is connected to input ground VI- and the other end of the capacitor C10; pin 2 of the integrated circuit IC2 is connected to a drive signal PUSH node; pin 3 of the integrated circuit IC2 is connected to a drive signal PULL node; pin 6 of the integrated circuit IC2 is connected to one end of a resistor R17 and one end of a capacitor C22; pin 5 of the integrated circuit IC2 is connected to the other end of the resistor R17, the other end of the capacitor C22 and the input ground VI-; pin 8 of the integrated circuit IC2 is connected to one end of a capacitor C21, the source of a junction field effect transistor Q9, one end of a capacitor C6 and one end of a resistor R20, and the connection point is connected to the output end of a reverse BUCK circuit (2) as a first input end of a half-bridge circuit (1); pin 9 of the integrated circuit IC2 is connected to the other end of the resistor R20 and the gate of the junction field effect transistor Q9; pin 10 of the integrated circuit IC2 is connected to the capacitor C2 1 is connected to the other end of the half-bridge circuit (1), and the connection point is connected to the power supply node of the driver chip power supply circuit (3) as the second input end of the half-bridge circuit (1); the 12th pin of the integrated circuit IC2 is connected to one end of the capacitor C9, one end of the resistor R6, the source of the junction field effect transistor Q2, the drain of the junction field effect transistor Q9, and the 2nd pin of the transformer B1; the 13th pin of the integrated circuit IC2 is connected to the other end of the resistor R6 and the gate of the junction field effect transistor Q2; the 14th pin of the integrated circuit IC2 is connected to the other end of the capacitor C9 and the cathode of the diode D1; the anode of the diode D1 is connected to the output end of the driver chip power supply circuit (3) as the third input end of the half-bridge circuit (1); one end of the inductor L1 is connected to the input VIN+, and the other end of the inductor L1 is connected to one end of the capacitor C2, the drain of the junction field effect transistor Q2, the VI+ power supply input node, and one end of the capacitor C4; the other end of the capacitor C2 is connected to the input ground VI-; the 1st pin of the transformer B1 is connected to the other end of the capacitor C4 and the other end of the capacitor C6; Pin 1 of the integrated circuit IC1 is connected to the secondary power supply node SVC3 and one end of the capacitor C1; Pin 6 of the integrated circuit IC1 is connected to the pin 5 of the integrated circuit IC3 and the input control signal PWM1 node; Pin 5 of the integrated circuit IC1 is connected to the pin 6 of the integrated circuit IC3 and the input control signal PWM2 node; Pin 3 of the integrated circuit IC1 is connected to the gate of the junction field effect transistor Q3 and one end of the resistor R5; Pin 4 of the integrated circuit IC1 is connected to the other end of the resistor R5, one end of the capacitor C3, the drain of the junction field effect transistor Q1, the source of the junction field effect transistor Q3 and the pin 3 of the transformer B1; Pin 2 of the integrated circuit IC1 is connected to the other end of the capacitor C3; Pin 8 of the integrated circuit IC1 is connected to the gate of the junction field effect transistor Q1 and one end of the resistor R1; Pin 7 of the integrated circuit IC1 is connected to the other end of the resistor R1, the source of the junction field effect transistor Q1 and the secondary ground GND2; the other end of the capacitor C1, the integrated circuit IC1 The 9th pin of the integrated circuit is connected to the secondary ground GND2; the drain of the junction field effect transistor Q3 is connected to the drain of the junction field effect transistor Q5 and the VC8 node; the 3rd pin of the integrated circuit IC3 is connected to one end of the connection resistor R10 and the gate of the junction field effect transistor Q5; the 4th pin of the integrated circuit IC3 is connected to one end of the capacitor C12, the other end of the resistor R10, the source of the junction field effect transistor Q5, the drain of the junction field effect transistor Q7, and the 4th pin of the transformer B1; the 2nd pin of the integrated circuit IC3 is connected to the other end of the capacitor C12; the 8th pin of the integrated circuit IC3 is connected to one end of the resistor R15 and the gate of the junction field effect transistor Q7; the 7th pin of the integrated circuit IC3 is connected to the other end of the resistor R15, the source of the junction field effect transistor Q7, and the secondary ground GND2; the 1st pin of the integrated circuit IC3 is connected to the secondary chip power supply node SVC3 and one end of the capacitor C17; the 9th pin of the integrated circuit IC3 and the other end of the capacitor C17 are connected to the secondary ground GND2.
3. The reverse BUCK driving power supply circuit as claimed in claim 2, characterized in that: The resistance values of the resistor R1, the resistor R5, the resistor R10 and the resistor R15 are 15KΩ, the resistance values of the resistor R6 and the resistor R20 are 15KΩ, the resistance value of the resistor R17 is 2KΩ, the capacitance values of the capacitors C1 and C17 are 4.7uF, the capacitance value of the capacitor C2 is 330nF, the capacitance value of the capacitor C3 and the capacitance value of the capacitor C12 are 470nF, the capacitance value of the capacitor C4 and the capacitor C6 are 4.7uF, the capacitance value of the capacitors C9, the capacitor C10 and the capacitor C21 are 1uF, and the capacitance value of the capacitor C22 is 1uF. The capacitance is 2.2nF, the inductance of inductor L1 is 0.47uH, the models of junction field effect transistor Q1, junction field effect transistor Q3, junction field effect transistor Q5 and junction field effect transistor Q7 are FDMS86300DC, the models of junction field effect transistor Q2 and junction field effect transistor Q9 are BSC320N20NS3G, the model of diode D1 is B16WS, the models of integrated circuit IC1 and integrated circuit IC3 are RMJ5101AD, and the model of integrated circuit IC2 is SI8233-AB-D-IM1.
4. The reverse BUCK driving power supply circuit according to claim 1, characterized in that: The reverse BUCK circuit (2) comprises a resistor R22, a transformer B2, a diode D3, a Schottky transistor D2, a junction field effect transistor Q10, a capacitor C24 and a capacitor C30; wherein the cathode of the Schottky transistor D2 is connected to the VI+ power supply input node and one end of the capacitor C30; the anode of the Schottky transistor D2 is connected to the drain of the junction field effect transistor Q10 and the 2nd pin of the transformer B2; the gate of the junction field effect transistor Q10 is connected to the input PWM signal; the source of the junction field effect transistor Q10 is connected to the resistor One end of the resistor R22 is connected to the CS node; the other end of the resistor R22 is connected to the input ground VI-; the 1st pin of the transformer B2 is connected to one end of the capacitor C24, the other end of the capacitor C30, and the 4th pin of the transformer B2, and the connection point is connected to the input end of the driver chip power supply circuit (3) and the first input end of the half-bridge circuit (1) as the output end of the reverse buck circuit (2); the 3rd pin of the transformer B2 is connected to the anode of the diode D3; the cathode of the diode D3 is connected to the other end of the capacitor C24 and the node VDD0.
5. The reverse BUCK driving power supply circuit as claimed in claim 4, characterized in that: The resistance of the resistor R22 is 0.2R, the capacitance of the capacitor C24 and the capacitance of the capacitor C30 are 10uF / 35V, the inductance of the transformer B2 is 0.44uH, the Schottky tube D2 model is IDL06G65C5, the diode D3 model is B16WS, and the junction field effect tube Q10 model is IPL65R130C7.
6. The reverse BUCK driving power supply circuit according to claim 1, characterized in that: The chip power supply circuit 3 comprises a resistor R2, a resistor R3, a resistor R4, a resistor R12, a resistor R14, a junction field effect transistor Q4, a junction field effect transistor Q6, a junction field effect transistor Q8, a voltage regulator DZ1, a voltage regulator DZ2, a voltage regulator DZ3, a capacitor C8, a capacitor C14, a capacitor C16 and a capacitor C19; wherein one end of the resistor R2 is connected to the connection node VI+ and one end of the resistor R3; the other end of the resistor R3 is connected to one end of the resistor R4; the other end of the resistor R4 is connected to the drain of the junction field effect transistor Q6, one end of the capacitor C8, the cathode of the voltage regulator DZ1 and the gate of the junction field effect transistor Q4; the source of the junction field effect transistor Q6, the other end of the capacitor C8 and the anode of the voltage regulator DZ1 are connected to the output end of the reverse buck circuit (2); the source of the junction field effect transistor Q4 is connected to the gate of the junction field effect transistor Q8. The source and one end of the capacitor C16 are connected together, and the connection point is connected to the second input end of the half-bridge circuit (1) and the third input end of the half-bridge circuit (1) as the power supply node of the driving chip circuit 3; the drain of the junction field effect transistor Q4 is connected to the other end of R2; the gate of the junction field effect transistor Q6 is connected to the anode of the voltage regulator tube DZ3 and one end of the resistor R12; the cathode of the voltage regulator tube DZ3 is connected to the node VDD0, one end of the capacitor C14, the drain of the junction field effect transistor Q8, and one end of the resistor R14; the gate of the junction field effect transistor Q8 is connected to the cathode of the voltage regulator tube DZ2, one end of the capacitor C19, and the other end of the resistor R14; the other end of the capacitor C16 is connected to the output end of the reverse buck circuit (2) together with the anode of the voltage regulator tube DZ2, the other end of the capacitor C19, the other end of the capacitor C14, and the other end of the resistor R12.
7. The reverse BUCK driving power supply circuit as claimed in claim 6, characterized in that: The resistance value of the resistor R2 is 300R, the resistance values of the resistor R3 and the resistor R4 are 240KΩ, the resistance value of the resistor R12 is 100KΩ, the resistance value of the resistor R14 is 5.1KΩ, the capacitance value of the capacitor C8 is 100nF, the capacitance values of the capacitors C14 and C16 are 10uF / 35V, the capacitance value of the capacitor C19 is 10nF, the model of the junction field effect transistor Q4 is LG65N280J, the model of the junction field effect transistor Q6 is 2N7002KW, the model of the junction field effect transistor Q8 is JRZ10N018L, the model of the Zener diode DZ1 is MM3Z13VT1G, the model of the Zener diode DZ2 is MM3Z12VT1G, and the model of the Zener diode DZ3 is MM3Z12VT1G.