Bootstrap capacitor charging circuit, buck-boost converter, chip and electronic equipment

Abstract

The invention provides a bootstrap capacitor charging circuit, a buck-boost converter, a chip and electronic equipment. The detection circuit detects whether the voltage at the two ends of the bootstrap capacitor is lower than the preset voltage or not, and transmits a third signal to the control circuit. And the control circuit performs logical operation on the first signal, the second signal and the third signal to obtain a fourth signal, and transmits the fourth signal used for controlling the on or off of the charging circuit to the charging circuit. And furthermore, the charging circuit charges the bootstrap capacitor by using the power supply voltage provided by the positive voltage power supply according to the fourth signal, and stops charging until the voltage at the two ends of the bootstrap capacitor is higher than the preset voltage. The bootstrap capacitor is charged by the power supply voltage provided by the positive voltage power supply. Therefore, the voltage at the two ends of the bootstrap capacitor can still be stabilized near the power supply voltage in a high-resistance stage. On the basis, the bootstrap capacitor charging circuit does not need to additionally add more complex sequential logic, the circuit structure can be simplified, and the cost can be reduced.

Description

Technical Field

[0001] The present application relates to the technical field of power management chips, and in particular to a bootstrap capacitor charging circuit, a buck-boost converter, a chip and an electronic device. Background Art

[0002] Switching power supplies are widely used in electronic products due to their high efficiency and high voltage adjustment capabilities. Switching power supplies can include: low-side power transistors, high-side power transistors and bootstrap capacitors. According to their basic topology, switching power supplies can be divided into three basic types: buck converter (Buck), boost converter (Boost), and buck-boost converter (Buck-Boost). For Buck with a positive output voltage, in the low-side power transistor turn-on stage, the potential of the switch node between the source of the high-side power transistor and the drain of the low-side power transistor is directly pulled to the ground potential, so that the potential of the lower plate of the bootstrap capacitor is the ground voltage, so that Buck can directly charge the bootstrap capacitor at this stage. Thereby, the voltage across the charged bootstrap capacitor is approximately equal to the charging voltage, so that the high-side power transistor is turned on normally. For Buck-Boost with a negative output voltage, in the low-side power transistor turn-on stage, the potential of the lower plate of the bootstrap capacitor is approximately equal to the output voltage. Therefore, Buck-Boost needs a power supply with a negative output voltage to charge the bootstrap capacitor. At this time, the power supply is a negative voltage power supply.

[0003] When the Buck-Boost load is light, Buck-Boost is in discontinuous conduction mode (DCM). In this way, when the high-side power transistor and the low-side power transistor are both turned off, that is, in the high-resistance stage in DCM, the potential of the lower plate of the bootstrap capacitor is 0, and the potential of the upper plate is positive, so that the negative voltage power supply cannot charge the bootstrap capacitor. Even when the load is very light, the switching cycle of Buck-Boost will be very long, which may cause the charge stored in the bootstrap capacitor to be discharged. In this way, when the high-side power transistor needs to be turned on in the next switching cycle, the voltage across the bootstrap capacitor is insufficient, so that the high-side power transistor cannot be turned on normally, causing Buck-Boost to work abnormally.

[0004] Based on this, if Buck-Boost still uses a negative voltage power supply to charge the bootstrap capacitor, it will require additional complex timing logic and corresponding charging circuits. As a result, Buck-Boost has the problem of complex circuits and high costs. Among them, the high-resistance stage refers to the stage where both the high-side power transistor and the low-side power transistor are turned off. Summary of the invention

[0005] The present application provides a bootstrap capacitor charging circuit, a buck-boost converter, a chip and an electronic device, which can use a positive voltage power supply to charge the bootstrap capacitor without adding more complex timing logic, simplifying the bootstrap capacitor charging circuit and reducing costs.

[0006] In a first aspect, the present application provides a bootstrap capacitor charging circuit, which is applied to a half-bridge buck-boost converter. The bootstrap capacitor charging circuit includes: a detection circuit, a control circuit and a charging circuit;

[0007] The first input end of the detection circuit and the output end of the charging circuit are both electrically connected to the upper plate of the bootstrap capacitor in the buck-boost converter, the second input end of the detection circuit is electrically connected to the lower plate of the bootstrap capacitor, the output end of the detection circuit is electrically connected to the first input end of the control circuit, the second input end of the control circuit is used to access a first signal, the first signal is used to drive the low-side power transistor in the buck-boost converter to turn on or off, the third input end of the control circuit is used to access a second signal, the second signal is used to indicate whether the buck-boost converter enters a high-resistance stage, the first output end of the control circuit is electrically connected to the control end of the charging circuit, and the input end of the charging circuit is electrically connected to a positive voltage power supply;

[0008] When the buck-boost converter enters the high-resistance stage, or the low-side power transistor is in the on stage, wherein:

[0009] The detection circuit is used to detect whether the voltage across the bootstrap capacitor is lower than a preset voltage, obtain a third signal, and transmit the third signal to the control circuit;

[0010] The control circuit is used for performing a logic operation on the first signal, the second signal and the third signal to obtain a fourth signal when the second signal indicates that the buck-boost converter enters the high-impedance stage, and transmitting the fourth signal to the charging circuit, wherein the fourth signal is used to control the charging circuit to be turned on or off;

[0011] The charging circuit is used to charge the bootstrap capacitor according to the fourth signal using the power supply voltage provided by the positive voltage power supply until the voltage across the bootstrap capacitor is higher than the preset voltage, and then stop charging.

[0012] Through the bootstrap capacitor charging circuit provided by the first aspect, when the buck-boost converter enters the high-impedance stage, or when the low-side power transistor is in the on stage, the detection circuit can detect whether the voltage across the bootstrap capacitor is lower than the preset voltage, and obtain a third signal, and transmit the third signal to the control circuit, so that the control circuit can obtain the third signal. In this way, the control circuit can perform a logical operation on the first signal, the second signal and the third signal to obtain a fourth signal, and transmit a fourth signal for controlling the on or off of the charging circuit to the charging circuit, so that the charging circuit can obtain the fourth signal. Furthermore, the charging circuit can charge the bootstrap capacitor using the power supply voltage provided by the positive voltage power supply according to the fourth signal until the voltage across the bootstrap capacitor is higher than the preset voltage and the charging is stopped. Since the charging circuit charges the bootstrap capacitor using the power supply voltage provided by the positive voltage power supply. Therefore, the voltage across the bootstrap capacitor can still be stabilized near the power supply voltage when the buck-boost converter enters the high-impedance stage. Based on this, the bootstrap capacitor charging circuit does not need to add more complex timing logic. Thus, the circuit structure of the bootstrap capacitor charging circuit can be simplified and the cost can be reduced.

[0013] In one possible design, the detection circuit includes: a voltage detection circuit, a pull-up current output circuit, a pull-down current output circuit, and a third signal output circuit;

[0014] The first input end of the voltage detection circuit is electrically connected to the upper plate of the bootstrap capacitor, the second input end of the voltage detection circuit and the input end of the pull-down current output circuit are both electrically connected to the lower plate of the bootstrap capacitor, the output end of the voltage detection circuit is electrically connected to the control end of the pull-down current output circuit, the output end of the pull-down current output circuit is electrically connected to the output end of the pull-up current output circuit, the input end of the pull-up current output circuit and the input end of the third signal output circuit are both electrically connected to the positive voltage power supply, the control end of the pull-up current output circuit is used to access the first bias current, the control end of the third signal output circuit is electrically connected between the output end of the pull-down current output circuit and the output end of the pull-up current output circuit, and the output end of the third signal output circuit is electrically connected to the first input end of the control circuit;

[0015] The pull-up current output circuit is used to generate a pull-up current according to the power supply voltage under the action of the first bias current, and transmit the pull-up current to the third signal output circuit;

[0016] The voltage detection circuit is used to detect whether the voltage across the bootstrap capacitor is lower than the preset voltage, obtain a control voltage, and transmit the control voltage to the pull-down current output circuit;

[0017] The pull-down current output circuit is used to generate a pull-down current under the action of the first control voltage, and transmit the pull-down current to the third signal output circuit;

[0018] The third signal output circuit is used to determine whether to pull up or down the potential of the control terminal of the third signal output circuit according to the magnitude relationship between the pull-up capability of the pull-up current and the pull-down capability of the pull-down current to generate the third signal.

[0019] In one possible design, the detection circuit further includes: a clamping circuit;

[0020] The first input terminal of the clamp circuit is electrically connected to the upper plate of the bootstrap capacitor, the second input terminal of the clamp circuit is electrically connected to the lower plate of the bootstrap capacitor, and the output terminal of the clamp circuit is electrically connected to the output terminal of the pull-down current output circuit;

[0021] The clamping circuit is used to pull up the potential of the control end of the third signal output circuit when the voltage across the bootstrap capacitor is equal to the clamping voltage, so as to clamp the voltage across the bootstrap capacitor to the clamping voltage.

[0022] In one possible design, the detection circuit further includes: a hysteresis current output circuit;

[0023] The input end of the hysteresis current output circuit is electrically connected to the positive voltage power supply, the control end of the hysteresis current output circuit is electrically connected to the second output end of the control circuit, and the output end of the hysteresis current output circuit is electrically connected to the output end of the pull-up current output circuit;

[0024] The hysteresis current output circuit is used to obtain a fifth signal from the control circuit, and under the action of the fifth signal, generate the hysteresis current according to the power supply voltage, and transmit the hysteresis current to the pull-up current output circuit, and the level of the fifth signal is opposite to the level of the fourth signal;

[0025] The pull-up current output circuit is used to increase the current value of the pull-up current under the action of the hysteresis current so as to keep the third signal constant and prevent the third signal from floating at a flip point, wherein the flip point refers to the moment when the third signal flips from the first level to the second level.

[0026] In one possible design, the hysteresis current output circuit includes: a first P-type transistor, a second P-type transistor and a third P-type transistor;

[0027] The source of the first P-type transistor and the source of the second P-type transistor are both electrically connected to the positive voltage power supply, the gate of the first P-type transistor, the gate and the drain of the second P-type transistor are all used to connect to the first bias current, the source of the first P-type transistor is electrically connected to the source of the third P-type transistor, the gate of the third P-type transistor is electrically connected to the second output terminal of the control circuit, and the drain of the third P-type transistor is electrically connected to the output terminal of the pull-up current output circuit.

[0028] In one possible design, the voltage detection circuit includes: a first N-type transistor, a second N-type transistor and a first resistor;

[0029] The drain and gate of the first N-type transistor are both electrically connected to the upper plate of the bootstrap capacitor, the source of the first N-type transistor is electrically connected to the drain and gate of the second N-type transistor, respectively, the source of the second N-type transistor is electrically connected to the first end of the first resistor, the control end of the pull-down current output circuit is electrically connected between the source of the second N-type transistor and the first end of the first resistor, and the second end of the first resistor is electrically connected to the lower plate of the bootstrap capacitor.

[0030] In one possible design, the clamping circuit includes: a diode, a second resistor, and a third N-type transistor;

[0031] The cathode of the diode is electrically connected to the upper plate of the bootstrap capacitor, the anode of the diode is electrically connected to the first end of the second resistor, the second end of the second resistor and the source of the third N-type transistor are both electrically connected to the lower plate of the bootstrap capacitor, the gate of the third N-type transistor is electrically connected between the anode of the diode and the first end of the second resistor, and the drain of the third N-type transistor is electrically connected to the output end of the pull-down current output circuit.

[0032] In one possible design, the third signal output circuit includes: a fourth P-type transistor and a buffer;

[0033] The source of the fourth P-type transistor is electrically connected to the positive voltage power supply, the gate of the fourth P-type transistor is electrically connected between the output end of the pull-down current output circuit and the output end of the pull-up current output circuit, the drain of the fourth P-type transistor and the input end of the buffer are both used to access the second bias current, and the output end of the buffer is electrically connected to the first input end of the control circuit.

[0034] In one possible design, the pull-up current output circuit includes: a fifth P-type transistor;

[0035] The source of the fifth P-type transistor is electrically connected to the positive voltage power supply, the gate of the fifth P-type transistor is used to access the first bias current, and the drain of the fifth P-type transistor is electrically connected to the output end of the pull-down current output circuit.

[0036] In one possible design, the pull-up current output circuit further includes: a sixth P-type transistor and a fourth N-type transistor;

[0037] The source of the sixth P-type transistor is electrically connected to the drain of the sixth P-type transistor, the gate of the sixth P-type transistor is grounded, the drain of the sixth P-type transistor is electrically connected to the source and gate of the fourth N-type transistor respectively, and the drain of the fourth N-type transistor is electrically connected to the output end of the pull-down current output circuit.

[0038] In one possible design, the pull-down current output circuit includes: a fifth N-type transistor;

[0039] The drain of the fifth N-type transistor is electrically connected to the output end of the pull-up current output circuit, the gate of the fifth N-type transistor is electrically connected to the output end of the voltage detection circuit, and the source of the fifth N-type transistor is electrically connected to the lower plate of the bootstrap capacitor.

[0040] In a possible design, the control circuit includes: a delay device, a first AND gate device, a second AND gate device, a NAND gate device, a NOR gate device, a first inverter and a second inverter;

[0041] The input end of the delay device is used to access the first signal, the output end of the delay device is electrically connected to the first input end of the first AND gate device and the first input end of the NAND gate device respectively, the second input end of the NAND gate device and the input end of the first inverter are both electrically connected to the output end of the detection circuit, the output end of the NAND gate device is electrically connected to the second input end of the first AND gate device, the output end of the first AND gate device is electrically connected to the first input end of the NOR gate device, the output end of the second inverter is electrically connected to the first input end of the second AND gate device, the second input end of the second AND gate device is used to access the second signal, the output end of the second AND gate device is electrically connected to the second input end of the NOR gate device, the output end of the NOR gate device is electrically connected to the input end of the second inverter, and the output end of the second inverter is electrically connected to the control end of the charging circuit.

[0042] In a possible design, the charging circuit includes: a switch circuit, a charging tube and a field effect transistor;

[0043] The control end of the switch circuit is electrically connected to the first output end of the control circuit, the first end of the switch circuit and the source of the charging tube are both electrically connected to the positive voltage power supply, the second end of the switch circuit is electrically connected to the gate of the charging tube, the drain of the charging tube is electrically connected to the gate and source of the field effect transistor respectively, and the drain of the field effect transistor is electrically connected to the upper plate of the bootstrap capacitor;

[0044] The switch circuit is used to control the charging tube to turn on according to the fourth signal, so that the power supply voltage charges the bootstrap capacitor through the body diode of the field effect transistor.

[0045] In one possible design, the switch circuit includes: a seventh P-type transistor and a sixth N-type transistor;

[0046] The gate of the seventh P-type transistor and the gate of the sixth N-type transistor are both electrically connected to the first output terminal of the control circuit, the source of the seventh P-type transistor is electrically connected to the positive voltage power supply, the drain of the seventh P-type transistor is electrically connected to the drain of the sixth N-type transistor, the gate of the charging tube is electrically connected between the drain of the seventh P-type transistor and the drain of the sixth N-type transistor, and the source of the sixth N-type transistor is grounded.

[0047] In a second aspect, the present application provides a half-bridge buck-boost converter, comprising: a high-side power transistor, a low-side power transistor, an inductor, a bootstrap capacitor, and a bootstrap capacitor charging circuit in the first aspect and each possible design of the first aspect;

[0048] The drain of the high-side power transistor is used to access the input voltage of the buck-boost converter, the source of the high-side power transistor is electrically connected to the drain of the low-side power transistor and the first end of the inductor respectively, the source of the low-side power transistor is used to output the output voltage of the buck-boost converter, a switch node is arranged between the source of the high-side power transistor and the drain of the low-side power transistor, the upper plate of the bootstrap capacitor is electrically connected to the output end of the bootstrap capacitor charging circuit, the lower plate of the bootstrap capacitor is electrically connected to the switch node, the gate of the high-side power transistor and the gate of the low-side power transistor are both used to access the drive signal, the drive signal is used to drive the gate of the high-side power transistor and the low-side power transistor to turn on or off, and the second end of the inductor is grounded.

[0049] The beneficial effects of the buck-boost converter provided in the second aspect and each possible design of the second aspect can be referred to the beneficial effects brought about by the first aspect and each possible implementation method of the first aspect, and will not be repeated here.

[0050] In a third aspect, the present application provides a chip, comprising: the bootstrap capacitor charging circuit in the above-mentioned first aspect and each possible design of the above-mentioned first aspect, and / or the buck-boost converter in the above-mentioned second aspect.

[0051] In a fourth aspect, the present application provides an electronic device, which includes the chip in the third aspect above.

[0052] The above description is only an overview of the technical solution of the embodiment of the present application. In order to more clearly understand the technical means of the embodiment of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the embodiment of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions of the embodiments of the present application, a brief introduction will be given below to the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0054] Figure 1 A schematic diagram of the structure of a bootstrap capacitor charging circuit provided in an embodiment of the present application;

[0055] Figure 2 A schematic diagram of the structure of a half-bridge buck-boost converter provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] In this application, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c alone can represent: a, b, c, a and b, a and c, or a, b, and c, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0057] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore should not be understood as a limitation on the present application.

[0058] The terms "connected" and "connected" should be understood in a broad sense. For example, the "connected" or "connected" of a circuit structure can refer to not only physical connection, but also electrical connection or signal connection. For example, it can be directly connected, that is, physically connected, or indirectly connected through at least one intermediate element, as long as the circuit is connected, or it can be the internal connection of two elements; signal connection can refer to signal connection through a circuit or through a media medium, such as radio waves. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0059] First, the professional terms involved in the embodiments of the present application are explained.

[0060] DCM means that in certain application scenarios, the inductor current in the buck-boost converter drops to zero in certain switching cycles. In this mode, in order to prevent the inductor current from continuing to flow and becoming negative current, the buck-boost converter turns off both the high-side power transistor and the low-side power transistor when the inductor current is 0, so that the inductor current is maintained at 0A to reduce power consumption.

[0061] The high-impedance phase refers to the phase in which both the high-side power transistor and the low-side power transistor are turned off.

[0062] Next, combine Figure 1 , the circuit structure of the bootstrap capacitor charging circuit 100 is described in detail.

[0063] Reference Figure 1 , Figure 1 Schematic diagram of a bootstrap capacitor charging circuit provided in an embodiment of the present application. Figure 1 As shown, the bootstrap capacitor charging circuit 100 may include: a detection circuit 110 , a control circuit 120 and a charging circuit 130 .

[0064] The first input terminal of the detection circuit 110 and the output terminal of the charging circuit 130 are both electrically connected to the upper plate of the bootstrap capacitor CBST in the buck-boost converter 1000, the second input terminal of the detection circuit 110 is electrically connected to the lower plate of the bootstrap capacitor CBST, the output terminal of the detection circuit 110 is electrically connected to the first input terminal of the control circuit 120, the second input terminal of the control circuit 120 is used to access the first signal LSON_FB, the first signal LSON_FB is used to drive the low-side power transistor LS in the buck-boost converter 1000 to turn on or off, the third input terminal of the control circuit 120 is used to access the second signal HZ, the second signal HZ is used to indicate whether the buck-boost converter 1000 enters the high-resistance stage, the first output terminal of the control circuit 120 is electrically connected to the control terminal of the charging circuit 130, and the input terminal of the charging circuit 130 is electrically connected to the positive voltage power supply.

[0065] Among them, the detection circuit 110, the control circuit 120 and the charging circuit 130 can be provided separately or integrated, and the embodiment of the present application does not specifically limit this.

[0066] Exemplarily, when the first signal LSON_FB is at a high level, the first signal LSON_FB drives the low-side power transistor LS to turn on. When the first signal LSON_FB is at a low level, the first signal LSON_FB drives the low-side power transistor LS to turn off.

[0067] Exemplarily, when the second signal HZ is at a high level, the second signal HZ indicates that the buck-boost converter 1000 enters the high impedance stage. When the second signal HZ is at a low level, the second signal HZ indicates that the buck-boost converter 1000 does not enter the high impedance stage.

[0068] When the buck-boost converter 1000 enters the high-resistance stage, or the low-side power transistor LS is in the on stage:

[0069] The detection circuit 110 can detect whether the voltage across the bootstrap capacitor CBST is lower than a preset voltage to obtain a third signal BOOT_CHG_OFF. In addition, the detection circuit 110 can transmit the third signal BOOT_CHG_OFF to the control circuit 120 so that the control circuit 120 can obtain the third signal BOOT_CHG_OFF.

[0070] Exemplarily, when it is detected that the voltage across the bootstrap capacitor CBST is lower than the preset voltage, the third signal BOOT_CHG_OFF is at a low level. When it is detected that the voltage across the bootstrap capacitor CBST is higher than the preset voltage, the third signal BOOT_CHG_OFF is at a high level.

[0071] Thus, the control circuit 120 can perform a logic operation on the first signal LSON_FB, the second signal HZ and the third signal BOOT_CHG_OFF to obtain the fourth signal EN_CHG. Furthermore, the control circuit 120 can transmit the fourth signal EN_CHG to the charging circuit 130 so that the charging circuit 130 can obtain the fourth signal EN_CHG.

[0072] The fourth signal EN_CHG is used to control the on or off of the charging circuit 130. For example, when the fourth signal EN_CHG is at a high level, the fourth signal EN_CHG can control the charging circuit 130 to be on. When the fourth signal EN_CHG is at a low level, the fourth signal EN_CHG can control the charging circuit 130 to be off.

[0073] The logic processing performed by the control circuit 120 is an AND operation, a NOR operation, and a combination logic of an AND-NOR operation.

[0074] Furthermore, the charging circuit 130 can be turned on according to the fourth signal EN_CHG. In this way, the charging circuit 130 can use the power supply voltage VDD provided by the positive voltage power supply to charge the bootstrap capacitor CBST, so that the voltage across the bootstrap capacitor CBST increases. Until the voltage across the bootstrap capacitor CBST is higher than the preset voltage, the third signal BOOT_CHG_OFF is at a high level, so that the fourth signal EN_CHG is at a low level, so that the charging circuit 130 is turned off. In this way, the charging circuit 130 stops charging.

[0075] Since the charging circuit 130 uses the power supply voltage VDD provided by the positive voltage power supply to charge the bootstrap capacitor CBST, the voltage across the bootstrap capacitor CBST can still be stabilized near the power supply voltage when the buck-boost converter 1000 enters the high-impedance stage. Based on this, the bootstrap capacitor charging circuit 100 does not need to add more complex timing logic, thereby simplifying the circuit structure of the bootstrap capacitor charging circuit 100 and reducing the cost.

[0076] The bootstrap capacitor charging circuit, buck-boost converter, chip and electronic device provided by the present application, when the buck-boost converter enters the high-resistance stage, or when the low-side power transistor is in the on stage, the detection circuit can detect whether the voltage across the bootstrap capacitor is lower than the preset voltage, and obtain a third signal, and transmit the third signal to the control circuit, so that the control circuit can obtain the third signal. In this way, the control circuit can perform a logical operation on the first signal, the second signal and the third signal to obtain a fourth signal, and transmit a fourth signal for controlling the opening or closing of the charging circuit to the charging circuit, so that the charging circuit can obtain the fourth signal. Furthermore, the charging circuit can charge the bootstrap capacitor using the power supply voltage provided by the positive voltage power supply according to the fourth signal, until the voltage across the bootstrap capacitor is higher than the preset voltage, and the charging is stopped. Since the charging circuit charges the bootstrap capacitor using the power supply voltage provided by the positive voltage power supply. Therefore, the voltage across the bootstrap capacitor can still be stabilized near the power supply voltage when the buck-boost converter enters the high-resistance stage. Based on this, the bootstrap capacitor charging circuit does not need to add more complex timing logic. Thus, the circuit structure of the bootstrap capacitor charging circuit can be simplified and the cost can be reduced.

[0077] Based on the description of the above embodiment, a possible implementation of the detection circuit 110 is exemplified. Figure 2 As shown, the detection circuit 110 includes: a voltage detection circuit 111 , a pull-up current output circuit 112 , a pull-down current output circuit 113 and a third signal output circuit 114 .

[0078] The first input terminal of the voltage detection circuit 111 is electrically connected to the upper plate of the bootstrap capacitor CBST, the second input terminal of the voltage detection circuit 111 and the input terminal of the pull-down current output circuit 113 are both electrically connected to the lower plate of the bootstrap capacitor CBST, the output terminal of the voltage detection circuit 111 is electrically connected to the control terminal of the pull-down current output circuit 113, the output terminal of the pull-down current output circuit 113 is electrically connected to the output terminal of the pull-up current output circuit 112, the input terminal of the pull-up current output circuit 112 and the input terminal of the third signal output circuit 114 are both electrically connected to a positive voltage power supply, the control terminal of the pull-up current output circuit 112 is used to connect to the first bias current IB1, the control terminal of the third signal output circuit 114 is electrically connected between the output terminal of the pull-down current output circuit 113 and the output terminal of the pull-up current output circuit 112, and the output terminal of the third signal output circuit 114 is electrically connected to the first input terminal of the control circuit 120.

[0079] The first input end of the voltage detection circuit 111 is the first input end of the detection circuit 110 , the second input end of the voltage detection circuit 111 is the second input end of the detection circuit 110 , and the output end of the third signal output circuit 114 is the output end of the detection circuit 110 .

[0080] Under the action of the first bias current IB1, the pull-up current output circuit 112 can generate a pull-up current according to the power supply voltage VDD, and the pull-up current output circuit 112 can transmit the pull-up current to the third signal output circuit 114, so that the third signal output circuit 114 can obtain the pull-up current.

[0081] The voltage detection circuit 111 can detect whether the voltage across the bootstrap capacitor CBST is lower than a preset voltage to obtain a control voltage. In addition, the voltage detection circuit 111 can transmit the control voltage to the pull-down current output circuit 113 so that the pull-down current output circuit 113 can obtain the control voltage.

[0082] Thus, under the control voltage, the pull-down current output circuit 113 can generate a pull-down current. Furthermore, the pull-down current output circuit 113 can transmit the pull-down current to the third signal output circuit 114, so that the third signal output circuit 114 can obtain the pull-down current.

[0083] Furthermore, the third signal output circuit 114 can determine whether to pull up or pull down the potential of the control terminal of the third signal output circuit 114 according to the magnitude relationship between the pull-up capability of the pull-up current and the pull-down capability of the pull-down current, so that the third signal output circuit 114 can generate the third signal BOOT_CHG_OFF. Thus, the detection circuit 110 can obtain the third signal BOOT_CHG_OFF.

[0084] When the pull-up capability of the pull-up current is greater than the pull-down capability of the pull-down current, the potential of the control end of the third signal output circuit 114 is pulled high. Thus, the third signal BOOT_CHG_OFF is at a high level. When the pull-up capability of the pull-up current is less than the pull-down capability of the pull-down current, the potential of the control end of the third signal output circuit 114 is pulled low. Thus, the third signal BOOT_CHG_OFF is at a low level.

[0085] In summary, under the action of the first bias current, the pull-up current output circuit can generate a pull-up current according to the power supply voltage, and transmit the pull-up current to the third signal output circuit, so that the third signal output circuit can obtain the pull-up current. The voltage detection circuit can detect whether the voltage across the bootstrap capacitor is lower than the preset voltage, obtain the control voltage, and transmit the control voltage to the pull-down current output circuit, so that the pull-down current output circuit can obtain the control voltage. In this way, the pull-down current output circuit can generate a pull-down current under the action of the first control voltage, and transmit the pull-down current to the third signal output circuit, so that the third signal output circuit can obtain the pull-down current. Furthermore, the third signal output circuit can determine whether to pull up or pull down the potential of the control end of the third signal output circuit according to the size relationship between the pull-up capability of the pull-up current and the pull-down capability of the pull-down current to generate a third signal. Thus, the detection circuit can obtain the third signal.

[0086] Based on the description of the above embodiment, another possible implementation of the detection circuit 110 is exemplified. Figure 2 As shown, the detection circuit 110 may further include: a clamping circuit 115 .

[0087] A first input terminal of the clamp circuit 115 is electrically connected to the upper plate of the bootstrap capacitor CBST, a second input terminal of the clamp circuit 115 is electrically connected to the lower plate of the bootstrap capacitor CBST, and an output terminal of the clamp circuit 115 is electrically connected to the output terminal of the pull-down current output circuit 113 .

[0088] When the voltage across the bootstrap capacitor CBST is equal to the clamping voltage, the clamping circuit 115 can pull up the potential of the control terminal of the third signal output circuit 114, so that the third signal BOOT_CHG_OFF is at a high level. In this way, the fourth signal EN_CHG is at a low level, so that the charging circuit 130 is turned off. Then, the charging circuit 130 stops charging the bootstrap capacitor CBST. Thus, the clamping circuit 115 can clamp the voltage across the bootstrap capacitor CBST to the clamping voltage.

[0089] Based on the description of the above embodiment, another possible implementation of the detection circuit 110 is exemplified. Figure 2 As shown, the detection circuit 110 may further include: a hysteresis current output circuit 116 .

[0090] The input end of the hysteresis current output circuit 116 is electrically connected to the positive voltage power supply, the control end of the hysteresis current output circuit 116 is electrically connected to the second output end of the control circuit 120, and the output end of the hysteresis current output circuit 116 is electrically connected to the output end of the pull-up current output circuit 112.

[0091] The hysteresis current output circuit 116 can obtain the fifth signal CHG_Z from the control circuit 120. Moreover, under the action of the fifth signal CHG_Z, the hysteresis current output circuit 116 can generate a hysteresis current according to the power supply voltage VDD, and transmit the hysteresis current to the pull-up current output circuit 112, so that the pull-up current output circuit 112 can obtain the hysteresis current.

[0092] The level of the fifth signal CHG_Z is opposite to the level of the fourth signal EN_CHG.

[0093] In this way, under the effect of the hysteresis current, the pull-up current output circuit 112 can increase the current value of the pull-up current, so that the third signal BOOT_CHG_OFF remains constant, and the third signal BOOT_CHG_OFF is prevented from floating at the flip point.

[0094] The flip point refers to the moment when the third signal BOOT_CHG_OFF flips from the first level to the second level. For example, the first level is a high level and the second level is a low level. For another example, the first level is a low level and the second level is a high level.

[0095] Based on the description of the above embodiment, a possible implementation of the hysteresis current output circuit 116 is exemplified. Figure 2 As shown, the hysteresis current output circuit 116 may include: a first P-type transistor MP1, a second P-type transistor MP2, and a third P-type transistor MP3.

[0096] The source of the first P-type transistor MP1 and the source of the second P-type transistor MP2 are both electrically connected to the positive voltage power supply, the gate of the first P-type transistor MP1, the gate and the drain of the second P-type transistor MP2 are all used to connect to the first bias current IB1, the source of the first P-type transistor MP1 is electrically connected to the source of the third P-type transistor MP3, the gate of the third P-type transistor MP3 is electrically connected to the second output terminal of the control circuit 120, and the drain of the third P-type transistor MP3 is electrically connected to the output terminal of the pull-up current output circuit 112.

[0097] The source of the first P-type transistor MP1 and the source of the second P-type transistor MP2 are both input terminals of the hysteresis current output circuit 116 , and the drain of the third P-type transistor MP3 is the output terminal of the hysteresis current output circuit 116 .

[0098] The first P-type transistor MP1, the second P-type transistor MP2 and the third P-type transistor MP3 may be metal-oxide semiconductor field effect transistors or gallium nitride transistors, which are not specifically limited in the embodiment of the present application.

[0099] Based on the description of the above embodiment, a possible implementation of the voltage detection circuit 111 is exemplified. Figure 2 As shown, the voltage detection circuit 111 may include: a first N-type transistor MN1, a second N-type transistor MN2 and a first resistor R1.

[0100] The drain and gate of the first N-type transistor MN1 are electrically connected to the upper plate of the bootstrap capacitor CBST, the source of the first N-type transistor MN1 is electrically connected to the drain of the second N-type transistor MN2 and the gate of the second N-type transistor MN2 respectively, the source of the second N-type transistor MN2 is electrically connected to the first end of the first resistor R1, the control end of the pull-down current output circuit 113 is electrically connected between the source of the second N-type transistor MN2 and the first end of the first resistor R1, and the second end of the first resistor R1 is electrically connected to the lower plate of the bootstrap capacitor CBST.

[0101] Among them, the drain of the first N-type transistor MN1 and the gate of the second N-type transistor MN2 are both the first input terminals of the voltage detection circuit 111, the second end of the first resistor R1 is the second input terminal of the voltage detection circuit 111, and the output terminal of the voltage detection circuit 111 is located between the source of the second N-type transistor MN2 and the first end of the first resistor R1.

[0102] The first N-type transistor MN1 and the second N-type transistor MN2 may be metal-oxide semiconductor field effect transistors or gallium nitride transistors, which are not specifically limited in the embodiment of the present application.

[0103] Based on the description of the above embodiment, a possible implementation of the clamping circuit 115 is exemplified. Figure 2 As shown, the clamp circuit 115 may include: a diode Z0, a second resistor R2, and a third N-type transistor MN3.

[0104] The cathode of the diode Z0 is electrically connected to the upper plate of the bootstrap capacitor CBST, the anode of the diode Z0 is electrically connected to the first end of the second resistor R2, the second end of the second resistor R2 and the source of the third N-type transistor MN3 are both electrically connected to the lower plate of the bootstrap capacitor CBST, the gate of the third N-type transistor MN3 is electrically connected between the anode of the diode Z0 and the first end of the second resistor R2, and the drain of the third N-type transistor MN3 is electrically connected to the output end of the pull-down current output circuit 113.

[0105] The cathode of the diode Z0 is the first input terminal of the clamp circuit 115 , the second terminal of the second resistor R2 is the second input terminal of the clamp circuit 115 , and the drain of the third N-type transistor MN3 is the output terminal of the clamp circuit 115 .

[0106] The clamping voltage is the clamping voltage of the diode Z0.

[0107] The third N-type transistor MN3 may be a metal-oxide semiconductor field effect transistor or a gallium nitride transistor, which is not specifically limited in the embodiment of the present application.

[0108] Based on the description of the above embodiment, a possible implementation of the third signal output circuit 114 is exemplified. Figure 2 As shown, the third signal output circuit 114 may include: a fourth P-type transistor MP4 and a buffer BUF.

[0109] The source of the fourth P-type transistor MP4 is electrically connected to the positive voltage power supply, the gate of the fourth P-type transistor MP4 is electrically connected between the output end of the pull-down current output circuit 113 and the output end of the pull-up current output circuit 112, the drain of the fourth P-type transistor MP4 and the input end of the buffer BUF are both used to access the second bias current IB2, and the output end of the buffer BUF is electrically connected to the first input end of the control circuit 120.

[0110] The gate of the fourth P-type transistor MP4 is the control terminal of the third signal output circuit 114 , the source of the fourth P-type transistor MP4 is the input terminal of the third signal output circuit 114 , and the output terminal of the buffer BUF is the output terminal of the third signal output circuit 114 .

[0111] The fourth P-type transistor MP4 may be a metal-oxide semiconductor field effect transistor or a gallium nitride transistor, which is not specifically limited in the embodiment of the present application.

[0112] Based on the description of the above embodiment, a possible implementation of the pull-up current output circuit 112 is exemplified. Figure 2 As shown, the pull-up current output circuit 112 may include: a fifth P-type transistor MP5.

[0113] The source of the fifth P-type transistor MP5 is electrically connected to the positive voltage power supply, the gate of the fifth P-type transistor MP5 is used to access the first bias current IB1 , and the drain of the fifth P-type transistor MP5 is electrically connected to the output end of the pull-down current output circuit 113 .

[0114] The source of the fifth P-type transistor MP5 is the input terminal of the pull-up current output circuit 112 , the gate of the fifth P-type transistor MP5 is the control terminal of the pull-up current output circuit 112 , and the drain of the fifth P-type transistor MP5 is the output terminal of the pull-up current output circuit 112 .

[0115] The fifth P-type transistor MP5 may be a metal-oxide semiconductor field effect transistor or a gallium nitride transistor, which is not specifically limited in the embodiment of the present application.

[0116] Based on the description of the above embodiment, another possible implementation of the pull-up current output circuit 112 is exemplified. Figure 2 As shown, the pull-up current output circuit 112 may further include: a sixth P-type transistor MP6 and a fourth N-type transistor MN4.

[0117] The source of the sixth P-type transistor MP6 is electrically connected to the drain of the sixth P-type transistor MP6, the gate of the sixth P-type transistor MP6 is grounded, the drain of the sixth P-type transistor MP6 is electrically connected to the source and gate of the fourth N-type transistor MN4 respectively, and the drain of the fourth N-type transistor MN4 is electrically connected to the output end of the pull-down current output circuit 113.

[0118] The sixth P-type transistor MP6 has a relatively high withstand voltage, and therefore, the sixth P-type transistor MP6 is a high-voltage transistor for withstanding high voltage.

[0119] The sixth P-type transistor MP6 may be a metal-oxide semiconductor field effect transistor or a gallium nitride transistor, which is not specifically limited in the embodiment of the present application.

[0120] The fourth N-type transistor MN4 is, for example, a metal-oxide semiconductor field effect transistor.

[0121] When the high-side power transistor HS is turned on, the voltage of the switch node SW is approximately the input voltage VIN of the buck-boost converter 1000. In this way, the upper plate voltage of the bootstrap capacitor CBST, that is, the voltage at the BOOT terminal, is the input voltage VIN and the voltage across the bootstrap capacitor CBST. Since the voltage of the switch node SW and the voltage at the BOOT terminal are higher than the power supply voltage VDD in some applications, the body diode of the fourth N-type transistor MN4, that is, the parasitic PN junction of the fourth N-type transistor MN4, can effectively prevent the charge in the bootstrap capacitor CBST from backflowing into the power supply voltage VDD.

[0122] Based on the description of the above embodiment, a possible implementation of the pull-down current output circuit 113 is exemplified. Figure 2 As shown, the pull-down current output circuit 113 may include: a fifth N-type transistor MN5.

[0123] The drain of the fifth N-type transistor MN5 is electrically connected to the output end of the pull-up current output circuit 112, the gate of the fifth N-type transistor MN5 is electrically connected to the output end of the voltage detection circuit 111, and the source of the fifth N-type transistor MN5 is electrically connected to the lower plate of the bootstrap capacitor CBST.

[0124] The source of the fifth N-type transistor MN5 is the input terminal of the pull-down current output circuit 113 , the gate of the fifth N-type transistor MN5 is the control terminal of the pull-down current output circuit 113 , and the drain of the fifth N-type transistor MN5 is the output terminal of the pull-down current output circuit 113 .

[0125] The fifth N-type transistor MN5 may be a metal-oxide semiconductor field effect transistor or a gallium nitride transistor, which is not specifically limited in the embodiment of the present application.

[0126] Based on the description of the above embodiment, a possible implementation of the control circuit 120 is exemplified. Figure 2 As shown, the control circuit 120 may include: a delay device 121 , a first AND gate device 123 , a second AND gate device 125 , a NAND gate device 122 , a NOR gate device 126 , a first inverter 124 and a second inverter 127 .

[0127] The input end of the delay device 121 is used to access the first signal LSON_FB, the output end of the delay device 121 is electrically connected to the first input end of the first AND gate device 123 and the first input end of the NAND gate device 122 respectively, the second input end of the NAND gate device 122 and the input end of the first inverter 124 are both electrically connected to the output end of the detection circuit 110, the output end of the NAND gate device 122 is electrically connected to the second input end of the first AND gate device 123, the output end of the first AND gate device 123 is electrically connected to the first input end of the NOR gate device 126, the output end of the second inverter 127 is electrically connected to the first input end of the second AND gate device 125, the second input end of the second AND gate device 125 is used to access the second signal HZ, the output end of the second AND gate device 125 is electrically connected to the second input end of the NOR gate device 126, the output end of the NOR gate device 126 is electrically connected to the input end of the second inverter 127, and the output end of the second inverter 127 is electrically connected to the control end of the charging circuit 130.

[0128] Among them, the second input end of the NAND gate device 122 and the input end of the first inverter 124 are both the first input end of the control circuit 120, the input end of the delay device 121 is the second input end of the control circuit 120, the second input end of the second AND gate device 125 is the third input end of the control circuit 120, the output end of the second inverter 127 is the second input end of the control circuit 120, the output end of the second inverter 127 is the first output end of the control circuit 120, and the output end of the NOR gate device 126 is the first output end of the control circuit 120.

[0129] The first AND gate device 123 and the second AND gate device 125 perform an AND operation, the NAND gate device 122 performs a NAND operation, and the NOR gate device 126 performs a NOR operation.

[0130] Based on the description of the above embodiment, a possible implementation of the charging circuit 130 is exemplified. Figure 2 As shown, the charging circuit 130 may include: a switch circuit 131, a charging tube MP0 and a field effect transistor MN0.

[0131] The control end of the switch circuit 131 is electrically connected to the first output end of the control circuit 120, the first end of the switch circuit 131 and the source of the charging tube MP0 are both electrically connected to the positive voltage power supply, the second end of the switch circuit 131 is electrically connected to the gate of the charging tube MP0, the drain of the charging tube MP0 is electrically connected to the gate of the field effect transistor MN0 and the source of the field effect transistor MN0 respectively, and the drain of the field effect transistor MN0 is electrically connected to the upper plate of the bootstrap capacitor CBST.

[0132] Among them, the control end of the switch circuit 131 is the control end of the charging circuit 130, the first end of the switch circuit 131 and the source of the charging tube MP0 are both input ends of the charging circuit 130, and the drain of the field effect transistor MN0 is the output end of the charging circuit 130.

[0133] The preset voltage is the sum of the gate-source voltage of the first N-type transistor MN1 , the gate-source voltage of the second N-type transistor MN2 , and the gate-source voltage of the fifth N-type transistor MN5 .

[0134] The switch circuit 131 can control the charging tube MP0 to turn on according to the fourth signal EN_CHG, so that the power supply voltage VDD charges the bootstrap capacitor CBST through the body diode of the field effect transistor MN0, that is, the parasitic PN junction of the field effect transistor MN0. Thus, the charging circuit 130 can charge the bootstrap capacitor CBST through the parasitic PN junction of the field effect transistor MN0.

[0135] In summary, the switch circuit can control the charging tube to turn on according to the fourth signal, so that the power supply voltage charges the bootstrap capacitor through the body diode of the field effect transistor. Thus, the charging circuit charges the bootstrap capacitor according to the fourth signal.

[0136] Based on the description of the above embodiment, a possible implementation of the switch circuit 131 is exemplified. Figure 2 As shown, the switch circuit 131 may include: a seventh P-type transistor MP7 and a sixth N-type transistor MN6.

[0137] The gate of the seventh P-type transistor MP7 and the gate of the sixth N-type transistor MN6 are both electrically connected to the output end of the control circuit 120, the source of the seventh P-type transistor MP7 is electrically connected to the positive voltage power supply, the drain of the seventh P-type transistor MP7 is electrically connected to the drain of the sixth N-type transistor MN6, the gate of the charging tube MP0 is electrically connected between the drain of the seventh P-type transistor MP7 and the drain of the sixth N-type transistor MN6, and the source of the sixth N-type transistor MN6 is grounded.

[0138] Among them, the gate of the seventh P-type transistor MP7 and the gate of the sixth N-type transistor MN6 are both control terminals of the switch circuit 131, the source of the seventh P-type transistor MP7 is the first terminal of the switch circuit 131, and the second terminal of the switch circuit 131 is located between the drain of the seventh P-type transistor MP7 and the drain of the sixth N-type transistor MN6.

[0139] The seventh P-type transistor MP7 and the sixth N-type transistor MN6 may be metal-oxide semiconductor field effect transistors or gallium nitride transistors, which are not specifically limited in the embodiment of the present application.

[0140] The working principle of the bootstrap capacitor charging circuit 100 is described in detail below.

[0141] When the buck-boost converter 1000 enters the high-impedance stage, when the voltage across the bootstrap capacitor CBST is lower than the preset voltage, the voltage across the first resistor R1 is smaller after the voltage across the bootstrap capacitor CBST is subtracted from the voltage across the first N-type transistor MN1 and the voltage across the second N-type transistor MN2, so that the current capacity generated by the fifth N-type transistor MN5 is smaller than the current capacity generated by the fifth P-type transistor MP5. In this way, the potential of the drain of the fifth P-type transistor MP5 will be pulled to a high level, so that the fourth P-type transistor MP4 is turned off, and the third signal BOOT_CHG_OFF is flipped to a low level.

[0142] Since the second signal HZ is at a high level, the first signal LSON_FB is at a low level, and the third signal BOOT_CHG_OFF is at a low level when the buck-boost converter 1000 enters the high impedance stage, the fourth signal EN_CHG is at a high level, and the fifth signal CHG_Z is at a low level. In this way, the seventh P-type transistor MP7 is turned off, the sixth N-type transistor MN6 is turned on, and the control charging tube MP0 is turned on, so that the power supply voltage VDD charges the bootstrap capacitor CBST through the body diode of the field effect transistor MN0.

[0143] In addition, if the buck-boost converter 1000 operates in the high impedance stage for a long time, the voltage across the bootstrap capacitor CBST is charged to VDD-VBD0 at the highest, where VDD is the power supply voltage and VBD0 is the forward voltage drop of the body diode of the field effect transistor MN0.

[0144] At the same time, the fifth signal CHG_Z is at a low level, turning on the third P-type transistor MP3, so that a hysteresis current is provided to the drain of the fifth P-type transistor MP5. In this way, under the effect of the hysteresis current, the current value of the pull-up current is increased, so that the third signal BOOT_CHG_OFF is kept constant, and the third signal BOOT_CHG_OFF is prevented from floating at the flip point.

[0145] When the voltage across the bootstrap capacitor CBST is charged to a preset voltage, the current capability generated by the fifth N-type transistor MN5 is greater than the current capability generated by the fifth P-type transistor MP5. In this way, the potential of the drain of the fifth P-type transistor MP5 will be pulled to a low level, turning on the fourth P-type transistor MP4, causing the third signal BOOT_CHG_OFF to flip to a high level. In this way, the fourth signal EN_CHG is at a low level, the seventh P-type transistor MP7 is turned on, and the sixth N-type transistor MN6 is turned off, causing the control charging tube MP0 to be turned off, so that the power supply voltage VDD stops charging the bootstrap capacitor CBST.

[0146] In addition, when the voltage across the bootstrap capacitor CBST reaches the clamping voltage of the diode Z0, the third N-type transistor MN3 is turned on to pull down the potential of the source of the sixth P-type transistor MP6, that is, the potential of the drain of the fifth P-type transistor MP5 is pulled down, so that the fourth P-type transistor MP4 is turned on, so that the third signal BOOT_CHG_OFF is flipped to a high level. In this way, the fourth signal EN_CHG is at a low level, the seventh P-type transistor MP7 is turned on, and the sixth N-type transistor MN6 is turned off, so that the control charging tube MP0 is turned off, so that the power supply voltage VDD stops charging the bootstrap capacitor CBST. Thereby, it is possible to prevent the voltage across the bootstrap capacitor CBST from being too large, causing damage to the subsequent circuit.

[0147] Based on this, theoretically, the voltage across the bootstrap capacitor CBST is controlled to be the sum of the gate-source voltage of the fifth N-type transistor MN5 , the gate-source voltage of the first N-type transistor MN1 , and the gate-source voltage of the second N-type transistor MN2 .

[0148] When the high-side power transistor HS is turned on, in some applications, the voltage of the switch node SW and the voltage of the BOOT terminal will be higher than the power supply voltage VDD, and the body diode of the field effect transistor MN0 and the body diode of the fourth N-type transistor MN4 can effectively prevent the charge in the bootstrap capacitor CBST from flowing back to the power supply voltage VDD. In addition, since the drain voltage of the fourth N-type transistor MN4 may be higher than the source voltage of the fourth N-type transistor MN4, no current flows through the fourth N-type transistor MN4, so that the potential of the source of the sixth P-type transistor MP6 will be pulled to a high level, so that the third signal BOOT_CHG_OFF is a low level.

[0149] In this way, the third signal BOOT_CHG_OFF is shielded by the delayed signal of the first signal LSON_FB. Furthermore, every time the low-side power transistor LS is just turned on, the fourth signal EN_CHG signal is prevented from being at a high level and lasting for a period of time, so that the charging tube MP0 is turned off. Thus, it is possible to prevent the voltage at both ends of the bootstrap capacitor CBST from increasing uncontrollably cycle by cycle. Otherwise, no matter how high the voltage at both ends of the bootstrap capacitor CBST is, every time the low-side power transistor LS is just turned on, the fourth signal EN_CHG will be at a high level and last for a period of time, so that the charging tube MP0 is turned on. Thus, the voltage at both ends of the bootstrap capacitor CBST will increase uncontrollably cycle by cycle.

[0150] When the low-side power transistor LS is turned on, when the voltage across the bootstrap capacitor CBST is low, the voltage across the first resistor R1 is smaller after the voltage across the bootstrap capacitor CBST is subtracted from the voltage across the first N-type transistor MN1 and the voltage across the second N-type transistor MN2, so that the current capacity generated by the fifth N-type transistor MN5 is smaller than the current capacity generated by the fifth P-type transistor MP5. In this way, the potential of the drain of the fifth P-type transistor MP5 will be pulled to a high level, so that the fourth P-type transistor MP4 is turned off, and the third signal BOOT_CHG_OFF is flipped to a low level.

[0151] Since when the low-side power transistor LS is turned on, the second signal HZ is at a low level, the first signal LSON_FB is at a high level, and the third signal BOOT_CHG_OFF is at a low level. Therefore, the fourth signal EN_CHG is at a high level. In this way, the seventh P-type transistor MP7 is turned off, the sixth N-type transistor MN6 is turned on, and the control charging tube MP0 is turned on, so that the power supply voltage VDD charges the bootstrap capacitor CBST through the body diode of the field effect transistor MN0.

[0152] When the voltage across the bootstrap capacitor CBST is charged high enough to make the current capacity generated by the fifth N-type transistor MN5 greater than the current capacity generated by the fifth P-type transistor MP5, the potential of the drain of the fifth P-type transistor MP5 will be pulled to a low level, turning on the fourth P-type transistor MP4, causing the third signal BOOT_CHG_OFF to flip to a high level. In this way, the fourth signal EN_CHG is at a low level, the seventh P-type transistor MP7 is turned on, the sixth N-type transistor MN6 is turned off, and the control charging tube MP0 is turned off, so that the power supply voltage VDD stops charging the bootstrap capacitor CBST.

[0153] The embodiment of the present application also provides a buck-boost converter. Figure 2 , Figure 2 The schematic diagram of the structure of a half-bridge buck-boost converter provided in an embodiment of the present application is shown in FIG. Figure 2 As shown, the buck-boost converter 1000 may include: a high-side power transistor HS, a low-side power transistor LS, an inductor L, a bootstrap capacitor CBST and a bootstrap capacitor charging circuit 100 .

[0154] The drain of the high-side power transistor HS is used to access the input voltage VIN of the buck-boost converter 1000, the source of the high-side power transistor HS is electrically connected to the drain of the low-side power transistor LS and the first end of the inductor L, respectively, the source of the low-side power transistor LS is used to output the output voltage of the buck-boost converter 1000, a switch node SW is arranged between the source of the high-side power transistor HS and the drain of the low-side power transistor LS, the upper plate of the bootstrap capacitor CBST is electrically connected to the output end of the bootstrap capacitor charging circuit 100, the lower plate of the bootstrap capacitor CBST is electrically connected to the switch node SW, the gate of the high-side power transistor HS and the gate of the low-side power transistor LS are both used to access the drive signal, the drive signal is used to drive the gate of the high-side power transistor HS and the low-side power transistor LS to turn on or off, and the second end of the inductor L is grounded.

[0155] Exemplarily, the driving signal may include: a first driving signal HSGATE and a second driving signal LSGATE, wherein the first driving signal HSGATE is used to drive the high-side power transistor HS to turn on or off, and the second driving signal LSGATE is used to drive the low-side power transistor LS to turn on or off.

[0156] When the first driving signal HSGATE is at a high level, the second driving signal LSGATE is at a low level, so that the high-side power transistor HS is turned on and the low-side power transistor LS is turned off.

[0157] When the first driving signal HSGATE is at a low level, the second driving signal LSGATE is at a high level, so that the high-side power transistor HS is turned off and the low-side power transistor LS is turned on.

[0158] In addition, since the second driving signal LSGATE and the first signal LSON_FB have different power domains, the second driving signal is represented by letters LSGATE and the first signal is represented by letters LSON_FB.

[0159] Wherein, when the low-side power transistor LS is in the on stage, the voltage of the switch node SW is approximately equal to the output voltage of the buck-boost converter 1000. At this time, the output voltage is a negative voltage. When the high-side power transistor HS is in the on stage, the voltage of the switch node SW is approximately equal to the input voltage of the buck-boost converter 1000. When the high-side power transistor HS and the low-side power transistor LS are turned off at the same time, that is, when the buck-boost converter 1000 enters the high-impedance stage, the voltage of the switch node SW is approximately the ground voltage, i.e., zero voltage.

[0160] In some embodiments, the buck-boost converter 1000 may further include a capacitor C1 , a first resistor R1 , and a second resistor R2 .

[0161] The upper plate of the capacitor C1 and the first end of the first resistor R1 are both electrically connected to the source of the low-side power transistor LS, the second end of the first resistor R1 is electrically connected to the first end of the second resistor R2, and the upper plate of the capacitor C1 and the second end of the second resistor R2 are both grounded.

[0162] The buck-boost converter provided in the embodiment of the present application has the same beneficial effects as the bootstrap capacitor charging circuit provided in the embodiment of the present application, which will not be described in detail here.

[0163] An embodiment of the present application also provides a chip, including: a bootstrap capacitor charging circuit, and / or a buck-boost converter.

[0164] Among them, the bootstrap capacitor charging circuit and the buck-boost converter can be integrated into one chip or into different chips, and the embodiments of the present application do not specifically limit this.

[0165] The chip provided in the embodiment of the present application has the same beneficial effects as the bootstrap capacitor charging circuit provided in the embodiment of the present application, which will not be described in detail here.

[0166] An embodiment of the present application also provides an electronic device, including: a chip.

[0167] In this application, electronic devices may include, but are not limited to, tablet computers, laptop computers, navigation systems, wearable devices, and smart home devices.

[0168] The electronic device provided in the embodiment of the present application has the same beneficial effects as the chip provided in the embodiment of the present application, which will not be described in detail here.

[0169] Finally, it should be noted that the above embodiments are only specific implementation methods of the present application, but the protection scope of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A bootstrap capacitor charging circuit, characterized in that: The bootstrap capacitor charging circuit is applied to a half-bridge buck-boost converter; The bootstrap capacitor charging circuit comprises: a detection circuit, a control circuit and a charging circuit; The first input end of the detection circuit and the output end of the charging circuit are both electrically connected to the upper plate of the bootstrap capacitor in the buck-boost converter, the second input end of the detection circuit is electrically connected to the lower plate of the bootstrap capacitor, the output end of the detection circuit is electrically connected to the first input end of the control circuit, the second input end of the control circuit is used to access a first signal, the first signal is used to drive the low-side power transistor in the buck-boost converter to turn on or off, the third input end of the control circuit is used to access a second signal, the second signal is used to indicate whether the buck-boost converter enters a high-resistance stage, the first output end of the control circuit is electrically connected to the control end of the charging circuit, and the input end of the charging circuit is electrically connected to a positive voltage power supply; When the buck-boost converter enters the high-resistance stage, or the low-side power transistor is in the on stage, wherein: The detection circuit is used to detect whether the voltage across the bootstrap capacitor is lower than a preset voltage, obtain a third signal, and transmit the third signal to the control circuit; The control circuit is used to perform a logic operation on the first signal, the second signal and the third signal to obtain a fourth signal, and transmit the fourth signal to the charging circuit, wherein the fourth signal is used to control the charging circuit to be turned on or off; The charging circuit is used to charge the bootstrap capacitor according to the fourth signal using the power supply voltage provided by the positive voltage power supply until the voltage across the bootstrap capacitor is higher than the preset voltage, and then stop charging.

2. The bootstrap capacitor charging circuit according to claim 1, characterized in that: The detection circuit comprises: a voltage detection circuit, a pull-up current output circuit, a pull-down current output circuit and a third signal output circuit; The first input end of the voltage detection circuit is electrically connected to the upper plate of the bootstrap capacitor, the second input end of the voltage detection circuit and the input end of the pull-down current output circuit are both electrically connected to the lower plate of the bootstrap capacitor, the output end of the voltage detection circuit is electrically connected to the control end of the pull-down current output circuit, the output end of the pull-down current output circuit is electrically connected to the output end of the pull-up current output circuit, the input end of the pull-up current output circuit and the input end of the third signal output circuit are both electrically connected to the positive voltage power supply, the control end of the pull-up current output circuit is used to access the first bias current, the control end of the third signal output circuit is electrically connected between the output end of the pull-down current output circuit and the output end of the pull-up current output circuit, and the output end of the third signal output circuit is electrically connected to the first input end of the control circuit; The pull-up current output circuit is used to generate a pull-up current according to the power supply voltage under the action of the first bias current, and transmit the pull-up current to the third signal output circuit; The voltage detection circuit is used to detect whether the voltage across the bootstrap capacitor is lower than the preset voltage, obtain a control voltage, and transmit the control voltage to the pull-down current output circuit; The pull-down current output circuit is used to generate a pull-down current under the action of the first control voltage, and transmit the pull-down current to the third signal output circuit; The third signal output circuit is used to determine whether to pull up or down the potential of the control terminal of the third signal output circuit according to the magnitude relationship between the pull-up capability of the pull-up current and the pull-down capability of the pull-down current to generate the third signal.

3. The bootstrap capacitor charging circuit according to claim 2, characterized in that: The detection circuit further includes: a clamping circuit; The first input terminal of the clamp circuit is electrically connected to the upper plate of the bootstrap capacitor, the second input terminal of the clamp circuit is electrically connected to the lower plate of the bootstrap capacitor, and the output terminal of the clamp circuit is electrically connected to the output terminal of the pull-down current output circuit; The clamping circuit is used to pull up the potential of the control end of the third signal output circuit when the voltage across the bootstrap capacitor is equal to the clamping voltage, so as to clamp the voltage across the bootstrap capacitor to the clamping voltage.

4. The bootstrap capacitor charging circuit according to claim 2, characterized in that: The detection circuit also includes: a hysteresis current output circuit; The input end of the hysteresis current output circuit is electrically connected to the positive voltage power supply, the control end of the hysteresis current output circuit is electrically connected to the second output end of the control circuit, and the output end of the hysteresis current output circuit is electrically connected to the output end of the pull-up current output circuit; The hysteresis current output circuit is used to obtain a fifth signal from the control circuit, and under the action of the fifth signal, generate the hysteresis current according to the power supply voltage, and transmit the hysteresis current to the pull-up current output circuit, and the level of the fifth signal is opposite to the level of the fourth signal; The pull-up current output circuit is used to increase the current value of the pull-up current under the action of the hysteresis current so as to keep the third signal constant and avoid the third signal floating at a flip point, wherein the flip point refers to the moment when the third signal flips from the first level to the second level.

5. The bootstrap capacitor charging circuit according to claim 4, characterized in that: The hysteresis current output circuit comprises: a first P-type transistor, a second P-type transistor and a third P-type transistor; The source of the first P-type transistor and the source of the second P-type transistor are both electrically connected to the positive voltage power supply, the gate of the first P-type transistor, the gate and the drain of the second P-type transistor are all used to connect to the first bias current, the source of the first P-type transistor is electrically connected to the source of the third P-type transistor, the gate of the third P-type transistor is electrically connected to the second output terminal of the control circuit, and the drain of the third P-type transistor is electrically connected to the output terminal of the pull-up current output circuit.

6. The bootstrap capacitor charging circuit according to claim 2, characterized in that: The voltage detection circuit includes: a first N-type transistor, a second N-type transistor and a first resistor; The drain and gate of the first N-type transistor are both electrically connected to the upper plate of the bootstrap capacitor, the source of the first N-type transistor is electrically connected to the drain and gate of the second N-type transistor, respectively, the source of the second N-type transistor is electrically connected to the first end of the first resistor, the control end of the pull-down current output circuit is electrically connected between the source of the second N-type transistor and the first end of the first resistor, and the second end of the first resistor is electrically connected to the lower plate of the bootstrap capacitor.

7. The bootstrap capacitor charging circuit according to claim 3, characterized in that: The clamping circuit comprises: a diode, a second resistor and a third N-type transistor; The cathode of the diode is electrically connected to the upper plate of the bootstrap capacitor, the anode of the diode is electrically connected to the first end of the second resistor, the second end of the second resistor and the source of the third N-type transistor are both electrically connected to the lower plate of the bootstrap capacitor, the gate of the third N-type transistor is electrically connected between the anode of the diode and the first end of the second resistor, and the drain of the third N-type transistor is electrically connected to the output end of the pull-down current output circuit.

8. The bootstrap capacitor charging circuit according to claim 2, characterized in that: The third signal output circuit includes: a fourth P-type transistor and a buffer; The source of the fourth P-type transistor is electrically connected to the positive voltage power supply, the gate of the fourth P-type transistor is electrically connected between the output end of the pull-down current output circuit and the output end of the pull-up current output circuit, the drain of the fourth P-type transistor and the input end of the buffer are both used to access the second bias current, and the output end of the buffer is electrically connected to the first input end of the control circuit.

9. The bootstrap capacitor charging circuit according to claim 2, characterized in that: The pull-up current output circuit comprises: a fifth P-type transistor; The source of the fifth P-type transistor is electrically connected to the positive voltage power supply, the gate of the fifth P-type transistor is used to access the first bias current, and the drain of the fifth P-type transistor is electrically connected to the output end of the pull-down current output circuit.

10. The bootstrap capacitor charging circuit according to claim 9, characterized in that: The pull-up current output circuit further includes: a sixth P-type transistor and a fourth N-type transistor; The source of the sixth P-type transistor is electrically connected to the drain of the sixth P-type transistor, the gate of the sixth P-type transistor is grounded, the drain of the sixth P-type transistor is electrically connected to the source and gate of the fourth N-type transistor respectively, and the drain of the fourth N-type transistor is electrically connected to the output end of the pull-down current output circuit.

11. The bootstrap capacitor charging circuit according to claim 2, characterized in that: The pull-down current output circuit comprises: a fifth N-type transistor; The drain of the fifth N-type transistor is electrically connected to the output end of the pull-up current output circuit, the gate of the fifth N-type transistor is electrically connected to the output end of the voltage detection circuit, and the source of the fifth N-type transistor is electrically connected to the lower plate of the bootstrap capacitor.

12. The bootstrap capacitor charging circuit according to any one of claims 1 to 11, characterized in that: The control circuit comprises: a delay device, a first AND gate device, a second AND gate device, a NAND gate device, a NOR gate device, a first inverter and a second inverter; The input end of the delay device is used to access the first signal, the output end of the delay device is electrically connected to the first input end of the first AND gate device and the first input end of the NAND gate device respectively, the second input end of the NAND gate device and the input end of the first inverter are both electrically connected to the output end of the detection circuit, the output end of the NAND gate device is electrically connected to the second input end of the first AND gate device, the output end of the first AND gate device is electrically connected to the first input end of the NOR gate device, the output end of the second inverter is electrically connected to the first input end of the second AND gate device, the second input end of the second AND gate device is used to access the second signal, the output end of the second AND gate device is electrically connected to the second input end of the NOR gate device, the output end of the NOR gate device is electrically connected to the input end of the second inverter, and the output end of the second inverter is electrically connected to the control end of the charging circuit.

13. The bootstrap capacitor charging circuit according to any one of claims 1 to 11, characterized in that: The charging circuit comprises: a switch circuit, a charging tube and a field effect transistor; The control end of the switch circuit is electrically connected to the first output end of the control circuit, the first end of the switch circuit and the source of the charging tube are both electrically connected to the positive voltage power supply, the second end of the switch circuit is electrically connected to the gate of the charging tube, the drain of the charging tube is electrically connected to the gate and source of the field effect transistor respectively, and the drain of the field effect transistor is electrically connected to the upper plate of the bootstrap capacitor; The switch circuit is used to control the charging tube to turn on according to the fourth signal, so that the power supply voltage charges the bootstrap capacitor through the body diode of the field effect transistor.

14. The bootstrap capacitor charging circuit according to claim 13, characterized in that: The switch circuit includes: a seventh P-type transistor and a sixth N-type transistor; The gate of the seventh P-type transistor and the gate of the sixth N-type transistor are both electrically connected to the first output terminal of the control circuit, the source of the seventh P-type transistor is electrically connected to the positive voltage power supply, the drain of the seventh P-type transistor is electrically connected to the drain of the sixth N-type transistor, the gate of the charging tube is electrically connected between the drain of the seventh P-type transistor and the drain of the sixth N-type transistor, and the source of the sixth N-type transistor is grounded.

15. A half-bridge buck-boost converter, characterized in that: include: A high-side power transistor, a low-side power transistor, an inductor, a bootstrap capacitor and a bootstrap capacitor charging circuit as claimed in any one of claims 1 to 14; The drain of the high-side power transistor is used to access the input voltage of the buck-boost converter, the source of the high-side power transistor is electrically connected to the drain of the low-side power transistor and the first end of the inductor respectively, the source of the low-side power transistor is used to output the output voltage of the buck-boost converter, a switch node is arranged between the source of the high-side power transistor and the drain of the low-side power transistor, the upper plate of the bootstrap capacitor is electrically connected to the output end of the bootstrap capacitor charging circuit, the lower plate of the bootstrap capacitor is electrically connected to the switch node, the gate of the high-side power transistor and the gate of the low-side power transistor are both used to access the drive signal, the drive signal is used to drive the gate of the high-side power transistor and the low-side power transistor to turn on or off, and the second end of the inductor is grounded.

16. A chip, characterized in that: include: The bootstrap capacitor charging circuit according to any one of claims 1 to 14, and / or the buck-boost converter according to claim 15.

17. An electronic device, characterized in that: include: The chip as claimed in claim 16.

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