Actuating circuit for power semiconductor component having transmission circuit and associated method

Abstract

The invention relates to an actuation circuit for a power semiconductor component having a transmission circuit for transmitting a signal from an input side to an output side, the transmission circuit having a transmitter, and a related method. The transmitter has two branches having a capacitive coupling between the input side and the output side. An input signal is applied to the first high voltage capacitor. The input signal is applied to the second high-voltage capacitor in an inverted manner. The secondary side terminals of the two high voltage capacitors are connected to the first and second input terminals of the comparator. An inverted output terminal of the comparator is connected to an input of the first voltage divider circuit. In each of the first and second sub-branches of the first voltage divider circuit, it is provided that a switch is arranged in parallel with a resistor and in series with a further resistor such that the switch of the second sub-branch is switched push-pull with the switch of the first sub-branch. The first voltage divider circuit is connected with the first input end of the comparator. The second voltage divider circuit is connected with the second input end of the comparator.

Description

Technical Field

[0001] The invention describes a control circuit having a transmission circuit for transmitting a signal from an input side to an output side, the input side and the output side having different potentials, respectively. Isolation of at least two different potentials is ensured in a capacitive manner by high-voltage capacitors on the primary side and the secondary side. Background Art

[0002] DE 10 2010 018 997 B4 discloses a control device for controlling a power semiconductor switch, the control device having a monolithically integrated control circuit, which controls the power semiconductor switch. A disadvantage of this is that two transmission branches are required, namely an opening (ON) transmission branch and a closing (OFF) transmission branch. The two transmission branches are each composed of two sub-branches and are each connected to a comparator. Summary of the invention

[0003] In view of this fact, the object of the present invention is to specify a simplified control circuit with a transmission circuit and an associated method, in which signals are conducted and transmitted in a permanent and self-sustaining manner.

[0004] According to the present invention, this object is achieved by a drive circuit having a transmission circuit, the transmission circuit being used to transmit a signal from an input side having a first reference potential to an output side having a second reference potential, the transmission circuit having a transmitter, the transmitter having a capacitive coupling between an input side and an output side, wherein the transmitter has two branches, namely a first transmission branch and a second transmission branch, wherein the capacitive coupling between the input side and the output side is implemented by a first high-voltage capacitor and a second high-voltage capacitor, the first high-voltage capacitor and the second high-voltage capacitor respectively forming a series circuit with the assigned first and second output side capacitors, wherein the input side terminal of the first high-voltage capacitor is configured to apply an input signal to the first high-voltage capacitor in a non-inverted manner, and the input side terminal of the second high-voltage capacitor is configured to apply an input signal to the second high-voltage capacitor in an inverted manner. , wherein the secondary-side terminal of the first high-voltage capacitor is connected to the first input of the comparator, and the secondary-side terminal of the second high-voltage capacitor is connected to the second input of the comparator, wherein the preferably inverted output terminal of the comparator constitutes the output of the drive circuit and is connected to the first input of the first voltage divider circuit, wherein the first output of the first voltage divider circuit is connected to the first input of the comparator, wherein the first voltage divider circuit has a first sub-branch and a second sub-branch, the first sub-branch has a parallel circuit consisting of a first resistor and a first switch and a second resistor connected in series therewith, the second sub-branch has a third resistor and a parallel circuit consisting of a fourth resistor and a second switch connected in series, wherein the first voltage divider circuit is configured for push-pull switching of the first and second switches, and wherein the second voltage divider circuit is connected to the second input of the comparator. The drive circuit has the following features.

[0005] Preferably, the capacitance value of each output-side capacitor is several times higher than the capacitance value of the respectively associated high-voltage capacitor.

[0006] It may also be preferred if the two voltage divider circuits are each connected to the same voltage source terminal.

[0007] It may be advantageous that the second voltage divider circuit has a first sub-branch and a second sub-branch, the first sub-branch having a parallel circuit consisting of an additional first resistor and an additional first switch and an additional second resistor connected in series therewith, the second sub-branch having an additional third resistor and a parallel circuit consisting of an additional fourth resistor and an additional second switch connected in series, and the first voltage divider circuit is constructed for push-pull switching of the additional first switch and the additional second switch.

[0008] It may also be preferred if the respective first switch is designed as an n-type MOS transistor and the respective second switch is designed as a p-type MOS transistor, or vice versa.

[0009] In this case, it can be advantageous if the inverting output of the comparator is connected to the signal evaluation circuit.

[0010] It may also be preferred that the components are monolithically integrated in a high voltage integrated circuit.

[0011] Furthermore, it may be advantageous if the second resistors and the third resistors are each formed by a single resistor or by a series circuit of a plurality of resistors, which preferably each have the same resistance value.

[0012] The object is also achieved by a method for operating a drive control circuit, wherein an output signal of a comparator on the secondary side is permanently applied to an input of a first voltage divider circuit, whereby a first output signal of the first voltage divider circuit has a first level value corresponding to a first switching state, and by applying an input signal on the primary side corresponding to a second switching state to the input and by transmitting the input signal on the primary side with the aid of a high-voltage capacitor, a voltage pulse is applied to two inputs of the comparator, respectively, which voltage pulse inverts a voltage difference at the two inputs of the comparator and thereby inverts an output of the comparator.

[0013] In this case, it can be advantageous if the respective voltage pulse is greater than the voltage difference at the two inputs of the comparator in static operation.

[0014] It may also be preferred that the two switches of the first voltage divider change their respective switching state by inverting the output of the comparator.

[0015] The term “connection” is to be understood as an electrically conductive connection which connects two components or parts to one another and is suitable for conducting required voltages and currents.

[0016] It should be understood that the different designs of the present invention, whether or not they are mentioned in conjunction with the drive control circuit or the method, can be implemented individually or in any combination to achieve improvements. In particular, the features mentioned and explained above and below can be used not only in the described combination, but also in other combinations or alone without departing from the scope of the present invention.

[0017] Further explanations, advantageous details and features of the present invention are given below in the following description of the present invention. Figures 1 to 4 The following is a description of the schematically illustrated embodiments or corresponding parts. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A block diagram of an important part of a first drive control circuit according to the present invention having a transmission circuit is shown;

[0019] Figure 2The basic circuit of the first driving circuit according to the present invention having a transmission circuit is shown;

[0020] Figure 3 shows selected switching elements;

[0021] Figure 4 The simulation results of the first design of the driving control circuit according to the present invention and the method according to the present invention are shown;

[0022] Figure 5 Simulation results for a second embodiment of the control circuit according to the invention and of the method according to the invention are shown. DETAILED DESCRIPTION

[0023] Figure 1 In order to explain the present invention, a block diagram of a control circuit D and a half-bridge circuit H driven thereby are shown. The control circuit D is composed of an input signal processing mechanism Y1, which is conductively connected to the first control sub-circuit Y2 and the second control sub-circuit Y3 and provides them with a processed input signal IN. The first control sub-circuit Y2 has a first signal amplifier A1 of a first transmission branch Z1 and a second signal amplifier A2 of a second transmission branch Z2, which are connected in parallel to each other. The dot-dash line marks the boundary between the primary side Y5 and the secondary side Y6 of the control circuit. The input signal is transmitted from the primary side to the secondary side via the two transmission branches Z1 and Z2.

[0024] The output ends of the two transmission branches Z1 and Z2 are conductively connected to the comparator K1. The output ends OUT of the two drive control sub-circuits Y2 and Y3 are respectively connected to the assigned drive circuits PD1 and PD2. The two drive circuits PD1 and PD2 are connected to the drive control input ends of the assigned first power switch P1 or second power switch P2, and the first power switch and the second power switch together constitute a half-bridge circuit H. The first signal evaluation circuit PD1 is connected to the first reference potential G1, and the first reference potential is consistent with the reference potential of the primary side in this embodiment. The second signal evaluation circuit PD2 has a floating second reference potential G2. The two power switches P1 and P2 are connected in parallel to each other and have a center tap Y4. The internal structure of the two transmission branches Z1 and Z2 is Figure 2 Shown in.

[0025] Figure 2A driving circuit with a transmission circuit according to the present invention is shown. The signal input end of the input signal IN is shown in the upper part. This signal input end is connected to the first signal amplifier A1 and the second signal amplifier A2, and the supply voltage terminals V5 and V6 of the signal amplifier are also shown. The first signal amplifier A1 is assigned to the first transmission branch Z1, and the second signal amplifier A2 with an inverted output end is assigned to the second transmission branch Z2. The output end of the first signal amplifier A1 is connected to the first contact of the first high-voltage capacitor C1. The output end of the second signal amplifier A2 is connected to the first contact of the second high-voltage capacitor C3. The circuit structure is on the primary side Y5 until the first contact of the first high-voltage capacitor C1 and the second high-voltage capacitor C3. The other circuit parts are on the secondary side Y6 through the capacitive coupling of the two high-voltage capacitors C1 and C3. The circuit is composed of the first transmission branch Z1 and the second transmission branch Z2, both of which are connected to the comparator K1.

[0026] The first transmission branch Z1 is formed by a first voltage divider circuit RS1 and a second output-side capacitor C2. The first voltage divider circuit RS1 comprises a first sub-branch, which is formed by a first switch S1 (here an n-channel MOS-FET) in parallel with a first resistor R1, which is connected with its first terminal to a voltage source V3. The second terminal of the parallel circuit is connected in series with a second resistor R2. The second terminal of the second resistor R2 is connected to the second terminal of a third resistor R3.

[0027] The second sub-branch of the first voltage divider circuit RS1 is formed by a second switch S2 (here a p-channel MOS-FET) in parallel with a fourth resistor R4, which is connected to a voltage source V4 with its first terminal. The second terminal of the parallel circuit is connected in series with a third resistor R3. The second terminal of the third resistor R3 is connected to the second terminal of the second resistor R2. There is an intermediate tap between the two resistors R2 and R3, which forms the first output terminal R12 of the first voltage divider circuit, which is connected to the first input terminal of the comparator K1. The second output side capacitor C2 is connected to the voltage source V4. The second terminal of the output side capacitor C2 is connected to the second contact of the first high-voltage capacitor C1, the first output terminal R12 of the first voltage divider circuit, and the first input terminal of the comparator K1. The output terminal of the comparator K1 is connected to the first input terminal R11 of the first voltage divider circuit RS1.

[0028] The second transmission branch Z2 is formed by the second voltage divider circuit RS2 and the fourth output side capacitor C4. The second voltage divider circuit RS2 includes a first sub-branch, which is formed by the third switch S3 in parallel with the fifth resistor R5, and the fifth resistor is connected to the voltage source V3 with its first terminal. The second terminal of the parallel circuit is connected in series with the sixth resistor R6. The second terminal of the sixth resistor R6 is connected to the second terminal of the seventh resistor R7.

[0029] The second sub-branch of the second voltage divider circuit RS2 is formed by connecting the fourth switch S4 in parallel with the eighth resistor R8, and the second resistor is connected to the voltage source V4 with its first terminal. The second terminal of the parallel circuit is connected in series with the seventh resistor R7. The second terminal of the seventh resistor R7 is connected to the second terminal of the sixth resistor R6. There is an intermediate tap between the two resistors R6 and R7, which forms the first output terminal R14 of the second voltage divider circuit, and the first output terminal is connected to the second input terminal V2 of the comparator K1. The first terminal of the fourth output side capacitor C4 is connected to the voltage source V4. The second terminal of the output side capacitor C4 is connected to the second contact portion of the third high-voltage capacitor C3 and to the first output terminal R14 of the second voltage divider circuit and the second input terminal of the comparator K1.

[0030] An inverting output terminal of the comparator K1 is connected to a first input terminal R11 of the first voltage divider circuit RS1.

[0031] The comparator K1 is connected to the voltage sources V3 and V4. The first input terminal of the comparator is connected to the first voltage divider circuit RS1. The second input terminal of the comparator is connected to the second voltage divider circuit RS2.

[0032] The resistors R1 to R8 may be present as individual resistors or may be formed by a circuit of a plurality of resistors or resistor groups having the same or different resistance values ​​so as to provide a required resistance value.

[0033] The capacitance values ​​of the two output side capacitors C2 and C4 are at least as large as the capacitance values ​​of the high voltage capacitors C1 and C3 respectively assigned. Advantageously, the capacitance values ​​of the two output side capacitors C2 and C4 are much larger than the capacitance values ​​of the high voltage capacitors C1 and C3 respectively assigned.

[0034] Ideally, the capacitance value of the two output-side capacitors C2 and C4 is approximately 20 times greater than the capacitance value of the respectively associated high-voltage capacitors C1 and C3. Figure 4 Described in more detail in .

[0035] In a simplified embodiment, the control circuit with the transmission circuit has only two switches in the first voltage divider circuit RS1. The second voltage divider circuit RS2 then has no switches and therefore does not change during operation with regard to its voltage divider ratio. The switching characteristics of this embodiment are Figure 5 Described in more detail in .

[0036] Figure 3 Three preferred designs of the power switches P1, P2, P3, and P4 of the half-bridge circuit H are shown, namely, IGBT and MOS-FET. Of course, it can also be understood as a parallel circuit of these structural elements.

[0037] Figure 4 The simulation results of the method according to the invention are shown. In the upper figure, the signal curve of the input signal IN can be seen. The input signal is at a first level at the beginning, which is a logic "0". At time t1, a switching pulse is applied and the input signal jumps to a second level corresponding to a logic "1". At time t2, the signal falls back from the second level, i.e., logic "1", to the first level which is again equivalent to a logic "0". The "logical" output signal OUT shown in the middle figure follows the input signal IN with a slight time offset in the actual implementation.

[0038] exist Figure 4 The following figure shows the voltage variation curves of the two input terminals V1 and V2 of the comparator K1 corresponding to the signal variation curve of the input signal IN in time. The voltage at the first input terminal V1 is initially at a fictitious voltage value of 2.3 V, because the first switch S1 is on and the second switch S2 is off. The voltage at the second input terminal V2 is initially at a fictitious voltage value of 2.7 V, because the third switch S3 is off and the fourth switch S4 is off. It is assumed here that the corresponding resistance values ​​of the resistors of the two voltage dividers RS1 and RS2 are set to the same size. It is also assumed that the voltage divider is symmetrical in terms of its internal resistance value.

[0039] At time t1, the voltage at the first input terminal V1 rises in a pulsed manner to a positive peak value. The voltage at the second input terminal V2 then simultaneously drops in a pulsed manner to a negative peak value. Subsequently, the voltage value at the first input terminal V1 drops to a value of 2.7 V. At the same time, the voltage value at the second input terminal V2 rises to a value of 2.3 V. The two voltage values ​​at the input terminals V1 and V2 now remain constant for a long time until a new switching process of the input signal IN occurs. Due to this second switching pulse, a voltage of 2.3 V is applied again at the first input terminal V1 after a relaxation time. At the same time, a voltage of 2.7 V is applied at the second input terminal V2 after a relaxation time. The voltage values ​​described are only used for clarification and are based on the assumption that the voltage divider is symmetrically constructed with respect to its resistance values.

[0040] The respective voltage value results from the alternating switching on and off of the switches S1 , S2 , S3 , S4 of the respective voltage divider RS1 , RS2 , which are driven via the inverting output of the comparator K1 .

[0041] Figure 5 like Figure 4 That is, it consists of a lower figure, a middle figure and an upper figure, wherein the upper figure shows the signal curve of the “logical” input signal IN already mentioned, and the middle figure shows the voltage curve of the “logical” output signal OUT.

[0042] The following figure describes the voltage variation curves of the two input terminals V1 and V2 of the comparator K1 corresponding to the signal variation curve of the input signal IN in time. Figure 2 These voltage curves are obtained when the switches S3 and S4 of the second voltage divider circuit are removed and the second voltage divider circuit does not change its division ratio over time.

[0043] The voltage at the first input terminal V1 is initially at a voltage value of 2.3 V. The voltage at the second input terminal V2 is initially at a voltage value of 2.5 V. At the time of the first switching pulse, the voltage at the first input terminal V1 rises in a pulsed manner to a positive peak value. At the same time, the voltage at the second input terminal V2 drops to a negative peak value. The voltage value at the first input terminal V1 reaches an average value of 2.7 V after a relaxation time. The voltage value at the second input terminal V2 reaches an average value of 2.5 V again. The two voltage values ​​at the input terminals V1 and V2 remain constant for a long time until a new switching process of the input signal IN occurs. Due to the second switching pulse of the input signal IN, the voltage at the first input terminal V1 drops from 2.7 V to a negative peak value and then reaches an average value of 2.3 V again. The voltage at the second input terminal V2 reaches an average value of 2.5 V again after a relaxation time. The voltage values ​​described are again only for clarification.

[0044] Reference numerals list

[0045] A1 First Signal Amplifier

[0046] A2 Second Signal Amplifier

[0047] A3 Third Signal Amplifier

[0048] C1 first high voltage capacitor

[0049] C2 Second output side capacitor

[0050] C3 The third high voltage capacitor

[0051] C4 Fourth output side capacitor

[0052] D drive control circuit

[0053] G1 first reference potential

[0054] G2 second reference potential

[0055] H half-bridge circuit

[0056] IN input signal

[0057] K1 Comparator

[0058] PD1 first signal evaluation circuit

[0059] PD2 second signal evaluation circuit

[0060] P1 first power switch

[0061] P2 second power switch

[0062] P3 third power switch

[0063] P4 fourth power switch

[0064] RS1 first voltage divider circuit

[0065] RS2 second voltage divider circuit

[0066] R1 first resistor

[0067] R2 second resistor

[0068] R3 the third resistor

[0069] R4 the fourth resistor

[0070] R5 fifth resistor

[0071] R6 Sixth resistor

[0072] R7 seventh resistor

[0073] R8 eighth resistor

[0074] R11 is the input terminal of the first voltage divider circuit

[0075] R12 The first output terminal of the first voltage divider circuit

[0076] R13 is the input terminal of the second voltage divider circuit

[0077] R14 The first output terminal of the second voltage divider circuit

[0078] S1 first switch

[0079] S2 second switch

[0080] S3 third switch

[0081] S4 fourth switch

[0082] V1 first comparator input

[0083] V2 second comparator input

[0084] V3 voltage source

[0085] V4 voltage source

[0086] Y1 input signal processing mechanism

[0087] Y2 first drive control sub-circuit

[0088] Y3 second drive control sub-circuit

[0089] Y4 center tap

[0090] Y5 primary side

[0091] Y6 secondary side

[0092] Z1 first transmission branch

[0093] Z2 second transmission branch

Claims

1. A control circuit (D) having a transmission circuit, the transmission circuit being used to transmit a signal from an input side (S2) having a first reference potential (G1) to an output side (S2) having a second reference potential (G2), the transmission circuit having a transmitter, the transmitter having a capacitive coupling between the input side (S1) and the output side (S2), wherein: The transmitter has two branches, namely a first transmission branch (Z1) and a second transmission branch (Z2), wherein: The capacitive coupling between the input side and the output side (S1, S2) is implemented by a first high-voltage capacitor and a second high-voltage capacitor (C1, C3), which respectively form a series circuit with the associated first and second output-side capacitors (C2, C4), wherein: The input side terminal of the first high-voltage capacitor (C1) is configured to apply an input signal (IN) to the first high-voltage capacitor in a non-inverting manner, and the input side terminal of the second high-voltage capacitor (C3) is configured to apply the input signal (IN) to the second high-voltage capacitor in an inverting manner, wherein the secondary-side terminal of the first high-voltage capacitor (C1) is connected to the first input (V1) of the comparator (K1), and the secondary-side terminal of the second high-voltage capacitor (C3) is connected to the second input (V2) of the comparator (K1), wherein the preferably inverting output terminal of the comparator (K1) constitutes the output (OUT) of the drive control circuit and is connected to the first input (R11) of the first voltage divider circuit (RS1), wherein the first output (R12) of the first voltage divider circuit (RS1) is connected to the first input (V1) of the comparator (K1), The first voltage divider circuit (RS1) has a first sub-branch and a second sub-branch, the first sub-branch has a parallel circuit consisting of a first resistor (R1) and a first switch (S1) and has a second resistor (R2) connected in series therewith, the second sub-branch has a third resistor (R3) and a parallel circuit consisting of a fourth resistor (R4) and a second switch (S2) connected in series, and the first voltage divider circuit is configured for push-pull switching of the first and second switches, and the second voltage divider circuit (RS2) is connected to a second input terminal (V2) of the comparator (K1).

2. The driving control circuit according to claim 1, wherein: The capacitance value of each output-side capacitor (C2, C4) is several times higher than the capacitance value of the respectively associated high-voltage capacitor (C1, C3).

3. The drive control circuit according to any one of the preceding claims, wherein: The two voltage divider circuits (RS1, RS2) are connected to the same voltage source terminals (V3, V4), respectively.

4. The drive control circuit according to any one of the preceding claims, wherein: The second voltage divider circuit (RS2) comprises a first sub-branch and a second sub-branch, the first sub-branch comprising a parallel circuit consisting of an additional first resistor (R5) and an additional first switch (S3) and an additional second resistor (R6) connected in series therewith, the second sub-branch comprising an additional third resistor (R7) and a parallel circuit consisting of an additional fourth resistor (R8) and an additional second switch (S4) connected in series, and the first voltage divider circuit is configured for push-pull switching of the additional first switch and the additional second switch.

5. The drive control circuit according to any one of the preceding claims, wherein: The respective first switch ( S1 , S3 ) is designed as an nMOS transistor and the respective second switch ( S2 , S4 ) is designed as a pMOS transistor, or vice versa.

6. A drive control circuit according to any one of the preceding claims, wherein: The output of the comparator (K1) is connected to a signal evaluation circuit (PD1).

7. A drive control circuit according to any one of the preceding claims, wherein: The components are monolithically integrated into a high voltage integrated circuit.

8. The drive control circuit according to any one of the preceding claims, wherein: Each second resistor ( R2 , R6 ) and each third resistor ( R3 , R7 ) is respectively formed by a single resistor or a series circuit composed of a plurality of resistors preferably having the same resistance value.

9. Method for operating a control circuit according to any one of the preceding claims, wherein: The preferably inverted output signal of the secondary-side comparator (K1) is permanently applied to the input (R11) of the first voltage divider circuit (RS1), whereby a first output signal of the first voltage divider circuit (RS1) has a first level value corresponding to the first switching state, By applying a primary-side input signal (IN) corresponding to a second switching state to an input terminal and by transmitting the primary-side input signal via high-voltage capacitors (C1, C3), voltage pulses are applied to two input terminals (V1, V2) of a comparator (K1), respectively, and the voltage pulses invert a voltage difference at the two input terminals (V1, V2) of the comparator (K1) and thus invert an output terminal of the comparator.

10. The method for operating a driver circuit according to claim 9, wherein: The respective voltage pulse is greater than the voltage difference at the two inputs (V1, V2) of the comparator (K1) in static operation.

11. The method for operating a driver circuit according to claim 9, wherein: By inverting the output terminal of the comparator, the two switches (S1, S2) of the first voltage divider (RS1) change their respective switching states.

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