High-speed level conversion circuit and chip

Abstract

The invention relates to the field of integrated circuits, and discloses a high-speed level conversion circuit and a chip, and the circuit comprises an in-phase and anti-phase signal output circuit which is used for outputting an in-phase first output signal and an anti-phase second output signal during the rising edge period of an input signal; the level boosting circuit is used for responding to the first output signal and the second output signal, entering a charging state and lifting the first output signal up to VBS; the substrate voltage regulating circuit is used for responding to the first output signal and the second output signal, generating a positive pulse differential waveform to enable a first NMOS tube of the conversion circuit to be quickly opened and generating a negative pulse differential waveform to enable a second NMOS tube to be quickly closed; the conversion circuit is used for pulling the output voltage to a low level in response to actions of the first NMOS tube and the second NMOS tube; and the inverting output buffer circuit is used for inverting the output voltage thereof to convert the low level into the target level. The level conversion circuit provided by the invention can realize high speed and wide level conversion range.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuits, and in particular to a high-speed level conversion circuit and a chip. Background Art

[0002] Level conversion circuits are widely used in mixed-signal circuits with multiple power supply voltage domains. In the field of mixed-signal design, mixed voltage domain design is often used to reduce circuit power consumption and increase circuit operating speed. Among them, key performance modules use high-voltage design, and high-speed and low-power modules use low-voltage design. At the interface between the two, a large number of level conversion circuits are required. Therefore, how to realize high-speed and low-cost level conversion circuits has always been a widely concerned issue.

[0003] There are two basic structures of voltage converter circuits, Figure 1a and Figure 1b For the existing design, Figure 1a For the circuit, Figure 1b It is the signal waveform diagram. Figure 1a The circuit 100 shown includes an input inverter circuit 110, a level conversion circuit 120 based on a cross-coupling structure, and an inverting output buffer circuit 130. The input inverter circuit 110 operates in a low voltage domain of 1.8V, and the level conversion circuit 120 and the inverting output buffer circuit 130 operate in a high voltage domain of 5V. The input inverter circuit 110 inverts the input signal to provide an inverted input signal. The level conversion circuit 120 includes: a cross-coupling structure composed of PMOS tubes 123 and 124 as a pull-up network to pull the output signal up to a high voltage; a pull-down network composed of NMOS tubes 121 and 122 to pull the output signal down to ground. The pull-up network based on cross-coupling has a positive feedback characteristic, which strengthens the voltage difference between Q1 and Q2, thereby performing level switching faster. The signal waveform during operation is shown as follows. Figure 1b As shown, the input signal V iL During the rising edge, NMOS tube 121 is turned on and NMOS tube 122 is turned off. At this time, the voltage at Q1 gradually decreases, and PMOS tube 124 gradually turns on, pulling Q2 to the high power supply voltage ( V ddH ), which helps turn off the PMOS tube 123, causing Q1 to discharge faster; the pull-up speed of the inverting output buffer circuit 130 from a low level to a high level is also faster. This architecture has very low power consumption in standby mode because neither circuit branch consumes static power. However, when the low power supply voltage ( V ddL) is low, the overdrive voltage of the pull-down transistors NMOS 121, 122 is low and cannot easily overcome the pull-up transistors PMOS 123, 124. Therefore, in order to improve the pull-down network, the size of the NMOS tubes 121, 122 is often larger, which reduces the overall efficiency and brings greater delay and power consumption.

[0004] Figure 2a and Figure 2b For the existing design 2, Figure 2a For the circuit, Figure 2b It is the signal waveform diagram. Figure 2a The circuit 200 shown includes an input inverter circuit 210, a level conversion circuit 220 based on a current mirror structure, and a cascade output buffer circuit 230. Among them, the input inverter circuit 210 operates in a low voltage domain of 1.8V, and the level conversion circuit 220 and the cascade output buffer circuit 230 operate in a high voltage domain of 5V. The input inverter circuit 210 inverts the input signal to provide an inverted input signal. The level conversion circuit 220 includes: a current mirror structure composed of PMOS tubes 223 and 224 as a pull-up network to pull the output signal up to a high voltage; a pull-down network composed of NMOS tubes 221 and 222 to pull the output signal down to ground. Finally, the output signal of the level converter is output through the cascade output buffer circuit 223. The signal waveform during operation is as shown below. Figure 2b As shown, the input signal V iL During the rising edge, NMOS tube 221 is turned on and NMOS tube 222 is turned off. At this time, the voltage at Q1 gradually decreases, and PMOS tube 224 gradually turns on, pulling Q2 to the high power supply voltage ( V ddH ), and finally converts the low voltage into a high voltage after passing through the cascade output buffer 223. In this circuit structure, although there is no competition between the pull-down network and the pull-up network, there is almost no regenerative interaction between the pull-down and pull-up networks and between the left and right branches of the circuit, so the conversion speed is low. In addition, it has a relatively large static power, which is mainly due to the presence of static current in one of the circuit branches according to the input state. Summary of the invention

[0005] The purpose of the present invention is to provide a high-speed level conversion circuit and chip, which can improve the over-drive voltage of the pull-down network of the level conversion circuit, increase the pull-down network strength without sacrificing the pull-up network strength, and realize high-speed level conversion. Compared with the existing design, it has the characteristics of high speed and wide level conversion range when the circuit size and load size are comparable.

[0006] In order to achieve the above-mentioned purpose, the first aspect of the present invention provides a high-speed level conversion circuit, which includes: an in-phase and inverted signal output circuit, a level boosting circuit, a substrate voltage adjustment circuit, a level conversion circuit based on a cross-coupling structure, and an inverted output buffer circuit, wherein the in-phase and inverted signal output circuit is used to output a first output signal in phase with the input signal and a second output signal in phase with the input signal during the rising edge of the input signal; the level boosting circuit is used to enter a charging state and raise the first output signal in response to the first output signal and the second output signal. V BS , wherein the V BS The substrate voltage regulating circuit is used to control the external bias voltage of the level boosting circuit; the substrate voltage regulating circuit is used to generate a positive pulse differential waveform in response to the first output signal and the second output signal to enable the first NMOS tube in the level conversion circuit to be quickly turned on, and to generate a negative pulse differential waveform to enable the second NMOS tube in the level conversion circuit to be quickly turned off, wherein the V BS is smaller than the threshold voltage of the first NMOS tube and the second NMOS tube; the level conversion circuit is used to pull the output voltage to a low level 0 in response to the first NMOS tube being quickly turned on and the second NMOS tube being quickly turned off; and the inverting output buffer circuit is used to invert the output voltage to convert the low level 0 to a target level.

[0007] Preferably, the in-phase and inverting signal output circuit is used to output a first output signal in phase with the input signal and a second output signal in phase with the input signal during the falling edge of the input signal; the level boosting circuit is used to enter a charging state and raise the second output signal in response to the first output signal and the second output signal. V BS ; The substrate voltage regulation circuit is used to generate a positive pulse differential waveform in response to the first output signal and the second output signal to quickly turn on the second NMOS tube in the level conversion circuit, and to generate a negative pulse differential waveform to quickly turn off the first NMOS tube in the level conversion circuit; the level conversion circuit is used to pull the output voltage to the target level in response to the second NMOS tube quickly turning on and the first NMOS tube quickly turning off; and the inverting output buffer circuit is used to invert the output voltage to convert the target level to a low level 0.

[0008] Preferably, the in-phase and inverted signal output circuit is a clock edge adjustment circuit, which is also used to align the center point of the rising edge of the first output signal with the center point of the falling edge of the second output signal, and to align the center point of the falling edge of the first output signal with the center point of the rising edge of the second output signal.

[0009] Preferably, the level boosting circuit comprises: a first circuit for entering a charging state in response to the first output signal and the second output signal during a rising edge of an input signal, or for raising the second output signal in response to the first output signal and the second output signal during a falling edge of an input signal. V BS and a second circuit for raising the first output signal in response to the first output signal and the second output signal during the rising edge of the input signal V BS , or, during the falling edge of the input signal, in response to the first output signal and the second output signal, enter the charging state. Preferably, the first circuit includes: a third NMOS tube, the gate of the third NMOS tube is connected to the first output signal, and the source of the third NMOS tube is connected to the external bias voltage; a first capacitor, the first end of the first capacitor is connected to the drain of the third NMOS tube, and the second end of the first capacitor is connected to the second output signal, and the second circuit includes: a fourth NMOS tube, the gate of the fourth NMOS tube is connected to the second output signal, and the source of the fourth NMOS tube is connected to the external bias voltage; a second capacitor, the first end is connected to the drain of the fourth NMOS tube, and the second end is connected to the first output signal.

[0010] Preferably, the first circuit further includes: a fifth NMOS tube, the source of the fifth NMOS tube is connected to the drain of the third NMOS tube, the drain of the fifth NMOS tube is connected to the first end of the first capacitor, and the second circuit further includes: a sixth NMOS tube, the source of the sixth NMOS tube is connected to the drain of the fourth NMOS tube, and the drain of the sixth NMOS tube is connected to the first end of the second capacitor.

[0011] Preferably, the first circuit further includes: a first resistor, a first end of the first resistor is connected to the drain of the third NMOS tube, and a second end of the first resistor is connected to the first end of the first capacitor; the second circuit further includes: a second resistor, a first end of the second resistor is connected to the drain of the fourth NMOS tube, and a second end of the second resistor is connected to the first end of the second capacitor.

[0012] Preferably, the first end of the second capacitor is connected to the gate of the first NMOS transistor in the level conversion circuit; the first end of the first capacitor is connected to the gate of the second NMOS transistor in the level conversion circuit.

[0013] Preferably, the substrate voltage regulation circuit includes: a first micro-branch, an input end of the first micro-branch is connected to the first output signal, and an output end of the first micro-branch is connected to the substrate of the first NMOS tube in the level conversion circuit; and a second micro-branch, an input end of the second micro-branch is connected to the second output signal, and an output end of the second micro-branch is connected to the substrate of the second NMOS tube in the level conversion circuit.

[0014] Through the above technical solution, the present invention creatively sets a same-phase and opposite-phase signal output circuit, a level boosting circuit, a substrate voltage regulating circuit, a level conversion circuit based on a cross-coupling structure, and an inverting output buffer circuit in the high-speed level conversion circuit, wherein the same-phase and opposite-phase signal output circuit is used to output a first output signal in phase with the input signal and a second output signal in phase with the input signal during the rising edge of the input signal; the level boosting circuit is used to enter a charging state and raise the first output signal in response to the first output signal and the second output signal. V BS , wherein the V BS The substrate voltage regulating circuit is used to control the external bias voltage of the level boosting circuit; the substrate voltage regulating circuit is used to generate a positive pulse differential waveform in response to the first output signal and the second output signal to enable the first NMOS tube in the level conversion circuit to be quickly turned on, and to generate a negative pulse differential waveform to enable the second NMOS tube in the level conversion circuit to be quickly turned off, wherein the V BS The voltage level of the first NMOS tube is smaller than the threshold voltage of the second NMOS tube; the level conversion circuit is used to pull the output voltage to the low level 0 in response to the first NMOS tube being quickly turned on and the second NMOS tube being quickly turned off; and the inverting output buffer circuit is used to invert the output voltage to convert the low level 0 to the target level. Therefore, the present invention uses an auxiliary level boosting circuit and a substrate voltage regulating circuit to increase the overdrive voltage of the pull-down network of the level conversion circuit, while not sacrificing the strength of the pull-up network, the pull-down network strength is increased, and high-speed level conversion is achieved. Compared with the existing design, it has the characteristics of high speed and wide level conversion range when the circuit size and load size are comparable.

[0015] A second aspect of the present invention provides a chip, wherein the chip comprises the high-speed level conversion circuit.

[0016] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings: Figure 1a It is a structural schematic diagram of an existing level conversion circuit design one; Figure 1b yes Figure 1a The signal waveform diagram corresponding to the level conversion circuit in; Figure 2a It is a structural schematic diagram of the existing level conversion circuit design 2; Figure 2b yes Figure 2a The signal waveform diagram corresponding to the level conversion circuit in; Figure 3 is a schematic structural diagram of a high-speed level conversion circuit provided by an embodiment of the present invention; and Figure 4 An embodiment of the present invention provides Figure 3 The signal waveform corresponding to the high-speed level conversion circuit in . DETAILED DESCRIPTION

[0018] The specific implementation of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the present invention, and is not used to limit the present invention.

[0019] Figure 3 FIG. 1 is a schematic diagram of a high-speed level conversion circuit provided by an embodiment of the present invention. Figure 3 As shown, the high-speed level conversion circuit 500 includes: an in-phase and inverting signal output circuit 510, a level boosting circuit 520, a substrate voltage adjustment circuit 530, a level conversion circuit 540 based on a cross-coupling structure, and an inverting output buffer circuit 550.

[0020] This embodiment proposes a high-speed level conversion circuit suitable for low latency and a wide voltage conversion range. The main idea is to use an auxiliary level boost circuit and a substrate voltage adjustment circuit (such as a differential circuit composed of capacitors and resistors) to increase the overdrive voltage of the pull-down NMOS network of the level conversion circuit, thereby increasing the pull-down network strength without sacrificing the pull-up network strength, thereby achieving high-speed level conversion.

[0021] For input signal V iLDuring the rising edge of Figure 4 As shown in FIG. 5 ), a high-speed level conversion circuit 500 can be used to implement high-speed level conversion with low latency and a wide voltage conversion range. The specific implementation content is described below.

[0022] The in-phase and inverted signal output circuit 510 is used to output a first output signal in phase with the input signal and a second output signal in phase with the input signal during a rising edge of the input signal.

[0023] The level boosting circuit 520 is used to enter a charging state and raise the first output signal in response to the first output signal and the second output signal. V BS Among them, the V BS is an external bias voltage for controlling the level boosting circuit. The substrate voltage regulating circuit 530 is used to generate a positive pulse differential waveform in response to the first output signal and the second output signal to quickly turn on the first NMOS transistor (for example, NMOS transistor 541) in the level conversion circuit 540, and to generate a negative pulse differential waveform to quickly turn off the second NMOS transistor (for example, NMOS transistor 542) in the level conversion circuit 540. V BS The voltage level of the NMOS transistor 541 is lower than the threshold voltage of the first NMOS transistor (eg, NMOS transistor 541) and the second NMOS transistor (eg, NMOS transistor 542). The level boosting circuit 520 enters the charging state to increase the overdrive voltage of the NMOS transistor 541, so that the NMOS transistor 541 is turned on faster.

[0024] The level conversion circuit 540 is used to pull the output voltage to a low level 0 in response to the first NMOS transistor (for example, the NMOS transistor 541 ) being quickly turned on and the second NMOS transistor (for example, the NMOS transistor 542 ) being quickly turned off.

[0025] The inverting output buffer circuit 550 is used to invert the output voltage to convert the low level 0 into a target level.

[0026] Among them, the inverse phase signal output circuit 510 (for example, a clock edge adjustment circuit), the level boosting circuit 520, and the substrate voltage adjustment circuit 530 operate at a low level (for example, 1.8V); the level conversion circuit 540 and the inverse phase output buffer circuit 550 operate at a high level / target level (for example, 5V).

[0027] Specifically, Figure 3 and Figure 4Take the working process of high-speed level conversion circuit as an example to describe.

[0028] When the input signal V iL From power ground (0V) to V ddL (e.g., 1.8V) period (i.e. Figure 4 During the rising edge of V iL The first output signal is in phase V iLC and a iL Inverted second output signal V iNLC .

[0029] At input signal V iL Convert from power ground 0V to V ddL ( V iLC is low level and V iNLC is high level) when the level boost circuit 520 enters the charging state; and the input signal V iL / First output signal V iLC Lifting, the lifting voltage is V BS (like Figure 4 shown V iLC_BS ),in V BS It is smaller than the threshold voltage of the NMOS tubes 541 and 542, thereby increasing the over-driving voltage of the input NMOS tube and enhancing the pull-down capability of the NMOS tube.

[0030] The substrate voltage regulating circuit 530 generates a positive pulse differential waveform (eg Figure 4 In V sub1 ), reducing the threshold voltage of NMOS tube 541, thereby increasing the overdrive voltage of NMOS tube 541, so that NMOS tube 541 is turned on faster; and when NMOS tube 542 is turned off, a negative pulse differential waveform is generated (for example Figure 4 In V sub2 ), increasing the threshold voltage of the NMOS tube 542, so that the NMOS tube 542 is turned off faster.

[0031] In response to the NMOS tube 541 being turned on quickly and the NMOS tube 542 being turned off quickly, the level conversion circuit 540, as the core circuit of the entire level conversion circuit system, outputs a signal at Q1 that is converted from a high voltage signal to a low voltage signal (i.e., the output voltage of the level conversion circuit 540 is converted from a high level to a low voltage signal). V ddH Pulled to low level 0), thereby realizing the entire level conversion circuit system from 0V to high power supply voltage signal (for example V ddH =5V) conversion.

[0032] The inverting output buffer circuit 550 inverts and buffers the output of the level conversion circuit 540 to pull the low level 0 to the high level / target level. V ddH (e.g. 5V) (e.g. Figure 4 In V oH rising edge of 0.

[0033] For input signal V iL During the falling edge of Figure 4 As shown in FIG. 5 ), a high-speed level conversion circuit 500 can be used to achieve high-speed level conversion with low latency and a wide voltage conversion range (ie, voltage conversion from 1.8V to 5V can be achieved). The specific implementation content is described below.

[0034] The in-phase and inverted signal output circuit 510 is used to output a first output signal in phase with the input signal and a second output signal in phase with the input signal during a falling edge of the input signal.

[0035] The level boosting circuit 520 is used to enter a charging state and raise the second output signal in response to the first output signal and the second output signal. V BS .

[0036] The substrate voltage regulation circuit 530 is used to generate a positive pulse differential waveform in response to the first output signal and the second output signal to quickly turn on the second NMOS tube (for example, NMOS tube 542) in the level conversion circuit, and to generate a negative pulse differential waveform to quickly turn off the first NMOS tube (for example, NMOS tube 541) in the level conversion circuit.

[0037] The level conversion circuit 540 is used to pull the output voltage toward the target level (i.e., the output voltage of the target voltage) in response to the second NMOS transistor (e.g., the NMOS transistor 542) being quickly turned on and the first NMOS transistor (e.g., the NMOS transistor 541) being quickly turned off. V ddH, for example 5V).

[0038] The inverting output buffer circuit 550 is used to invert the output voltage to convert the target level (i.e. V ddH , for example 5V) is a low level 0.

[0039] Specifically, Figure 3 and Figure 4 Take the working process of high-speed level conversion circuit as an example to describe.

[0040] When the input signal V iL Depend on V ddL (e.g., 1.8V) drops to the power ground (0V) (i.e. Figure 4 During the falling edge of V iL The first output signal is in phase V iLC and a iL Inverted second output signal V iNLC .

[0041] At input signal V iL For V ddL Converted to power ground 0V ( V iLC is low level and V iNLC is a high level), the level boosting circuit 520 enters a charging state; and the second output signal V iNLC Lifting, the lifting voltage is V BS (like Figure 4 shown V iNLC_BS ),in V BS It is smaller than the threshold voltage of the NMOS tubes 541 and 542, thereby increasing the over-driving voltage of the input NMOS tube and enhancing the pull-down capability of the NMOS tube.

[0042] The substrate voltage regulating circuit 530 generates a positive pulse differential waveform (eg Figure 4 In V sub2), reducing the threshold voltage of NMOS tube 542, thereby increasing the overdrive voltage of NMOS tube 542, so that NMOS tube 542 is turned on faster; and when NMOS tube 541 is turned off, a negative pulse differential waveform is generated (for example Figure 4 In V sub1 ), increasing the threshold voltage of the NMOS tube 541, so that the NMOS tube 541 is turned off faster.

[0043] In response to the NMOS tube 542 being turned on quickly and the NMOS tube 541 being turned off quickly, the level conversion circuit 540, as the core circuit of the entire level conversion circuit system, outputs the conversion of the low voltage signal at Q1 to a high voltage signal (i.e., the output voltage of the level conversion circuit 540 is pulled from a low level 0 to a high level). V ddH ), so that the entire level conversion circuit system is realized by a high power supply voltage signal (such as V ddH =5V) to 0V.

[0044] The inverting output buffer circuit 550 performs inverting buffering on the output of the level conversion circuit 540 to convert the high level / target level V ddH (e.g. 5V) is pulled to low level 0 (e.g. Figure 4 In V oH falling edge of 0.

[0045] In one embodiment, the in-phase and inverted signal output circuit 510 may be a clock edge adjustment circuit.

[0046] Correspondingly, the clock edge adjustment circuit is also used to align the center point of the rising edge of the first output signal with the falling edge of the second output signal, and to align the center point of the falling edge of the first output signal with the rising edge of the second output signal.

[0047] In this embodiment, in addition to outputting two signals that are in phase and inversely phase with the input signal, the clock edge adjustment circuit also aligns the centers of the rising and falling edges of the two signals, thereby avoiding charge leakage of capacitors 523 and 524 of the subsequent level boosting circuit.

[0048] The specific structure of the level boosting circuit 520 is described below.

[0049] The level boosting circuit 520 includes: a first circuit for entering a charging state in response to the first output signal and the second output signal during a rising edge of an input signal, or for raising the second output signal in response to the first output signal and the second output signal during a falling edge of an input signal. V BS and a second circuit for raising the first output signal in response to the first output signal and the second output signal during the rising edge of the input signal V BS , or, during the falling edge of the input signal, in response to the first output signal and the second output signal, enter the charging state.

[0050] like Figure 3 As shown, the first circuit includes: a third NMOS transistor (for example, NMOS transistor 526), ​​the gate of the third NMOS transistor (for example, NMOS transistor 526) is connected to the first output signal (for example, V iLC ), the source of the third NMOS transistor (eg, NMOS transistor 526) is connected to the external bias voltage (eg, V BS ) connected; a first capacitor (eg, capacitor 524), a first end of which is connected to the drain of the third NMOS transistor (eg, NMOS transistor 526), ​​and a second end of which is connected to the second output signal (eg, V iNLC ) are connected.

[0051] like Figure 3 As shown, the second circuit includes: a fourth NMOS transistor (for example, NMOS transistor 521), the gate of the fourth NMOS transistor (for example, NMOS transistor 521) is connected to the second output signal (for example, V iNLC ), the source of the fourth NMOS transistor (eg, NMOS transistor 521) is connected to the external bias voltage (eg, V BS ) connected; a second capacitor (eg, capacitor 523), a first end of which is connected to the drain of the fourth NMOS transistor (eg, NMOS transistor 521), and a second end of which is connected to the first output signal (eg, V iLC ) are connected.

[0052] In one embodiment, if Figure 3As shown, the first circuit also includes: a fifth NMOS tube (for example, NMOS tube 525), the source of the fifth NMOS tube (for example, NMOS tube 525) is connected to the drain of the third NMOS tube (for example, NMOS tube 526), ​​and the drain of the fifth NMOS tube (for example, NMOS tube 525) is connected to the first end of the first capacitor (for example, capacitor 524).

[0053] like Figure 3 As shown, the second circuit also includes: a sixth NMOS tube (for example, NMOS tube 522), the source of the sixth NMOS tube (for example, NMOS tube 522) is connected to the drain of the fourth NMOS tube (for example, NMOS tube 521), and the drain of the sixth NMOS tube (for example, NMOS tube 522) is connected to the first end of the second capacitor (for example, capacitor 523).

[0054] In this embodiment, the fifth NMOS tube and the sixth NMOS tube are used to V BS Furthermore, compared with the resistor, the fifth NMOS transistor and the sixth NMOS transistor have a stronger isolation effect.

[0055] In another embodiment, the first circuit further includes: a first resistor (not shown), a first end of the first resistor is connected to the drain of the third NMOS transistor, and a second end of the first resistor is connected to the first end of the first capacitor.

[0056] The second circuit further includes: a second resistor (not shown), a first end of the second resistor is connected to the drain of the fourth NMOS transistor, and a second end of the second resistor is connected to the first end of the second capacitor.

[0057] In this embodiment, the first resistor and the second resistor are used to V BS Isolate the impact that the signal may bring.

[0058] The connection method of two capacitors (eg, capacitors 523 and 524 ) in the level boosting circuit 520 is described below.

[0059] like Figure 3 As shown, the first end of the second capacitor (e.g., capacitor 523) is connected to the gate of the first NMOS transistor (e.g., NMOS transistor 541) in the level conversion circuit 540. The first end of the first capacitor (e.g., capacitor 524) is connected to the gate of the second NMOS transistor (e.g., NMOS transistor 542) in the level conversion circuit 540.

[0060] The specific structure of the substrate voltage regulating circuit 530 is described below.

[0061] like Figure 3 As shown, the substrate voltage regulating circuit 530 includes: a first micro-branch (which includes a capacitor 531 and a resistor 532 connected in series), an input end of the first micro-branch and the first output signal (for example, V iLC ) is connected to the output end of the first micro-branch (for example, V sub1 ) is connected to the substrate of the first NMOS transistor (for example, NMOS transistor 541) in the level conversion circuit 540; and a second micro-branch (which includes a capacitor 533 and a resistor 534 connected in series), the input end of the second micro-branch is connected to the second output signal (for example, V iNLC ) is connected to the output end of the second micro-branch (for example, V sub2 ) is connected to the substrate of the second NMOS transistor (for example, the NMOS transistor 542) in the level conversion circuit 540.

[0062] Specifically, Figure 3 and Figure 4 Take the working process of high-speed level conversion circuit as an example to describe.

[0063] When the input signal V iL From power ground (0V) to V ddL (e.g., 1.8V) period (i.e. Figure 4 During the rising edge of V iL The same phase signal (i.e. the first output signal V iLC ), the inverting input signal buffer stage composed of NMOS tubes 511, 513 and PMOS tubes 512, 514 outputs and V iL The inverted signal (i.e. the second output signal V iNLC ).in V iLC Rising edge and V iNLC The center point of the falling edge is aligned, V iLC Falling edge and V iNLCThe center points of the rising edges are aligned to avoid charge leakage of the capacitors 523 and 524 of the subsequent level boosting circuit 520.

[0064] At input signal V iL From 0 to V ddL Convert ( V iLC is low level and V iNLC is high level), the level boost circuit composed of capacitor 524, NMOS tubes 525, 526 starts to charge capacitor 524; and at this time, the level boost circuit composed of capacitor 523, NMOS tubes 521, 522 will input signal V iL / First output signal V iLC Lifting, the lifting voltage is V BS (like Figure 4 shown V iLC_BS , you can V iLC Lift to V ddL + V BS ),in V BS It is smaller than the threshold voltage of the NMOS tubes 541 and 542 , thereby increasing the over-driving voltage of the input NMOS tube, enhancing the pull-down capability of the NMOS tube, and preventing the NMOS tubes 541 and 542 from being turned on erroneously.

[0065] The differential circuit composed of capacitor 531 and resistor 532 will generate a positive pulse differential waveform (for example Figure 4 In V sub1 ), reducing the threshold voltage of the NMOS tube 541, thereby increasing the overdrive voltage of the NMOS tube 541 (i.e., causing the substrate voltage of the NMOS tube 541 to increase temporarily), so that the NMOS tube 541 is turned on faster; and the differential circuit composed of the capacitor 533 and the resistor 534 will generate a negative pulse differential waveform when the NMOS tube 542 is turned off (for example Figure 4 In V sub2 ), increasing the threshold voltage of the NMOS tube 542, causing the substrate voltage of the NMOS tube 542 to temporarily decrease, causing the NMOS tube 542 to be turned off more quickly, further preventing the NMOS tube 542 from turning on, and reducing the subthreshold leakage.

[0066] In response to the NMOS tube 541 being turned on quickly and the NMOS tube 542 being turned off quickly, the level conversion circuit 540, as the core circuit of the entire level conversion circuit system, outputs a signal at Q1 that is converted from a high voltage signal to a low voltage signal (i.e., the output voltage of the level conversion circuit 540 is converted from a high level to a low voltage signal). V ddH Pull to low level 0), thereby realizing the entire level conversion circuit system from 0 to high power supply voltage signal (for example V ddH =5V). That is, when NMOS tube 541 is turned on and NMOS tube 542 is turned off, PMOS tube 544 is turned on and PMOS tube 543 is turned off, the voltage at Q1 drops to the power ground, and the voltage at Q2 rises to V ddH .

[0067] The inverting output buffer circuit 550 inverts and buffers the output of the level conversion circuit 540 to pull the low level 0 to the high level / target level. V ddH (e.g. 5V) (e.g. Figure 4 In V oH That is, the high voltage is output through the inverting output buffer circuit 550. V ddH The inverting output buffer circuit 550 includes a PMOS transistor 552 and an NMOS transistor 551. Figure 4 shown.

[0068] When the input signal V iL Depend on V ddL (e.g., 1.8V) drops to the power ground (0V) (i.e. Figure 4 During the falling edge of V iL The same phase signal (i.e. the first output signal V iLC ), the inverting input signal buffer stage composed of NMOS tubes 511, 513 and PMOS tubes 512, 514 outputs and V iL The inverted signal (i.e. the second output signal V iNLC ).in V iLC Rising edge and V iNLC The center point of the falling edge is aligned, V iLCFalling edge and V iNLC The center points of the rising edges are aligned to avoid charge leakage of the capacitors 523 and 524 of the subsequent level boosting circuit 520.

[0069] At input signal V iL Depend on V ddL to 0 transition ( V iLC is low level and V iNLC is high level), the level boost circuit composed of capacitor 523, NMOS tubes 521, 522 starts charging capacitor 523; and at this time, the level boost circuit composed of capacitor 524, NMOS tubes 525, 526 converts the second output signal V iNLC Lifting, the lifting voltage is V BS (like Figure 4 shown V iNLC_BS , you can V iLC Lift to V ddL + V BS ),in V BS It is smaller than the threshold voltage of the NMOS tubes 541 and 542 , thereby increasing the over-driving voltage of the input NMOS tube, enhancing the pull-down capability of the NMOS tube, and preventing the NMOS tubes 541 and 542 from being turned on erroneously.

[0070] The differential circuit composed of capacitor 533 and resistor 534 will generate a positive pulse differential waveform (for example Figure 4 In V sub2 ), reducing the threshold voltage of the NMOS tube 542, thereby increasing the overdrive voltage of the NMOS tube 542 (i.e., causing the substrate voltage of the NMOS tube 542 to increase temporarily), so that the NMOS tube 542 is turned on faster; and the differential circuit composed of the capacitor 531 and the resistor 532 will generate a negative pulse differential waveform when the NMOS tube 541 is turned off (for example Figure 4 In V sub1 ), increasing the threshold voltage of the NMOS tube 541, causing the substrate voltage of the NMOS tube 541 to temporarily decrease, causing the NMOS tube 541 to be turned off more quickly, further preventing the NMOS tube 541 from turning on, and reducing the subthreshold leakage.

[0071] In response to the NMOS tube 542 being turned on quickly and the NMOS tube 541 being turned off quickly, the level conversion circuit 540, as the core circuit of the entire level conversion circuit system, outputs the conversion of the low voltage signal at Q1 to a high voltage signal (i.e., the output voltage of the level conversion circuit 540 is pulled from a low level 0 to a high level). V ddH ), so that the entire level conversion circuit system is realized by a high power supply voltage signal (such as V ddH =5V) to 0V. That is, when NMOS tube 542 is turned on and NMOS tube 541 is turned off, PMOS tube 543 is turned on and PMOS tube 544 is turned off, the voltage at Q1 rises to V ddH , the voltage at Q2 drops to the power ground (0V).

[0072] The inverting output buffer circuit 550 performs inverting buffering on the output of the level conversion circuit 540 to convert the high level / target level V ddH (e.g. 5V) is pulled to low level 0 (e.g. Figure 4 In V oH That is, the inverting output buffer circuit 550 outputs a low level 0V.

[0073] The present invention accelerates the opening speed of NMOS tubes 541 and 542 by means of auxiliary boost circuit and substrate voltage regulation circuit, and increases the overdrive voltage at the same time, solving the problem of weak pull-down network strength in design 1. At the same time, the threshold voltage of NMOS tubes 541 and 542 in the closing stage is increased by means of substrate voltage modulation circuit, reducing leakage power consumption. Under the same level conversion circuit size and load requirements, the high level conversion delay of the present design is about Figure 1a One quarter of the design shown, Figure 2a One-half of design two shown.

[0074] The specific structures of the level conversion circuit 540 and the inverting output buffer circuit 550 based on the cross-coupling structure can be referred to in the prior art. The specific structures are not the main improvement of the present invention and will not be described in detail here.

[0075] The high-speed level conversion circuit may include a clock edge adjustment circuit, a level boost circuit, a substrate voltage adjustment circuit, a level conversion circuit with a cross-coupled transistor as a load, and an output buffer circuit. Among them, the clock edge adjustment circuit, the level boost circuit, and the substrate voltage adjustment circuit work in the low voltage domain, and the level conversion circuit and the output buffer circuit work in the high voltage domain. The entire voltage conversion circuit has only one low voltage domain input signal ViL The input signal first passes through the clock edge adjustment circuit to generate a pair of complementary input signals V iLC and V iNLC , when the input signal V iL When switching from low to high, V iLC The signal changes from low level to high level. V iNLC The signal changes from high level to low level. At this time, V iLC The signal is used as an input signal to connect the capacitor bottom plate of the positive end level boost circuit, the control switch of the negative end level boost capacitor and the positive end substrate voltage adjustment circuit. The level boost circuit will V iLC The signal is boosted, and the body potential of the NMOS tube at the positive end of the level conversion circuit is connected to the output end of the substrate voltage regulation circuit. The body potential will increase first and then decrease. V iLC During the transition from low level to high level, the input tube at the positive end of the level conversion circuit will be turned on quickly. V iNLC The signal is used as an input signal to connect to the capacitor bottom plate of the negative end level boost circuit, the control switch of the positive end level boost capacitor and the negative end substrate voltage adjustment circuit. V iNLC The signal will precharge the negative-end level boost circuit. At the same time, the body potential of the negative-end input NMOS tube of the level conversion circuit is connected to the output end of the substrate voltage regulation circuit. The body potential will decrease first and then increase. V iNLC During the conversion from low level to high level, the input tube at the negative end of the level conversion circuit will be quickly turned off, and then the positive feedback process of the level conversion circuit will finally complete the conversion of the input signal from the low voltage domain to the high voltage domain.

[0076] In summary, the present invention creatively utilizes an auxiliary level boosting circuit and a substrate voltage regulating circuit to increase the overdrive voltage of the pull-down network of the level conversion circuit, increases the pull-down network strength without sacrificing the pull-up network strength, and realizes high-speed level conversion. Compared with the existing design, it has the characteristics of high speed and wide level conversion range when the circuit size and load size are comparable.

[0077] An embodiment of the present invention provides a chip, wherein the chip includes the high-speed level conversion circuit.

[0078] The preferred embodiments of the present invention are described in detail above in conjunction with the accompanying drawings. However, the present invention is not limited to the specific details in the above embodiments. Within the technical concept of the present invention, a variety of simple modifications can be made to the technical solution of the present invention, and these simple modifications all belong to the protection scope of the present invention.

[0079] Also need to say bright It is noted that the various specific technical features described in the above specific embodiments can be combined in any suitable manner without contradiction. In order to avoid unnecessary repetition, the present invention will not further explain various possible combinations.

[0080] In addition, various embodiments of the present invention may be arbitrarily combined, and as long as they do not violate the concept of the present invention, they should also be regarded as the contents disclosed by the present invention.

Claims

1. A high-speed level conversion circuit, characterized in that: The high-speed level conversion circuit includes: an inverse signal output circuit, a level boost circuit, a substrate voltage adjustment circuit, a level conversion circuit based on a cross-coupling structure, and an inverse output buffer circuit. The in-phase and inverted signal output circuit is used to output a first output signal in phase with the input signal and a second output signal in phase with the input signal during a rising edge of the input signal; The level boosting circuit is used to enter a charging state and raise the first output signal in response to the first output signal and the second output signal. V BS , wherein the V BS An external bias voltage for controlling the level boosting circuit; The substrate voltage regulating circuit is used to generate a positive pulse differential waveform in response to the first output signal and the second output signal to quickly turn on the first NMOS transistor in the level conversion circuit, and to generate a negative pulse differential waveform to quickly turn off the second NMOS transistor in the level conversion circuit, wherein the V BS is smaller than the threshold voltage of the first NMOS tube and the second NMOS tube; The level conversion circuit is used for pulling the output voltage to a low level 0 in response to the first NMOS tube being quickly turned on and the second NMOS tube being quickly turned off; and The inverting output buffer circuit is used to invert the output voltage to convert the low level 0 into a target level.

2. The high-speed level conversion circuit according to claim 1, characterized in that: The in-phase and inverted signal output circuit is used to output a first output signal in phase with the input signal and a second output signal in phase with the input signal during the falling edge of the input signal; The level boosting circuit is used to enter a charging state and raise the second output signal in response to the first output signal and the second output signal. V BS ; The substrate voltage regulating circuit is used to generate a positive pulse differential waveform in response to the first output signal and the second output signal to quickly turn on the second NMOS transistor in the level conversion circuit, and to generate a negative pulse differential waveform to quickly turn off the first NMOS transistor in the level conversion circuit; The level conversion circuit is used for pulling the output voltage to the target level in response to the second NMOS tube being quickly turned on and the first NMOS tube being quickly turned off; as well as The inverting output buffer circuit is used to invert the output voltage to convert the target level into a low level 0.

3. The high-speed level conversion circuit according to claim 1 or 2, characterized in that: The in-phase and inverted signal output circuit is a clock edge adjustment circuit. The clock edge adjustment circuit is further used to align the center point of the rising edge of the first output signal with the falling edge of the second output signal, and to align the center point of the falling edge of the first output signal with the rising edge of the second output signal.

4. The high-speed level conversion circuit according to claim 1 or 2, characterized in that: The level boosting circuit comprises: The first circuit is used to enter a charging state in response to the first output signal and the second output signal during a rising edge of an input signal, or to raise the second output signal in response to the first output signal and the second output signal during a falling edge of an input signal. V BS ;as well as a second circuit for raising the first output signal in response to the first output signal and the second output signal during a rising edge of an input signal; V BS , or, during the falling edge of the input signal, in response to the first output signal and the second output signal, enter the charging state.

5. The high-speed level conversion circuit according to claim 4, characterized in that: The first circuit includes: a third NMOS transistor, a gate of the third NMOS transistor is connected to the first output signal, and a source of the third NMOS transistor is connected to the external bias voltage; a first capacitor, a first end of the first capacitor is connected to the drain of the third NMOS transistor, and a second end of the first capacitor is connected to the second output signal, The second circuit includes: a fourth NMOS tube, a gate of the fourth NMOS tube is connected to the second output signal, and a source of the fourth NMOS tube is connected to the external bias voltage; a second capacitor, a first end of which is connected to the drain of the fourth NMOS tube, and a second end of which is connected to the first output signal.

6. The high-speed level conversion circuit according to claim 5, characterized in that: The first circuit further includes: a fifth NMOS transistor, the source of the fifth NMOS transistor is connected to the drain of the third NMOS transistor, the drain of the fifth NMOS transistor is connected to the first end of the first capacitor, The second circuit further includes: a sixth NMOS transistor, a source of the sixth NMOS transistor is connected to a drain of the fourth NMOS transistor, and a drain of the sixth NMOS transistor is connected to a first end of the second capacitor.

7. The high-speed level conversion circuit according to claim 5, characterized in that: The first circuit further includes: a first resistor, a first end of the first resistor is connected to the drain of the third NMOS transistor, a second end of the first resistor is connected to the first end of the first capacitor, The second circuit further includes: a second resistor, a first end of the second resistor is connected to the drain of the fourth NMOS transistor, and a second end of the second resistor is connected to the first end of the second capacitor.

8. The high-speed level conversion circuit according to claim 5, characterized in that: A first end of the second capacitor is connected to a gate of a first NMOS transistor in the level conversion circuit; The first end of the first capacitor is connected to the gate of the second NMOS transistor in the level conversion circuit.

9. The high-speed level conversion circuit according to claim 8, characterized in that: The substrate voltage regulating circuit comprises: a first micro-branch, wherein an input end of the first micro-branch is connected to the first output signal, and an output end of the first micro-branch is connected to a substrate of a first NMOS tube in the level conversion circuit; and A second micro-branch, wherein an input end of the second micro-branch is connected to the second output signal, and an output end of the second micro-branch is connected to a substrate of a second NMOS tube in the level conversion circuit.

10. A chip, characterized in that: The chip comprises the high-speed level conversion circuit according to any one of claims 1-9.

Images