A testing method for packets based on the normal and abnormal formats of PCIe Switch devices

Abstract

The present invention provides a test method for packets with normal and abnormal formats based on a PCIe Switch device. A test environment is built by using a PCIe protocol analyzer and a PCIe simulator, and the function of the PCIe Switch device is verified by using the PCIe simulator as an RC and an EP device to send packets; according to a preset test scenario, packet tests with normal and abnormal formats are performed. Advantageous effects of the present invention: A test method for packets with normal and abnormal formats based on a PCIe Switch device can, through an FPGA prototype verification system, perform packet tests with normal and abnormal formats on the PCIe Switch device before tape-out, discover design defects early, and reduce risks.

Description

Technical Field

[0001] The present invention belongs to the field of communication technologies, and in particular, relates to a method for testing packets with normal and abnormal formats based on a PCIe Switch device. Background Art

[0002] As a high-speed data interface, the PCIe Switch device is widely used in various scenarios that require high-bandwidth data transmission, such as servers, data centers, high-performance computing, etc. Its main function is to route and switch PCIe signals to achieve data interconnection between multiple PCIe devices. However, as the scale and complexity of the PCIe Switch device continue to increase, the internal packet path has become increasingly complex.

[0003] In actual application tests, due to the complexity of the internal structure of the PCIe Switch device, many types of packet paths cannot be intuitively presented to the tester. Testers usually can only judge whether the device functions properly by observing the final output results, and cannot understand in detail the transmission path and processing process of packets inside the device.

[0004] Therefore, there is an urgent need for a method that can effectively test the packet paths with normal and abnormal formats of the PCIe Switch device, so as to timely discover design defects before tape-out, improve test efficiency and coverage, and ensure the stability and reliability of the device. Summary of the Invention

[0005] In view of this, the present invention aims to propose a method for testing packets with normal and abnormal formats based on a PCIe Switch device to at least solve one of the problems in the background art.

[0006] To achieve the above object, the technical solution of the present invention is realized as follows:

[0007] A method for testing packets with normal and abnormal formats based on a PCIe Switch device, comprising:

[0008] Connecting at least two PCIe simulators to a PCIe protocol analyzer, where the first PCIe simulator simulates an RC device and the second PCIe simulator simulates an EP device, and establishing a virtual topology mapping of the PCIe Switch device based on an FPGA prototype verification system, where RC is Root Complex and EP is Endpoint;

[0009] Dynamically generating test packets with normal and abnormal formats according to a preset exception type library, where the exception type library is obtained by traversing the exception scenarios defined in the PCIe protocol specification through a finite state machine;

[0010] Inject test packets into the PCIe Switch device, capture the packet streams at the input / output ports through a protocol analyzer, and reconstruct the transmission path of the packets inside the Switch based on the timestamp synchronization mechanism and path marking fields;

[0011] Calculate path coverage rate and exception handling response time metrics based on the captured packet paths and contents, and adjust the packet types and injection frequencies of the test scenarios in real time until the preset coverage threshold is reached.

[0012] Furthermore, the construction of the FPGA prototype verification system includes:

[0013] Perform dynamic instrumentation on the RTL code of the PCIe Switch device, insert path tracing probes to capture packet jump events between virtual channels and ports;

[0014] Generate engineering constraint conditions based on coverage-driven constrained random testing, and the constraint conditions include clock domain crossing coverage rate and path branch coverage rate;

[0015] Synthesize the instrumented RTL code into an FPGA programmable file and burn it into the FPGA chip to form a prototype verification platform that supports packet path backtracking.

[0016] Furthermore, the preset exception type library includes TLP header field error, ECRC check error, and address out-of-bounds error.

[0017] Furthermore, the generation method of the exception type library includes:

[0018] Analyze the PCIe protocol specification and extract the legal field value ranges of the TLP layer and data link layer;

[0019] Generate format exception packets based on a protocol-aware mutation testing strategy, perform bit flipping, boundary value out-of-bounds, and sequence scrambling operations on legal fields to generate format exception packets;

[0020] Add error injection tags to each exception packet, and the tags contain the types of error handling mechanisms expected to trigger the Switch device.

[0021] Furthermore, generating format exception packets based on a protocol-aware mutation testing strategy includes:

[0022] According to the criticality weights of the TLP header fields defined in the PCIe protocol specification, sort the fields by priority, and the calculation formula for the criticality weights is:

[0023] = × ;

[0024] Among them, is the weight of the i-th field;

[0025] Perform bit-flip mutation on high-weight fields, and the number of flipped bits N = × field length;

[0026] Perform boundary value out-of-bounds mutation on medium and low-weight fields, and set the field value to the legal maximum value +1 or the legal minimum value - 1;

[0027] Among them, it is defined that ≥0.5 is a high-weight field, and it is defined that <0.5 is a medium and low-weight field.

[0028] Furthermore, the preset test scenarios include cross-layer path verification:

[0029] Path test from RC to EP: Configure the Bar space attribute of the EP device to be read-write, and set the remapping rule of the address translation table to verify the compliance of the Switch device with address translation;

[0030] Path test from EP to EP: Inject packets with virtual function tags between EP devices to verify the support ability of the Switch device for the SR-IOV virtualization path;

[0031] Path test from EP to RC: Simulate MSI-X interrupt packets in the EP device to verify the response accuracy of the Switch device to the priority arbitration and interrupt forwarding mechanisms.

[0032] Furthermore, the calculation method of the coverage threshold includes:

[0033] Path coverage: Calculate the ratio of the tested paths to the total paths according to the port connection relationship of the internal crossbar of the Switch device;

[0034] Exception handling coverage: Count the percentage of the triggered error handling mechanism types in the types defined by the protocol specification;

[0035] Dynamic adjustment strategy: If the path coverage is lower than the first preset threshold, add multi-hop forwarding test scenarios from EP to EP; if the exception handling coverage is lower than the second preset threshold, increase the bit-flip density of the mutation test;

[0036] The first preset threshold includes 90%, and the second preset threshold includes 85%.

[0037] Further, this solution discloses an electronic device, including a processor and a memory communicatively connected to the processor and used for storing executable instructions of the processor, where the processor is used to execute the previous test method for normal and abnormal packets in the PCIe Switch device format.

[0038] Further, this solution discloses a server, including at least one processor and a memory communicatively connected to the processor, where the memory stores instructions executable by the at least one processor, and when the instructions are executed by the processor, the at least one processor is enabled to execute a test method for normal and abnormal packets in the PCIe Switch device format.

[0039] Further, this solution discloses a computer-readable storage medium storing a computer program, where when the computer program is executed by a processor, a test method for normal and abnormal packets in the PCIe Switch device format is implemented.

[0040] Compared with the prior art, the test method for normal and abnormal packets in the PCIe Switch device format according to the present invention has the following beneficial effects:

[0041] (1) For the test method for normal and abnormal packets in the PCIe Switch device format according to the present invention, through the FPGA prototype verification system, it is possible to perform tests on normal and abnormal packets in the PCIe Switch device format before tape-out, discover design defects early, and reduce risks;

[0042] (2) For the test method for normal and abnormal packets in the PCIe Switch device format according to the present invention, by constructing three test scenarios to cover normal and abnormal packet transmission paths in different directions, it is possible to more comprehensively verify the normal and abnormal processing functions of the PCIe Switch device;

[0043] (3) For the test method for normal and abnormal packets in the PCIe Switch device format according to the present invention, using a PCIe protocol analyzer for packet collection and analysis can more accurately judge the behavior of the PCIe Switch device and improve the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] The drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0045] Figure 1Schematic diagram of building an FPGA prototype verification system according to an embodiment of the present invention;

[0046] Figure 2 Schematic diagram of the test process for the simulator in the embodiment of the present invention to send poisoned packets from the RC device to the EP device;

[0047] Figure 3 Schematic diagram of the test process for using the simulator to send poisoned packets from the EP device to the EP device according to an embodiment of the present invention;

[0048] Figure 4 Schematic diagram of the test process for using the simulator to send poisoned packets from the EP device to the RC device according to an embodiment of the present invention. Detailed implementation manners

[0049] It should be noted that, without conflict, the embodiments in the present invention and the features in the embodiments may be combined with each other.

[0050] The present invention will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0051] The present solution discloses a test method for packets in normal and abnormal formats based on a PCIe Switch device. In this embodiment, taking the test method for poisoned packets as an example, in the initial stage of chip R & D, an effective FPGA prototype verification environment and PCIe test instruments are used to test poisoned packets, providing an effective test method:

[0052] As Figure 1 shown, according to the completed RTL code, after formal verification in the UVM stage, a phased TAG file is formed for FPGA prototype verification testing. Through engineering constraints on different FPGA prototype verification platforms, the RTL code is formed into an FPGA - testable bit file and burned into the FPGA prototype verification platform for testing; for a formed chip, it is necessary to combine with the design requirements and the hardware board to form a chip verification platform (i.e., the FPGA formed board) for testing;

[0053] As Figure 2 shown, build a test environment, use a PCIe simulator as the RC device, and the EP device is a device with an editable and readable Bar space to receive packets, and connect a PCIe protocol analyzer between the Switch device and the EP device to collect the packet situation transmitted in the path:

[0054] ① Enumeration process: Send Cfg messages through the configured simulator to configure the Bus Number, Memory Base and Limit, PCI Command / status, and Bridge control of the Switch device. In this test, send cfg messages through the simulator to configure the Bus Number of the UP (Upstream Port) of the Switch device to 0x030201, Memory Base and Limit to 0xEF00EA00, PCI Command / status to 0x100547, and Bridge control to 0x10000; configure the Bus Number of the DP (Downstream Port) of the Switch device to 0x030302, Memory Base and Limit to 0xEF00ED00, PCI Command / status to 0x100547, and Bridge control to 0x10000; configure the PCI Command / status of the EP (Endpoint) port of the Switch device to 0x100547 and the Bar Address to 0xEF000000, so that the space is within the address space allocation of the Switch;

[0055] ② Poisoned message sending: Configure the simulator to send Mem type messages with the address EF000000, and enable the poisoned bit of the message to make the message a poisoned message. Collect the poisoned messages sent to the EP device through the analyzer, and compare the address of the constructed sent message with the message status collected by the analyzer to confirm that the poisoned message passes the switch verification. This process is the sending and receiving of poisoned messages through the PCIe Switch device. The processing of Switch messages requires register reading according to different design methods;

[0056] As Figure 3 shown, use the PCIe simulator as the EP device. Through the simulator properties, simulate the Nvme hard disk so that the EP is an Nvme device, and connect the PCIe protocol analyzer between the Switch device and the EP device to collect the message conditions transmitted in the path:

[0057] ① Enumeration process: Complete the link between the Switch device, EP, and simulator device through configuration. At this time, turn on the RC device and automatically complete the enumeration operation through the commercial RC. After the enumeration is completed, the mounting status of the Switch and EP devices can be viewed through the lspci command.

[0058] ② Poisoned message sending: Check the Bar space allocation of the EP using the lspci command to obtain the readable and writable address of the Bar space. Configure the simulator to send a Mem-type message to this address and enable the poisoning bit of the message to make it a poisoned message. Collect the poisoned message sent to the EP device through the analyzer and compare the address of the constructed sent message with the message status collected by the analyzer to confirm that the poisoned message passes the switch verification.

[0059] As Figure 4 shown, use a PCIe simulator as the EP device. Through the simulator properties, simulate an Nvme hard drive so that the EP is an Nvme device. Connect the PCIe protocol analyzer between the Switch device and the RC device to collect the message situation transmitted in the path:

[0060] ① Enumeration process: Complete the link by configuring the Switch device simulator. At this time, turn on the RC device and automatically complete the enumeration operation through the commercial RC. After the enumeration is completed, the mounting situation of the Switch and the simulator can be viewed using the lspci command.

[0061] ② Poisoned message sending: Allocate a memory address of the RC through software (for example, the address is FA000000 - FB000000). Configure the simulator to send a Mem-type message within this address range and enable the poisoning bit of the message to make it a poisoned message. Collect the poisoned message sent to the EP device through the analyzer and compare the address of the constructed sent message with the message status collected by the analyzer to confirm that the poisoned message passes the switch verification.

[0062] Those of ordinary skill in the art can realize that the units and method steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of the two. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0063] In several embodiments provided by the present application, it should be understood that the disclosed methods and systems can be implemented in other ways. For example, the division of the above-mentioned units is only a logical function division. In actual implementation, there can be other division methods. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. The above-mentioned units may or may not be physically separated. The components shown as units may or may not be physical units, that is, they can be located in one place or distributed to multiple network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiments of the present invention.

[0064] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention, and they should all be covered by the scope of the claims and the description of the present invention.

[0065] The above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A method for testing normal and abnormal messages based on PCIe Switch device format, characterized in that: include: A PCIe protocol analyzer is interconnected with at least two PCIe simulators, wherein a first PCIe simulator simulates an RC device and a second PCIe simulator simulates an EP device, and a virtual topology mapping of a PCIe Switch device is established based on an FPGA prototype verification system, wherein the RC is a Root Complex and the EP is an Endpoint; Dynamically generate test messages with normal and abnormal formats according to a preset abnormal type library, wherein the abnormal type library is obtained by traversing abnormal scenarios defined in the PCIe protocol specification through a finite state machine; Inject test packets into the PCIe Switch device, capture the packet flow of the input / output port through a protocol analyzer, and reconstruct the transmission path of the packet inside the Switch based on the timestamp synchronization mechanism and the path tag field; Based on the captured message path and content, the path coverage and exception handling response time indicators are calculated, and the message type and injection frequency of the test scenario are adjusted in real time until the preset coverage threshold is reached.

2. A method for testing messages with normal and abnormal formats based on PCIe Switch devices according to claim 1, characterized in that: The construction of the FPGA prototype verification system includes: Dynamically instrument the RTL code of the PCIe Switch device and insert path tracing probes to capture the message jump events between virtual channels and ports; Generate engineering constraints based on coverage-driven constrained random testing, where the constraints include clock domain crossing coverage and path branch coverage; The RTL code after the insertion is synthesized into an FPGA programmable file and burned into the FPGA chip to form a prototype verification platform that supports message path backtracing.

3. A method for testing messages with normal and abnormal formats based on PCIe Switch devices according to claim 1, characterized in that: The preset exception type library includes TLP header field error, ECRC check error, and address out-of-bounds error.

4. A method for testing messages with normal and abnormal formats based on PCIe Switch devices according to claim 1, characterized in that: The method for generating the exception type library comprises: Parse the PCIe protocol specification and extract the legal field value range of the TLP layer and data link layer; The mutation test strategy based on protocol perception generates format-abnormal messages, performs bit flipping, boundary value crossing, and sequence disorder operations on legal fields to generate format-abnormal messages; An error injection label is added to each abnormal message, where the label includes the type of error handling mechanism that is expected to be triggered by the Switch device.

5. A method for testing messages with normal and abnormal formats based on PCIe Switch devices according to claim 4, characterized in that: The protocol-aware mutation test strategy generates format-abnormal messages, including: According to the TLP header field criticality weight defined in the PCIe protocol specification, the fields are prioritized. The criticality weight calculation formula is: = × ； in, is the weight of the i-th field; Perform bit flip mutation on high-weight fields, flipping the number of bits N= ×Field length; Perform boundary value mutation on medium and low weight fields, setting the field value to the legal maximum value +1 or the legal minimum value -1; Among them, the definition ≥0.5 is a high-weight field, defined <0.5 is a medium-low weight field.

6. A method for testing messages with normal and abnormal formats based on PCIe Switch devices according to claim 1, characterized in that: The preset test scenarios include cross-level path verification: Path test from RC to EP: Configure the Bar space attribute of the EP device to be readable and writable, and set the remapping rules of the address translation table to verify the compliance of the Switch device with address translation; EP-to-EP path test: Inject packets with virtual function labels between EP devices to verify the switch device's support for SR-IOV virtualized paths. Path test from EP to RC: Simulate MSI-X interrupt messages in the EP device to verify the accuracy of the Switch device's response to the priority arbitration and interrupt forwarding mechanism.

7. A method for testing messages with normal and abnormal formats based on PCIe Switch devices according to claim 1, characterized in that: The calculation method of the coverage threshold includes: Path coverage: Calculates the ratio of tested paths to total paths based on the port connection relationship of the crossbar switch inside the Switch device; Exception handling coverage: The percentage of error handling mechanism types triggered by statistics to the types defined in the protocol specification; Dynamic adjustment strategy: If the path coverage is lower than the first preset threshold, add a multi-hop forwarding test scenario from EP to EP; if the exception handling coverage is lower than the second preset threshold, increase the bit flip density of the mutation test.

8. An electronic device, comprising a processor and a memory connected to the processor for storing instructions executable by the processor, characterized in that: The processor is used to execute a test method based on normal and abnormal messages in PCIe Switch device format as described in any one of claims 1-7 above.

9. A server, characterized in that: The invention comprises at least one processor and a memory in communication connection with the processor, wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the processor so that the at least one processor executes a test method based on normal and abnormal messages in PCIe Switch device format as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the method for testing messages based on normal and abnormal formats of a PCIe Switch device according to any one of claims 1 to 7 is implemented.

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