Semiconductor device

Abstract

The wiring member (50) has a joined surface (55) that is in contact with the joining member (60). The bonded surface (55) covers at least a portion of each of the plurality of diode regions (2) in a plan view as viewed in a direction perpendicular to the surface electrode (10). The plurality of diode regions (2) have a first diode region (21), a second diode region (22), and a third diode region (23). In plan view, the second diode region (22) is located in the first direction (101) with respect to the first diode region (21) and is separated from the first diode region (21). In plan view, the third diode region (23) is located in a second direction (102) perpendicular to the first direction (101) with respect to the first diode region (21), and is separated from each of the first diode region (21) and the second diode region (22).

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device. Background Art

[0002] Semiconductor elements such as insulated gate bipolar transistors (IGBTs) and reverse conducting insulated gate bipolar transistors (RC-IGBTs) generate heat when power is turned on, when power is started, and when power is stopped. Due to this heat, the life of a semiconductor device equipped with semiconductor elements is sometimes shortened. As a result, the reliability of the semiconductor device is reduced. Therefore, a technology for dissipating the heat generated by the heat generated by the semiconductor element is required.

[0003] As an example of a semiconductor device, Japanese Patent Application Laid-Open No. 2022-158037 describes a semiconductor device having an RC-IGBT chip disposed on a copper circuit pattern. In this semiconductor device, a lead is bonded to a surface electrode (emitter) of the RC-IGBT. The lead is used as an external wiring. Summary of the invention

[0004] When a short circuit occurs in the RC-IGBT, the IGBT region of the RC-IGBT generates heat. In particular, heat is generated in the portion of the IGBT region close to the surface electrode. According to the semiconductor device described in the above-mentioned patent document 1, the surface of the RC-IGBT is electrically connected to the outside using leads. Therefore, the heat generated in the portion of the RC-IGBT chip close to the surface electrode cannot be fully dissipated. The present disclosure is made in view of the above-mentioned situation, and its purpose is to provide a semiconductor device that can improve the heat dissipation of the portion close to the surface electrode.

[0005] The semiconductor device involved in the present disclosure includes an insulated gate bipolar transistor region, a plurality of diode regions, a surface electrode, a bonding component and a wiring component. The plurality of diode regions are in contact with the insulated gate bipolar transistor region. The surface electrode is in contact with the insulated gate bipolar transistor region and the plurality of diode regions. The bonding component is arranged on the surface electrode. The wiring component is bonded to the surface electrode through the bonding component. The insulated gate bipolar transistor region and the plurality of diode regions constitute a reverse conducting insulated gate bipolar transistor. The wiring component has a bonded surface in contact with the bonding component. When viewed from above along a direction perpendicular to the surface electrode, the bonded surface covers at least a portion of each of the plurality of diode regions. The plurality of diode regions include a first diode region, a second diode region and a third diode region. When viewed from above, the second diode region is located in a first direction relative to the first diode region and is separated from the first diode region. When viewed from above, the third diode region is located in a second direction perpendicular to the first direction relative to the first diode region and is separated from each of the first diode region and the second diode region.

[0006] The foregoing and other objects, features, aspects and advantages of the present disclosure will become apparent from the following detailed description of the present disclosure when read with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 It is a schematic plan view showing the structure of the semiconductor device according to the first embodiment.

[0008] Figure 2 It is along Figure 1 Schematic diagram of the cross section along line II-II.

[0009] Figure 3 It is a schematic plan view showing the structure of a semiconductor element.

[0010] Figure 4 It is a schematic cross-sectional view showing the structure of a semiconductor element.

[0011] Figure 5 It is a schematic plan view showing the structure of a semiconductor element according to a first modification of the first embodiment.

[0012] Figure 6 FIG. 1 is a schematic plan view showing a structure of a semiconductor element according to a second modification of the first embodiment.

[0013] Figure 7 It is a schematic plan view showing the structure of a semiconductor device according to a third modification of the first embodiment.

[0014] Figure 8 It is a schematic plan view showing the structure of a semiconductor device according to the second embodiment.

[0015] Fig. 9 It is along Figure 8 Schematic diagram of the cross section of line IX-IX.

[0016] Fig.10 It is a schematic plan view showing the structure of a semiconductor element according to the third embodiment.

[0017] Fig.11 It is a schematic plan view showing the structure of a semiconductor device according to a third embodiment.

[0018] Fig.12 It is along Fig.11 Schematic diagram of the cross section along line XII-XII.

[0019] Fig.13 It is a schematic plan view showing the structure of a semiconductor device according to a fourth embodiment.

[0020] Fig.14 It is a schematic plan view showing the structure of a semiconductor device according to the fifth embodiment.

[0021] Fig.15 It is a schematic cross-sectional view showing the structure of a semiconductor device according to a sixth embodiment.

[0022] Fig.16 It is a schematic cross-sectional view showing the structure of a semiconductor device according to a variation of the sixth embodiment.

[0023] Fig.17 It is a schematic cross-sectional view showing the structure of a semiconductor device according to a seventh embodiment.

[0024] Fig.18 It is a schematic plan view showing the structure of a semiconductor device according to an eighth embodiment.

[0025] Fig.19 It is along Fig.18 Schematic diagram of the cross section of line XIX-XIX.

[0026] Fig. 20 It is a schematic cross-sectional view showing the structure of a semiconductor device according to a ninth embodiment. DETAILED DESCRIPTION

[0027] Hereinafter, the embodiment of the present disclosure will be described based on the drawings. In addition, in the following drawings, the same or corresponding parts are denoted by the same reference numerals, and their description will not be repeated.

[0028] Implementation Method 1

[0029] <Structure of semiconductor device>

[0030] First, use Figure 1 and Figure 2 The structure of the semiconductor device 100 according to the first embodiment will be described. Figure 1 A plurality of diode regions 2 described later are shown using dotted lines.

[0031] like Figure 1 and Figure 2 As shown, the semiconductor device 100 according to the first embodiment mainly includes a semiconductor element 30, a bonding member 60, and a wiring member 50. The bonding member 60 bonds the semiconductor element 30 and the wiring member 50. The wiring member 50 electrically connects the semiconductor element 30 and an external device (not shown).

[0032] like Figure 2 and Figure 3 As shown, the semiconductor element 30 includes a front surface electrode 10, a back surface electrode 11, an insulated gate bipolar transistor region 1, a plurality of diode regions 2, and a termination region 4. In addition, the insulated gate bipolar transistor region 1 is also referred to as an IGBT region 1 hereinafter.

[0033] like Figure 2 As shown, the semiconductor element 30 has a first surface 71 and a second surface 72. The second surface 72 is located on the opposite side of the first surface 71. The direction from the first surface 71 toward the second surface 72 is set as a third direction 103. The third direction 103 is a direction perpendicular to the surface electrode 10. The surface electrode 10 is provided on the first surface 71. The surface electrode 10 is an emitter. The back electrode 11 is provided on the second surface 72. The back electrode 11 is a collector.

[0034] The IGBT region 1 and the plurality of diode regions 2 constitute the first surface 71 and the second surface 72. The IGBT region 1 is in contact with each of the front surface electrode 10 and the back surface electrode 11. The IGBT region 1 is electrically connected to each of the front surface electrode 10 and the back surface electrode 11.

[0035] like Figure 2 As shown, each of the plurality of diode regions 2 is in contact with the IGBT region 1. Each of the plurality of diode regions 2 is in contact with each of the surface electrode 10 and the back electrode 11. Each of the plurality of diode regions 2 is electrically connected to each of the surface electrode 10 and the back electrode 11.

[0036] The plurality of diode regions 2 are separated from each other. When viewed in a direction perpendicular to the surface electrode 10 (hereinafter also referred to as a plan view), each of the plurality of diode regions 2 has a rectangular shape, for example.

[0037] The terminal region 4 is in contact with the IGBT region 1. The terminal region 4 surrounds the IGBT region 1 and the plurality of diode regions 2. The terminal region 4 constitutes a part of the second surface 72. The detailed structure of the terminal region 4 will be described later.

[0038] like Figure 2 As shown, the bonding member 60 is provided on the surface electrode 10 . The bonding member 60 is, for example, solder. The bonding member 60 is surrounded by the terminal region 4 in a plan view. The bonding member 60 transfers heat from the surface electrode 10 to the wiring member 50 .

[0039] The wiring member 50 is metal-bonded to the surface electrode 10 via the bonding member 60. Specifically, the wiring member 50 is electrically connected to the surface electrode 10 via the bonding member 60. The wiring member 50 is made of metal.

[0040] like Figure 1 and Figure 2 As shown, the wiring component 50 has a flat plate portion 49 and a conductive plate portion 51. The wiring component 50 is a DLB (Direct Lead Bonding) electrode. When viewed from above, the flat plate portion 49 is rectangular in shape. The flat plate portion 49 is in contact with the bonding component 60. In the third direction 103, the bonding component 60 is provided between the flat plate portion 49 and the surface electrode 10. The flat plate portion 49 can also be separated from the surface electrode 10. When viewed from above, the flat plate portion 49 is surrounded by the terminal area 4.

[0041] like Figure 1 and Figure 2 As shown, the flat plate portion 49 has a first end portion 81 and a second end portion 82. The first end portion 81 extends, for example, along the extending direction of the long sides of the plurality of diode regions 2. In the flat plate portion 49, the second end portion 82 is disposed on the opposite side of the first end portion 81. The extending direction of the second end portion 82 may be substantially parallel to the extending direction of the first end portion 81, for example.

[0042] like Figure 2 As shown, the flat plate portion 49 has a joined surface 55 and a surface 56. The joined surface 55 is a surface of the flat plate portion 49 that contacts the joining member 60. In other words, the flat plate portion 49 is in contact with the joining member 60 at the joined surface 55. The joined surface 55 is, for example, planar. The surface 56 is on the opposite side of the joined surface 55. From another perspective, the surface 56 is arranged in a direction opposite to the third direction 103 relative to the joined surface 55.

[0043] like Figure 1 As shown, when viewed from above, the flat plate portion 49 covers at least a portion of each of the plurality of diode regions 2. From another perspective, when viewed from above, the bonded surface 55 (see Figure 2 ) covers at least a portion of each of the plurality of diode regions 2.

[0044] like Figure 1 and Figure 2 As shown, the conductive plate portion 51 is connected to the flat plate portion 49. Specifically, for example, at the first end portion 81, the conductive plate portion 51 is connected to the flat plate portion 49. The conductive plate portion 51 is, for example, arranged in a direction opposite to the third direction 103 relative to the flat plate portion 49. The conductive plate portion 51 is separated from the bonding member 60. The interface between the conductive plate portion 51 and the flat plate portion 49 becomes a connecting portion 59. In other words, at the connecting portion 59, the conductive plate portion 51 and the flat plate portion 49 are connected. The conductive plate portion 51 constitutes a path for the current flowing between the surface electrode 10 and an external device (not shown).

[0045] The extending direction of the conductive plate portion 51 is substantially parallel to the extending direction of the long sides of the plurality of diode regions 2. In other words, the connecting portion 59 extends along the direction in which the long sides of each of the plurality of diode regions 2 extend.

[0046] <Structure of semiconductor devices>

[0047] Next, use Figure 3 and Figure 4 The structure of the semiconductor element 30 will be described. Figure 3 The surface electrode 10 is not shown. Figure 4 The cross section shown is a cross section perpendicular to the surface electrode 10 .

[0048] like Figure 3 As shown, the semiconductor element 30 is an island type RC-IGBT. Specifically, a plurality of diode regions 2 are arranged in an island shape. From another perspective, in a region overlapping with a surface electrode 10, two or more diode regions 2 are arranged in a row along the first direction 101 and the second direction 102 when viewed from above.

[0049] The plurality of diode regions 2 include a first diode region 21, a second diode region 22, and a third diode region 23. The first diode region 21 is, for example, a diode region 2 located at a corner among the plurality of diode regions 2. The second diode region 22 is separated from the first diode region 21. When viewed from above, the direction from the first diode region 21 toward the second diode region 22 is the first direction 101. From another perspective, when viewed from above, the second diode region 22 is located in the first direction 101 relative to the first diode region 21.

[0050] The third diode region 23 is separated from each of the first diode region 21 and the second diode region 22. When viewed from above, the direction from the first diode region 21 toward the third diode region 23 is the second direction 102. From another perspective, the third diode region 23 is located in the second direction 102 relative to the first diode region 21. The second direction 102 is a direction perpendicular to the first direction 101. The long sides of each of the plurality of diode regions 2 may be parallel to the second direction 102, for example.

[0051] like Figure 3 As shown, the plurality of diode regions 2 have a plurality of columns 20. Each of the plurality of columns 20 is composed of a plurality of diode regions 2 arranged along the second direction 102. The number of diode regions 2 included in one column 20 is not particularly limited, and is, for example, 4. In the column 20, for example, the four diode regions 2 may also be arranged substantially at equal intervals along the second direction 102. The plurality of columns 20 are arranged along the first direction 101. The plurality of columns 20 may also be arranged at equal intervals along the first direction 101. The number of columns 20 is not particularly limited, and is, for example, 8.

[0052] Each of the plurality of diode regions 2 is surrounded by the IGBT region 1. From another perspective, the IGBT region 1 has a portion sandwiched by two diode regions 2 in the first direction 101. The IGBT region 1 has a portion sandwiched by two diode regions 2 in the second direction 102.

[0053] The semiconductor element 30 is shaped like a rectangle when viewed from above. When viewed from above, the direction in which the long sides of the semiconductor element 30 extend is a first direction 101 . When viewed from above, the direction in which the short sides of the semiconductor element 30 extend is a second direction 102 .

[0054] like Figure 4 As shown, the semiconductor element 30 has a semiconductor substrate 70. The structure of the diode region 2 is described. The semiconductor substrate 70 has, for example, an n-type drift layer 43, an n+ type carrier storage layer 32, a p-type base layer 35, a p-type anode layer 28, an n-type buffer layer 37, and an n+ type cathode layer 29.

[0055] The n+ type carrier storage layer 32 is provided on the n− type drift layer 43. The n+ type carrier storage layer 32 has a higher concentration of n-type impurities than the n− type drift layer 43. The p type base layer 35 is provided on the n+ type carrier storage layer 32.

[0056] The p-type anode layer 28 is provided on the p-type base layer 35. The p-type anode layer 28 is provided in the diode region 2. The p-type impurity concentration of the p-type anode layer 28 is higher than the p-type impurity concentration of the p-type base layer 35. The p-type anode layer 28 constitutes the first surface 71 (refer to Figure 2) part.

[0057] The n-type buffer layer 37 is provided in the third direction 103 with respect to the n-type drift layer 43. The n-type buffer layer 37 is in contact with the n-type drift layer 43. The n-type buffer layer 37 has a higher concentration of n-type impurities than the n-type drift layer 43.

[0058] The n+ type cathode layer 29 is provided in the third direction 103 relative to the n type buffer layer 37. The n+ type cathode layer 29 is in contact with the n type buffer layer 37. The n+ type cathode layer 29 is provided in the diode region 2. The n+ type cathode layer 29 is electrically connected to the back electrode 11. The n+ type cathode layer 29 constitutes the second surface 72 (refer to Figure 2 ) part.

[0059] The semiconductor substrate 70 in the diode region 2 is provided with a first trench gate 31 a. The first trench gate 31 a extends from the first surface 71 toward the third direction 103. The first trench gate 31 a reaches the n− type drift layer 43. The first trench gate 31 a is electrically connected to the surface electrode 10.

[0060] Next, the structure of the IGBT region 1 is described. The semiconductor substrate 70 has an n+ type source layer 33, a p+ type contact layer 38, and a p-type collector layer 36. The n+ type source layer 33 is provided on the p-type base layer 35. The n+ type source layer 33 is provided in the IGBT region 1. The n+ type source layer 33 constitutes the first surface 71 (see Figure 2 ) part.

[0061] The p+ type contact layer 38 is provided on the p-type base layer 35. The p+ type contact layer 38 is provided in the IGBT region 1 and the terminal region 4. The p+ type contact layer 38 is separated from the n+ type source layer 33. The p-type impurity concentration of the p+ type contact layer 38 is higher than the p-type impurity concentration of the p-type base layer 35. The p-type impurity concentration of the p+ type contact layer 38 may be the same as the p-type impurity concentration of the p-type anode layer 28.

[0062] The p-type collector layer 36 is provided in the third direction 103 with respect to the n-type buffer layer 37. The p-type collector layer 36 is in contact with the n-type buffer layer 37. The p-type collector layer 36 is provided in the IGBT region 1. The p-type collector layer 36 constitutes the second surface 72 (see Figure 2 ). The p-type collector layer 36 is electrically connected to the back electrode 11. The p-type collector layer 36 is in contact with the n+ type cathode layer 29. The interface between the p-type collector layer 36 and the n+ type cathode layer 29 becomes the boundary between the diode region 2 and the IGBT region 1.

[0063] A second trench gate 31b and a third trench gate 31c are provided on the semiconductor substrate 70 in the IGBT region 1. The second trench gate 31b extends from the first surface 71 along the third direction 103. The second trench gate 31b reaches the n-type drift layer 43. The second trench gate 31b is in contact with the n+ type source layer 33. An interlayer insulating film 34 is provided on the second trench gate 31b. The second trench gate 31b and the surface electrode 10 are electrically insulated by the interlayer insulating film 34.

[0064] The third trench gate 31c extends from the first surface 71 along the third direction 103. The third trench gate 31c reaches the n-type drift layer 43. The third trench gate 31c is in contact with the p+ type contact layer 38. The third trench gate 31c is electrically connected to the surface electrode 10.

[0065] Next, the structure of the termination region 4 will be described. The semiconductor substrate 70 includes a p-type termination well layer 41, an n+ type channel stop layer 42, and a p-type termination collector layer 36a.

[0066] The p-type termination well layer 41 is provided in the termination region 4. The p-type termination well layer 41 is in contact with the n-type drift layer 43. The p-type termination well layer 41 constitutes the first surface 71 (see Figure 2 ). The semiconductor substrate 70 has, for example, three p-type terminal well layers 41. Each of the three p-type terminal well layers 41 is separated from each other. When viewed from above, each of the three p-type terminal well layers 41 has a ring shape. Each of the three p-type terminal well layers 41 surrounds the IGBT region 1 and the plurality of diode regions 2.

[0067] The n+ type channel stopper layer 42 is provided in the termination region 4. The n+ type channel stopper layer 42 constitutes the first surface 71 (see Figure 2 ). The n+ type channel stopper layer 42 has a ring shape when viewed from above. The n+ type channel stopper layer 42 surrounds the p type termination well layer 41.

[0068] A termination electrode 10a is provided on the p-type termination well layer 41 and the n+ type channel stop layer 42. The termination electrode 10a is electrically connected to the p-type termination well layer 41 and the n+ type channel stop layer 42.

[0069] The terminal region 4 is provided with a terminal protection film 5. The terminal protection film 5 covers the surface electrode 10, the terminal electrode 10a and the interlayer insulating film 34. The terminal protection film 5 is made of polyimide, for example. The end surface of the terminal protection film 5 close to the IGBT region 1 serves as a boundary between the terminal region 4 and the IGBT region 1.

[0070] The p-type terminal collector layer 36a is provided in the third direction 103 with respect to the n-type buffer layer 37. The p-type terminal collector layer 36a is in contact with the n-type buffer layer 37. The p-type terminal collector layer 36a is provided in the terminal region 4. The p-type terminal collector layer 36a constitutes the second surface 72 (see Figure 2 ) part. The structure of the p-type terminal collector layer 36a is substantially the same as the structure of the p-type collector layer 36.

[0071] Next, the operation and effects of the semiconductor device 100 according to the first embodiment will be described.

[0072] The RC-IGBT generates heat during power-on, at the start of power-on, and at the end of power-on. Specifically, when power is applied to the IGBT region 1, the IGBT region 1 generates heat. Sometimes a copper circuit pattern is connected to the back electrode 11 of the RC-IGBT. In this case, the copper circuit pattern is used to dissipate heat from the portion of the RC-IGBT close to the back electrode 11. However, when a short circuit occurs in the RC-IGBT, particularly large amounts of heat are generated in the portion of the IGBT region 1 close to the surface electrode 10. In this case, the RC-IGBT is sometimes immediately damaged due to the heat.

[0073] According to the semiconductor device 100 involved in the first embodiment, the bonded surface 55 of the wiring member 50 covers at least a portion of each of the plurality of diode regions 2 when viewed from above. When viewed from above, the second diode region 22 is located in the first direction 101 relative to the first diode region 21. The second diode region 22 is separated from the first diode region 21. When viewed from above, the third diode region 23 is located in the second direction 102 relative to the first diode region 21. The third diode region 23 is separated from each of the first diode region 21 and the second diode region 22. Therefore, the contact area between the plurality of diode regions 2 and the IGBT region 1 can be increased. As a result, when the IGBT region 1 generates heat, heat can be efficiently transferred from the IGBT region 1 to the plurality of diode regions 2. In addition, by covering at least a portion of each of the plurality of diode regions 2, the bonded surface 55 can efficiently transfer heat from each of the plurality of diode regions 2 to the wiring member 50. As a result, the heat dissipation of the portion of the semiconductor device 100 close to the surface electrode 10 can be improved.

[0074] According to the semiconductor device 100 according to the first embodiment, the heat dissipation of the portion of the semiconductor device 100 close to the surface electrode 10 can be improved. Therefore, when a short circuit occurs in the RC-IGBT, the temperature of the semiconductor device 100 can be prevented from being excessively increased locally. As a result, the short circuit tolerance of the semiconductor device 100 can be increased.

[0075] According to the semiconductor device 100 involved in the first embodiment, the shape of the first diode region 21 is a rectangle when viewed from above. The wiring component 50 has a flat plate portion 49 and a conductive plate portion 51. The connecting portion 59 between the flat plate portion 49 and the conductive plate portion 51 extends in the direction in which the long side of the first diode region 21 extends. Therefore, compared with the case where the connecting portion 59 extends in the direction in which the short side of the first diode region 21 extends, the uniformity of the current flowing between the first diode region 21 and the connecting portion 59 can be improved. Therefore, the increase in the amount of heat caused by the local concentration of current can be suppressed. As a result, when the plurality of diode regions 2 are energized, the heat dissipation of the semiconductor device 100 can be improved.

[0076] (First Modification of Implementation Example 1)

[0077] Next, use Figure 5 The structure of the semiconductor device 100 according to the first modification of the first embodiment will be described. Figure 5 The surface electrode 10 is not shown.

[0078] In the above description, the structure in which each of the plurality of diode regions 2 is rectangular in shape when viewed from above is described, but the structure of the semiconductor device 100 involved in the present disclosure is not limited to the above structure. Figure 5 As shown, when viewed from above, each of the plurality of diode regions 2 may also be in a square shape. From another perspective, the length of the diode region 2 in the first direction 101 and the length of the diode region 2 in the second direction 102 may also be substantially the same. One side of each of the plurality of diode regions 2 is substantially parallel to the first direction 101.

[0079] Thus, the difference between the uniformity of the current flowing between the plurality of diode regions 2 and the connection portion 59 when the connection portion 59 of the wiring member 50 extends along the first direction 101 and the uniformity of the current flowing between the plurality of diode regions 2 and the connection portion 59 when the connection portion 59 extends along the second direction 102 can be reduced. From another perspective, the heat dissipation of the semiconductor device 100 can be sufficiently improved in both the case where the connection portion 59 extends along the first direction 101 and the case where the connection portion 59 extends along the second direction 102. Therefore, the configuration of the conductive plate portion 51 can be determined in consideration of the wiring between the conductive plate portion 51 and the external device while maintaining the heat dissipation of the plurality of diode regions 2. As a result, the degree of freedom of wiring can be improved.

[0080] (Second Modification of Implementation Example 1)

[0081] Next, use Figure 6The structure of the semiconductor device 100 according to the second modification of the first embodiment will be described. Figure 6 The surface electrode 10 is not shown.

[0082] like Figure 6 As shown, the density of the diode regions 2 may also be reduced in the center of the region where the plurality of diode regions 2 are arranged. Specifically, when viewed from above, the smallest rectangular region surrounding all of the plurality of diode regions 2 is the imaginary region 91. The imaginary line located between the outer edge (first outer edge 92) of the imaginary region 91 and the center (first center 93) of the imaginary region 91 is the boundary line 95.

[0083] The imaginary region 91 is composed of an outer peripheral region 96 and a central region 97. The outer peripheral region 96 is located between the first outer edge 92 and the boundary line 95. The central region 97 is located inside the boundary line 95. The central region 97 is connected to the outer peripheral region 96. The central region 97 is surrounded by the outer peripheral region 96.

[0084] When viewed from above, the density of the plurality of diode regions 2 in the central region 97 is smaller than the density of the plurality of diode regions 2 in the peripheral region 96. The size of the diode region 2 in the central region 97 may also be smaller than the size of the diode region 2 in the peripheral region 96. Specifically, for example, the length of the diode region 2 in the second direction 102 in the central region 97 is shorter than the length of the diode region 2 in the second direction 102 in the peripheral region 96.

[0085] The length of the diode region 2 in the central region 97 in the first direction 101 may be substantially the same as the length of the diode region 2 in the peripheral region 96 in the first direction 101. In a plan view, the plurality of diode regions 2 may include square diode regions 2 and rectangular diode regions 2.

[0086] When the plurality of diode regions 2 are energized, the temperature of the central region 97 is likely to rise compared to the peripheral region 96. According to the semiconductor device 100 according to the second modification of the first embodiment, the density of the plurality of diode regions 2 in the central region 97 is smaller than the density of the plurality of diode regions 2 in the peripheral region 96 when viewed from above. Therefore, when the plurality of diode regions 2 are energized, it is possible to suppress the temperature of the central region 97 from becoming excessively higher than the temperature of the peripheral region 96. Thus, when the plurality of diode regions 2 are energized, the heat dissipation of the portion of the semiconductor device 100 close to the surface electrode 10 can be improved.

[0087] (Third Modification of Implementation Example 1)

[0088] Next, use Figure 7The structure of the semiconductor device 100 according to the third modification of the first embodiment will be described. Figure 7 As shown, the wiring member 50 may also cover the entirety of each of the plurality of diode regions 2. Specifically, when viewed from above, the bonded surface 55 (see Figure 2 ) may also cover the entirety of each of the plurality of diode regions 2. When viewed from above, the bonding member 60 (see Figure 2 ) may also cover the entirety of each of the plurality of diode regions 2. From another perspective, the plurality of diode regions 2 are surrounded by the outer edge of the flat plate portion 49 when viewed from above.

[0089] This can further increase the heat energy transferred from the plurality of diode regions 2 to the wiring member 50 via the surface electrode 10 and the bonding member 60. Therefore, the heat dissipation of the portion of the semiconductor device 100 close to the surface electrode 10 can be further improved.

[0090] In addition, in the above description, the structure in which the first diode region 21 is located at the corners of the plurality of diode regions 2 is described, but the position of the first diode region 21 may not be the corners of the plurality of diode regions 2. The diode region 2 may be provided in a direction opposite to the first direction 101 and in a direction opposite to the second direction 102 with respect to the first diode region 21.

[0091] Implementation Method 2

[0092] Next, use Figure 8 and Fig. 9 The structure of the semiconductor device 100 according to the second embodiment will be described. The semiconductor device 100 according to the second embodiment mainly differs from the semiconductor device 100 according to the first embodiment in that it has a protective film 6, and is substantially the same as the semiconductor device 100 according to the first embodiment in other respects. The following will focus on the differences from the semiconductor device 100 according to the first embodiment.

[0093] like Figure 8 and Fig. 9As shown, the semiconductor device 100 may also have a protective film 6. The protective film 6 is provided on the terminal region 4. The protective film 6 covers the terminal region 4. The protective film 6 is in contact with the surface electrode 10. The protective film 6 covers a portion of the surface electrode 10. When viewed from above, the protective film 6 surrounds the plurality of diode regions 2. The protective film 6 is composed of, for example, a nitride film such as polyimide, a silicon nitride film (SiN: Silicon Nitride) and a semi-insulating silicon nitride film (SInSiN: Semi-Insulating Silicon Nitride), or an oxide film such as SIPOS (Semi-Insulating Poly-crystalline Silicon). By providing the protective film 6 on the terminal region 4, the concentration of the electric field in the terminal region 4 can be alleviated.

[0094] Implementation 3

[0095] Next, use Figures 10 to 12 The structure of the semiconductor device 100 according to the third embodiment will be described. The semiconductor device 100 according to the third embodiment mainly differs from the semiconductor device 100 according to the first embodiment in that the distance between the outer edge of the bonded surface 55 and each of the terminal regions 4 and the plurality of diode regions 2 when viewed from above is sufficiently long, and the other points are substantially the same as the semiconductor device 100 according to the first embodiment. The following will focus on the points that are different from the semiconductor device 100 according to the first embodiment.

[0096] like Fig.10 As shown, the shortest distance between the terminal region 4 and the plurality of diode regions 2 when viewed from above is set to a first distance L1. Specifically, the first distance L1 is the distance between the terminal protection film 5 of the terminal region 4 (see Figure 4 ) and the n+ type cathode layer 29 (refer to Figure 4 The first distance L1 is, for example, the shortest distance between the terminal region 4 and the plurality of diode regions 2 in the first direction 101.

[0097] like Fig.11 and Fig.12 As shown, the joined surface 55 (see Fig.12 The shortest distance between the outer edge (second outer edge 98) of the n+ type cathode layer 29 and the plurality of diode regions 2 is set to the second distance L2. Specifically, the second distance L2 is the distance between the second outer edge 98 and the n+ type cathode layer 29 (see FIG. Figure 4 The second distance L2 is, for example, the shortest distance between the second outer edge 98 and the plurality of diode regions 2 in the first direction 101. When viewed from above, the second outer edge 98 may substantially overlap with the outer edge of the flat plate portion 49.

[0098] like Fig.12 As shown, the distance between the first surface 71 and the second surface 72 in the third direction 103 is set to the thickness H of the IGBT region 1 in the third direction 103. The thickness H is the thickness of the semiconductor substrate 70 (see Figure 4 ). The thickness H is substantially the same as the thickness of the diode region 2 in the third direction 103.

[0099] like Figures 10 to 12 As shown, the first distance L1 is greater than the thickness H. The second distance L2 is greater than the thickness H. The second distance L2 is shorter than the first distance L1.

[0100] According to the semiconductor device 100 according to the third embodiment, the first distance L1 is equal to or greater than the thickness H. Thus, the distance between the terminal region 4 and the plurality of diode regions 2 becomes sufficiently long. Thus, it is possible to suppress the inflow of holes from the terminal region 4 into the plurality of diode regions 2. Thus, when the plurality of diode regions 2 are energized, it is possible to suppress the loss of power.

[0101] When the plurality of diode regions 2 are energized, carriers diffuse from the diode region 2 in a direction inclined at an angle of 45° or less relative to the third direction 103. Heat is generated in the region where the carriers diffuse. According to the semiconductor device 100 involved in the third embodiment, the second distance L2 is greater than or equal to the thickness H. Therefore, when viewed from above, the bonded surface 55 can cover the region where the carriers diffuse when the plurality of diode regions 2 are energized. As a result, the heat dissipation of the semiconductor device 100 can be further improved.

[0102] Implementation 4

[0103] Next, use Fig.13 The structure of the semiconductor device 100 according to the fourth embodiment is described. The semiconductor device 100 according to the fourth embodiment mainly differs from the semiconductor device 100 according to the first embodiment in that the semiconductor device 100 has a diode region 2 arranged with a gate pad 7 interposed therebetween, and is substantially the same as the semiconductor device 100 according to the first embodiment in other respects. The following describes the differences from the semiconductor device 100 according to the first embodiment.

[0104] like Fig.13As shown, the semiconductor device 100 has a gate pad 7. When viewed from above, the gate pad 7 is provided, for example, in a first direction 101 relative to the center (second center 94) of the surface electrode 10. The gate pad 7 is adjacent to the terminal region 4, for example. When viewed from above, an imaginary line passing through the second center 94 and parallel to the first direction 101 is set as a center line A. When viewed from above, the center line A passes through the gate pad 7, for example. The gate pad 7 is configured to be input to the control IGBT region 1 (refer to Figure 2 ) is turned on.

[0105] In the semiconductor device 100 , the gate pad 7 is provided on the opposite side to the back surface electrode 11 . From another perspective, the gate pad 7 is provided in the direction opposite to the third direction 103 with respect to the IGBT region 1 .

[0106] The plurality of diode regions 2 have two sets of diode regions sandwiching pads. Specifically, the plurality of diode regions 2 have a fourth diode region 24, a fifth diode region 25, a sixth diode region 26, and a seventh diode region 27. The fourth diode region 24, the fifth diode region 25, the sixth diode region 26, and the seventh diode region 27 are separated from each other.

[0107] The fifth diode region 25 is disposed in the second direction 102 relative to the fourth diode region 24. In the second direction 102, the fourth diode region 24 and the fifth diode region 25 are disposed across the gate pad 7. From another perspective, the gate pad 7 is disposed between the fourth diode region 24 and the fifth diode region 25 in a plan view.

[0108] The seventh diode region 27 is disposed in the second direction 102 relative to the sixth diode region 26. In the second direction 102, the sixth diode region 26 and the seventh diode region 27 are disposed across the gate pad 7. From another perspective, the gate pad 7 is disposed between the sixth diode region 26 and the seventh diode region 27 in a plan view.

[0109] The flat plate portion 49 does not cover the gate pad 7. From another perspective, the bonded surface 55 (see Figure 2 ) is separated from the gate pad 7. When viewed from above, the portion of the flat plate portion 49 close to the gate pad 7 is divided into two branches. Specifically, the flat plate portion 49 has a main body 80, a first portion 61, and a second portion 62. The first portion 61 is connected to the main body 80. The first portion 61 is arranged in a first direction 101 relative to the main body 80. When viewed from above, the first portion 61 overlaps with each of the fourth diode region 24 and the sixth diode region 26.

[0110] The second portion 62 is connected to the main body 80. The second portion 62 is disposed in the first direction 101 relative to the main body 80. The second portion 62 is separated from the first portion 61. The second portion 62 is disposed in the second direction 102 relative to the first portion 61. The second portion 62 overlaps each of the fifth diode region 25 and the seventh diode region 27 when viewed from above. The gate pad 7 is disposed between the first portion 61 and the second portion 62 when viewed from above.

[0111] When viewed from above, the conductive plate portion 51 is, for example, disposed in a direction opposite to the gate pad 7 relative to the second center 94. From another perspective, when viewed from above, the conductive plate portion 51 is, for example, disposed in a direction opposite to the first direction 101 relative to the second center 94. When viewed from above, the second center 94 is, for example, located between the conductive plate portion 51 and the gate pad 7.

[0112] According to the semiconductor device 100 involved in the fourth embodiment, the plurality of diode regions 2 include the fourth diode region 24 and the fifth diode region 25. The gate pad 7 is provided between the fourth diode region 24 and the fifth diode region 25. Therefore, compared with the case where the fourth diode region 24 and the fifth diode region 25 are not provided, when the total area of ​​the plurality of diode regions 2 in a plan view is the same, the density of the plurality of diode regions 2 can be reduced. Therefore, the heat dissipation of the portion of the semiconductor device 100 close to the surface electrode 10 when the plurality of diode regions 2 are energized can be improved.

[0113] According to the semiconductor device 100 involved in the fourth embodiment, the flat plate portion 49 has the first portion 61 and the second portion 62. When viewed from above, the first portion 61 overlaps with the fourth diode region 24. When viewed from above, the second portion 62 overlaps with the fifth diode region 25. Therefore, it is possible to increase the heat energy transferred from each of the fourth diode region 24 and the fifth diode region 25 to the wiring member 50. As a result, the heat dissipation of the fourth diode region 24 and the fifth diode region 25 can be improved.

[0114] According to the semiconductor device 100 according to the fourth embodiment, the conductive plate portion 51 is provided in the direction opposite to the gate pad 7 with respect to the second center 94 in a plan view. Therefore, interference between the gate wiring connected to the gate pad 7 and the conductive plate portion 51 can be suppressed. Thus, the degree of freedom of wiring can be improved.

[0115] Furthermore, the plurality of diode regions 2 may include one set of sandwiched pad diode regions. In other words, the plurality of diode regions 2 may not include the sixth diode region 26 and the seventh diode region 27.

[0116] Implementation method 5

[0117] Next, use Fig.14 The structure of the semiconductor device 100 according to the fifth embodiment will be described. The semiconductor device 100 according to the fifth embodiment mainly differs from the semiconductor device 100 according to the fourth embodiment in that the temperature detection diode 8 is covered by the bonding surface 55, and is substantially the same as the semiconductor device 100 according to the fourth embodiment in other respects. The following will focus on the differences from the semiconductor device 100 according to the fourth embodiment.

[0118] like Fig.14 As shown, the semiconductor device 100 has a temperature detection diode 8, an anode pad 12, and a cathode pad 13. When viewed from above, the temperature detection diode 8 is disposed between any two diode regions among the plurality of diode regions 2. The temperature detection diode 8 is disposed, for example, near the center of the semiconductor device 100. Specifically, when viewed from above, the second center 94 may overlap with the temperature detection diode 8. When viewed from above, the center line A may pass through the temperature detection diode 8. When viewed from above, the flat plate portion 49 covers the temperature detection diode 8. From another perspective, when viewed from above, the bonded surface 55 (see Figure 2 ) covers the temperature detection diode 8.

[0119] The anode pad 12 is electrically connected to the temperature detection diode 8. The cathode pad 13 is electrically connected to the temperature detection diode 8. When viewed from above, the flat plate portion 49 does not cover each of the anode pad 12 and the cathode pad 13. In other words, when viewed from above, the bonded surface 55 (see Figure 2 ) is separated from each of the anode pad 12 and the cathode pad 13.

[0120] When viewed from above, the conductive plate portion 51 may be disposed in the first direction 101 relative to the second center 94. When viewed from above, the conductive plate portion 51 may be disposed between the second center 94 and the gate pad 7. In addition, when the semiconductor device 100 has a plurality of surface electrodes 10, the second center 94 is set to be the center of the smallest rectangular region surrounding all of the plurality of surface electrodes 10 when viewed from above.

[0121] According to the semiconductor device 100 according to the fifth embodiment, the temperature detection diode 8 is covered by the bonding surface 55. Therefore, heat can be easily transferred from the temperature detection diode 8 to the wiring member 50. Thus, the heat dissipation property of the temperature detection diode 8 can be improved.

[0122] In addition, the temperature detection diode 8 may also be disposed along the gate pad 7 . The temperature detection diode 8 may also be disposed in the first direction 101 relative to the second center 94 .

[0123] Implementation 6

[0124] Next, use Fig.15 The structure of the semiconductor device 100 according to the sixth embodiment is described. The semiconductor device 100 according to the sixth embodiment is different from the semiconductor device 100 according to the first embodiment mainly in that the wiring member 50 has a rising portion 52. The other aspects are substantially the same as the semiconductor device 100 according to the first embodiment. The following describes the differences from the semiconductor device 100 according to the first embodiment. In addition, Fig.15 The cross section shown is Figure 2 The cross section shown corresponds.

[0125] like Fig.15 As shown, the wiring member 50 has a rising portion 52. The rising portion 52 is connected to the flat plate portion 49. The rising portion 52 is different from the conductive plate portion 51. At the second end portion 82, the rising portion 52 is connected to the flat plate portion 49. The rising portion 52 is separated from the conductive plate portion 51. The rising portion 52 is inclined relative to the flat plate portion 49 in a direction from the surface electrode 10 toward the flat plate portion 49. The inclination angle of the rising portion 52 relative to the flat plate portion 49 is not particularly limited.

[0126] According to the semiconductor device 100 according to the sixth embodiment, the wiring member 50 has the rising portion 52. Therefore, the surface area of ​​the wiring member 50 can be increased compared to the case where the wiring member 50 does not have the rising portion 52. Thus, the heat dissipation from the wiring member 50 to the outside of the semiconductor device 100 can be improved.

[0127] (Variation of Implementation Example 6)

[0128] like Fig.16 As shown, a first concave-convex portion 53 may also be provided on the surface 56 of the flat plate portion 49. Specifically, a plurality of first concave portions 75 and a plurality of first convex portions 76 may also be provided on the surface 56. Each of the plurality of first convex portions 76 is separated from each other. In the first direction 101, the plurality of first convex portions 76 are provided between the conductive plate portion 51 and the rising portion 52. A first concave portion 75 is provided between two adjacent first convex portions 76. Each of the plurality of first convex portions 76 extends, for example, along the second direction 102. The size of each of the plurality of first concave portions 75 and the plurality of first convex portions 76 is not particularly limited.

[0129] According to the semiconductor device 100 according to the modification of the sixth embodiment, the first concavo-convex portion 53 is provided on the surface 56 of the flat plate portion 49. This can further increase the surface area of ​​the wiring member 50. As a result, the heat dissipation of the semiconductor device 100 can be further improved.

[0130] Implementation 7

[0131] Next, the structure of the semiconductor device 100 according to the seventh embodiment will be described. The semiconductor device 100 according to the seventh embodiment mainly differs from the semiconductor device 100 according to the sixth embodiment in that the flat plate portion 49 has the third protrusion 79, and is substantially the same as the semiconductor device 100 according to the sixth embodiment in other respects. The following description will focus on the differences from the semiconductor device 100 according to the sixth embodiment.

[0132] like Fig.17 As shown, the flat plate portion 49 has a plate-shaped portion 48 and a third protrusion 79. The plate-shaped portion 48 is a portion constituting the surface 56, the first end portion 81, and the second end portion 82. The third protrusion 79 is arranged in the third direction 103 relative to the plate-shaped portion 48. The third protrusion 79 is convex along the third direction 103. The plate-shaped portion 48 and the third protrusion 79 constitute the bonded surface 55. The third protrusion 79 is in contact with the bonding component 60. The bottom surface of the third protrusion 79 can be, for example, flat, or can be convex along the third direction 103. The third protrusion 79 can also be separated from the surface electrode 10. When viewed from above, the third protrusion 79 is, for example, surrounded by the bonding component 60. When viewed from above, for example, the third protrusion 79 can also cover the entirety of each of the plurality of diode regions 2.

[0133] According to the semiconductor device 100 involved in the seventh embodiment, the flat plate portion 49 has the third protrusion 79. Therefore, in the process of manufacturing the semiconductor device 100, the third protrusion 79 pushes the bonding member 60 before curing outward along the in-plane direction perpendicular to the third direction 103. As a result, the flat plate portion 49 and the bonding member 60 can be effectively brought into close contact. As a result, the generation of a gap at the boundary between the flat plate portion 49 and the bonding member 60 is suppressed.

[0134] Implementation 8

[0135] Next, use Fig.18 and Fig.19 The structure of the semiconductor device 100 according to the eighth embodiment will be described. The semiconductor device 100 according to the eighth embodiment mainly differs from the semiconductor device 100 according to the sixth embodiment in that a through hole 99 is provided in the flat plate portion 49. The other aspects are substantially the same as the semiconductor device 100 according to the sixth embodiment. The following will focus on the differences from the semiconductor device 100 according to the sixth embodiment.

[0136] like Fig.18 and Fig.19As shown, at least one through hole 99 is provided in the flat plate portion 49. Specifically, the number of the through hole 99 may be one or more than two. The through hole 99 extends along the third direction 103. The through hole 99 penetrates the surface 56 and the joined surface 55. A portion of the joining member 60 is located in the through hole 99.

[0137] In the process of manufacturing the semiconductor device 100, when the surface electrode 10 and the wiring member 50 are bonded using the bonding member 60, the bonding member 60 is heated. As a result, pressure is applied from the bonding member 60 to the semiconductor element 30 due to the thermal expansion of the bonding member 60. According to the semiconductor device 100 involved in the eighth embodiment, at least one through hole 99 is provided in the flat plate portion 49. Therefore, when the surface electrode 10 and the wiring member 50 are bonded using the bonding member 60, the bonding member 60 wets and spreads inside the through hole 99. As a result, when the surface electrode 10 and the wiring member 50 are bonded, the pressure applied from the bonding member 60 to the semiconductor element 30 can be reduced. As a result, the cracking of the semiconductor element 30 can be suppressed.

[0138] Implementation method 9

[0139] Next, use Fig. 20 The structure of the semiconductor device 100 according to the ninth embodiment will be described. The semiconductor device 100 according to the ninth embodiment mainly differs from the semiconductor device 100 according to the sixth embodiment in that the second concavo-convex portion 54 is provided on the bonded surface 55, and is substantially the same as the semiconductor device 100 according to the sixth embodiment in other respects. The following will focus on the differences from the semiconductor device 100 according to the sixth embodiment.

[0140] like Fig. 20 As shown, a second concave-convex portion 54 is provided on the joined surface 55. Specifically, a plurality of second concave portions 77 and a plurality of second convex portions 78 are provided on the joined surface 55. Each of the plurality of second convex portions 78 is separated from each other. In the first direction 101, the plurality of second convex portions 78 are provided between the conductive plate portion 51 and the rising portion 52. A second concave portion 77 is provided between two adjacent second convex portions 78. Each of the plurality of second convex portions 78 extends, for example, along the second direction 102. The second concave-convex portion 54 is in contact with the joining component 60. The size of each of the plurality of second concave portions 77 and the plurality of second convex portions 78 is not particularly limited.

[0141] According to the semiconductor device 100 involved in the ninth embodiment, the second concavo-convex portion 54 is provided on the bonded surface 55. Therefore, the bonding strength between the surface electrode 10 and the wiring component 50 using the bonding component 60 can be improved by the anchoring effect. Specifically, when the surface electrode 10 and the wiring component 50 are bonded using the bonding component 60, the molten bonding component 60 enters the second concavo-convex portion 54. Thus, the wiring component 50 and the bonding component 60 can be effectively attached. As a result, the bonding strength between the surface electrode 10 and the wiring component 50 can be improved.

[0142] In the modification of the sixth embodiment and the seventh to ninth embodiments, the wiring member 50 has the structure having the rising portion 52 , but the structure of the wiring member 50 is not limited to the above structure. Specifically, the wiring member 50 may not have the rising portion 52 .

[0143] The embodiments disclosed this time should be considered in all respects as illustrative and non-restrictive. The scope of the present disclosure is indicated by the claims rather than the above description, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0144] Hereinafter, various aspects of the present disclosure are collectively described as notes.

[0145] (Note 1)

[0146] A semiconductor device, wherein:

[0147] have:

[0148] Insulated Gate Bipolar Transistor region;

[0149] A plurality of diode regions contacting the insulated gate bipolar transistor region;

[0150] A surface electrode in contact with the insulated gate bipolar transistor region and the plurality of diode regions;

[0151] A bonding component is disposed on the surface electrode; and

[0152] a wiring member joined to the surface electrode via the joining member,

[0153] The insulated gate bipolar transistor region and the plurality of diode regions constitute a reverse conducting insulated gate bipolar transistor.

[0154] The wiring member has a surface to be joined that contacts the joining member.

[0155] The bonded surface covers at least a portion of each of the plurality of diode regions when viewed from above in a direction perpendicular to the surface electrode.

[0156] When viewed from above, the plurality of diode regions have:

[0157] a first diode region;

[0158] A second diode region is located in a first direction relative to the first diode region and is separated from the first diode region; and

[0159] The third diode region is located in a second direction perpendicular to the first direction relative to the first diode region and is separated from each of the first diode region and the second diode region.

[0160] (Note 2)

[0161] A semiconductor device according to note 1, wherein:

[0162] The wiring component has:

[0163] a flat plate portion constituting the above-mentioned joined surface; and

[0164] The conductive plate portion is connected to the flat plate portion and is separated from the bonding member.

[0165] (Note 3)

[0166] A semiconductor device according to note 2, wherein:

[0167] When viewed from above, the first diode region is in a rectangular shape.

[0168] A connection portion between the flat plate portion and the conductive plate portion extends along a direction in which a long side of the first diode region extends.

[0169] (Note 4)

[0170] A semiconductor device according to note 2 or 3, wherein:

[0171] The device further comprises a gate pad, the gate pad being arranged in a direction from the insulated gate bipolar transistor region toward the surface electrode relative to the insulated gate bipolar transistor region and receiving a signal for controlling conduction of the insulated gate bipolar transistor region.

[0172] The plurality of diode regions include a fourth diode region and a fifth diode region separated from the fourth diode region.

[0173] When viewed from above, the gate pad is disposed between the fourth diode region and the fifth diode region.

[0174] In the plan view, the bonded surface is separated from the gate pad.

[0175] The above-mentioned flat plate portion has:

[0176] A first portion overlapping the fourth diode region when viewed from above; and

[0177] The second portion overlaps with the fifth diode region when viewed from above,

[0178] The second part is separated from the first part.

[0179] (Note 5)

[0180] A semiconductor device according to note 4, wherein:

[0181] When viewed from above, the gate pad is disposed in the first direction relative to the center of the surface electrode.

[0182] The conductive plate portion is provided in a direction opposite to the gate pad with respect to the center of the surface electrode in the plan view.

[0183] (Note 6)

[0184] A semiconductor device according to any one of Notes 2 to 5, wherein:

[0185] The wiring member has a rising portion connected to the flat plate portion and different from the conductive plate portion.

[0186] The rising portion is inclined relative to the flat plate portion in a direction from the surface electrode toward the flat plate portion.

[0187] (Note 7)

[0188] A semiconductor device according to any one of Notes 2 to 6, wherein:

[0189] The flat plate portion has a surface on the opposite side of the joined surface.

[0190] The surface is provided with a first concavo-convex portion.

[0191] (Note 8)

[0192] A semiconductor device according to any one of Notes 2 to 7, wherein:

[0193] The flat plate portion has a convex portion, and the convex portion is convex in a direction from the flat plate portion toward the surface electrode.

[0194] The convex portion constitutes a part of the joined surface.

[0195] (Note 9)

[0196] A semiconductor device according to any one of Notes 2 to 8, wherein:

[0197] The flat plate portion is provided with at least one through hole.

[0198] (Note 10)

[0199] A semiconductor device according to any one of Notes 2 to 9, wherein:

[0200] A second concavo-convex portion is provided on the above-mentioned joined surface,

[0201] The second concave-convex portion is in contact with the joining member.

[0202] (Note 11)

[0203] A semiconductor device according to note 1 or 2, wherein:

[0204] In the plan view, each of the plurality of diode regions has a square shape.

[0205] (Note 12)

[0206] A semiconductor device according to any one of Notes 1 to 11, wherein:

[0207] In the plan view, when the smallest rectangular region surrounding all of the plurality of diode regions is taken as a virtual region, and a virtual line located between the outer edge of the virtual region and the center of the virtual region is taken as a boundary line,

[0208] The above-mentioned imaginary area is composed of a peripheral area and a central area.

[0209] The outer peripheral area is located between the outer edge of the imaginary area and the boundary line.

[0210] The central area is located inside the boundary line and connected to the peripheral area.

[0211] In the plan view, a density of the plurality of diode regions in the central region is lower than a density of the plurality of diode regions in the outer peripheral region.

[0212] (Note 13)

[0213] A semiconductor device according to any one of Notes 1 to 12, wherein:

[0214] In the plan view, the bonded surface covers the entirety of each of the plurality of diode regions.

[0215] (Note 14)

[0216] A semiconductor device according to any one of Notes 1 to 13, wherein:

[0217] Also available:

[0218] a terminal region contacting the IGBT region and surrounding the IGBT region and the plurality of diode regions; and

[0219] The protective film is arranged on the terminal area.

[0220] (Note 15)

[0221] A semiconductor device according to any one of Notes 1 to 13, wherein:

[0222] further comprising a terminal region, the terminal region being in contact with the insulated gate bipolar transistor region and surrounding the insulated gate bipolar transistor region and the plurality of diode regions,

[0223] The shortest distance between the terminal region and the plurality of diode regions in the plan view is equal to or greater than a thickness of the insulated gate bipolar transistor region in a direction perpendicular to the surface electrode.

[0224] (Note 16)

[0225] A semiconductor device according to any one of Notes 1 to 15, wherein:

[0226] The shortest distance between the outer edge of the bonded surface and the plurality of diode regions in the plan view is equal to or greater than the thickness of the insulated gate bipolar transistor region in a direction perpendicular to the surface electrode.

[0227] (Note 17)

[0228] A semiconductor device according to any one of Notes 1 to 16, wherein:

[0229] further comprising a temperature detection diode, the temperature detection diode being disposed between any two of the plurality of diode regions when viewed from above,

[0230] The bonded surface covers the temperature detection diode in the plan view.

Claims

1. A semiconductor device, characterized in that: have: Insulated Gate Bipolar Transistor region; a plurality of diode regions in contact with the insulated gate bipolar transistor region; a surface electrode in contact with the insulated gate bipolar transistor region and the plurality of diode regions; A bonding component is disposed on the surface electrode; as well as a wiring member joined to the surface electrode via the joining member, The insulated gate bipolar transistor region and the plurality of diode regions constitute a reverse conducting insulated gate bipolar transistor, The wiring member has a surface to be joined that contacts the joining member. The bonded surface covers at least a portion of each of the plurality of diode regions when viewed from above in a direction perpendicular to the surface electrode. When viewed from above, the plurality of diode regions have: a first diode region; a second diode region located in a first direction relative to the first diode region and separated from the first diode region; as well as The third diode region is located in a second direction perpendicular to the first direction relative to the first diode region and is separated from each of the first diode region and the second diode region.

2. The semiconductor device according to claim 1, wherein: The wiring component has: a flat plate portion constituting the joined surface; and The conductive plate portion is connected to the flat plate portion and is separated from the bonding member.

3. The semiconductor device according to claim 2, wherein: In the plan view, the first diode region has a rectangular shape, A connection portion between the flat plate portion and the conductive plate portion extends along a direction in which a long side of the first diode region extends.

4. The semiconductor device according to claim 2 or 3, characterized in that The device further comprises a gate pad, the gate pad being arranged in a direction from the insulated gate bipolar transistor region toward the surface electrode relative to the insulated gate bipolar transistor region and receiving a signal for controlling conduction of the insulated gate bipolar transistor region, The plurality of diode regions include a fourth diode region and a fifth diode region separated from the fourth diode region. In the plan view, the gate pad is disposed between the fourth diode region and the fifth diode region, In the plan view, the bonded surface is separated from the gate pad, The flat plate portion has: a first portion overlapping the fourth diode region when viewed from above; and a second portion overlapping the fifth diode region when viewed from above, The second portion is separated from the first portion.

5. The semiconductor device according to claim 4, wherein: When viewed from above, the gate pad is arranged in the first direction relative to the center of the surface electrode. The conductive plate portion is disposed in a direction opposite to the gate pad with respect to the center of the surface electrode in the plan view.

6. The semiconductor device according to claim 2 or 3, characterized in that: The wiring member has a rising portion connected to the flat plate portion and different from the conductive plate portion, The rising portion is inclined relative to the flat plate portion in a direction from the surface electrode toward the flat plate portion.

7. The semiconductor device according to claim 2 or 3, characterized in that: The flat plate portion has a surface on the opposite side of the joined surface, A first concavo-convex portion is provided on the surface.

8. The semiconductor device according to claim 2 or 3, characterized in that: The flat plate portion has a convex portion, and the convex portion is convex in a direction from the flat plate portion toward the surface electrode. The convex portion constitutes a part of the joined surface.

9. The semiconductor device according to claim 2 or 3, characterized in that: The flat plate portion is provided with at least one through hole.

10. The semiconductor device according to claim 2 or 3, characterized in that: A second concavo-convex portion is provided on the joined surface, The second concavo-convex portion is in contact with the joining member.

11. The semiconductor device according to claim 1 or 2, characterized in that: In the plan view, each of the plurality of diode regions has a square shape.

12. The semiconductor device according to any one of claims 1 to 3, wherein: In the plan view, when the smallest rectangular area surrounding all of the plurality of diode areas is taken as a virtual area, and a virtual line located between the outer edge of the virtual area and the center of the virtual area is taken as a boundary line, The imaginary area is composed of a peripheral area and a central area. The peripheral area is located between the outer edge of the imaginary area and the boundary line. The central area is located inside the dividing line and connected to the peripheral area. In the plan view, a density of the plurality of diode regions in the central region is lower than a density of the plurality of diode regions in the outer peripheral region.

13. The semiconductor device according to any one of claims 1 to 3, characterized in that In the plan view, the bonded surface covers the entirety of each of the plurality of diode regions.

14. The semiconductor device according to any one of claims 1 to 3, wherein: Also available: a terminal region contacting the IGBT region and surrounding the IGBT region and the plurality of diode regions; and A protective film is arranged on the terminal area.

15. The semiconductor device according to any one of claims 1 to 3, wherein: further comprising a terminal region, the terminal region being in contact with the insulated gate bipolar transistor region and surrounding the insulated gate bipolar transistor region and the plurality of diode regions, The shortest distance between the terminal region and the plurality of diode regions in the plan view is equal to or greater than a thickness of the insulated gate bipolar transistor region in a direction perpendicular to the surface electrode.

16. The semiconductor device according to any one of claims 1 to 3, characterized in that The shortest distance between the outer edge of the bonded surface and the plurality of diode regions in the plan view is equal to or greater than the thickness of the insulated gate bipolar transistor region in a direction perpendicular to the surface electrode.

17. The semiconductor device according to any one of claims 1 to 3, characterized in that further comprising a temperature detection diode, the temperature detection diode being provided between any two diode regions among the plurality of diode regions in the plan view, The bonded surface covers the temperature detection diode in the plan view.

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