Transistor with storage effect and semiconductor device thereof

Abstract

The invention relates to a transistor with a storage effect and a semiconductor device thereof, the transistor with the storage effect has the storage effect due to the fact that a material with the storage effect is added to an insulating layer or a semiconductor layer, a channel electrode is arranged in a channel region, and the channel electrode and a channel can form junction capacitance, so that the storage effect is achieved. The transistor is also provided with a planar transistor structure and a vertical transistor structure, so that the difference between two lines representing a state 0 and a state 1 can be expanded by adding charge regulation of a channel electrode junction capacitor, the existing 2 state is changed into a multi-state, meanwhile, regulation is changed into a three-dimensional state from a two-dimensional state, and the transistor can be further expanded into a multi-dimensional state; the invention provides a thought of reducing the area of a required circuit and reducing the energy consumption of equipment, and the application scene of the transistor is greatly expanded.

Description

Technical Field

[0001] The invention belongs to the field of semiconductors, and in particular relates to a transistor with a storage effect and a semiconductor device thereof. Background Art

[0002] In recent years, as Moore's Law gradually comes to an end, the construction of new advanced electronic information devices has become one of the hot topics in the post-Moore era. Among them, electronic devices based on two-dimensional van der Waals heterostructures are hailed by the industry as a breakthrough point in the post-Moore era. At the same time, ferroelectric field-effect transistors prepared using materials with storage effects as gate dielectrics are one of the new information devices that are expected to break through the thermodynamic limitations of traditional CMOS devices, and have broad application prospects in low-power chips and non-volatile long-range storage.

[0003] However, currently ferroelectric field-effect transistors have only two states, and the contrast between the states is not high, which limits their further application in small size and high density. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a transistor with a storage effect and a semiconductor device thereof. The transistor is provided with a channel electrode in the channel region, and the channel electrode can form a junction capacitance with the channel, so that the difference between the two lines representing state 0 and state 1 can be expanded by adding the charge control of the junction capacitance of the channel electrode, from two states to multiple states, and at the same time, the control is changed from two dimensions to three dimensions, and can be further expanded to multiple dimensions; the present invention provides a way of reducing the required circuit area and reducing the energy consumption of the equipment, greatly expanding the application scenarios of the transistor, or considering adding logic gate functions and artificial synaptic bionic functions. When realizing the logic function, one function of the channel electrode is to extract voltage from the channel. The existing COMS process technology can fully realize or be compatible with the new structure of the present invention. Similarly, the triode process can also propose a new structure for adding a channel electrode.

[0005] The present invention provides a transistor with a memory effect, comprising:

[0006] substrate;

[0007] A channel region, a source region and a drain region located on one side of the substrate, wherein the substrate and the doped region serve as the source region and the drain region of the transistor respectively; the channel region has a first end and a second end opposite to each other in the extension direction; the source region is in electrical contact with the first end to form a source electrode; the drain region is in electrical contact with the second end to form a drain electrode;

[0008] A gate located between the source region and the drain region, the gate surrounding a portion of the channel region, and a gate insulating layer being provided between the channel region and a region opposite to the gate;

[0009] One or more materials with memory effect among ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, memory effect materials, semiconductor materials, superconducting materials, conductor materials, insulating materials, dielectric materials, two-dimensional materials, one-dimensional materials, three-dimensional materials, perovskite materials, oxides, sulfides, cyanides, hydrides, and silicides located between the gate and the gate insulating layer, or a gate insulating layer is provided between the gate and the material with memory effect, or the gate insulating layer itself is a material with memory effect;

[0010] A channel electrode is provided on the gate insulating layer between the gate and the channel region or on the material having a storage effect, or a channel electrode is provided in the channel region, and the channel electrode is separated from the source and the drain;

[0011] The at least one channel electrode is composed of a conductor, a semiconductor, or a combination of a conductor and a semiconductor. The purpose of the channel electrode is to form a junction capacitor with the connection part, or to extract the local voltage of the connection area, or to regulate the connection area.

[0012] Optionally, the channel electrode includes one or more sub-channel electrodes, and at least one sub-channel electrode is used to control the transistor.

[0013] Optionally, the channel electrode is processed by a doping process, or / and a deposition process, or / and an epitaxial process, or / and a self-assembly process, or / and a spin coating process, or / and a sputtering process, or / and a filling process, or / and a Roll-to-Roll process, or / and a hydrothermal process, or / and an imprinting process, or / and a rolling process, or / and a printing process, or / and an evaporation process.

[0014] Furthermore, the control transistor includes at least one sub-channel electrode for storing a junction capacitor of charges.

[0015] Furthermore, the at least one sub-channel electrode is connected to the channel region and the gate insulating layer to control the transistor.

[0016] Furthermore, when there are a plurality of sub-channel electrodes, the plurality of sub-channel electrodes are located on the same side surface or a plurality of different side surfaces of the channel region.

[0017] Optionally, in the extension direction, the width of the channel region is uneven or uniform; in the direction from the end of the channel electrode connected to the channel region pointing to the end of the channel electrode away from the channel region, the width of the channel electrode is uneven or uniform.

[0018] Optionally, the substrate is a semiconductor substrate or an insulating substrate.

[0019] Optionally, the channel electrode is composed of any one of metals selected from Pt, Pd, Au, Ni, Ag, Cu, Al, Mo, In, and Ti, or any alloy thereof. For example, the channel electrode is composed of Pt.

[0020] One or more of ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, semiconductor materials, superconducting materials, conductor materials, insulating materials, dielectric materials, two-dimensional materials, one-dimensional materials, three-dimensional materials, perovskite materials, oxides, sulfides, cyanides, hydrides, and silicides are used as insulating layer additional layers, insulating layer materials, insulating layer additional materials, semiconductor layer materials, semiconductor channel materials, or channel electrode materials to achieve logic polymorphism and storage polymorphism.

[0021] Optionally, the ferroelectric material is H3S, NbN, LaH 10 、BaTiO3、PbZr x Ti 1-x O3, BiFeO3, CIPS (CuIn x P (3-x) S y , such as CuInP2S6), HZO (HfZrO x ), MoTe2, ZrTiO4, PbTiO3, Ba(Zr,Ti)O3, SrTiO3, BaWO4, BaFe 12 O 19 、YBCO(YBa2Cu3O 7-x , such as YBa2Cu3O7), BFMO (BiFe 1-x MnxO3, such as BiFe 0.9 Mn 0.1 O3), PCMO(Pr 1-x CaxMnO3, such as Pr 0.7 Ca 0.3 MnO3), LBCO(La 2-x BaxCuO4, such as La 1.9 Ba 0.1 CuO4), SmFeAsO 1-x Fx (e.g. SmFeAsO 0.85 F 0.15 ), CaK(Fe 1-x Mx)4As4 (e.g. CaKFe4As4), NdFe 1-x MxDV 0.85 (e.g. NdFeAsO 0.85 ) etc.

[0022] Optionally, the phase change material is VO2, Ge15 Sb 85 , Ga 36 Sb 64 、Fe3O4、NbO2、PEG((C2H4O)n)、Alloys of indium(In) and tin(Sn)、C 60 , C 70 etc.;RMS(Re x Mo 1-x S2)、GST((GeTe) x (Sb2Te3) y ,AIST((Ag 1-x In x )(Sb 1- x Te x )2, such as Ag5In5Sb 60 Te 30 ), GSST (e.g. Ge2Sb2Se1Te4, Ge2Sb2Se4Te1), Gd5 (Si1Ge 1-X )4 (e.g. Gd5Si2Ge2), LaFe 13-x Si x (e.g. LaFe 12 Si), La 0.5 Pr 0.5 Fe 11.5-x Co x Si 1.5 C 0.2 (For example, La 0.5 Pr 0.5 Fe 10.7 Co 0.8 Si 1.5 C 0.2 (e.g. Ge2Sb2Te5), Sb2Te3, GSB((GeSn) x (Sb) y (e.g. GeSnSb), AST((AlSb2) x (Te) y , such as Al 1.5 Sb3Te), TASG(Ti 48 As 30 Si 12 Ge 10 ) one or more of the following.

[0023] Optionally, the magnetoelectric material is ZrTiO4, Fe2O3, Fe3O4, SrBaTiO3, Sr 1-x Ba x TiO3、Bi4Ge3O 12 、BaTiO3、Ba 0.8Sr 0.2 TiO3, NiO, NiZnFe2O4, LiNbO3, BTO-PZT, BaFe 12 O 19 , Cr2O3, BiFeO3, BiMnO3 and LuFe2O4, FCSB(Fe 90 Co 78 Si 12 B 10 )、PMN-PZT((Pb(Mg 1 / 3 Nb 2 / 3 )O3) 1-x -(Pb(Zr 1-y Ti y )O3) x , such as Pb(Mg x Nb 1-x )O3-PbZrO3-PbTiO3), PMN-PT((Pb(Mg 1 / 3 Nb 2 / 3 )O3) 1-x -(PbTiO3) x , such as Pb(Mg 1 / 3 Nb 2 / 3 )O3-PbTiO3).

[0024] Optionally, the quantum effect material is one or more of YBCO, PbLaTiO3, CdSe, GaAs, PbSe, BBO, PPLN and lead, zinc-tin alloy, cold atomic gas (such as rubidium, lithium, sodium), iron, nickel, cobalt and other magnetic materials.

[0025] Optionally, the resistive switching effect material is ZrO2, TiO2, Ta2O5, BiFeO3, SrRuO3, SrZrO3, Fe3O4, ZnFe2O4, BaTiO3, Pb(Mg 1 / 3 Nb 2 / 3 )O3-PbTiO3, Ba(Sr 0.7 Ba 0.3 )TiO3, In2O3-SnO2, Cu2ZnSnSe4, polystyrene (PS), La1-xSrxMnO3, (Pb,Fe)NbO3CuO x (such as CuO 0.5 )、MoS 2-x O4 (such as MoS2O4), HfO x (such as HfO2), WO X (such as WO2), PCMO(Pr 1-x Ca x MnO3, such as Pr 0.7 Ca0.3 MnO3), LSMO(La x Sr 1-x MnO3, such as La 0.5 Sr 0.5 MnO3), LCMO(La x Ca 1-x MnO3, such as La 0.7 Ca 0.3 MnO3) and the like.

[0026] Optionally, the storage effect material is Fe3O4, Fe2O3, CoFe (cobalt-iron alloy), FeCo, FeAlSi, FePt, MnFe, FeNi, CoPt, CoFeB, SbI3, polycarbonate, Si3N4, SiO2, SiO x N y , Se, BaFe 12 O 19 , NiFe, AgCl, AgBr, Ge2Sb2Te5, GeSbTe, Al2O3 / Fe, FeAlO x , polyaniline (PANI) or more.

[0027] Optionally, the superconducting material is H2S, CeCu2Si, CeTIn5, CePt3Si, Ba 0.6 K 0.4 Fe2As2, LaNiC2, LaNiGa2, CaPtAs, Y3Fe5O 12 / Al, 2H-MX2 (M=transition metals; 10-x Cu x (PO4)6, (Li,Fe)OHFeSe, CuInCo2Te4, YBa2Cu3O7 (yttrium alloy copper oxide), Ba(Fe1-xCox)2As2, Pb, MgB2, CuInSe2, LaFeAsO, Ba(Fe,Co)2As2, BSCCO, GdBCO, IBi2Sr2Ca2Cu3O 10 (BSCCO), T l2 One or more of Ba2CuO6, YBa2Fe3Se5.

[0028] Optionally, the semiconductor effect material is one or more of Si, In2Se3, GaAs, GaP, CdSe, ZnSe, PbSe, BN, ZnS, PbS, InP, GaN, Al2Se3, AlAs, InAs, SiGe, and CdSe.

[0029] Optionally, the perovskite material is CsPbBr3, MAPbI 3-x Cl x 、SBT(SrBi 1-x Ti x O9, such as SrBiTiO9), BLT (Bi 4-x La x Ti3O 12 , for example, Bi 3.5 La 0.5 Ti3O 12 )、PZT(PbZr 1-x T ix O3. For example, PbZr 0.7 Ti 0.3 O3), Cs 1-x FA x PbBr3, such as Cs 0.8 FA 0.2 One or more of PbBr3, CH3NH3PbX3 (such as CH3NH3PbBr3, CH3NH3PbI3).

[0030] Optionally, the two-dimensional material is one or more of GaS, h-BN, As2Te3, Bi2S3, 2H-WS2, GaSe, GeS, GeSe, HfS2, HfSe2, In2Se3, MoS2, 2H-MoS2, MoTe2, MoSe2, MoSSe, MoWS2, MoWSe2, ReS2, ReSe2, Sb2Te3, SnS2, SnSe2, 1T-TaS2, WSe2, ZrSe2, ZrSe3, and ACS.

[0031] The present invention also provides a semiconductor device comprising a plurality of the transistors.

[0032] Furthermore, the plurality of transistors are connected to any single layer of the following or a composite layer stacked in any direction: a metal layer, a semiconductor, and an insulating layer.

[0033] Furthermore, a control electrode is added externally to realize device storage and / or logic output.

[0034] Optionally, the semiconductor device serves as a storage array unit of a memory, and the channel electrode and the channel form a junction capacitor for storing charges; the gate and the channel electrode serve as input control electrodes of the storage unit in the memory.

[0035] The present invention also provides an electronic device, comprising any semiconductor device as described above.

[0036] A semiconductor device provided by the present invention has a channel electrode connected to the channel. The channel electrode can be used to control the channel and can also be used as an input electrode, an output electrode, etc., so that the semiconductor device integrates more functions.

[0037] The present invention also provides a storage array, comprising:

[0038] Semiconductor devices, a plurality of the semiconductor devices are arrayed in rows and columns, and source regions of the plurality of semiconductor devices are connected to a fixed potential;

[0039] a plurality of word lines, wherein gates of semiconductor devices located in the same row among the plurality of semiconductor devices are connected to a corresponding one of the word lines;

[0040] a plurality of first bit lines, channel control regions of semiconductor devices located in the same row or the same column among the plurality of semiconductor devices being connected to corresponding first bit lines; and

[0041] a plurality of second bit lines, wherein drain regions of semiconductor devices located in the same column of the plurality of semiconductor devices are connected to a corresponding second bit line,

[0042] Among them, the multiple first bit lines are used to apply a control area voltage in a write operation, the multiple second bit lines are used to apply a drain voltage in a write operation and a read operation, and are used to detect a drain current in a read operation, and the drain current is used to characterize the storage state of the multiple semiconductor devices.

[0043] Optionally, the plurality of semiconductor devices share a semiconductor substrate to form a common source structure.

[0044] The present invention also provides a data operation method of a storage array, comprising:

[0045] In a write operation, a gate voltage is applied via a selected word line among a plurality of word lines, and a drain voltage is applied via a selected second bit line among a plurality of second bit lines to turn on a selected semiconductor device, and a control region voltage is applied to the selected semiconductor device via a selected first bit line among a plurality of first bit lines to change a storage state of the selected semiconductor device; and

[0046] In a read operation, a gate voltage is applied via a selected word line among a plurality of word lines, and a drain voltage is applied via a selected second bit line among a plurality of second bit lines to put a selected semiconductor device into a conductive state, and a drain current of the selected semiconductor device is detected via the selected second bit line among the plurality of second bit lines to obtain a storage state of the selected semiconductor device.

[0047] Optionally, in a read operation, the plurality of first bit lines are disconnected or connected to a fixed potential.

[0048] Optionally, the multiple semiconductor devices respectively include multiple channel control regions, and in a write operation, corresponding control region voltages are applied to the multiple channel control regions respectively to write multi-bit digital values, and in a read operation, the drain current modulated jointly by the multiple channel control regions is detected to read the multi-bit digital values.

[0049] The present invention also provides a semiconductor memory device, comprising a plurality of the above-mentioned devices;

[0050] The voltage writing and erasing methods are arranged in combination with the voltage of each port and the voltage of the control area.

[0051] The present invention also provides a semiconductor device, comprising a plurality of the transistors described above;

[0052] The voltage writing and erasing methods are arranged by combining the gate voltage, the drain voltage and the control region voltage.

[0053] The structure of the present invention can be implemented using existing process lines or adjusted based on existing process steps. The channel electrode and control region materials can be semiconductor materials, conductor materials, or a combination of several materials. The actual preparation process may vary depending on factors such as the manufacturer, device size, and process technology. The structure of the present invention can be adjusted based on the subject of the patent.

[0054] The transistor of the present invention can be illustrated by a three-dimensional structure diagram or a two-dimensional structure diagram.

[0055] Beneficial Effects

[0056] The present invention provides a channel electrode in the channel region so that the difference between the two lines representing state 0 and state 1 can be expanded by adding charge control of the channel electrode junction capacitance, from two states to multiple states, and at the same time the control is changed from two dimensions to three dimensions, and can be further expanded to multiple dimensions; the present invention provides a way of reducing the required circuit area and reducing the energy consumption of the equipment, greatly expanding the application scenarios of the transistor, or considering adding logic gate functions and artificial synapse bionic functions. When realizing the logic function, one function of the channel electrode is to extract voltage from the channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0057] Figure 1 Schematic diagram of the structure of the transistor of the present invention; wherein 1 is a drain, 2 is a gate insulating layer, 3 is a gate, 4 is a channel, 5 is a source, 6 is a substrate, 7 is a channel electrode, and 8 is a material having a storage effect;

[0058] Figure 2 Schematic diagram of a planar three-dimensional structure cross section of a transistor of the present invention; wherein 101 is a metal layer, 102 is a material having a storage effect, 103 is a gate insulating layer, 104 is a drain, 105 is a source, 106 is a substrate, and 107 is a control gate;

[0059] Figure 3 201 is a schematic diagram of a vertical three-dimensional structure cross section of a transistor of the present invention; wherein 201 is a drain, 202 is a gate insulating layer, 203 is a material having a storage effect, 204 is a gate insulating layer, 205 is a source, 206 is a substrate, and 207 is a control gate;

[0060] Figure 4 It is another vertical three-dimensional structure schematic diagram of the transistor of the present invention;

[0061] Figure 5 A schematic diagram of a storage array of transistors of the present invention;

[0062] Figure 6 A schematic diagram of the writing and reading operations of the transistor of the present invention;

[0063] Figure 7 The working principle of the device is shown in the following figure;

[0064] Figure 8 A schematic diagram of a random access storage test result provided by an embodiment of the present invention;

[0065] Fig. 9 Another schematic diagram of random access storage test results provided by an embodiment of the present invention;

[0066] Fig.10 It is a schematic diagram of a typical process flow for preparing a transistor with a channel electrode added according to the present invention. DETAILED DESCRIPTION

[0067] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0068] The present invention may be embodied in various forms, some examples of which will be described below.

[0069] See also Figures 1 to 3 In an embodiment of the present invention, a transistor is provided, comprising: a substrate; a channel region, a source region and a drain region located on one side of the substrate; the channel region has a first end and a second end opposite to each other in an extension direction; the source region is electrically in contact with the first end to form a source electrode; the drain region is electrically in contact with the second end to form a drain electrode; a gate electrode is located between the source region and the drain region, the gate electrode surrounds part of the channel region, and a gate insulating layer is provided between the channel region and the region opposite to the gate electrode; a material with a storage effect is located between the gate electrode and the gate insulating layer; a channel electrode is provided in the channel region, and the channel electrode is separated from the source electrode and the drain electrode.

[0070] The transistor may be in a vertical transistor structure, including a substrate, the channel region extending upward from the source surface, the direction of extension of the channel region being perpendicular to the plane of the substrate surface, and the drain being specifically located on the surface of the channel region facing away from the substrate. A gate insulating layer is provided on the sidewall of the channel region, and a gate is provided on the surface of the gate insulating layer facing away from the channel region, i.e., on the outside of the gate insulating layer. The gate can affect the channel region based on its own electric field, thereby controlling the on and off of the vertical transistor, i.e., the semiconductor device body. In addition to being separated from the source and drain to avoid direct contact, the channel electrode also needs to be separated from the gate to avoid direct contact.

[0071] In the embodiment of the present invention, the above-mentioned channel electrode can be used as an input terminal or an output terminal, and can also be used as a control terminal. In this case, the semiconductor device is at least a four-terminal device. At this time, the channel electrode can have the ability to control the channel, the input electrode ability, or the output electrode ability. Specifically, the above-mentioned channel electrode may include an insulating end in contact with the channel. That is, the above-mentioned channel electrode is specifically divided into a conductive end and an insulating end. The channel electrode is in contact with the channel region through the insulating end. At this time, the channel electrode is similar to a gate, and the channel region can also be controlled based on the electric field. At this time, the semiconductor device has two gates that can control the channel region. It should be noted that the above-mentioned gate or gate-like structure can regulate other electrodes, or a gate or a gate-like structure can be regulated by other two ports or multiple ports. The specific regulation relationship is determined by the specific application and is not specifically limited here.

[0072] For vertical transistors, the embodiments of the present invention are based on the general vertical transistor preparation process, by first adding a substrate, then sequentially growing a source electrode, a channel region, and a gate, and then setting a channel electrode in the channel region not connected to the gate, and realizing the function of storing or outputting voltage based on the channel electrode. The channel electrode can be on any side and the number can be multiple. Finally, the drain is grown to complete the preparation of the semiconductor device. The method of adding each layer of the above structure can be but is not limited to coating, stripping, transfer, photolithography, etching, deposition, etc.

[0073] A semiconductor device provided by the present invention integrates more functions by setting a channel electrode based on a vertical transistor.

[0074] Figure 4 Another vertical three-dimensional structure schematic diagram of the transistor of the present invention is shown below:

[0075] The invention comprises a semiconductor substrate, a semiconductor layer located on the semiconductor substrate, and a doped region located in the semiconductor layer.

[0076] The memory transistor is described in detail by taking an N-channel transistor as an example. The semiconductor substrate is, for example, an N-type doped single crystal silicon substrate, which serves as the source region of the memory transistor, and the doping region is, for example, an N-type doped doping region, which serves as the drain region of the memory transistor. The semiconductor layer is, for example, a P-type doped epitaxial layer. However, the present invention is not limited thereto, and the memory transistor may be any one of an N-channel transistor and a P-channel transistor, and depending on the channel type, the layers and doping regions in the memory transistor have corresponding doping types.

[0077] The memory transistor further includes a first trench controlling the doped region and the semiconductor layer and extending into the semiconductor substrate, and a second trench controlling the doped region and extending into the semiconductor layer.

[0078] A gate stack consisting of a gate dielectric layer and a gate conductor is formed in the first trench. The gate dielectric is located at the bottom and sidewalls of the first trench, the gate conductor fills the first trench, and the gate dielectric separates the gate conductor from the semiconductor substrate, the semiconductor layer, and the doped region. When the storage transistor is in the on state, under the action of the voltage applied by the gate conductor, a substantially vertically extending channel region extending from one surface of the semiconductor layer to another surface is formed in the semiconductor layer along the sidewalls of the first trench.

[0079] A channel control region and a first insulating layer are formed at the lower part and the upper part of the second trench, respectively. The top surface of the channel control region is located below the doped region, and the first insulating layer isolates the two from each other. In the storage transistor, the channel control region is in direct contact with the semiconductor layer, the channel control region is composed of a conductive material, such as a metal, the semiconductor layer is composed of an N-type semiconductor, and a junction capacitor is formed between the channel control region and the semiconductor layer.

[0080] The gate dielectric layer of the storage transistor is composed of, for example, silicon oxide, the gate conductor is composed of, for example, doped polysilicon, the channel control region is composed of, for example, Pt, and the first insulating layer is composed of, for example, silicon oxide. However, the present invention is not limited to this, and the corresponding layers and / or regions in the storage transistor can be composed of materials known to those skilled in the art. The channel control region is composed of, for example, any stack of a conductor, a semiconductor, or a conductor and a semiconductor. Preferably, the channel control region is composed of any one metal selected from Pt, Pd, Au, Ni, Ag, Cu, Al, Mo, In, Ti, or any alloy thereof, for example, the channel control region is composed of Pt.

[0081] Optionally, the ferroelectric material is H3S, NbN, LaH 10 、BaTiO3、PbZr x Ti 1-x O3, BiFeO3, CIPS (CuIn x P (3-x) S y , such as CuInP2S6), HZO (HfZrO x ), MoTe2, ZrTiO4, PbTiO3, Ba(Zr,Ti)O3, SrTiO3, BaWO4, BaFe 12 O 19 、YBCO(YBa2Cu3O 7-x , such as YBa2Cu3O7), BFMO (BiFe 1-x MnxO3, such as BiFe 0.9 Mn 0.1 O3), PCMO(Pr 1-x CaxMnO3, such as Pr 0.7 Ca 0.3 MnO3), LBCO(La 2-x BaxCuO4, such as La 1.9 Ba 0.1 CuO4), SmFeAsO 1-x Fx (e.g. SmFeAsO 0.85 F 0.15 ), CaK(Fe 1-x Mx)4As4 (e.g. CaKFe4As4), NdFe 1-x MxDV 0.85 (e.g. NdFeAsO 0.85 ) etc.

[0082] Optionally, the phase change material is VO2, Ge 15 Sb 85 , Ga36 Sb 64 、Fe3O4、NbO2、PEG((C2H4O)n)、Alloys of indium(In) and tin(Sn)、C 60 , C 70 etc.;RMS(Re x Mo 1-x S2)、GST((GeTe) x (Sb2Te3) y ,AIST((Ag 1-x In x )(Sb 1- x Te x )2, such as Ag5In5Sb 60 Te 30 ), GSST (e.g. Ge2Sb2Se1Te4, Ge2Sb2Se4Te1), Gd5 (Si1Ge 1-X )4 (e.g. Gd5Si2Ge2), LaFe 13-x Si x (e.g. LaFe 12 Si), La 0.5 Pr 0.5 Fe 11.5-x Co x Si 1.5 C 0.2 (For example, La 0.5 Pr 0.5 Fe 10.7 Co 0.8 Si 1.5 C 0.2 (e.g. Ge2Sb2Te5), Sb2Te3, GSB((GeSn) x (Sb) y (e.g. GeSnSb), AST((AlSb2) x (Te) y , such as Al 1.5 Sb3Te), TASG(Ti 48 As 30 Si 12 Ge 10 ) one or more of the following.

[0083] Optionally, the magnetoelectric material is ZrTiO4, Fe2O3, Fe3O4, SrBaTiO3, Sr 1-x Ba x TiO3、Bi4Ge3O 12 、BaTiO3、Ba 0.8 Sr 0.2TiO3, NiO, NiZnFe2O4, LiNbO3, BTO-PZT, BaFe 12 O 19 , Cr2O3, BiFeO3, BiMnO3 and LuFe2O4, FCSB(Fe 90 Co 78 Si 12 B 10 )、PMN-PZT((Pb(Mg 1 / 3 Nb 2 / 3 )O3) 1-x -(Pb(Zr 1-y Ti y )O3) x , such as Pb(Mg x Nb 1-x )O3-PbZrO3-PbTiO3), PMN-PT((Pb(Mg 1 / 3 Nb 2 / 3 )O3) 1-x -(PbTiO3) x , such as Pb(Mg 1 / 3 Nb 2 / 3 )O3-PbTiO3).

[0084] Optionally, the quantum effect material is one or more of YBCO, PbLaTiO3, CdSe, GaAs, PbSe, BBO, PPLN and lead, zinc-tin alloy, cold atomic gas (such as rubidium, lithium, sodium), iron, nickel, cobalt and other magnetic materials.

[0085] Optionally, the resistive switching effect material is ZrO2, TiO2, Ta2O5, BiFeO3, SrRuO3, SrZrO3, Fe3O4, ZnFe2O4, BaTiO3, Pb(Mg 1 / 3 Nb 2 / 3 )O3-PbTiO3, Ba(Sr 0.7 Ba 0.3 )TiO3, In2O3-SnO2, Cu2ZnSnSe4, polystyrene (PS), La1-xSrxMnO3, (Pb,Fe)NbO3CuO x (such as CuO 0.5 )、MoS 2-x O4 (such as MoS2O4), HfO x (such as HfO2), WO X (such as WO2), PCMO(Pr 1-x Ca x MnO3, such as Pr 0.7 Ca 0.3MnO3), LSMO(La x Sr 1-x MnO3, such as La 0.5 Sr 0.5 MnO3), LCMO(La x Ca 1-x MnO3, such as La 0.7 Ca 0.3 MnO3) and the like.

[0086] Optionally, the storage effect material is Fe3O4, Fe2O3, CoFe (cobalt-iron alloy), FeCo, FeAlSi, FePt, MnFe, FeNi, CoPt, CoFeB, SbI3, polycarbonate, Si3N4, SiO2, SiO x N y , Se, BaFe 12 O 19 , NiFe, AgCl, AgBr, Ge2Sb2Te5, GeSbTe, Al2O3 / Fe, FeAlO x , polyaniline (PANI) or more.

[0087] Optionally, the superconducting material is H2S, CeCu2Si, CeTIn5, CePt3Si, Ba 0.6 K 0.4 Fe2As2, LaNiC2, LaNiGa2, CaPtAs, Y3Fe5O 12 / Al, 2H-MX2 (M=transition metals; 10-x Cu x (PO4)6, (Li,Fe)OHFeSe, CuInCo2Te4, YBa2Cu3O7 (yttrium alloy copper oxide), Ba(Fe1-xCox)2As2, Pb, MgB2, CuInSe2, LaFeAsO, Ba(Fe,Co)2As2, BSCCO, GdBCO, IBi2Sr2Ca2Cu3O 10 (BSCCO), T l2 One or more of Ba2CuO6, YBa2Fe3Se5.

[0088] Optionally, the semiconductor effect material is one or more of Si, In2Se3, GaAs, GaP, CdSe, ZnSe, PbSe, BN, ZnS, PbS, InP, GaN, Al2Se3, AlAs, InAs, SiGe, and CdSe.

[0089] Optionally, the perovskite material is CsPbBr3, MAPbI 3-x Cl x 、SBT(SrBi 1-x Ti x O9, such as SrBiTiO9), BLT (Bi 4-x La x Ti3O 12 , for example, Bi 3.5 La 0.5 Ti3O 12 )、PZT(PbZr 1-x T ix O3. For example, PbZr 0.7 Ti 0.3 O3), Cs 1-x FA x PbBr3, such as Cs 0.8 FA 0.2 One or more of PbBr3, CH3NH3PbX3 (such as CH3NH3PbBr3, CH3NH3PbI3).

[0090] Optionally, the two-dimensional material is one or more of GaS, h-BN, As2Te3, Bi2S3, 2H-WS2, GaSe, GeS, GeSe, HfS2, HfSe2, In2Se3, MoS2, 2H-MoS2, MoTe2, MoSe2, MoSSe, MoWS2, MoWSe2, ReS2, ReSe2, Sb2Te3, SnS2, SnSe2, 1T-TaS2, WSe2, ZrSe2, ZrSe3, and ACS.

[0091] Further, the storage transistor includes a second insulating layer, a drain electrode, a gate electrode and a channel electrode located on the second insulating layer, and a source electrode located on the surface of the semiconductor substrate opposite to the semiconductor layer. The second insulating layer covers the surface of the doped region as an interlayer dielectric layer. The drain electrode is connected to the doped region via a conductive via controlling the second insulating layer. The gate electrode is connected to the gate conductor via a conductive via controlling the second insulating layer. The channel electrode is connected to the channel control region via a conductive via controlling the second insulating layer and the first insulating layer.

[0092] According to the memory transistor of this embodiment, the channel control region of the memory transistor is adjacent to one side surface of the gate conductor, and the channel control region and the gate conductor respectively extend approximately vertically in the semiconductor layer. A gate dielectric is sandwiched between the gate conductor and the semiconductor layer, and in a write operation and a read operation, a gate voltage applied to the gate conductor acts on an adjacent region of the semiconductor layer, thereby forming a substantially vertically extending channel extending from one surface of the semiconductor layer to the other surface between the gate conductor and the channel control region. The channel control region is in direct contact with the semiconductor layer to form a junction capacitor.

[0093] The transistor according to this embodiment includes a plurality of memory cells arranged in a matrix, wherein the memory cells are memory cells formed based on a channel electrode and an inversion mode resistive field effect transistor, wherein the semiconductor device body is an inversion mode resistive field effect transistor with a vertical structure, and the channel electrode is in contact with a channel region in the transistor.

[0094] In the row direction, the storage cells in each row are connected to each other through the gates and to the word line together, and the information of the selected storage cells is read, written and erased by controlling the potential of the word line; in the column direction, the drain and source of the storage cells from the first row to the last row of each column are connected in sequence, the source of the storage cell in the first row is led to the source end bit line, and the drain of the storage cell in the last row is led to the drain end bit line; the channel electrodes of each unit are connected in each column and can also be connected in each row to form row / column lines.

[0095] According to another aspect of the present invention, there is provided a storage array, comprising: the above-mentioned multiple storage transistors, the multiple storage transistors are arranged in an array in rows and columns, and the source regions of the multiple storage transistors are connected to a fixed potential; multiple word lines, the gates of the storage transistors located in the same row among the multiple storage transistors are connected to a corresponding word line; multiple first bit lines, the channel control regions of the storage transistors located in the same row or the same column among the multiple storage transistors are connected to a corresponding first bit line; and multiple second bit lines, the drain regions of the storage transistors located in the same column among the multiple storage transistors are connected to a corresponding second bit line, wherein the multiple first bit lines are used to apply a control voltage in a programming operation, the multiple second bit lines are used to apply a drain voltage, and are used to detect a drain current in a reading operation, and the drain current is used to characterize the storage state of the multiple storage transistors.

[0096] Optionally, the plurality of storage transistors share a semiconductor substrate to form a common source structure.

[0097] Figure 5 and 6 A schematic diagram of a memory cell in a memory array performing a write operation is shown.

[0098] The memory device includes a word line driver module, a bit line driver module, and a memory array. The word line driver module is connected to the gate of the memory transistor 10 via a word line WL, the bit line driver module is connected to the channel electrode of the memory transistor 10 via a bit line BL1, and is connected to the drain of the memory transistor 10 via a bit line BL2.

[0099] In a write operation, a gate voltage Vgs is provided via the word line WL, a control region voltage Vc is provided via the bit line BL1, and a drain voltage Vds is provided via the bit line BL2. The source of the storage transistor 10 is grounded. At this time, the storage transistors 10 in the storage array are in an on state, and the unselected storage transistors in the storage array are in an off state. Preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 50V, and the drain voltage Vds is 0.05 to 50V. More preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 25V, and the drain voltage Vds is 0.05 to 25V. More preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 15V, and the drain voltage Vds is 0.05 to 15V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 10V, and the drain voltage Vds is 0.05 to 10V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 5V, and the drain voltage Vds is 0.05 to 5V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 2.5V, and the drain voltage Vds is 0.05 to 2.5V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 1.8V, and the drain voltage Vds is 0.05 to 2V. Most preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 1.5V, and the drain voltage Vds is 0.05 to 1.5V.

[0100] Further, in a write operation, a gate voltage Vgs is provided via the word line WL, a control region voltage Vc is provided via the bit line BL1, and a drain voltage Vds is provided via the bit line BL2. The source of the storage transistor 10 is grounded. At this time, the storage transistors 10 in the storage array are in an on state, and the unselected storage transistors in the storage array are in an off state. Preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 50V, the drain voltage Vds is 0.05 to 50V, and the control region voltage Vc is -50 to 50V. More preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 25V, the drain voltage Vds is 0.05 to 25V, and the control region voltage Vc is -20 to 20V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 15V, the drain voltage Vds is 0.05 to 15V, and the control region voltage Vc is -10 to 10V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 10V, the drain voltage Vds is 0.05 to 10V, and the control region voltage Vc is -10 to 10V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 5V, the drain voltage Vds is 0.05 to 5V, and the control region voltage Vc is -5 to 5V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 2.5V, the drain voltage Vds is 0.05 to 2.5V, and the control region voltage Vc is -5 to 5V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 1.8 V, the drain voltage Vds is 0.05 to 2 V, and the control region voltage Vc is -2 to 2 V. Most preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 1.5 V, the drain voltage Vds is 0.05 to 1.5 V, and the control region voltage Vc is -2 to 2 V.

[0101] Furthermore, the write operation includes, for example, data erasure and data programming. In data erasure, the control region voltage Vc of the storage transistor 10 is, for example, 1.5V, and the junction capacitance of the storage transistor 10 is discharged to release the charge. In data programming, the control region voltage Vc of the storage transistor 10 is, for example, -1.5V, so that the voltage difference of the gate voltage Vgs relative to the control region voltage Vc exceeds a predetermined value, and the junction capacitance of the storage transistor 10 is charged to store the charge. The write operation can change the storage state of the storage transistor 10, for example, the erase state of the storage transistor 10 is a high resistance state, which is used to represent the digital value 0, and the write state is a low resistance state, which is used to represent the digital value 1.

[0102] In the read operation, a gate voltage Vgs is provided via the word line WL, and a drain voltage Vds is provided via the bit line BL2. The source of the storage transistor 10 is grounded. The channel electrode of the storage transistor 10 is in a suspended state due to the disconnection of the bit line BL1. At this time, the storage transistors 10 in the storage array are in an on state, and the unselected storage transistors in the storage array are in an off state. Preferably, in the read operation, the gate voltage Vgs of the storage transistor 10 is 1.2V, and the drain voltage Vds is 2V.

[0103] Further, the read operation includes detecting the drain current Ids of the storage transistor 10. In the write operation of the storage transistor 10, the storage state of the storage transistor 10 is related to the resistance state. Even if the same bias conditions, that is, the same gate voltage, drain voltage and source voltage are used, the drain current of the storage transistor in different storage states is different.

[0104] Therefore, by comparing the drain current Ids with the current reference Iref, the storage state of the storage transistor 10 can be determined according to the size of the drain current Ids. For example, when the drain current of the storage transistor 10 is greater than the current reference Iref, the digital value stored in the storage transistor 10 is determined to be 1, and when the drain current of the storage transistor 10 is less than or equal to the current reference Iref, the digital value stored in the storage transistor 10 is determined to be 0. There can be multiple current references Iref, thereby realizing multi-state storage.

[0105] Therefore, the channel electrode output voltage V CG Compared with the voltage reference Vref, the channel electrode output voltage V CG The size of can determine the storage state of the transistor 10. For example, when the channel electrode output voltage of the transistor 10 is greater than the voltage reference Vref, it is determined that the digital value output by the transistor 10 is 1. CG When the voltage is less than or equal to the voltage reference Vref, it is determined that the digital value of the logic output of the transistor 10 is 0. There may also be multiple voltage references Vref to implement multi-state logic.

[0106] The semiconductor device body of the inversion mode resistive field effect transistor of the channel electrode can adopt a transistor structure, specifically a conductive electrode layer, a resistive memory layer stack structure or a general

[0107] A channel electrode is set in a pass transistor structure, a FINFET (fin field effect transistor) structure, a FLASH (flash memory) structure or a GAA structure, while the source region and the drain region can adopt an n / p type ion implantation structure or a NiGe alloy structure.

[0108] A semiconductor device provided by the present invention can simultaneously perform the functions of storing information and switching in a formed storage array, and realizes the integration of storage function and switch control function in one transistor.

[0109] based on Figure 7 , the original transistor storage mechanism: after writing, it is a blue line. After writing, the electric field of the dielectric layer attracts the channel electrons. After erasing, it is a red line. After erasing, the dielectric layer attracts holes and the electron current in the channel decreases. These are two states in the XY direction. This embodiment adds a channel electrode. According to the junction capacitance mechanism, the channel of the transistor includes a channel electrode. The channel electrode and the channel form a junction capacitance, so that the transistor has the ability to store charge. By controlling the junction capacitance channel electrode at the same time during programming, the junction capacitance charge is changed and the channel electrons are adjusted in the XZ direction. According to the ferroelectric regulation of the channel current mechanism plus the junction capacitance storage regulation of the channel current mechanism, three-dimensional storage control can be achieved.

[0110] like Figure 8 Due to the addition of ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, superconducting effect materials, semiconductor effect materials, etc., the transistor can have two states of storing 0 and storing 1. Then the logical states 0 and 1 given when the transistor stores 0 are different from the logical states 0 and 1 when the transistor stores 1, so polymorphic storage can be achieved.

[0111] like Fig. 9 Due to the addition of ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, superconducting effect materials, semiconductor effect materials, etc., the transistor can have two new storage states of 0 and 1 after adding a channel electrode to introduce the junction capacitance of the channel and the channel electrode and having a charge storage effect. Therefore, the logic states 0 and 1 given by the new storage 0 of the transistor and the logic states 0 and 1 when the transistor stores 1 are different, and are also different from the states when the storage is not regulated by the channel electrode before, so multi-state storage can be achieved. By regulating the storage state of the transistor through the channel electrode, more multi-state storage can be achieved.

[0112] By adding ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, superconducting effect materials, and semiconductor effect materials and organically combining them with channel electrodes to control the storage state of the transistor, more states of storage can be achieved than in devices that originally only have ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, superconducting effect materials, and semiconductor effect materials without channel electrodes, or only have channel electrodes without adding ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, superconducting effect materials, and semiconductor effect materials.

[0113] In addition, the manufacturing technology of the transistor used in the embodiment of the present invention is further introduced. Fig.10 A schematic diagram of a typical process flow for preparing a transistor with a channel electrode added to an embodiment of the present invention is provided, (1) Preparing a substrate: First, select an appropriate semiconductor material as a substrate and perform chemical and physical treatments to remove impurities and impure substances. (2) Forming various parts of the transistor: Using oxidation, photolithography, doping, deposition and etching techniques, form the transistor channel, gate oxide layer, source, drain, channel electrode, and gate. (3) Forming contacts: Using photolithography and etching techniques, form metal contacts on the gate, source region, drain region, and control region to connect to an external circuit. (4) Surface planarization: During the preparation process, an uneven surface may appear. Surface planarization treatment is required. (5) Metallization: In the final step, the entire transistor is metallized to connect the transistor electrode to an external circuit.

[0114] The above is just a typical process flow for the preparation of a channel electrode transistor. The new structure can be implemented using existing process lines or adjusted based on existing process steps. The control area material can be a semiconductor material, a conductor material, or a combination of several materials. The actual preparation process may vary depending on factors such as the manufacturer, device size, and process technology.

Claims

1. A transistor with a memory effect, characterized in that: include: substrate; A channel region, a source region and a drain region located on one side of the substrate, wherein the substrate and the doped region serve as the source region and the drain region of the transistor respectively; The channel region has a first end and a second end opposite to each other in the extension direction; the source region is in electrical contact with the first end to form a source electrode; the drain region is in electrical contact with the second end to form a drain electrode; A gate located between the source region and the drain region, the gate surrounding a portion of the channel region, and a gate insulating layer being provided between the channel region and a region opposite to the gate; One or more materials with memory effect among ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, memory effect materials, semiconductor materials, superconducting materials, conductor materials, insulating materials, dielectric materials, two-dimensional materials, one-dimensional materials, three-dimensional materials, perovskite materials, oxides, sulfides, cyanides, hydrides, and silicides located between the gate and the gate insulating layer, or a gate insulating layer is provided between the gate and the material with memory effect, or the gate insulating layer itself is a material with memory effect; A channel electrode is provided on the gate insulating layer between the gate and the channel region or on the material having a storage effect, or a channel electrode is provided in the channel region, and the channel electrode is separated from the source and the drain; The at least one channel electrode is composed of a conductor, a semiconductor, or a combination of a conductor and a semiconductor.

2. The transistor according to claim 1, characterized in that: The channel electrode region is composed of any one of a conductor and a semiconductor or any combination thereof.

3. The transistor according to claim 2, characterized in that: The control transistor includes at least one sub-channel electrode for storing a junction capacitor of charges.

4. The transistor according to claim 2, characterized in that: The at least one sub-channel electrode is connected to the channel region and the gate insulating layer to regulate the storage charge of the transistor.

5. The transistor according to claim 2, characterized in that: When there are a plurality of sub-channel electrodes, the plurality of sub-channel electrodes are located on the same side surface or a plurality of different side surfaces of the channel region.

6. The transistor according to claim 1, characterized in that: The channel electrode region is composed of any one metal selected from Pt, Pd, Au, Ni, Ag, Cu, Al, Mo, In, Ti or any alloy thereof.

7. The transistor according to claim 1, characterized in that: The material having the storage effect is H3S, NbN, LaH 10 、BaTiO3、PbZr x Ti 1-x O3、BiFeO 3、 CIPS, HZO, MoTe2, ZrTiO4, PbTiO3, Ba(Zr,Ti)O3, SrTiO3, BaWO4, BaFe 12 O 19 , YBCO, BFMO, PCMO, LBCO, SmFeAsO 1-x Fx, CaK(Fe 1-x Mx)4As4、NdFe 1-x MxDV 0.85 One or more of the .

8. The transistor according to claim 1, characterized in that The channel electrode is processed by a doping process, or / and a deposition process, or / and an epitaxial process, or / and a self-assembly process, or / and a spin coating process, or / and a sputtering process, or / and a filling process, or / and a Roll-to-Roll process, or / and a hydrothermal process, or / and an imprinting process, or / and a rolling process, or / and a printing process, or / and an evaporation process.

9. The transistor according to claim 1, characterized in that: One or more of ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, semiconductor materials, superconducting materials, conductor materials, insulating materials, dielectric materials, two-dimensional materials, one-dimensional materials, three-dimensional materials, perovskite materials, oxides, sulfides, cyanides, hydrides, and silicides as insulating layer additional layers, insulating layer materials, insulating layer additional materials, semiconductor layer materials, semiconductor channel materials, or channel electrode materials.

10. A semiconductor device, characterized in that: It comprises a plurality of transistors as claimed in any one of claims 1 to 8.

11. The semiconductor device according to claim 10, wherein: The plurality of transistors are connected to any single layer of the following or a composite layer stacked in any direction: a metal layer, a semiconductor, an insulating layer.

12. The semiconductor device according to claim 11, characterized in that: At the same time, an external control electrode is added to realize device storage and / or logic output.

13. An electronic device, characterized in that: The invention comprises a semiconductor device as claimed in any one of claims 10 to 12.

14. A storage array comprising: The transistor according to any one of claims 1 to 9, wherein a plurality of said transistors are arranged in an array in rows and columns, and source regions of said plurality of transistors are connected to a fixed potential; a plurality of word lines, wherein gates of transistors in the same row of the plurality of transistors are connected to a corresponding one of the word lines; a plurality of first bit lines, wherein channel control regions of transistors in the same row or column of the plurality of transistors are connected to corresponding first bit lines; as well as a plurality of second bit lines, wherein drain regions of transistors in the same column of the plurality of transistors are connected to a corresponding second bit line, Among them, the multiple first bit lines are used to apply the control area voltage in the write operation, the multiple second bit lines are used to apply the drain voltage in the write operation and the read operation, and are used to detect the drain current in the read operation, and the drain current is used to characterize the storage state of the multiple transistors.

15. The storage array according to claim 14, characterized in that: The plurality of transistors share a semiconductor substrate to form a common source structure.

16. A data operation method for a storage array according to claim 14 or 15, comprising: In a write operation, a gate voltage is applied via a selected word line among a plurality of word lines, and a drain voltage is applied via a selected second bit line among a plurality of second bit lines to turn on a selected transistor, and a control region voltage is applied to the selected transistor via a selected first bit line among a plurality of first bit lines to change a storage state of the selected transistor; as well as In a read operation, a gate voltage is applied via a selected word line among multiple word lines, and a drain voltage is applied via a selected second bit line among multiple second bit lines to put a selected transistor in an on state, and a drain current of the selected transistor is detected via the selected second bit line among the multiple second bit lines to obtain a storage state of the selected transistor.

17. The data operation method according to claim 16, characterized in that: In a read operation, the plurality of first bit lines are disconnected or connected to a fixed potential.

18. The data operation method according to claim 16, characterized in that: The multiple transistors respectively include multiple channel control regions. In a write operation, corresponding control region voltages are applied to the multiple channel control regions to write multi-bit digital values. In a read operation, the drain current modulated jointly by the multiple channel control regions is detected to read the multi-bit digital values.

19. A semiconductor memory device, characterized in that: Comprising a plurality of devices according to any one of claims 1 to 18; The voltage writing and erasing methods are arranged in combination with the voltage of each port and the voltage of the control area.

20. A semiconductor device, characterized in that: Comprising a plurality of transistors according to any one of claims 1 to 18; The voltage writing and erasing methods are arranged by combining the gate voltage, the drain voltage and the control region voltage.

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