Semiconductor device and electronic device

Abstract

The invention relates to a semiconductor device and an electronic device. The semiconductor device comprises a semiconductor device body and a channel electrode. A voltage dividing layer is formed on the semiconductor device body when the semiconductor device body works, the semiconductor device body comprises a body electrode electrically connected with the voltage dividing layer, and at least two ports are formed on the semiconductor device body; the channel electrode is in contact with the partial voltage layer, the channel electrode is separated from the body electrode, and the channel electrode and the body electrode serve as ports except the ports in the semiconductor device body; the channel electrode is arranged in the channel region, and the logic function of the transistor device can be regulated and controlled by additionally adding the channel electrode.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, and in particular relates to a semiconductor device and an electronic apparatus. Background Art

[0002] Many existing semiconductor devices have relatively simple functions, for example, they cannot realize logic gate and storage functions at the same time. Semiconductor devices in the post-Moore era are generally developing towards small area and multi-functional integration, so how to provide a semiconductor device with integrated functions is an urgent problem that technicians in this field need to solve.

[0003] By adding additional channel electrodes, the logical function of the transistor device can be controlled.

[0004] The following are the advantages of adding channel electrodes to control the implementation of logic:

[0005] 1. Flexibility and programmability: After adding the channel electrode, the electrical characteristics of the transistor can be programmed and adjusted as needed. By controlling the voltage of the channel electrode, the conductive properties and working state of the transistor can be changed to achieve different logical functions.

[0006] 2. Low power consumption: By adding a channel electrode and regulating its voltage, the transistor device can consume less power in an inactive state.

[0007] 3. Logical complexity: By adding channel electrodes, more complex logical functions can be implemented in transistor devices. By combining and connecting multiple transistors in series, more complex logic circuits can be constructed. Summary of the invention

[0008] The technical problem to be solved by the present invention is to provide a semiconductor device and an electronic device, wherein the semiconductor device solves the problem that the ferroelectric field effect transistor cannot be further applied.

[0009] The present invention provides a semiconductor device, comprising a semiconductor device body and a channel electrode;

[0010] The semiconductor device body forms a voltage division layer when in operation, and the semiconductor device body includes a body electrode electrically connected to the voltage division layer, so that the semiconductor device body forms at least two ports; the channel electrode is in contact with the voltage division layer, and the channel electrode and the body electrode are separated from each other, serving as a port outside the port in the semiconductor device body.

[0011] Preferably, the voltage-dividing layer comprises any one of the following single layers or a composite layer stacked in any direction:

[0012] Metal layer, semiconductor, insulating layer.

[0013] Preferably, the voltage division layer is a channel formed when the semiconductor device body is in operation, the body electrode is located at an end of the channel, and the channel electrode is in contact with a side wall of the channel and / or an end of the channel.

[0014] Preferably, the semiconductor device body comprises a plurality of semiconductor materials to form a plurality of semiconductor layers, so that the channel is formed based on the plurality of semiconductor layers during operation.

[0015] Preferably, the body electrode comprises a first electrode and a second electrode which are arranged opposite to each other, the first electrode and the second electrode are connected via the channel; the channel electrode and the first electrode, and the channel electrode and the second electrode are separated from each other.

[0016] Preferably, the channel electrode is processed by a doping process, or / and a deposition process, or / and an epitaxial process, or / and a self-assembly process, or / and a spin coating process, or / and a sputtering process, or / and a filling process, or / and a Roll-to-Roll process, or / and a hydrothermal process, or / and an imprinting process, or / and a rolling process, or / and a printing process, or / and an evaporation process.

[0017] Preferably, the semiconductor device is used as a logic gate device, and the first electrode, the second electrode, the gate electrode and the channel electrode are each used as one of the following ports, and the ports include:

[0018] Input end, output end, control end.

[0019] Preferably, the semiconductor device serves as a NOT gate device, the gate serves as an input terminal, the channel electrode serves as an output terminal, one of the first electrode or the second electrode is connected to an external power supply, and the other electrode is grounded; the voltage of the external power supply is less than the conduction voltage between the first electrode and the second electrode, and the voltage of the external power supply is not less than the conduction voltage between the first electrode or the second electrode connected to the external power supply and the channel electrode.

[0020] Preferably, the semiconductor device serves as a multi-input gate device, including at least two channel electrodes, at least one of the channel electrodes is in contact with the channel through an insulating end, and serves as an input terminal together with the gate; at least one of the channel electrodes is in direct contact with the channel, and serves as an output terminal; one of the first electrode or the second electrode is connected to an external power supply, and the other electrode is grounded.

[0021] Furthermore, the semiconductor device body comprises:

[0022] substrate;

[0023] A channel region, a source region and a drain region located on the same side of the substrate; the channel region has a first end and a second end opposite to each other in the axial direction; the source region is in electrical contact with the first end, and the drain region is in electrical contact with the second end;

[0024] A gate insulating layer located on the surface of the channel region, wherein the gate insulating layer surrounds a portion of the channel region;

[0025] The channel is located on a surface of the gate insulating layer facing away from the substrate, and the axis direction of the channel is perpendicular to the substrate surface; the body electrode is located on a surface of the channel facing away from the substrate;

[0026] One or more of ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, semiconductor materials, superconducting materials, conductor materials, insulating materials, dielectric materials, two-dimensional materials, one-dimensional materials, three-dimensional materials, perovskite materials, oxides, sulfides, cyanides, hydrides, and silicides are used as insulating layer additional layers, insulating layer materials, insulating layer additional materials, semiconductor layer materials, semiconductor channel materials, or channel electrode materials to achieve logic polymorphism and storage polymorphism.

[0027] Optionally, the channel region is composed of any metal selected from Pt, Pd, Au, Ni, Ag, Cu, Al, Mo, In, Ti, or any alloy thereof, or any stack thereof. For example, the channel region is composed of Pt.

[0028] Optionally, the ferroelectric material is H 3 S, NbN, LaH 10 、BaTiO 3 、PbZr x Ti 1-x O 3 、BiFeO 3 、CIPS(CuIn x P (3-x) S y , such as CuInP 2 S 6 )、HZO(HfZrO x ), MoTe 2 、ZrTiO 4 、PbTiO 3 、Ba(Zr,Ti)O 3 、SrTiO 3 、BaWO 4 ,BaFe 12 O 19 、YBCO(YBa 2 Cu 3 O 7-x , such as YBa2 Cu 3 O 7 ), BFMO(BiFe 1-x MxD 3 , such as BiFe 0.9 Mn 0.1 O 3 ), PCMO(Pr 1-x CaxMnO 3 , for example, Pr 0.7 Ca 0.3 MnO 3 ), LBCO(La 2-x BaxCuO 4 , such as La 1.9 Ba 0.1 CuO 4 ), SmFeAsO 1-x Fx (e.g. SmFeAsO 0.85 F 0.15 ), CaK(Fe 1-x Mx) 4 As 4 (e.g. CaKFe 4 As 4 ), NdFe 1-x MxDV 0.85 (e.g. NdFeAsO 0.85 ) etc.

[0029] Optionally, the phase change material is VO 2 ,Ge 15 Sb 85 , Ga 36 Sb 64 , Fe 3 O 4 、NbO 2 PEG((C 2 H 4 O)n), alloys of indium (In) and tin (Sn), C 60 , C 70 etc.;RMS(Re x Mo 1-x S 2 )、GST((GeTe) x (Sb 2 Te 3 ) y ,AIST((Ag 1-x In x )(Sb 1- x Te x ) 2 , such as Ag5 In 5 Sb 60 Te 30 ), GSST (e.g. Ge 2 Sb 2 Se 1 Te 4 ,Ge 2 Sb 2 Se 4 Te 1 ), Gd 5 (Si 1 Ge 1-X ) 4 (For example, Gd 5 Si 2 Ge 2 ), LaFe 13-x Si x (e.g. LaFe 12 Si), La 0.5 Pr 0.5 Fe 11.5-x Co x Si 1.5 C 0.2 (For example, La 0.5 Pr 0.5 Fe 10.7 Co 0.8 Si 1.5 C 0.2 (For example, 2 Sb 2 Te 5 ), Sb 2 Te 3 、GSB((GeSn) x (Sb) y (such as GeSnSb), AST ((AlSb 2 ) x (Te) y , such as Al 1.5 Sb 3 Te), TASG (Ti 48 As 30 Si 12 Ge 10 ) one or more of the following.

[0030] Optionally, the magnetoelectric material is ZrTiO 4 , Fe 2 O 3 , Fe 3 O 4 、SrBaTiO 3 , Sr 1-x Ba x TiO3 、Bi 4 Ge 3 O 12 、BaTiO 3 , Ba 0.8 Sr 0.2 TiO 3 、NiO、NiZnFe 2 O 4 、LiNbO 3 、BTO-PZT、BaFe 12 O 19 Cr 2 O 3 、BiFeO 3 、BiMnO 3 and LuFe 2 O 4 FCSB(Fe 9T Co 78 Si 12 B 10 )、PMN-PZT((Pb(Mg 1 / 3 Nb 2 / 3 ) 3 ) 1-x -(Pb(Zr 1-y Ti y ) 3 ) x , such as Pb(Mg x Nb 1-x ) 3 -PbZrO 3 -PbTiO 3 )、PMN-PT((Pb(Mg 1 / 3 Nb 2 / 3 ) 3 ) 1-x -(PbTiO 3 ) x , such as Pb(Mg 1 / 3 Nb 2 / 3 ) 3 -PbTiO 3 ) one or more of the following.

[0031] Optionally, the quantum effect material is YBCO, PbLaTiO 3 , CdSe, GaAs, PbSe, BBO, PPLN and lead, zinc-tin alloy, cold atomic gas (such as rubidium, lithium, sodium), iron, nickel, cobalt and other magnetic materials one or more.

[0032] Optionally, the resistive switching effect material is ZrO 2 、TiO 2 、2 O 5 、BiFeO 3 、SrRuO 3 、SrZrO 3 , Fe 3 O 4 、ZnFe 2 O 4 、BaTiO 3 、Pb(Mg 1 / 3 Nb 2 / 3 ) 3 -PbTiO 3 、Ba(Sr 0.7 Ba 0.3 )TiO 3 、In 2 O 3 -SnO 2 , Cu 2 ZnSnSe 4 , polystyrene (PS), La1-xSrxMnO 3 、(Pb,Fe)NbO 3 CuO x (such as CuO 0.5 )、MoS 2-x O 4 (such as MoS 2 O 4 ), HfO x (such as HfO 2 ), WO X (such as WO 2 )、PCMO(Pr 1-x Ca x MnO 3 , for example, Pr 0.7 Ca 0.3 MnO 3 )、LSMO(La x Sr 1-x MnO 3 , such as La 0.5 Sr 0.5 MnO 3 )、LCMO(La x Ca 1-x MnO 3 , such as La 0.7 Ca 0.3 MnO 3 ) etc.

[0033] Optionally, the storage effect material is Fe 3 O 4 , Fe 2 O3 、CoFe(Cobalt-iron alloy), FeCo, FeAlSi, FePt, MnFe, FeNi, CoPt, CoFeB, SbI 3 , polycarbonate, Si 3 N 4 、SiO 2 、SiO x N y , Se, BaFe 12 O 19 、NiFe、AgCl、AgBr、Ge 2 Sb 2 Te 5 、GeSbTe、Al 2 O 3 / Fe、FeAlO x , polyaniline (PANI) or more.

[0034] Optionally, the superconducting material is H 2 S, CeCu 2 Si、CeTIn 5 , CePt 3 Si, Ba 0.6 K 0.4 Fe 2 As 2 、LaNiC 2 、LaNiGa 2 、CaPtAs、Y 3 Fe 5 O 12 / Al, 2H-MX 2 (M=transition metals; X=chalcogenides), 2H-NbSe 2 ,(magic-angle twisted trilayer graphene)(MATTG).,2H-WS 2 、2HeTaS 2 、1Td-MoTe 2 , W 2 N 3 、1T-PdTe 2 , Pb 10-x Cu x (PO 4 ) 6 、(Li,Fe)OHFeSe、CuInCo 2 Te 4 , YBa 2 Cu 3 O 7(yttrium alloy copper oxide), Ba(Fe1-xCox) 2 As 2 、Pb、MgB 2 、CuInSe 2 、LaFeAsO、Ba(Fe,Co) 2 As 2 、BSCCO、GdBCO、IBi 2 Sr 2 Ca 2 Cu 3 O 10 (BSCCO), T l2 Ba 2 CuO 6 , YBa 2 Fe 3 Se 5 One or more of the .

[0035] Optionally, the semiconductor effect material is Si, In 2 Se 3 , GaAs, GaP, CdSe, ZnSe, PbSe, BN, ZnS, PbS, InP, GaN, Al 2 Se 3 , AlAs, InAs, SiGe, CdSe or more.

[0036] Optionally, the perovskite material is CsPbBr 3 MAPbI 3-x Cl x 、SBT(SrBi 1-x Ti x O 9 , such as SrBiTiO 9 )、BLT(Bi 4-x La x Ti 3 O 12 , for example, Bi 3.5 La 0.5 Ti 3 O 12 )、PZT(PbZr 1-x T ix O 3 For example, PbZr 0.7 Ti 0.3 O 3 ), Ca 1-x FA x PbB 3 , for example, Cs 0.8 FA 0.2 PbB 3 , CH3 NH 3 PbX 3 (such as CH 3 NH 3 PbB 3 , CH 3 NH 3 PbI 3 ) one or more of the following.

[0037] Optionally, the two-dimensional material is GaS, h-BN, As 2 Te 3 、Bi 2 S 3 、2H-WS 2 、GaSe、GeS、GeSe、HfS 2 , HfSe 2 、In 2 Se 3 、MoS 2 , 2H-MoS 2 、MoTe 2 、MoSe 2 、MoSSe、MoWS 2 、MoWSe 2 、ReS 2 、ReSe 2 , Sb 2 Te 3 、SnS 2 SnSe 2 , 1T-TaS 2 ,WSe 2 、ZrSe 2 、ZrSe 3 , one or more of ACS.

[0038] The invention also provides an electronic device, comprising the semiconductor device.

[0039] The present invention also provides an array, wherein the array units include the semiconductor device and the electronic device.

[0040] The structure of the present invention can be implemented using existing process lines or adjusted based on existing process steps. The channel electrode and control region materials can be semiconductor materials, conductor materials, or a combination of several materials. The actual preparation process may vary depending on factors such as the manufacturer, device size, and process technology. The structure of the present invention can be adjusted based on the subject of the patent.

[0041] The transistor of the present invention can be illustrated by a three-dimensional structure diagram or a two-dimensional structure diagram.

[0042] Beneficial Effects

[0043] The present invention provides a channel electrode in the channel region, so that the difference between the two lines representing state 0 and state 1 can be expanded by adding the charge control of the junction capacitance of the channel electrode. By adding the channel electrode, the channel electrode can form a junction capacitance with the channel, and the logic function of the transistor device can be controlled. When realizing the logic function, one function of the channel electrode is to extract voltage from the channel. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1 Add electrode schematics for two-terminal device capacitors and memristors;

[0045] Figure 2 Schematic diagram of adding channel electrodes to the triode;

[0046] Figure 3 Schematic diagram of adding channel electrodes to a MOS tube; wherein 101 is a metal layer, 102 is a gate, 103 is a gate insulating layer, 104 is a drain, 105 is a source, 106 is a substrate, and 107 is a control gate;

[0047] Figure 4 Schematic diagram of adding a channel electrode to a ferroelectric MOS tube; wherein 201 is a metal layer, 202 is a ferroelectric material, 203 is a gate insulating layer, 204 is a drain, 205 is a source, 206 is a substrate, and 207 is a control gate;

[0048] Figure 5A -C is the functional test result of the transistor logic gate;

[0049] Figure 6 The single-transistor device structure can realize the NOT logic gate;

[0050] Figure 7 A schematic diagram of a typical process flow for adding a channel electrode transistor;

[0051] Figure 8 is a schematic circuit diagram of a memory array according to an embodiment of the present invention. DETAILED DESCRIPTION

[0052] The present invention will be further described below in conjunction with specific embodiments. It should be understood that these embodiments are only used to illustrate the present invention and are not intended to limit the scope of the present invention. In addition, it should be understood that after reading the content taught by the present invention, those skilled in the art can make various changes or modifications to the present invention, and these equivalent forms fall within the scope limited by the appended claims of the application equally.

[0053] In an embodiment of the present invention, a semiconductor device includes a semiconductor device body and a channel electrode; the semiconductor device body forms a voltage division layer when in operation, and the semiconductor device body includes a body electrode electrically connected to the voltage division layer, so that the semiconductor device body forms at least two ports; the channel electrode is in contact with the voltage division layer, and the channel electrode and the body electrode are separated from each other, serving as a port outside the port in the semiconductor device body; the channel electrode is arranged in the channel region.

[0054] The above-mentioned semiconductor device body is the main structure relative to the prior art, the above-mentioned body electrode belongs to one end of the semiconductor device, the channel electrode belongs to one end of the semiconductor device, and according to the difference in the structure of the semiconductor device body, it will also add at least one end in the semiconductor device, so that the semiconductor device is at least a three-terminal device. Of course, according to the difference in the structure of the semiconductor device body, the above-mentioned semiconductor device can also be at least a four-terminal device, a five-terminal device, etc., and the details will be described in detail in the following invention embodiments, and will not be repeated here. In general, the embodiments of the present invention are specifically connected to one or more electrodes, semiconductors, insulator structures as ports outside the two ends in the upper, lower, left, right, front and back (except for the two ports as electrodes at the two ends or semiconductors at the two ends or insulating layers at the two ends), thereby realizing multi-port control and more logic, optoelectronics, storage, sensing, and bionic functions than ordinary traditional transistor output curves and transfer curves. It should be noted that in the present application, the entire semiconductor device usually includes at least three ports, which usually include an input port, an output port, a control port, etc. Specifically, one port can regulate one or more other ports, or multiple ports can regulate one port, depending on the specific situation.

[0055] The above-mentioned body electrode and channel electrode both need to contact the voltage-dividing layer, so as to form an electrical connection with the voltage-dividing layer. The above-mentioned body electrode and channel electrode need to be made of at least a conductive material, which is usually made of a metal material. Since the above-mentioned voltage-dividing layer connects multiple ends of the entire semiconductor device, the voltage-dividing layer can distribute voltage to multiple ends and transmit electrical signals when working. In the embodiment of the present invention, the above-mentioned voltage-dividing layer can specifically be a single-layer structure or a composite layer structure, and when it is a composite layer structure, its stacking direction is not specifically limited in the embodiment of the present invention. The material of the above-mentioned voltage-dividing layer can specifically be metal or non-metal, and when its material is non-metal, it can specifically be a semiconductor or an insulating material, so the voltage-dividing layer includes any of the following single layers or composite layers stacked in any direction: metal layer, semiconductor, insulating layer.

[0056] Specifically, in an embodiment of the present invention, the voltage division layer is a channel formed when the semiconductor device body is working. At this time, the body electrode is usually located at the end of the channel, and the channel electrode is usually in contact with the side wall of the channel and / or the end of the channel.

[0057] In the embodiment of the present invention, the semiconductor device body includes multiple semiconductor materials to form multiple semiconductor layers, so as to form the channel based on the multiple semiconductor layers during operation. Therefore, the channel formed based on the multiple semiconductor layers is a semiconductor channel.

[0058] The stacking direction of the multi-layer semiconductor layer in the semiconductor device body is not fixed to the axial direction of the channel formed when it is working. When the stacking direction of the multi-layer semiconductor layer is consistent with the axial direction of the channel, a multi-layer semiconductor layer stacked along the axial direction of the channel can be formed; when the stacking direction of the multi-layer semiconductor layer is perpendicular to or intersecting with the axial direction of the channel, the various semiconductor materials corresponding to the multi-layer semiconductor layer can also be specifically stacked along the axial direction perpendicular to the channel, or in any one or several directions to form a multi-layer semiconductor layer with a specific structure. That is, the channel can be formed by a multi-layer semiconductor material, and each layer of semiconductor material forms a semiconductor layer, so that a pn junction, an npn structure, a pnp structure, or even a multi-layer structure can be formed in the channel. It should be noted that the doping types of adjacent semiconductor layers can be the same or different. When the doping types of adjacent semiconductor layers are the same, their doping concentrations need to be different, so as to form different functional junctions, thereby forming a semiconductor channel with a preset function. Correspondingly, the channel electrode 2 can be connected to any of the above semiconductor layers according to actual application needs to achieve the corresponding function.

[0059] The semiconductor device is used as a logic gate device, and the first electrode, the second electrode, the gate electrode and the channel electrode are each used as one of the following ports, and the ports include:

[0060] Input end, output end, control end.

[0061] The semiconductor device serves as a NOT gate device, the gate serves as an input terminal, the channel electrode serves as an output terminal, one of the first electrode or the second electrode is connected to an external power supply, and the other electrode is grounded; the voltage of the external power supply is less than the conduction voltage between the first electrode and the second electrode, and the voltage of the external power supply is not less than the conduction voltage between the first electrode or the second electrode connected to the external power supply and the channel electrode.

[0062] The semiconductor device serves as a multi-input gate device, including at least two channel electrodes, at least one of which is in contact with the channel through an insulating end and serves as an input terminal together with the gate; at least one of which is in direct contact with the channel and serves as an output terminal; one of the first electrode or the second electrode is connected to an external power supply, and the other electrode is grounded.

[0063] The semiconductor device body comprises:

[0064] substrate;

[0065] A channel region, a source region and a drain region located on the same side of the substrate; the channel region has a first end and a second end opposite to each other in the axial direction; the source region is in electrical contact with the first end, and the drain region is in electrical contact with the second end;

[0066] A gate insulating layer located on the surface of the channel region, wherein the gate insulating layer surrounds a portion of the channel region;

[0067] The channel is located on a surface of the gate insulating layer facing away from the substrate, and the axis direction of the channel is perpendicular to the substrate surface; the body electrode is located on a surface of the channel facing away from the substrate;

[0068] The new materials such as ferroelectric material, phase change material, perovskite material, oxide material, sulfide material or magnetoelectric material located between the gate and the gate insulating layer or the gate insulating layer itself is a new material such as ferroelectric material, phase change material, perovskite material, oxide material, sulfide material or magnetoelectric material.

[0069] Optionally, the channel electrode region is composed of a semiconductor layer, a conductor layer or any stack thereof.

[0070] Optionally, the channel electrode is composed of any metal selected from Pt, Pd, Au, Ni, Ag, Cu, Al, Mo, In, Ti, or any alloy thereof, or any stack thereof. For example, the channel electrode is composed of Pt. The purpose of the channel electrode is to form a junction capacitance with the connection part, or to extract the local voltage of the connection area, or to regulate the connection area.

[0071] Optionally, the ferroelectric material is H 3 S, NbN, LaH 10 、BaTiO 3 、PbZr x Ti 1-x O 3 、BiFeO 3 、CIPS(CuIn x P (3-x) S y , such as CuInP2 S 6 )、HZO(HfZrO x ), MoTe 2 、ZrTiO 4 、PbTiO 3 、Ba(Zr,Ti)O 3 、SrTiO 3 、BaWO 4 ,BaFe 12 O 19 、YBCO(YBa 2 Cu 3 O 7-x , such as YBa 2 Cu 3 O 7 ), BFMO(BiFe 1-x MxD 3 , such as BiFe 0.9 Mn 0.1 O 3 ), PCMO(Pr 1-x CaxMnO 3 , for example, Pr 0.7 Ca 0.3 MnO 3 ), LBCO(La 2-x BaxCuO 4 , such as La 1.9 Ba 0.1 CuO 4 ), SmFeAsO 1-x Fx (e.g. SmFeAsO 0.85 F 0.15 ), CaK(Fe 1-x Mx) 4 As 4 (e.g. CaKFe 4 As 4 ), NdFe 1-x MxDV 0.85 (e.g. NdFeAsO 0.85 ) etc.

[0072] Optionally, the phase change material is VO 2 ,Ge 15 Sb 85 , Ga 36 Sb 64 , Fe 3 O 4 、NbO 2 PEG((C 2 H 4O)n), alloys of indium (In) and tin (Sn), C 60 , C 70 etc.;RMS(Re x Mo 1-x S 2 )、GST((GeTe) x (Sb 2 Te 3 ) y ,AIST((Ag 1-x In x )(Sb 1- x Te x ) 2 , such as Ag 5 In 5 Sb 60 Te 30 ), GSST (e.g. Ge 2 Sb 2 Se 1 Te 4 ,Ge 2 Sb 2 Se 4 Te 1 ), Gd 5 (Si 1 Ge 1-X ) 4 (For example, Gd 5 Si 2 Ge 2 ), LaFe 13-x Si x (e.g. LaFe 12 Si), La 0.5 Pr 0.5 Fe 11.5-x Co x Si 1.5 C 0.2 (For example, La 0.5 Pr 0.5 Fe 10.7 Co 0.8 Si 1.5 C 0.2 (For example, Ge 2 Sb 2 Te 5 ), Sb 2 Te 3 、GSB((GeSn) x (Sb) y (such as GeSnSb), AST((AlSb 2 ) x (Te) y , such as Al1.5 Sb 3 Te), TASG (Ti 48 As 30 Si 12 Ge 10 ) one or more of the following.

[0073] Optionally, the magnetoelectric material is ZrTiO 4 , Fe 2 O 3 , Fe 3 O 4 、SrBaTiO 3 , Sr 1-x Ba x TiO 3 、Bi 4 Ge 3 O 12 、BaTiO 3 , Ba 0.8 Sr 0.2 TiO 3 、NiO、NiZnFe 2 O 4 、LiNbO 3 、BTO-PZT、BaFe 12 O 19 Cr 2 O 3 、BiFeO 3 、BiMnO 3 and LuFe 2 O 4 FCSB(Fe 90 Co 78 Si 12 B 10 )、PMN-PZT((Pb(Mg 1 / 3 Nb 2 / 3 ) 3 ) 1-x -(Pb(Zr 1-y Ti y ) 3 ) x , such as Pb(Mg x Nb 1-x ) 3 -PbZrO 3 -PbTiO 3 )、PMN-PT((Pb(Mg 1 / 3 Nb 2 / 3 ) 3 ) 1-x -(PbTiO 3 ) x , such as Pb(Mg1 / 3 Nb 2 / 3 ) 3 -PbTiO 3 ) one or more of the following.

[0074] Optionally, the quantum effect material is YBCO, PbLaTiO 3 , CdSe, GaAs, PbSe, BBO, PPLN and lead, zinc-tin alloy, cold atomic gas (such as rubidium, lithium, sodium), iron, nickel, cobalt and other magnetic materials one or more.

[0075] Optionally, the resistive switching effect material is ZrO 2 、TiO 2 、 2 O 5 、BiFeO 3 、SrRuO 3 、SrZrO 3 , Fe 3 O 4 、ZnFe 2 O 4 、BaTiO 3 、Pb(Mg 1 / 3 Nb 2 / 3 ) 3 -PbTiO 3 、Ba(Sr 0.7 Ba 0.3 )TiO 3 、In 2 O 3 -SnO 2 , Cu 2 ZnSnSe 4 , polystyrene (PS), La1-xSrxMnO 3 、(Pb,Fe)NbO 3 CuO x (such as CuO 0.5 )、MoS 2-x O 4 (such as MoS 2 O 4 ), HfO x (such as HfO 2 ), WO X (such as WO 2 )、PCMO(Pr 1-x Ca x MnO 3 , for example, Pr 0.7 Ca 0.3 MnO 3 )、LSMO(La x Sr 1-xMnO 3 , such as La 0.5 Sr 0.5 MnO 3 )、LCMO(La x Ca 1-x MnO 3 , such as La 0.7 Ca 0.3 MnO 3 ) etc.

[0076] Optionally, the storage effect material is Fe 3 O 4 , Fe 2 O 3 、CoFe(Cobalt-iron alloy), FeCo, FeAlSi, FePt, MnFe, FeNi, CoPt, CoFeB, SbI 3 , polycarbonate, Si 3 N 4 、SiO 2 、SiO x N y , Se, BaFe 12 O 19 、NiFe、AgCl、AgBr、Ge 2 Sb 2 Te 5 、GeSbTe、Al 2 O 3 / Fe、FeAlO x , polyaniline (PANI) or more.

[0077] Optionally, the superconducting material is H 2 S, CeCu 2 Si、CeTIn 5 , CePt 3 Si, Ba 0.6 K 0.4 Fe 2 As 2 、LaNiC 2 、LaNiGa 2 、CaPtAs、Y 3 Fe 5 O 12 / Al, 2H-MX 2 (M=transition metals; X=chalcogenides), 2H-NbSe 2 ,(magic-angle twisted trilayer graphene)(MATTG).,2H-WS2 、2HeTaS 2 、1Td-MoTe 2 , W 2 N 3 、1T-PdTe 2 , Pb 10-x Cu x (PO 4 ) 6 、(Li,Fe)OHFeSe、CuInCo 2 Te 4 , YBa 2 Cu 3 O 7 (yttrium alloy copper oxide), Ba(Fe1-xCox) 2 As 2 、Pb、MgB 2 、CuInSe 2 、LaFeAsO、Ba(Fe,Co) 2 As 2 、BSCCO、GdBCO、IBi 2 Sr 2 Ca 2 Cu 3 O 10 (BSCCO), T l2 Ba 2 CuO 6 , YBa 2 Fe 3 Se 5 One or more of the .

[0078] Optionally, the semiconductor effect material is Si, In 2 Se 3 , GaAs, GaP, CdSe, ZnSe, PbSe, BN, ZnS, PbS, InP, GaN, Al 2 Se 3 , AlAs, InAs, SiGe, CdSe or more.

[0079] Optionally, the perovskite material is CsPbBr 3 MAPbI 3-x Cl x 、SBT(SrBi 1-x Ti x O 9 , such as SrBiTiO 9 )、BLT(Bi 4-x La x Ti 3 O 12 , for example, Bi3.5 La 0.5 Ti 3 O 12 )、PZT(PbZr 1-x T ix O 3 For example, PbZr 0.7 Ti 0.3 O 3 ), Cs 1-x FA x PbB 3 , for example, Cs 0.8 FA 0.2 PbB 3 , CH 3 NH 3 PbX 3 (such as CH 3 NH 3 PbB 3 , CH 3 NH 3 PbI 3 ) one or more of the following.

[0080] Optionally, the two-dimensional material is GaS, h-BN, As 2 Te 3 、Bi 2 S 3 、2H-WS 2 、GaSe、GeS、GeSe、HfS 2 , HfSe 2 、In 2 Se 3 、MoS 2 、2H-MoS 2 、MoTe 2 、MoSe 2 、MoSSe、MoWS 2 、MoWSe 2 、ReS 2 、ReSe 2 , Sb 2 Te 3 、SnS 2 SnSe 2 , 1T-TaS 2 ,WSe 2 、ZrSe 2 、ZrSe 3 , one or more of ACS.

[0081] The present invention further provides an electronic device, comprising the semiconductor device provided by any of the above-mentioned embodiments of the invention. The remaining structure of the electronic device can refer to the prior art and will not be described in detail here.

[0082] Since the semiconductor device provided by the above-mentioned embodiment of the invention is provided with a channel electrode connected to the channel, the channel electrode can be used to control the channel, and can also be used as an input electrode, an output electrode, etc., so that the semiconductor device integrates more functions. Correspondingly, a single component in the above-mentioned electronic device can also integrate more functions, thereby increasing the application scenarios of the electronic device.

[0083] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0084] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0085] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0086] Introduction to adding channel electrodes to two-terminal devices:

[0087] In the embodiment of the present invention, the semiconductor device can be used as a logic gate device, and the port includes: an input terminal, an output terminal, and a control terminal. Thus, it can be used as a logic gate device. The logic gate device may include or exclude the control terminal, but usually needs to have one or more input terminals and one or more output terminals. The semiconductor device can be used as a logic gate device, specifically as a NOT gate, a NOR gate, a NAND gate, an AND-NOR gate, an OR-NAND gate, a tri-state gate, a transmission gate, a multiplexer, an XOR gate, an XNOR gate, and the like.

[0088] Introduction to adding channel electrodes to three-terminal devices:

[0089] In the embodiment of the present invention, the semiconductor device can be used as a logic gate device, and the port includes: a base, a collector, an emitter, and a control electrode. Thus, it can be used as a logic gate device. The logic gate device may include or exclude the control terminal, but usually needs to have one or more input terminals and one or more output terminals. The semiconductor device can be used as a logic gate device, specifically as a NOT gate, a NOR gate, a NAND gate, an AND-NOR gate, an OR-NAND gate, a tri-state gate, a transmission gate, a multiplexer, an XOR gate, an XNOR gate, and the like.

[0090] Introduction to adding channel electrodes to three-terminal MOS tubes:

[0091] In an embodiment of the present invention, the semiconductor device can be used as a logic gate device, and the port includes: a source, a drain, a gate, and a control gate. Thus, it can be used as a logic gate device. The logic gate device may include or exclude the control terminal, but usually needs to have one or more input terminals and one or more output terminals. The semiconductor device can be used as a logic gate device, specifically as a NOT gate, a NOR gate, a NAND gate, an AND-NOR gate, an OR-NAND gate, a tri-state gate, a transmission gate, a multiplexer, an XOR gate, an XNOR gate, and the like.

[0092] Introduction to logical mechanism:

[0093] (1) Classification and characteristics of logic gates

[0094]

[0095] (2) Figure 5A As shown, in the single transistor dual input gate device structure embodiment of the present invention, the typical logic characteristic curve of the single transistor dual input NAND gate device structure is obtained through experimental measurement. The experiment shows that the single transistor dual input gate device structure can successfully realize the NAND logic gate. By introducing an additional logic gate as the second input. As shown in the logic NAND gate truth table of Table A, only when input 1 and input 2 are logic 1, the output will be logic 0. The measured data is shown in Table B. The single transistor dual input gate device structure can effectively realize the NAND logic gate, and the drain voltage and source voltage remain stable. In this table, the drain voltage V DS =0.8V and source voltage VSS=0V.

[0096] like Figure 5BAs shown, in the single transistor dual input gate AND device structure embodiment of the present invention, the typical logic characteristic curve of the single transistor dual input AND gate device structure is obtained through experimental measurement. The experiment shows that the AND logic gate can be successfully realized by using a single transistor dual input gate device structure. By introducing an additional logic gate as the second input. As shown in the logic AND gate truth table of Table A, only if input 1 and input 2 are logic 1, the output will be logic 1. The measured data is shown in Table B. The single transistor dual input gate device structure can effectively realize the AND logic gate, and the drain voltage and source voltage remain stable. In this table, the drain voltage VDS = 6V and the source voltage VSS = 0V.

[0097] like Figure 5C As shown, in the single transistor dual input gate OR device structure embodiment of the present invention, the typical logic characteristic curve of the single transistor dual input OR gate device structure is obtained through experimental measurement. The experiment shows that the OR logic gate can be successfully realized by using a single transistor dual input gate device structure. By introducing an additional logic gate as the second input. As shown in the logic OR gate truth table of Table A, as long as input 1 or input 2 is logic 0, the output will be logic 0. The measured data is shown in Table B. The single transistor dual input gate device structure can effectively realize the OR logic gate, and the drain voltage and source voltage remain stable. In this table, the drain voltage VDS = 6V and the source voltage VSS = 0V.

[0098] like Figure 6 As shown in FIG. 1 , in the single transistor NOT gate device structure embodiment of the present invention, a typical logic characteristic curve of the single transistor NOT gate device structure is obtained through experimental measurement. The experiment shows that the single transistor device structure can successfully implement the NOT logic gate. As shown in A, the logic NOT gate truth table has opposite input and output logics. The measured data is shown in B, and the single transistor device structure can effectively implement the NOT logic gate, and the drain voltage and source voltage remain stable. In this table, the drain voltage V DS ≤1V and source voltage VSS=0V.

[0099] In addition, the manufacturing technology of the transistor used in the embodiment of the present invention is further introduced. Figure 7A schematic diagram of a typical process flow for preparing a transistor with a channel electrode added to an embodiment of the present invention is provided, (1) preparing a substrate: first, selecting an appropriate semiconductor material as a substrate, and subjecting it to chemical and physical treatment to remove impurities and impure substances. (2) forming various parts of the transistor: using oxidation, photolithography, doping, deposition and etching techniques to form a transistor channel, gate oxide layer, source, drain, channel electrode, and gate. (3) forming contacts: using photolithography and etching techniques to form metal contacts on the gate, source region, drain region, and control region to connect to an external circuit. (4) surface flattening: during the preparation process, an uneven surface may occur. Surface flattening treatment is required. (5) metallization: in the final step, the entire transistor is metallized to connect the transistor electrode to an external circuit.

[0100] Figure 8 A schematic diagram of a memory cell in a memory array performing a write operation is shown.

[0101] The memory device includes a word line driver module, a bit line driver module, and a memory array. The word line driver module is connected to the gate of the memory transistor 10 via a word line WL, the bit line driver module is connected to the channel electrode of the memory transistor 10 via a bit line BL1, and is connected to the drain of the memory transistor 10 via a bit line BL2.

[0102] In a write operation, a gate voltage Vgs is provided via the word line WL, a control region voltage Vc is provided via the bit line BL1, and a drain voltage Vds is provided via the bit line BL2. The source of the storage transistor 10 is grounded. At this time, the storage transistors 10 in the storage array are in an on state, and the unselected storage transistors in the storage array are in an off state. Preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 50V, and the drain voltage Vds is 0.05 to 50V. More preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 25V, and the drain voltage Vds is 0.05 to 25V. More preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 15V, and the drain voltage Vds is 0.05 to 15V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 10V, and the drain voltage Vds is 0.05 to 10V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 5V, and the drain voltage Vds is 0.05 to 5V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 2.5V, and the drain voltage Vds is 0.05 to 2.5V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 1.8V, and the drain voltage Vds is 0.05 to 2V. Most preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 1.5V, and the drain voltage Vds is 0.05 to 1.5V.

[0103] Further, in a write operation, a gate voltage Vgs is provided via the word line WL, a control region voltage Vc is provided via the bit line BL1, and a drain voltage Vds is provided via the bit line BL2. The source of the storage transistor 10 is grounded. At this time, the storage transistors 10 in the storage array are in an on state, and the unselected storage transistors in the storage array are in an off state. Preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 50V, the drain voltage Vds is 0.05 to 50V, and the control region voltage Vc is -50 to 50V. More preferably, in a write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 25V, the drain voltage Vds is 0.05 to 25V, and the control region voltage Vc is -20 to 20V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 15V, the drain voltage Vds is 0.05 to 15V, and the control region voltage Vc is -10 to 10V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.5 to 10V, the drain voltage Vds is 0.05 to 10V, and the control region voltage Vc is -10 to 10V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 5V, the drain voltage Vds is 0.05 to 5V, and the control region voltage Vc is -5 to 5V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 2.5V, the drain voltage Vds is 0.05 to 2.5V, and the control region voltage Vc is -5 to 5V. More preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 1.8 V, the drain voltage Vds is 0.05 to 2 V, and the control region voltage Vc is -2 to 2 V. Most preferably, in the write operation, the gate voltage Vgs of the storage transistor 10 is 0.7 to 1.5 V, the drain voltage Vds is 0.05 to 1.5 V, and the control region voltage Vc is -2 to 2 V.

[0104] Furthermore, the write operation includes, for example, data erasure and data programming. In data erasure, the control region voltage Vc of the storage transistor 10 is, for example, 1.5V, and the junction capacitance of the storage transistor 10 is discharged to release the charge. In data programming, the control region voltage Vc of the storage transistor 10 is, for example, -1.5V, so that the voltage difference of the gate voltage Vgs relative to the control region voltage Vc exceeds a predetermined value, and the junction capacitance of the storage transistor 10 is charged to store the charge. The write operation can change the storage state of the storage transistor 10, for example, the erase state of the storage transistor 10 is a high resistance state, which is used to represent the digital value 0, and the write state is a low resistance state, which is used to represent the digital value 1.

[0105] In the read operation, a gate voltage Vgs is provided via the word line WL, and a drain voltage Vds is provided via the bit line BL2. The source of the storage transistor 10 is grounded. The channel electrode of the storage transistor 10 is in a suspended state due to the disconnection of the bit line BL1. At this time, the storage transistors 10 in the storage array are in an on state, and the unselected storage transistors in the storage array are in an off state. Preferably, in the read operation, the gate voltage Vgs of the storage transistor 10 is 1.2V, and the drain voltage Vds is 2V.

[0106] Further, the read operation includes detecting the drain current Ids of the storage transistor 10. In the write operation of the storage transistor 10, the storage state of the storage transistor 10 is related to the resistance state. Even if the same bias conditions, that is, the same gate voltage, drain voltage and source voltage are used, the drain current of the storage transistor in different storage states is different.

[0107] Therefore, by comparing the drain current Ids with the current reference Iref, the storage state of the storage transistor 10 can be determined according to the size of the drain current Ids. For example, when the drain current of the storage transistor 10 is greater than the current reference Iref, the digital value stored in the storage transistor 10 is determined to be 1, and when the drain current of the storage transistor 10 is less than or equal to the current reference Iref, the digital value stored in the storage transistor 10 is determined to be 0. There can be multiple current references Iref, thereby realizing multi-state storage.

[0108] Therefore, the channel electrode output voltage V CG Compared with the voltage reference Vref, the channel electrode output voltage V CG The size of can determine the storage state of the transistor 10. For example, when the channel electrode output voltage of the transistor 10 is greater than the voltage reference Vref, it is determined that the digital value output by the transistor 10 is 1. CG When the voltage is less than or equal to the voltage reference Vref, it is determined that the digital value of the logic output of the transistor 10 is 0. There may also be multiple voltage references Vref to implement multi-state logic.

[0109] When the transistor 10 is replaced with other two-terminal devices, three-terminal devices, or multi-terminal devices, similar operations can be achieved.

[0110] Therefore, by comparing the device current Ids with the current reference Iref, the storage state of the storage transistor 10 can be determined according to the size of the device current Ids. For example, when the device current is greater than the current reference Iref, the digital value stored in the device 10 is determined to be 1, and when the device current of the device 10 is less than or equal to the current reference Iref, the digital value stored in the device 10 is determined to be 0. There may also be multiple current references Iref.

[0111] Using channel electrode output voltage V CG Compared with the voltage reference Vref, the channel electrode output voltage V CG The storage state of the device 10 can be determined by the size of . For example, when the channel electrode output voltage of the device 10 is greater than the voltage reference Vref, it is determined that the digital value stored in the device 10 is 1. CG When the voltage is less than or equal to the voltage reference Vref, it is determined that the digital value of the logic output of the device 10 is 0. There may also be multiple voltage references Vref.

[0112] The above is just a typical process flow for the preparation of a channel electrode transistor. The new structure can be implemented using existing process lines or adjusted based on existing process steps. The control area material can be a semiconductor material, a conductor material, or a combination of several materials. The actual preparation process may vary depending on factors such as the manufacturer, device size, and process technology.

[0113] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0114] The semiconductor device and the electronic device provided by the present invention are introduced in detail above. The principles and implementation methods of the present invention are described in detail using specific examples herein. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made to the present invention without departing from the principles of the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. A semiconductor device, characterized in that: including a semiconductor device body and a channel electrode; The semiconductor device body forms a voltage division layer when in operation, and the semiconductor device body includes a body electrode electrically connected to the voltage division layer, so that the semiconductor device body forms at least two ports; the channel electrode is in contact with the voltage division layer, and the channel electrode and the body electrode are separated from each other, serving as a port outside the port in the semiconductor device body.

2. The semiconductor device according to claim 1, wherein: The voltage-dividing layer includes any of the following single layers or composite layers stacked in any direction: Metal layer, semiconductor, insulating layer.

3. The semiconductor device according to claim 1, wherein: The channel electrode is composed of any one of a conductor and a semiconductor or any of them.

4. The semiconductor device according to claim 2, characterized in that The voltage division layer is a channel formed by the semiconductor device body when the semiconductor device body is working. The body electrode is located at the end of the channel, and the channel electrode is in contact with the side wall of the channel and / or the end of the channel.

5. The semiconductor device according to claim 4, characterized in that The semiconductor device body includes a plurality of semiconductor materials to form a plurality of semiconductor layers, so as to form the channel during operation based on the plurality of semiconductor layers.

6. The semiconductor device according to claim 4, characterized in that The body electrode includes a first electrode and a second electrode which are arranged opposite to each other. The first electrode and the second electrode are connected via the channel. The channel electrode and the first electrode, as well as the channel electrode and the second electrode are separated from each other.

7. The semiconductor device according to claim 1, wherein: The channel electrode is processed by a doping process, or / and a deposition process, or / and an epitaxial process, or / and a self-assembly process, or / and a spin coating process, or / and a sputtering process, or / and a filling process, or / and a Roll-to-Roll process, or / and a hydrothermal process, or / and an imprinting process, or / and a rolling process, or / and a printing process, or / and an evaporation process.

8. The semiconductor device according to claim 1, wherein: The semiconductor device is used as a logic gate device, and the first electrode, the second electrode, the gate electrode and the channel electrode are each used as one of the following ports, and the ports include: Input end, output end, control end.

9. The semiconductor device according to claim 1, wherein: The semiconductor device serves as a NOT gate device, the gate serves as an input terminal, the channel electrode serves as an output terminal, one of the first electrode or the second electrode is connected to an external power supply, and the other electrode is grounded; the voltage of the external power supply is less than the conduction voltage between the first electrode and the second electrode, and the voltage of the external power supply is not less than the conduction voltage between the first electrode or the second electrode connected to the external power supply and the channel electrode.

10. The semiconductor device according to claim 1, wherein: The semiconductor device serves as a multi-input gate device, including at least two channel electrodes, at least one of which is in contact with the channel through an insulating end and serves as an input terminal together with the gate; at least one of which is in direct contact with the channel and serves as an output terminal; one of the first electrode or the second electrode is connected to an external power supply, and the other electrode is grounded.

11. The semiconductor device according to claim 1, wherein: The semiconductor device body comprises: substrate; A channel region, a source region and a drain region located on the same side of the substrate; the channel region has a first end and a second end opposite to each other in the axial direction; the source region is in electrical contact with the first end, and the drain region is in electrical contact with the second end; A gate insulating layer located on the surface of the channel region, wherein the gate insulating layer surrounds a portion of the channel region; The channel is located on a surface of the gate insulating layer facing away from the substrate, and the axis direction of the channel is perpendicular to the substrate surface; the body electrode is located on a surface of the channel facing away from the substrate; One or more of ferroelectric materials, magnetoelectric materials, phase change materials, quantum effect materials, resistive effect materials, storage effect materials, semiconductor materials, superconducting materials, conductor materials, insulating materials, dielectric materials, two-dimensional materials, one-dimensional materials, three-dimensional materials, perovskite materials, oxides, sulfides, cyanides, hydrides, and silicides are used as insulating layer additional layers, insulating layer materials, insulating layer additional materials, semiconductor layer materials, semiconductor channel materials, or channel electrode materials to achieve logic polymorphism and storage polymorphism.

12. An electronic device, characterized in that: The invention comprises a semiconductor device as claimed in any one of claims 1 to 11.

13. An array, characterized in that: The array unit comprises the semiconductor device or the electronic apparatus according to any one of claims 1 to 12.

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