Stacked polycrystalline or single-crystal-like nanoplatelet devices and methods of making the same
By defining the active region and gate structure through photolithography and etching processes, and combining it with metal-induced window crystallization, efficient integration of nanosheet devices is achieved. This solves the complexity of nanosheet stacking manufacturing and the problem of parasitic channels, thereby improving device performance and reducing costs.
Patent Information
- Application Number
- CN202411940713.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-26
- Publication Date
- 2026-02-24
- Estimated Expiration
- 2044-12-26
AI Technical Summary
Traditional nanosheet stacking manufacturing processes are complex and costly, and suffer from parasitic channel effects, which affect transistor performance and efficiency.
The active region and gate structure are defined by photolithography and etching processes, nanosheet crystallization is performed through metal-induced windows, and device integration is achieved by combining interconnect via technology, which simplifies the epitaxial process and suppresses parasitic channels.
It reduces production costs, improves device performance and integration, enhances device reliability and stability, and meets the requirements of high performance, miniaturization and low power consumption.
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Figure CN119907285B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductor technology, and in particular to a stacked polycrystalline or quasi-single-crystal nanosheet device and its fabrication method. Background Technology
[0002] With the rapid development of semiconductor technology, especially at advanced process nodes, device miniaturization and performance improvement have become key research focuses. Against this backdrop, channel structure, as one of the key factors determining transistor performance, makes innovation in its design and manufacturing processes particularly important. Traditional channel structures mainly include two forms: nanowires and nanosheets. Each has its advantages and disadvantages, but in terms of performance, nanosheet structures exhibit more significant advantages due to their larger contact area and more efficient charge transport characteristics.
[0003] However, the complexity and high cost of nanosheet stacking fabrication processes have been major bottlenecks restricting its widespread application. Traditional nanosheet stacking fabrication typically employs epitaxial processes, which involve precisely controlling material growth to alternately form channel layers and sacrificial layers on a substrate. The sacrificial layers are then removed using chemical or physical methods, leaving the desired nanosheet structure. Although this method can produce high-quality nanosheets, its high cost and extremely high equipment precision requirements limit its application in large-scale production.
[0004] Furthermore, traditional nanosheet stacking manufacturing processes suffer from a significant problem—the parasitic channel effect of the substrate. The presence of parasitic channels severely impacts transistor performance, leading to increased leakage current and power consumption, thereby reducing the overall efficiency and reliability of the device.
[0005] Therefore, exploring new nanosheet manufacturing processes to reduce costs, improve production efficiency, and effectively suppress parasitic channeling effects has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0006] The purpose of this invention is to provide a stacked polycrystalline or quasi-single-crystal nanosheet device and its preparation method. This method not only simplifies the complexity of traditional epitaxial processes and reduces production costs, but also effectively solves the problem of parasitic channeling effect.
[0007] In a first aspect, the present invention provides a method for fabricating stacked polycrystalline or quasi-single-crystalline nanosheet devices, comprising the following steps:
[0008] A multilayer stacked nanosheet structure is formed on the substrate;
[0009] The active region is defined and the gate structure is formed through photolithography and etching processes;
[0010] A metal-induced window is etched on one side of the gate structure, and the multilayer stacked amorphous nanosheets are crystallized into polycrystalline or quasi-monocrystalline nanosheet channels through metal-induced crystallization.
[0011] Contact holes are etched on the other side of the gate structure, and a second-stage silicide is formed;
[0012] Through-hole technology, the integration of stacked polycrystalline or near-monocrystalline nanosheet devices is achieved.
[0013] As a preferred embodiment of this technical solution, the following steps are included:
[0014] S1. Sequentially deposit SiO2 / a-Si stack, SiO2 / a-GeSi or SiO2 / a-Ge stack on the substrate, and perform ion implantation and thinning on the a-Si, a-GeSi or a-Ge layers;
[0015] S2. Repeat step S1 to form multiple stacked structures on SiO2 / a-Si stack, SiO2 / a-GeSi or SiO2 / a-Ge stack;
[0016] S3. Define the active region through photolithography and etching processes, deposit Si3N4 and perform planarization;
[0017] S4. Etch out the gate structure to form the boundary of the channel region, and then deposit the gate dielectric layer and the gate electrode material in sequence to form the gate structure;
[0018] S5. A metal-inducing window is etched on one side of the gate structure, and Ni is deposited in the metal-inducing window. After annealing and acid washing, the first-stage silicide is obtained.
[0019] S6. Anneal the first-level silicide to allow it to diffuse along a-Si, a-GeSi or a-Ge nanosheets to the Si3N4 / a-Si, Si3N4 / a-GeSi or Si3N4 / a-Ge interface, inducing a-Si, a-GeSi or a-Ge to crystallize into polycrystalline or near-single crystals.
[0020] S7. Etch contact holes on the other side of the gate structure and deposit Ni in the metal-induced window. After annealing and acid washing, the second-stage silicide is obtained.
[0021] S8. Through interconnect via technology, the integration of stacked polycrystalline or near-monocrystalline nanosheet devices is completed.
[0022] In a preferred embodiment of this technical solution, in step S1, for the a-Si layer, the implanted ion is P, the energy is 10-20 keV, and the dose is 5e14 / cm. 2 ;
[0023] During the thinning process, the a-Si layer is thinned to 8-12 nm using an etching process.
[0024] In a preferred embodiment of this technical solution, in step S2, the thickness of SiO2 in the stacked structure is less than the thickness of SiO2 in step S1.
[0025] As a preferred embodiment of this technical solution, the material of the gate dielectric layer includes any one of silicon dioxide, silicon nitride, and high-K materials.
[0026] As a preferred embodiment of this technical solution, in step S4, the gate electrode material includes any one of polycrystalline silicon, heavily doped polycrystalline silicon, and metal gate material.
[0027] As a preferred embodiment of this technical solution, in steps S5 and S7, the annealing process is performed with a temperature of 300-450℃ and a time of 1-10 minutes.
[0028] As a preferred embodiment of this technical solution, in steps S5 and S7, during the acid washing process, aqua regia is used to remove unreacted Ni.
[0029] As a preferred embodiment of this technical solution, in step S6, the annealing process is performed with a temperature of 350-575℃ and a time of 12-24h.
[0030] Secondly, the present invention also discloses stacked polycrystalline or near-single-crystal nanosheet devices prepared by the above preparation method, which should also fall within the protection scope of the present invention.
[0031] The method for fabricating stacked polycrystalline or near-single-crystalline nanosheet devices of the present invention has at least the following beneficial effects:
[0032] First, through a metal-induced crystallization process, this invention can transform multilayered stacked nanosheet structures into polycrystalline or near-single-crystal nanosheet channels. Compared to amorphous or low-crystalline materials, polycrystalline or near-single-crystal materials exhibit higher carrier mobility and lower resistivity, thereby significantly improving the conductivity and operating speed of the device. Furthermore, near-single-crystal nanosheet channels also possess excellent structural and thermal stability, contributing to improved device performance stability under long-term operation and high-temperature environments. Second, this invention employs photolithography and etching processes to define the active region and form the gate structure. Precise patterning technology ensures the accuracy and consistency of the device structure, laying a solid foundation for subsequent crystallization and contact hole formation steps. Thus, through the etching of the metal-induced window and the metal-induced crystallization process, localized crystallization control of the nanosheet structure is achieved, avoiding the material waste and process complexity that may result from global crystallization. Furthermore, the stacked nanosheet structure itself enables high device integration, and this invention further integrates stacked polycrystalline or near-monocrystalline nanosheet devices through interconnect via technology. This allows the devices to maintain high performance while achieving even higher integration and smaller size, which is of great significance for meeting the demands of modern electronic devices for high performance, miniaturization, and low power consumption. Finally, although the fabrication process of this invention involves multiple delicate steps, efficient batch production can be achieved by optimizing process parameters and process control, thereby reducing the fabrication cost of individual devices. Simultaneously, because the stacked nanosheet structure enables high device integration, more devices can be fabricated on the same chip area, further improving production efficiency and reducing costs.
[0033] Therefore, the fabrication method for stacked polycrystalline or near-single-crystalline nanosheet devices provided by this invention exhibits significant technical advantages in improving device performance, optimizing fabrication processes, increasing device integration density, enhancing device reliability, and reducing fabrication costs. It not only simplifies the complexity of traditional epitaxial processes and reduces production costs, but also effectively solves the problem of parasitic channel effects, providing a practical solution for the manufacture of high-performance transistors at advanced process nodes. Attached Figure Description
[0034] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0035] Figure 1 This is a schematic diagram of step S1 of the present invention, which involves depositing a SiO2 / a-Si stack on a substrate and performing ion implantation on the a-Si layer.
[0036] Figure 2 This is a schematic diagram of the thinning of the a-Si layer in step S1 of the present invention;
[0037] Figure 3 This is a schematic diagram of step S2 of the present invention, which shows the formation of a stacked structure in the SiO2 / a-Si stack.
[0038] Figure 4 This is a schematic diagram of step S2 of the present invention, in which a stacked structure is formed in the SiO2 / a-Si stack and the a-Si layer is thinned.
[0039] Figure 5 This is a schematic diagram of the present invention in which an a-Ge layer replaces the a-Si layer in a stacked structure;
[0040] Figure 6 This is a schematic diagram of step S3 of the present invention, which defines the active region through photolithography and etching processes;
[0041] Figure 7 This is a schematic diagram of step S3 of the present invention, which involves depositing Si3N4 in the active region and performing planarization.
[0042] Figure 8 This is a schematic diagram of the gate structure being etched in step S4 of the present invention;
[0043] Figure 9 This is a schematic diagram of step S4 of the present invention, in which a gate dielectric layer and a gate dielectric are deposited at the etched gate structure;
[0044] Figure 10 This is a schematic diagram of step S5 of the present invention, in which a metal induction window is etched on one side of the gate structure.
[0045] Figure 11 This is a schematic diagram of step S5 of the present invention, in which Ni is deposited in a metal-induced window, followed by annealing and acid washing to obtain the first-stage silicide;
[0046] Figure 12 This is a schematic diagram of step S6 of the present invention, in which the first-level silicide is annealed to diffuse along the a-Si nanosheet to the Si3N4 / a-Si interface, inducing a-Si to crystallize into polycrystalline or near-single crystal.
[0047] Figure 13 This is a schematic diagram of step S6 of the present invention, in which the first-level silicide is annealed to diffuse along the a-Ge nanosheets to the Si3N4 / a-Ge interface, inducing a-Ge to crystallize into polycrystalline or near-single crystals.
[0048] Figure 14This is a schematic diagram of step S7 of the present invention, in which a contact hole is etched on the other side of the gate structure and Ni is deposited in the metal-induced window, followed by annealing and acid washing to obtain the second-stage silicide.
[0049] Figure 15 This is a schematic diagram illustrating the integration of stacked polycrystalline or near-monocrystalline nanosheet devices through interconnect via technology in step S8 of the present invention. Detailed Implementation
[0050] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0051] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.
[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "installed," "connected," and "linked" should be interpreted broadly; for example, they may refer to a fixed connection, a detachable connection, or an integral connection; they may refer to a mechanical connection or an electrical connection; they may refer to a direct connection or an indirect connection through an intermediate medium; and they may refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.
[0053] Example
[0054] like Figure 1-15 As shown, this embodiment provides a method for fabricating stacked polycrystalline or quasi-single-crystalline nanosheet devices, specifically including the following steps:
[0055] S1. First, deposit a SiO2 layer on the substrate as an insulating layer. The thickness can be adjusted according to specific needs, but sufficient isolation effect should be ensured. Then, deposit an amorphous silicon (a-Si) layer with a thickness of 30-50 nm as the initial channel layer. Then, perform ion implantation on the a-Si layer, such as implanting P ions, with an implantation energy of 10-20 keV and an implantation dose of 5e14 / cm. 2 To improve the efficiency and effectiveness of the subsequent crystallization process, the a-Si layer is thinned to 10 nm using an etching process. On the one hand, a thinner channel layer reduces the electron transport distance in the channel, increasing electron mobility and thus improving the device's response speed. On the other hand, thinning the a-Si layer to an appropriate thickness ensures that the crystallization process is uniform throughout the channel layer, thereby forming a high-quality polycrystalline or near-single-crystal nanosheet channel. At the same time, thinning the a-Si layer to 10 nm also helps to reduce the influence of parasitic capacitance, thereby further improving the device's performance and reliability.
[0056] In this embodiment, to further expand the performance drive of the device, the a-Si layer can also be replaced with amorphous germanium silicon (a-GeSi) or amorphous germanium (a-Ge).
[0057] When amorphous germanium-silicon (a-GeSi) is used as the initial channel layer, P ions can be implanted during ion implantation of a-GeSi at an implantation energy of 10-20 keV and an implantation dose of 5E14 / cm. 2 Finally, the a-GeSi layer was thinned to less than 8-12 nm using an etching process;
[0058] When amorphous germanium (a-Ge) is used as the initial channel layer, P ions can be implanted during ion implantation of a-Ge at an implantation energy of 10-20 keV and an implantation dose of 5E14 / cm. 2 Finally, the a-Ge layer is thinned to less than 8-12 nm using an etching process.
[0059] S2. Repeat step S1, first deposit a SiO2 layer, then deposit an a-Si layer, an a-GeSi layer, or an a-Ge layer to form multiple stacked structures on the SiO2 / a-Si stack, SiO2 / a-GeSi, or SiO2 / a-Ge stack. The thickness of the SiO2 layer in this stacked structure is less than the thickness of the SiO2 layer in step S1. The thinning of the SiO2 layer helps to accurately control the subsequent process and optimize the device performance.
[0060] S3. Define the active region through photolithography and etching processes to lay the foundation for subsequent gate structure fabrication. Then, deposit a layer of Si3N4 and perform planarization to eliminate the impact of surface unevenness on subsequent processes.
[0061] S4. Etch out the gate structure to form the boundary of the channel region, and then deposit the gate dielectric layer and the gate electrode material in sequence to form the gate structure;
[0062] The gate dielectric layer is made of materials such as SiO2, silicon nitride (SiNx) and high-K materials. The high-K materials include hafnium oxide (HfO2), titanium oxide (TiO2), zirconium oxide (ZrO2), tantalum pentoxide (Ta2O5), etc. In this embodiment, the gate dielectric layer can be made of conventional SiO2.
[0063] The gate electrode material includes polycrystalline silicon, metal gate materials and heavily doped polycrystalline silicon, etc. Among them, the metal gate material includes tungsten (W), titanium (Ti), nickel (Ni) and their alloys or compounds. In this embodiment, the gate electrode material is preferably TiN / W.
[0064] S5. SiO2 is deposited on Si3N4 and the gate structure, and a metal-inducing window is etched on one side of the gate structure to provide a channel for the subsequent metal-induced crystallization process. Then, Ni is deposited in the metal-inducing window and annealed at 300-450℃ for 1-10 min to form NiSi2. Then, aqua regia is used for acid washing to remove unreacted Ni to ensure the purity of the crystallization process and obtain the first-stage silicide.
[0065] S6. Anneal the first-stage silicide at 350-575℃ for 12-24h. During this process, the first-stage silicide NiSi2 diffuses along a-Si, a-GeSi or a-Ge amorphous nanosheets to the Si3N4 / a-Si, Si3N4 / a-GeSi or Si3N4 / a-Ge interface, inducing a-Si, a-GeSi or a-Ge to crystallize into polycrystalline or near-single crystals, thereby achieving the crystallization of the channel layer.
[0066] Specifically, when a metal (such as Ni) is deposited in an initial channel layer such as amorphous silicon (a-Si), amorphous germanium silicon (a-GeSi), or amorphous germanium (a-Ge) and annealed at a certain temperature, metal atoms diffuse into the amorphous material and react with it to form metal silicides (such as NiSi2). In this reaction, the metal atoms act as nuclei or "catalysts" within the amorphous material, promoting its crystallization. As the annealing process continues, the metal silicides diffuse along the amorphous nanosheets, inducing the surrounding amorphous material to gradually transform into a polycrystalline or near-single-crystal structure.
[0067] First, the crystallized channel layer exhibits higher electron mobility and lower resistivity, which not only helps reduce electron transport losses in the channel and improve device response and switching speeds, but also reduces defects and scattering centers in the channel, further enhancing device performance. Second, the crystallized channel layer possesses better thermal and chemical stability, maintaining stable performance under harsh environments such as high temperature and high humidity, thus helping to extend device lifespan and improve reliability. Finally, through the metal-induced crystallization process, the degree of crystallization and grain size of the channel layer can be precisely controlled, thereby optimizing device structure and performance, enabling more refined device design and higher integration.
[0068] S7. Etch contact holes on the other side of the gate structure and deposit Ni in the metal-induced window. After annealing and acid washing, a second-level silicide is obtained to prepare for subsequent metallization connection.
[0069] S8. Finally, the integration of stacked polycrystalline or near-monocrystalline nanosheet devices is completed through interconnect via technology. For information on interconnect via technology, please refer to existing technologies, which will not be elaborated on here.
[0070] In summary, this invention, through multilayer stacking and metal-induced crystallization techniques, fabricates high-performance stacked polycrystalline or near-single-crystalline nanosheet channel devices with excellent electrical performance and stability. It not only avoids the high cost of traditional epitaxial processes and reduces device fabrication costs through innovative stacking and crystallization techniques, but also effectively suppresses parasitic channeling effects and improves device reliability and stability by precisely controlling process parameters and material selection. In practical applications, the number of stacked layers and material selection can be adjusted according to specific needs, providing possibilities for further optimization of device performance.
[0071] The above description does not provide detailed explanations of the technical aspects of each layer's patterning and etching. However, those skilled in the art should understand that various technical means can be used to form layers and regions of the desired shape. Furthermore, to create the same structure, those skilled in the art can design methods that are not entirely identical to those described above.
[0072] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for fabricating stacked polycrystalline or near-single-crystalline nanosheet devices, characterized in that, Includes the following steps: S1. Sequentially deposit SiO2 / a-Si stack, SiO2 / a-GeSi or SiO2 / a-Ge stack on the substrate, and perform ion implantation and thinning on the a-Si, a-GeSi or a-Ge layers; S2. Repeat step S1 to form multiple stacked structures on SiO2 / a-Si stack, SiO2 / a-GeSi or SiO2 / a-Ge stack; S3. Define the active region through photolithography and etching processes, deposit Si3N4 and perform planarization; S4. Etch out the gate structure to form the boundary of the channel region, and then deposit the gate dielectric layer and the gate electrode material in sequence to form the gate structure; S5. A metal-inducing window is etched on one side of the gate structure, and Ni is deposited in the metal-inducing window. After annealing and acid washing, the first-stage silicide is obtained. S6. Anneal the first-level silicide to allow it to diffuse along a-Si, a-GeSi or a-Ge nanosheets to the Si3N4 / a-Si, Si3N4 / a-GeSi or Si3N4 / a-Ge interface, inducing a-Si, a-GeSi or a-Ge to crystallize into polycrystalline or near-single crystals. S7. Etch contact holes on the other side of the gate structure and deposit Ni in the metal-induced window. After annealing and acid washing, the second-stage silicide is obtained. S8. Through interconnect via technology, the integration of stacked polycrystalline or near-monocrystalline nanosheet devices is completed.
2. The preparation method according to claim 1, characterized in that, In step S1, for the a-Si layer, during ion implantation, the implanted ion is P, the energy is 10-20 keV, and the dose is 5e14 / cm. 2 ; During the thinning process, the a-Si layer is thinned to 8-12 nm using an etching process.
3. The preparation method according to claim 1, characterized in that, In step S2, the thickness of SiO2 in the stacked structure is less than the thickness of SiO2 in step S1.
4. The preparation method according to claim 1, characterized in that, In step S4, the material of the gate dielectric layer includes any one of silicon dioxide, silicon nitride, and high-K materials.
5. The preparation method according to claim 1, characterized in that, In step S4, the gate electrode material includes any one of polycrystalline silicon, heavily doped polycrystalline silicon, and metal gate material.
6. The preparation method according to claim 1, characterized in that, In steps S5 and S7, the annealing process is performed with a temperature of 300-450℃ and a time of 1-10 minutes.
7. The preparation method according to claim 1, characterized in that, In steps S5 and S7, during the acid washing process, aqua regia is used to remove unreacted Ni.
8. The preparation method according to claim 1, characterized in that, In step S6, the annealing process is performed at a temperature of 350-575℃ for 12-24 hours.
9. A stacked polycrystalline or near-single-crystalline nanosheet device, characterized in that, It is prepared according to any one of claims 1-8.
Citation Information
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