Array substrate and display panel

Abstract

The invention discloses an array substrate and a display panel, the array substrate comprises a substrate, an active layer and a first metal layer, the active layer is arranged on the substrate, the active layer comprises a first channel part and a second channel part which are directly or indirectly connected, and a first gap is formed between the first channel part and the second channel part; the first metal layer is located on the side, away from the substrate, of the active layer and comprises a first conductive part and a second conductive part which are directly or indirectly connected, a second notch is formed between the first conductive part and the second conductive part, and the orthographic projection of the first conductive part on the substrate at least partially covers the orthographic projection of the first channel part on the substrate; the orthographic projection of the second conductive part on the substrate at least partially covers the orthographic projection of the second channel part on the substrate, and the orthographic projection of the first gap on the substrate is at least partially overlapped with the orthographic projection of the second gap on the substrate.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and in particular to an array substrate and a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) has the characteristics of self-luminescence, high brightness, wide viewing angle, high contrast, flexibility, and low energy consumption, and therefore has attracted widespread attention.

[0003] However, the problem of afterimage currently seriously affects the display effect of the display panel. Summary of the invention

[0004] The embodiments of the present application provide an array substrate and a display panel, aiming to improve the image sticking problem and thereby enhance the display effect.

[0005] An embodiment of the present application provides an array substrate, including a substrate, an active layer and a first metal layer, the active layer is arranged on the substrate, the active layer includes a first channel portion and a second channel portion that are directly or indirectly connected, and a first gap is formed between the first channel portion and the second channel portion; the first metal layer is located on a side of the active layer away from the substrate, the first metal layer includes a first conductive portion and a second conductive portion that are directly or indirectly connected, and a second gap is formed between the first conductive portion and the second conductive portion, the orthographic projection of the first conductive portion on the substrate at least partially covers the orthographic projection of the first channel portion on the substrate, the orthographic projection of the second conductive portion on the substrate at least partially covers the orthographic projection of the second channel portion on the substrate, and the orthographic projection of the first gap on the substrate at least partially overlaps with the orthographic projection of the second gap on the substrate.

[0006] According to an implementation of the first aspect of the present application, the orthographic projection of the first channel portion on the substrate overlaps with the orthographic projection of the first conductive portion on the substrate or is located within the orthographic projection of the first conductive portion on the substrate, the orthographic projection of the second channel portion on the substrate overlaps with the orthographic projection of the second conductive portion on the substrate or is located within the orthographic projection of the second conductive portion on the substrate, the first conductive portion and the first channel portion both extend along the first direction, the second conductive portion and the second channel portion both extend along the second direction, and the first direction and the second direction are intersecting; optionally, the first direction, the second direction and the thickness direction of the array substrate are intersecting in pairs; optionally, the first direction, the second direction and the array substrate are intersecting in pairs; The thickness directions of the column substrates are perpendicular to each other; optionally, the active layer also includes a first connecting portion, and the two second channel portions are connected to the same first channel portion through the first connecting portion, and the first channel portion, the second channel portion, and the first connecting portion form a U-shape in the orthographic projection on the substrate; optionally, the first metal layer also includes a second connecting portion connecting the first conductive portion and the second conductive portion, and the first conductive portion, the second conductive portion, and the second connecting portion form a U-shape in the orthographic projection on the substrate; optionally, the three first channel portions and the two second channel portions are alternately connected through the first connecting portion, and the first channel portion, the second communicating portion, and the second connecting portion form an S-shape in the orthographic projection on the substrate.

[0007] According to an implementation scheme of the first aspect of the present application, it also includes: a second metal layer, located on the side of the first metal layer facing away from the substrate, the second metal layer includes a third conductive portion, the orthographic projection of the first channel portion on the substrate at least partially overlaps with the orthographic projection of the third conductive portion on the substrate, and / or the orthographic projection of the second channel portion on the substrate at least partially overlaps with the orthographic projection of the third conductive portion on the substrate; optionally, the orthographic projection of the first channel portion on the substrate and the orthographic projection of the second channel portion on the substrate are both located within the orthographic projection of the third conductive portion on the substrate.

[0008] According to an implementation scheme of the first aspect of the present application, the orthographic projection of the first conductive portion on the substrate at least partially overlaps with the orthographic projection of the third conductive portion on the substrate, and / or the orthographic projection of the second conductive portion on the substrate at least partially overlaps with the orthographic projection of the third conductive portion on the substrate; optionally, the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the second conductive portion on the substrate are both located within the orthographic projection of the third conductive portion on the substrate.

[0009] According to an implementation manner of the first aspect of the present application, the second metal layer also includes an opening portion formed by being completely or partially enclosed by the third conductive portion; the array substrate also includes a third metal layer, the third metal layer is located on the side of the second metal layer away from the substrate, the third metal layer includes a fourth conductive portion, and at least a portion of the fourth conductive portion is electrically connected to the first conductive portion and / or the second conductive portion through the opening portion; optionally, the orthographic projection of the fourth conductive portion on the substrate at least partially overlaps with the orthographic projection of the first conductive portion on the substrate, and / or the orthographic projection of the fourth conductive portion on the substrate at least partially overlaps with the orthographic projection of the second conductive portion on the substrate.

[0010] According to an implementation scheme of the first aspect of the present application, the orthographic projection of the opening portion on the substrate at least partially overlaps with the orthographic projection of the first conductive portion on the substrate, and / or the orthographic projection of the opening portion on the substrate at least partially overlaps with the orthographic projection of the second conductive portion on the substrate; optionally, the orthographic projection of the opening portion on the substrate is covered by the orthographic projection of the first conductive portion on the substrate; optionally, the orthographic projection of the opening portion on the substrate is covered by the orthographic projection of the second conductive portion on the substrate.

[0011] According to the implementation scheme of the first aspect of the present application, it also includes: a first insulating layer, located between the first metal layer and the second metal layer; a second insulating layer, located between the second metal layer and the third metal layer, the first insulating layer and the second insulating layer are both provided with vias, at least part of the fourth conductive part is electrically connected to the first conductive part and / or the second conductive part through the opening part and the vias on the first insulating layer and the second insulating layer; optionally, the orthographic projection of the via on the substrate is located within the orthographic projection of the opening part on the substrate.

[0012] According to an implementation of the first aspect of the present application, the opening is completely enclosed by the third conductive portion, and an orthographic projection of the third conductive portion on the substrate at least partially overlaps with an orthographic projection of the fourth conductive portion on the substrate.

[0013] According to an implementation scheme of the first aspect of the present application, the opening portion is formed by partially enclosing the third conductive portion, and the orthographic projection of the fourth conductive portion on the substrate is located outside the orthographic projection of the third conductive portion on the substrate; optionally, the opening portion is configured as a notch that is recessed inward from the contour edge of the third conductive portion of the second metal layer; optionally, the orthographic projection of the fourth conductive portion on the substrate at least partially overlaps with the orthographic projection of the opening portion on the substrate.

[0014] On the other hand, an embodiment of the present application further provides a display panel, comprising the array substrate of any of the above embodiments.

[0015] In the array substrate of the embodiment of the present application, a channel can be formed between the active layer and the first metal layer by making the orthographic projection of the first conductive part on the substrate at least partially cover the orthographic projection of the first channel part on the substrate, and the orthographic projection of the second conductive part on the substrate at least partially cover the orthographic projection of the second channel part on the substrate. By making the orthographic projection of the first notch formed between the first channel part and the second channel part and the orthographic projection of the second notch formed between the first conductive part and the second conductive part at least partially overlap, the area of ​​the first conductive part and the second conductive part is minimized without changing the channel area, so that the shape of the first metal layer is shrunk and approaches the first channel part and the second channel part, the polarization effect of the first metal layer on the active layer is weakened, the afterimage problem of the array substrate is improved, and the display effect of the array substrate is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solution of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 A schematic diagram of a top view of an array substrate according to some embodiments of the present application;

[0018] Figure 2 An example is shown Figure 1 A partial enlarged view of the middle array substrate at position A;

[0019] Figure 3 An example is shown Figure 2 A cross-sectional view of the array substrate at section BB;

[0020] Figure 4 An example is shown Figure 2 A schematic diagram of a top view of the structure of the first channel portion and the first conductive portion;

[0021] Figure 5 An example is shown Figure 2 A schematic diagram of a top view of the structure of the second channel portion and the second conductive portion;

[0022] Figure 6 Another example is shown Figure 1 A partial enlarged view of the middle array substrate at position A;

[0023] Figure 7 Another example is shown Figure 1 A partial enlarged view of the middle array substrate at position A;

[0024] Figure 8 An example is shown Figure 7 A cross-sectional view of the array substrate at the CC section;

[0025] Fig. 9 Another example is shown Figure 1 A partial enlarged view of the middle array substrate at position A;

[0026] Fig.10 A schematic diagram of a top view of a display panel according to some embodiments of the present application;

[0027] Fig.11 An example is shown Fig.10 The cross-sectional view of the panel at section DD is shown in FIG.

[0028] Reference numerals:

[0029] 10. array substrate; 20. display panel;

[0030] 100. Substrate;

[0031] 200, active layer; 210, first channel portion; 220, second channel portion; 230, first notch; 240, first connecting portion;

[0032] 300, first metal layer; 310, first conductive portion; 320, second conductive portion; 330, second notch; 340, second connecting portion;

[0033] 400, second metal layer; 410, third conductive portion; 420, opening;

[0034] 500, third metal layer; 510, fourth conductive portion; 520, data line; 530, power line;

[0035] 600, first insulating layer; 610, second insulating layer; 611, via hole; 620, third insulating layer;

[0036] 700, pixel definition layer; 710, pixel definition portion; 720, pixel opening; 730, pixel unit; 740, first electrode; 750, second electrode;

[0037] AA, display area; x, first direction; y, second direction; z, thickness direction of the array substrate. DETAILED DESCRIPTION

[0038] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than to limit the present application. For those skilled in the art, the present application can be implemented without the need for some of these specific details. The following description of the embodiments is only to provide a better understanding of the present application by illustrating the examples of the present application.

[0039] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "include..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

[0040] The applicant has found that in the related art, the afterimage problem seriously affects the display effect of the display panel. Among them, the medium-term afterimage and long-term afterimage are mainly caused by the polarization effect of the potential of the first metal layer in the array substrate on the active layer.

[0041] In view of the above problems, the applicant proposes an array substrate, comprising a substrate, an active layer and a first metal layer, the active layer is arranged on the substrate, the active layer comprises a first channel portion and a second channel portion which are directly or indirectly connected, and a first gap is formed between the first channel portion and the second channel portion; the first metal layer is located on the side of the active layer away from the substrate, the first metal layer comprises a first conductive portion and a second conductive portion which are directly or indirectly connected, and a second gap is formed between the first conductive portion and the second conductive portion, the orthographic projection of the first conductive portion on the substrate at least partially covers the orthographic projection of the first channel portion on the substrate, the orthographic projection of the second conductive portion on the substrate at least partially covers the orthographic projection of the second channel portion on the substrate, and the orthographic projection of the first gap on the substrate at least partially overlaps with the orthographic projection of the second gap on the substrate.

[0042] In the array substrate provided by the present application, a channel can be formed between the active layer and the first metal layer by making the orthographic projection of the first conductive part on the substrate at least partially cover the orthographic projection of the first channel part on the substrate, and the orthographic projection of the second conductive part on the substrate at least partially cover the orthographic projection of the second channel part on the substrate. By making the orthographic projection of the first notch formed between the first channel part and the second channel part at least partially overlap with the orthographic projection of the second notch formed between the first conductive part and the second conductive part, the area of ​​the first conductive part and the second conductive part is minimized without changing the channel area, so that the shape of the first metal layer is shrunk and approaches the first channel part and the second channel part, the polarization effect of the first metal layer on the active layer is weakened, the afterimage problem of the array substrate is improved, and the display effect of the array substrate is improved.

[0043] In order to better understand the present application, the array substrate and the display panel of the embodiment of the present application are described in detail below in conjunction with the accompanying drawings. It is noted that the x direction in the accompanying drawings is the first direction, the y direction is the second direction, and the z direction is the thickness direction of the array substrate. In the accompanying drawings, for the convenience of drawing, the dimensions in the drawings are not necessarily proportional to the actual dimensions, and some hierarchical structures in the array substrate are not drawn.

[0044] Please refer to Figures 1 to 3 , Figure 1 A schematic diagram of a top view of an array substrate according to some embodiments of the present application; Figure 2 An example is shown Figure 1 A partial enlarged view of the middle array substrate at position A; Figure 3 An example is shown Figure 2 A cross-sectional view of the array substrate at section BB.

[0045] like Figure 1 and Figure 3 As shown, an embodiment of the first aspect of the present application provides an array substrate 10, the array substrate 10 includes a substrate 100, an active layer 200 and a first metal layer 300, the active layer 200 is disposed on the substrate 100, the active layer 200 includes a first channel portion 210 and a second channel portion 220 that are directly or indirectly connected, and a first notch 230 is formed between the first channel portion 210 and the second channel portion 220. The first metal layer 300 is located on a side of the active layer 200 that is away from the substrate 100, the first metal layer 300 includes a first conductive portion 310 and a second conductive portion 320 that are directly or indirectly connected, and a second notch 330 is formed between the first conductive portion 310 and the second conductive portion 320. The orthographic projection of the first conductive portion 310 on the substrate 100 at least partially covers the orthographic projection of the first channel portion 210 on the substrate 100, the orthographic projection of the second conductive portion 320 on the substrate 100 at least partially covers the orthographic projection of the second channel portion 220 on the substrate 100, and the orthographic projection of the first notch 230 on the substrate 100 at least partially overlaps with the orthographic projection of the second notch 330 on the substrate 100.

[0046] Optionally, the array substrate 10 may also be provided with a pixel driving circuit, and a plurality of thin film transistors may be provided in the pixel driving circuit. The specific composition of the pixel driving circuit is not limited in the embodiment of the present application, and the pixel driving circuit may be any one of 2T1C, 7T1C and 8T1C. The overlapping area of ​​the active layer 200 and the first metal layer 300 forms a channel of one of the thin film transistors. The first electrode of the capacitor structure and the gate of at least part of the thin film transistor may be arranged in the first metal layer 300.

[0047] Optionally, the first notch 230 may be completely enclosed by the first channel portion 210 and the second channel portion 220, or the first channel portion 210 and the second channel portion 220 may only enclose part of the first notch 230. The same is true for the second notch 330. In the array substrate 10 provided in the embodiment of the present application, a channel can be formed between the active layer 200 and the first metal layer 300 by making the orthographic projection of the first conductive portion 310 on the substrate 100 at least partially cover the orthographic projection of the first channel portion 210 on the substrate 100, and the orthographic projection of the second conductive portion 320 on the substrate 100 at least partially cover the orthographic projection of the second channel portion 220 on the substrate 100. By making the orthographic projections of the first notch 230 formed between the first channel portion 210 and the second channel portion 220 at least partially overlap with those of the second notch 330 formed between the first conductive portion 310 and the second conductive portion 320, the areas of the first conductive portion 310 and the second conductive portion 320 are minimized without changing the channel area on the active layer 200, so that the shape of the first metal layer 300 is shrunk and approaches the first channel portion 210 and the second channel portion 220, thereby weakening the polarization effect of the first metal layer 300 on the active layer 200, improving the afterimage problem of the array substrate 10, and further improving the display effect of the array substrate 10.

[0048] Please refer to Figure 2 , Figure 4 and Figure 5 , Figure 4 An example is shown Figure 2 A schematic diagram of a top view of the structure of the first channel portion and the first conductive portion; Figure 5 An example is shown Figure 2 Schematic diagram of the top view of the second channel portion and the second conductive portion.

[0049] like Figure 2 , Figure 4 and Figure 5 As shown, in some optional embodiments, the orthographic projection of the first channel portion 210 on the substrate 100 overlaps with the orthographic projection of the first conductive portion 310 on the substrate 100 or is located within the orthographic projection of the first conductive portion 310 on the substrate 100, and the orthographic projection of the second channel portion 220 on the substrate 100 overlaps with the orthographic projection of the second conductive portion 320 on the substrate 100 or is located within the orthographic projection of the second conductive portion 320 on the substrate 100. The first channel portion 210 is completely covered by the first conductive portion 310, and the second channel portion 220 is completely covered by the second conductive portion 320, thereby increasing the area of ​​the channel.

[0050] Optionally, the first conductive portion 310 and the first channel portion 210 both extend along a first direction (x direction in the figure), the second conductive portion 320 and the second channel portion 220 both extend along a second direction (y direction in the figure), and the first direction x and the second direction y intersect.

[0051] Optionally, the first direction x, the second direction y and the thickness direction of the array substrate (z direction in the figure) are arranged to intersect each other.

[0052] Optionally, the first direction x, the second direction y and the thickness direction z of the array substrate are perpendicular to each other. It can also be understood that the first direction x is the left-right direction of the array substrate 10 , and the second direction y is the up-down direction of the array substrate 10 .

[0053] Optionally, the active layer 200 further includes a first connecting portion 240, and the first connecting portion 240 extends along a curve. The two second channel portions 220 are connected to the same first channel portion 210 through the first connecting portion 240, and the orthographic projection of the first channel portion 210, the second channel portion 220 and the first connecting portion 240 on the substrate 100 forms a U shape. The first notch 230 is formed by partially enclosing the two second channel portions 220, the two first connecting portions 240 and the one first channel portion 210.

[0054] Optionally, the first metal layer 300 further includes a second connecting portion 340, and the second connecting portion extends along a curve. The two first conductive portions 310 are connected to the same second conductive portion 320 through the second connecting portion 340, and the orthographic projections of the first conductive portion 310, the second conductive portion 320, and the second connecting portion 340 on the substrate 100 form a U shape. The second notch 330 is formed by partially enclosing the two second conductive portions 320, the two second connecting portions 340, and one first conductive portion 310.

[0055] Please refer to Figures 4 to 6 , Figure 6 Another example is shown Figure 1 A partial enlarged view of the array substrate at position A.

[0056] like Figures 4 to 6 As shown, in some optional embodiments, three first channel portions 210 and two second channel portions 220 are alternately connected through the first connecting portion 240, and the first channel portion 210, the second channel portion 220 and the first connecting portion 240 form an S-shape in the orthographic projection on the substrate 100. Similarly, the first conductive portion 310, the second conductive portion 320 and the second connecting portion 340 form an S-shape in the orthographic projection on the substrate 100. Two first notches 230 are formed between the first channel portion 210, the second channel portion 220 and the first connecting portion 240, and two second notches 330 are formed between the first conductive portion 310, the second conductive portion 320 and the second connecting portion 340.

[0057] In other embodiments, the projections of the first channel portion 210 and the second channel portion 220 on the substrate 100 may also be formed into other special shapes, as long as the projection shapes of the first conductive portion 310 and the second conductive portion 320 are close to the orthographic projection shapes of the first channel portion 210 and the second channel portion 220 .

[0058] Please refer to Figure 7 and Figure 8 , Figure 7 Another example is shown Figure 1 A partial enlarged view of the middle array substrate at position A; Figure 8 An example is shown Figure 7 Cross-sectional view of the array substrate at the CC section.

[0059] like Figure 7 and Figure 8 As shown, in some optional embodiments, the array substrate 10 may further include a second metal layer 400, the second metal layer 400 includes a third conductive portion 410, the orthographic projection of the first channel portion 210 on the substrate 100 at least partially overlaps with the orthographic projection of the third conductive portion 410 on the substrate 100, and / or the orthographic projection of the second channel portion 220 on the substrate 100 at least partially overlaps with the orthographic projection of the third conductive portion 410 on the substrate 100.

[0060] Optionally, an orthographic projection of the first channel portion 210 on the substrate 100 and an orthographic projection of the second channel portion 220 on the substrate 100 are both located within an orthographic projection of the third conductive portion 410 on the substrate 100 .

[0061] In some optional embodiments, the orthographic projection of the first conductive portion 310 on the substrate 100 at least partially overlaps with the orthographic projection of the third conductive portion 410 on the substrate 100, and / or the orthographic projection of the second conductive portion 320 on the substrate 100 at least partially overlaps with the orthographic projection of the third conductive portion 410 on the substrate 100.

[0062] Optionally, the first metal layer 300 and the second metal layer 400 can form a signal line (such as a scan signal line and a voltage reset signal line), and at the same time, the first metal layer 300 and the second metal layer 400 can also form a first plate and a second plate of a capacitor structure, respectively. The gate of the thin film transistor can be reused as the first plate of the capacitor structure.

[0063] Optionally, the orthographic projection of the first conductive portion 310 on the substrate 100 and the orthographic projection of the second conductive portion 320 on the substrate 100 are both located within the orthographic projection of the third conductive portion 410 on the substrate 100 .

[0064] In the array substrate 10 provided in the embodiment of the present application, the first conductive part 310, the second conductive part 320 and the third conductive part 410 can together constitute a storage capacitor in the pixel driving circuit, and the storage capacitor is used to reduce and eliminate image flicker, thereby improving the display stability of the display panel. The capacity of the capacitor formed between the first conductive part 310, the second conductive part 320 and the third conductive part 410 is determined by the overlapping area between the first conductive part 310, the second conductive part 320 and the third conductive part 410. By reducing the area of ​​the first conductive part 310 and the second conductive part 320, the overlapping area between the first conductive part 310, the second conductive part 320 and the third conductive part 410 can also be reduced, thereby reducing the capacitance, improving the charging rate of the array substrate 10, and improving the problems of uneven display and afterimage under low grayscale. By making the first channel portion 210 , the second channel portion 220 , the first conductive portion 310 and the second conductive portion 320 all covered by the third conductive portion 410 and the third conductive portion 410 not retracted like the first conductive portion 310 and the second conductive portion 320 , the difference in substrate polarization caused by the afterimage test screen is reduced.

[0065] In some optional embodiments, the second metal layer 400 further includes an opening 420 formed by being completely or partially enclosed by the third conductive portion 410. The array substrate 10 further includes a third metal layer 500, which is located on a side of the second metal layer 400 away from the substrate 100, and the third metal layer 500 includes a fourth conductive portion 510, at least part of which is electrically connected to the first conductive portion 310 and / or the second conductive portion 320 through the opening 420.

[0066] Optionally, the third metal layer 500 may further include a data line 520 and a power line 530 .

[0067] Optionally, the other end of the fourth conductive portion 510 is electrically connected to another thin film transistor to transmit the initialization voltage Vref to the gate of the driving transistor.

[0068] Optionally, the orthographic projection of the fourth conductive portion 510 on the substrate 100 at least partially overlaps with the orthographic projection of the first conductive portion 310 on the substrate 100 , and / or the orthographic projection of the fourth conductive portion 510 on the substrate 100 at least partially overlaps with the orthographic projection of the second conductive portion 320 on the substrate 100 .

[0069] Optionally, the material of the active layer 200 may include polysilicon or metal oxide. The material of any one or more of the first metal layer 300, the second metal layer 400, and the third metal layer 500 may include metal materials such as silver, aluminum, and copper.

[0070] In the array substrate 10 provided in the embodiment of the present application, the initialization voltage Vref is transmitted to the gate of the driving transistor by electrically connecting at least a portion of the fourth conductive portion 510 to the first conductive portion 310 and / or the second conductive portion 320 through the opening portion 420, and the other end of the fourth conductive portion 510 is electrically connected to another thin film transistor.

[0071] In some optional embodiments, the orthographic projection of the opening portion 420 on the substrate 100 at least partially overlaps with the orthographic projection of the first conductive portion 310 on the substrate 100 , and / or the orthographic projection of the opening portion 420 on the substrate 100 at least partially overlaps with the orthographic projection of the second conductive portion 320 on the substrate 100 .

[0072] Optionally, the orthographic projection of the opening portion 420 on the substrate 100 is covered by the orthographic projection of the first conductive portion 310 on the substrate 100 .

[0073] Optionally, the orthographic projection of the opening portion 420 on the substrate 100 is covered by the orthographic projection of the second conductive portion 320 on the substrate 100 .

[0074] In the array substrate 10 provided in the embodiment of the present application, by making the opening portion 420 overlap with the first conductive portion 310 and / or the second conductive portion 320, when preparing the third metal layer 500, the fourth conductive portion 510 can directly pass through the opening portion 420 to be electrically connected to the first conductive portion 310 and / or the second conductive portion 320.

[0075] In some optional embodiments, the array substrate 10 may further include a first insulating layer 600 and a second insulating layer 610, wherein the first insulating layer 600 is located between the first metal layer 300 and the second metal layer 400, and the second insulating layer 610 is located between the second metal layer 400 and the third metal layer 500. Vias 611 are provided on the first insulating layer 600 and the second insulating layer 610, and at least part of the fourth conductive portion 510 is electrically connected to the first conductive portion 310 and / or the second conductive portion 320 through the opening 420 and the vias 611 on the first insulating layer 600 and the second insulating layer 610.

[0076] Optionally, the orthographic projection of the via hole 611 on the substrate 100 is located within the orthographic projection of the opening 420 on the substrate 100 .

[0077] Optionally, the array substrate 100 may further include a third insulating layer 620 , and the third insulating layer 620 is located between the active layer 200 and the first metal layer 300 .

[0078] In the array substrate 10 provided in the embodiment of the present application, an insulating layer is provided between adjacent metal layers to avoid short circuit between metal layers. By making the orthographic projection of the via hole 611 on the substrate 100 located within the orthographic projection of the opening 420 on the substrate 100, the projection area of ​​the via hole 611 is smaller than the projection area of ​​the opening 420, so that when the fourth conductive part 510 passes through the opening 420 and is electrically connected to the first conductive part 310 and / or the second conductive part 320, the insulating layer can still block the fourth conductive part 510 from the third conductive part 410, thereby reducing the risk of short circuit between the third conductive part 410 and the fourth conductive part 510.

[0079] Please continue to refer to Figure 7 and Figure 8 In some optional embodiments, the opening portion 420 is completely enclosed by the third conductive portion 410 , and the orthographic projection of the third conductive portion 410 on the substrate 100 at least partially overlaps with the orthographic projection of the fourth conductive portion 510 on the substrate 100 .

[0080] The opening 420 is equivalent to a through hole opened on the third conductive part 410. Since the fourth conductive part 510 needs to connect the first conductive part 310, the second conductive part 320 and another thin film transistor, the orthographic projection of the fourth conductive part 510 on the substrate 100 will definitely overlap with the orthographic projection of the third conductive part 410 on the substrate 100.

[0081] Please refer to Fig. 9 , Fig. 9 Another example is shown Figure 1 A partial enlarged view of the array substrate at position A.

[0082] like Fig. 9 As shown, in some optional embodiments, the opening 420 is formed by partially enclosing the third conductive portion 410, and the orthographic projection of the fourth conductive portion 510 on the substrate 100 is located outside the orthographic projection of the third conductive portion 410 on the substrate 100. This makes the projections of the fourth conductive portion 510 and the third conductive portion 410 not overlap, thereby reducing the parasitic capacitance between the third conductive portion 410 and the fourth conductive portion 510.

[0083] Optionally, an orthographic projection of the fourth conductive portion 510 on the substrate 100 at least partially overlaps with an orthographic projection of the opening 420 on the substrate 100 .

[0084] Optionally, the opening 420 is configured as a notch that is recessed inwardly on the contour edge of the third conductive portion 410. After the first metal layer 300 is provided with the second notch 330, the overlapping area with the second metal layer 400 is reduced. The opening 420 is configured as a notch that is recessed inwardly from the contour edge of the third conductive portion 410 of the second metal layer 400, which can moderately reduce the degree of reduction in the overlapping area between the first metal layer 300 and the second metal layer 400, thereby ensuring that the capacitance between the first metal layer 300 and the second metal layer 400 can meet the requirements.

[0085] The embodiment of the second aspect of the present application further provides a display panel 20, comprising the array substrate 10 of any of the above-mentioned first aspect embodiments. Since the display panel 20 provided by the embodiment of the second aspect of the present application comprises the array substrate 10 of any of the above-mentioned first aspect embodiments, the display panel 20 provided by the embodiment of the second aspect of the present application has the beneficial effects of the array substrate 10 of any of the above-mentioned first aspect embodiments, which will not be described in detail here.

[0086] The display panel 20 in the embodiment of the present application includes but is not limited to mobile phones, personal digital assistants (PDA), tablet computers, e-books, televisions, access control systems, smart landline phones, consoles and other devices with display functions.

[0087] Please refer to Fig.10 and Fig.11 , Fig.10 A schematic diagram of a top view of a display panel according to some embodiments of the present application; Fig.11 An example is shown Fig.10 The cross-sectional view of the panel at section DD is shown in FIG.

[0088] like Fig.10 and Fig.11 As shown, in some optional embodiments, the display panel 20 includes a display area AA, and the display panel 20 located in the display area AA includes a pixel definition layer 700, and the pixel definition layer 700 is located on the side of the third metal layer 500 away from the substrate 100. The pixel definition layer 700 includes a pixel defining portion 710 and a pixel opening 720 formed by the pixel defining portion 710, and the pixel opening 720 is used to accommodate a pixel unit 730. A first electrode 740 is provided on the side of the pixel unit 730 facing the array substrate 10, and a second electrode 750 is provided on the side of the pixel unit 730 away from the array substrate 10.

[0089] Optionally, the first electrode 740 and the second electrode 750 are electrically connected to the pixel unit 730, and the second electrode 750 and the first electrode 740 are used to provide power to the pixel unit 730 to drive the pixel unit 730 to emit light. Specifically, one of the first electrode 740 and the second electrode 750 is an anode, and the other is a cathode. The embodiment of the present application is described by taking the first electrode 740 as an anode and the second electrode 750 as a cathode.

[0090] The above is only a specific implementation of the present application. Those skilled in the art can clearly understand that for the convenience and simplicity of description, the specific working processes of the systems, modules and units described above can refer to the corresponding processes in the aforementioned method embodiments, and will not be repeated here. It should be understood that the protection scope of the present application is not limited to this. Any technician familiar with the technical field can easily think of various equivalent modifications or replacements within the technical scope disclosed in this application, and these modifications or replacements should be included in the protection scope of this application.

Claims

1. An array substrate, characterized in that: include: substrate; An active layer is disposed on the substrate, the active layer comprising a first channel portion and a second channel portion that are directly or indirectly connected, and a first gap is formed between the first channel portion and the second channel portion; A first metal layer is located on a side of the active layer away from the substrate, the first metal layer includes a first conductive portion and a second conductive portion that are directly or indirectly connected, a second gap is formed between the first conductive portion and the second conductive portion, an orthographic projection of the first conductive portion on the substrate at least partially covers an orthographic projection of the first channel portion on the substrate, an orthographic projection of the second conductive portion on the substrate at least partially covers an orthographic projection of the second channel portion on the substrate, and an orthographic projection of the first gap on the substrate at least partially overlaps with an orthographic projection of the second gap on the substrate.

2. The array substrate according to claim 1, characterized in that: The orthographic projection of the first channel portion on the substrate overlaps with the orthographic projection of the first conductive portion on the substrate or is located within the orthographic projection of the first conductive portion on the substrate, the orthographic projection of the second channel portion on the substrate overlaps with the orthographic projection of the second conductive portion on the substrate or is located within the orthographic projection of the second conductive portion on the substrate, the first conductive portion and the first channel portion both extend along a first direction, the second conductive portion and the second channel portion both extend along a second direction, and the first direction and the second direction are arranged to intersect; Preferably, the first direction, the second direction and the thickness direction of the array substrate are arranged to intersect each other; Preferably, the first direction, the second direction and the thickness direction of the array substrate are perpendicular to each other; Preferably, the active layer further comprises a first connecting portion, two of the second channel portions are connected to the same first channel portion via the first connecting portion, and the first channel portion, the second channel portion and the first connecting portion form a U-shape in an orthographic projection on the substrate; Preferably, the first metal layer further comprises a second connecting portion connecting the first conductive portion and the second conductive portion, and the first conductive portion, the second conductive portion and the second connecting portion form a U-shape in the orthographic projection of the substrate; Preferably, three of the first channel portions and two of the second channel portions are alternately connected via first connecting portions, and the first channel portions, the second communicating portions, and the second connecting portions form an S-shape in the orthographic projection of the substrate.

3. The array substrate according to claim 1, characterized in that: Also includes: a second metal layer, located on a side of the first metal layer facing away from the substrate, the second metal layer comprising a third conductive portion, an orthographic projection of the first channel portion on the substrate at least partially overlaps with an orthographic projection of the third conductive portion on the substrate, and / or an orthographic projection of the second channel portion on the substrate at least partially overlaps with an orthographic projection of the third conductive portion on the substrate; Preferably, the orthographic projection of the first channel portion on the substrate and the orthographic projection of the second channel portion on the substrate are both located within the orthographic projection of the third conductive portion on the substrate.

4. The array substrate according to claim 3, characterized in that: The orthographic projection of the first conductive portion on the substrate at least partially overlaps with the orthographic projection of the third conductive portion on the substrate, and / or the orthographic projection of the second conductive portion on the substrate at least partially overlaps with the orthographic projection of the third conductive portion on the substrate; Preferably, the orthographic projection of the first conductive part on the substrate and the orthographic projection of the second conductive part on the substrate are both located within the orthographic projection of the third conductive part on the substrate.

5. The array substrate according to claim 4, characterized in that: The second metal layer further includes an opening portion which is completely or partially enclosed by the third conductive portion; The array substrate further includes a third metal layer, the third metal layer is located on a side of the second metal layer away from the substrate, the third metal layer includes a fourth conductive portion, at least part of the fourth conductive portion is electrically connected to the first conductive portion and / or the second conductive portion through the opening; Preferably, the orthographic projection of the fourth conductive portion on the substrate at least partially overlaps with the orthographic projection of the first conductive portion on the substrate, and / or the orthographic projection of the fourth conductive portion on the substrate at least partially overlaps with the orthographic projection of the second conductive portion on the substrate.

6. The array substrate according to claim 5, characterized in that: The orthographic projection of the opening on the substrate at least partially overlaps with the orthographic projection of the first conductive portion on the substrate, and / or the orthographic projection of the opening on the substrate at least partially overlaps with the orthographic projection of the second conductive portion on the substrate; Preferably, an orthographic projection of the opening portion on the substrate is covered by an orthographic projection of the first conductive portion on the substrate.

7. The array substrate according to claim 6, characterized in that: Also includes: A first insulating layer, located between the first metal layer and the second metal layer; a second insulating layer, located between the second metal layer and the third metal layer, the first insulating layer and the second insulating layer are both provided with via holes, and at least part of the fourth conductive part is electrically connected to the first conductive part and / or the second conductive part through the opening and the via holes on the first insulating layer and the second insulating layer; Preferably, the orthographic projection of the via hole on the substrate is located within the orthographic projection of the opening on the substrate.

8. The array substrate according to claim 5, characterized in that: The opening is completely surrounded by the third conductive portion, and an orthographic projection of the third conductive portion on the substrate at least partially overlaps with an orthographic projection of the fourth conductive portion on the substrate.

9. The array substrate according to claim 5, characterized in that: The opening is configured as a notch that is recessed inward from the contour edge of the third conductive portion of the second metal layer. Alternatively, the opening is partially enclosed by the third conductive portion, and the orthographic projection of the fourth conductive portion on the substrate is located outside the orthographic projection of the third conductive portion on the substrate; Preferably, an orthographic projection of the fourth conductive portion on the substrate at least partially overlaps with an orthographic projection of the opening on the substrate.

10. A display panel, characterized in that: It comprises the array substrate as described in any one of claims 1 to 9.

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