Anti-thimble flip LED chip and preparation method thereof

Abstract

The invention relates to the technical field of LEDs, and discloses an anti-thimble flip LED chip and a preparation method thereof, and the anti-thimble flip LED chip comprises a substrate and an epitaxial layer which are stacked in sequence; a groove is formed in the epitaxial layer, an N-type electrode is arranged in the groove, a current blocking layer and a transparent conducting layer are further arranged on the epitaxial layer, a P-type electrode, a passivation layer and bonding pads are arranged on the transparent conducting layer, and the bonding pads comprise the P-type bonding pad and the N-type bonding pad; the anti-thimble layer is in contact with the passivation layer, is arranged between the P-type bonding pad and the N-type bonding pad, and consists of a plurality of metal layers which are arranged according to preset gaps. According to the flip LED chip and the manufacturing method thereof, the possibility of electric leakage caused by the fact that the ejector pin bursts the chip structure when the flip LED chip is packaged and fixed can be reduced, and the problem of electric leakage caused by communication of the P-type electrode and the N-type electrode due to overflow of solder paste is effectively avoided due to the fact that the metal layers in ejector pin protection are arranged at intervals.

Description

Technical Field

[0001] The invention relates to the technical field of LEDs, and in particular to an anti-ejection flip-chip LED chip and a preparation method thereof. Background Art

[0002] Flip-chip LED chips have the characteristics of no wire bonding and high current resistance, and are widely used in COB lighting, soft light strips, backlight, display and other fields. The packaging of flip-chip LED chips is mainly to transfer the chip to the substrate by sucking the substrate with a nozzle and holding the front of the chip with a pin, and then reflow soldering is performed. With the help of solder paste, the electrical connection between the pad and the substrate is achieved, and the chip is also fixed on the substrate.

[0003] At present, the structure of the flip-chip LED chip basically includes a substrate 1, an epitaxial layer 2, a current blocking layer 3, a transparent conductive layer 4, a P-type electrode 5, an N-type electrode 6, a passivation layer 7 and a pad 8, wherein the epitaxial layer 2 includes an N-type semiconductor layer 21, a multi-quantum well layer 22 and a P-type semiconductor layer 23, and the pad 8 includes a P-type pad 81 and an N-type pad 82. Figure 1 During the packaging and die bonding process of the flip-chip LED chip, the ejector pin will push against the passivation layer 7 on the front of the LED chip. The passivation layer 7 is mostly made of brittle materials and is easily broken by the ejector pin, causing the transparent conductive layer 4 and the epitaxial layer 2 to be easily damaged, resulting in leakage, and deteriorating the reliability of the flip-chip LED chip. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide an anti-ejection pin flip-chip LED chip and a preparation method thereof, which are used to solve the problem of ejection pins breaking the chip structure during flip-chip LED chip packaging and solid crystal bonding, thereby reducing the possibility of chip damage causing leakage, and effectively avoiding the leakage problem caused by the connection between P-type electrodes and N-type electrodes due to solder paste overflow.

[0005] In order to solve the above technical problems, the first aspect of the present invention provides a flip-chip LED chip with anti-ejection pin, comprising a substrate and an epitaxial layer stacked in sequence; The epitaxial layer is provided with a groove, an N-type electrode is provided in the groove, a current blocking layer and a transparent conductive layer are further provided on the epitaxial layer, the transparent conductive layer covers the current blocking layer and exposes the groove, a P-type electrode, a passivation layer and a pad are provided on the transparent conductive layer, the passivation layer covers the P-type electrode and the groove, the pad includes a P-type pad and an N-type pad, the P-type pad and the N-type pad penetrate the passivation layer and are electrically connected to the corresponding P-type electrode and N-type electrode; The anti-push-pin flip-chip LED chip further comprises an anti-push-pin layer in contact with the passivation layer, the anti-push-pin layer is arranged between the P-type pad and the N-type pad, and the anti-push-pin layer is composed of a plurality of metal layers arranged at a preset gap.

[0006] As an improvement of the above solution, the P-type electrode and the N-type electrode each include an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etching stop layer and an adhesion layer stacked in sequence, wherein: The ohmic contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, and the thickness of the ohmic contact layer is 5Å to 100Å; The reflective layer includes at least one of an Al layer and an Ag layer, and the thickness of the reflective layer is 100nm to 300nm; The coating layer comprises at least two of a Ti layer, a Ni layer, and a Pt layer, and the thickness of the coating layer is 100 nm to 1000 nm; The conductive layer includes at least one of an Au layer and a Cu layer, and the thickness of the conductive layer is 200nm to 1500nm; The etch stop layer comprises a Pt layer, and the thickness of the etch stop layer is 200nm-600nm; The adhesion layer includes a Ti layer, and the thickness of the adhesion layer is 30Å~150Å.

[0007] As an improvement of the above solution, the anti-throwing layer is arranged on the transparent conductive layer, and the passivation layer covers the anti-throwing layer.

[0008] As an improvement of the above solution, the anti-thrust layer includes an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etching barrier layer and an adhesion layer stacked in sequence, wherein: The ohmic contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, and the thickness of the ohmic contact layer is 5Å to 100Å; The reflective layer includes at least one of an Al layer and an Ag layer, and the thickness of the reflective layer is 100nm to 300nm; The coating layer comprises at least two of a Ti layer, a Ni layer, and a Pt layer, and the thickness of the coating layer is 100 nm to 1000 nm; The conductive layer includes at least one of an Au layer and a Cu layer, and the thickness of the conductive layer is 200nm to 1500nm; The etch stop layer comprises a Pt layer, and the thickness of the etch stop layer is 200nm-600nm; The adhesion layer includes a Ti layer, and the thickness of the adhesion layer is 30Å~150Å.

[0009] As an improvement of the above scheme, the anti-top-pin layer is arranged on the passivation layer, and a protective layer is also arranged on the passivation layer, the protective layer covers the anti-top-pin layer, and the P-type pad and the N-type pad penetrate the protective layer and the passivation layer and are electrically connected to the corresponding P-type electrode and N-type electrode.

[0010] As an improvement of the above solution, the anti-thrust layer includes a contact layer, a buffer layer and an adhesion layer stacked in sequence, wherein: The contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, and the thickness of the contact layer is 30Å to 500Å; The buffer layer includes at least one of an Au layer, an Al layer, and a Cu layer, and the thickness of the buffer layer is 200nm to 1500nm; The adhesion layer includes a Ti layer, and the thickness of the adhesion layer is 30Å~150Å; Alternatively, the anti-thrust layer comprises an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etching stop layer and an adhesion layer stacked in sequence, wherein: The ohmic contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, and the thickness of the ohmic contact layer is 5Å to 100Å; The reflective layer includes at least one of an Al layer and an Ag layer, and the thickness of the reflective layer is 100nm to 300nm; The coating layer comprises at least two of a Ti layer, a Ni layer, and a Pt layer, and the thickness of the coating layer is 100 nm to 1000 nm; The conductive layer includes at least one of an Au layer and a Cu layer, and the thickness of the conductive layer is 200nm to 1500nm; The etch stop layer comprises a Pt layer, and the thickness of the etch stop layer is 200nm-600nm; The adhesion layer includes a Ti layer, and the thickness of the adhesion layer is 30Å~150Å.

[0011] As an improvement of the above solution, the preset gap between adjacent metal layers is L1, and the width of the metal layer is L2, satisfying: L2=0.35L1~10L1.

[0012] As an improvement of the above solution, the distance between the anti-ejection layer and the P-type pad is a1, and the distance between the anti-ejection layer and the N-type pad is a2, satisfying: a1=a2=1.5L1~33L2; The width of the anti-thrust layer is b; the width of the P-type pad or the N-type pad is c, satisfying: b≤c.

[0013] As an improvement of the above solution, the protective layer includes at least one of a SiO2 layer and an Al2O3 layer, and the thickness of the protective layer is 200nm~1000nm.

[0014] The second aspect of the present invention further provides a method for preparing the anti-ejection flip-chip LED chip, comprising: Providing a substrate, preparing an epitaxial layer on the substrate, and etching the epitaxial layer to form a groove for arranging an N-type electrode; Preparing a current blocking layer and a transparent conductive layer on the epitaxial layer, so that the transparent conductive layer covers the current blocking layer and leaks out of the groove; Preparing a P-type electrode on the transparent conductive layer and preparing an N-type electrode in the groove; preparing a passivation layer on the transparent conductive layer; Preparing an anti-thrust layer on the transparent conductive layer or the passivation layer, so that the anti-thrust layer and the passivation layer are in contact with each other; Etching the passivation layer until the P-type electrode and the N-type electrode are exposed to form a P-type through hole and an N-type through hole; Preparing a P-type pad and an N-type pad at the upper ends of the P-type through hole and the N-type through hole, and electrically connecting the P-type pad and the N-type pad to the corresponding P-type electrode and the N-type electrode through the P-type through hole and the N-type through hole; Wherein, the anti-thrust layer is arranged between the P-type pad and the N-type pad, and the anti-thrust layer is composed of a plurality of metal layers arranged according to a preset gap.

[0015] The implementation of the present invention has the following beneficial effects: In the present invention, an anti-ejection layer in contact with the passivation layer is provided on the flip-chip LED chip, which can play a buffering and isolating role, maintain the structural integrity of the flip-chip LED chip, and reduce the possibility of leakage caused by the ejection pin breaking the chip structure during the packaging and solidification of the flip-chip LED chip. In addition, the anti-ejection layer can cooperate with the passivation layer to reduce the risk of chemical erosion, improve the electrical performance stability of the flip-chip LED chip, and improve the yield of the flip-chip LED chip.

[0016] Furthermore, the metal layer is used as the anti-ejection layer, and the ductility of the metal can play a buffering role to prevent the ejection pin from directly breaking the transparent conductive layer and the epitaxial layer. The metal layer is arranged in a manner according to a preset gap, so that after the passivation layer is broken by the ejection pin, the solder paste of the N-type pad and the P-type pad overflows and contacts the anti-ejection layer, the N-type pad and the P-type pad remain in an open circuit state, which will not cause a short circuit in the chip. At the same time, the heat can be evenly distributed, the occurrence of local overheating can be reduced, and the luminous brightness and uniformity can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 : A schematic diagram of the structure of a flip-chip LED chip in the prior art; Figure 2 : A schematic structural diagram of a flip-chip LED chip with an anti-ejection pin provided in the first embodiment of the present invention; Figure 3 : A schematic structural diagram of a flip-chip LED chip with anti-ejection pin provided in the second embodiment of the present invention; Figure 4 : A schematic structural diagram of the anti-thimble layer in the present invention; Figure 5 : A top view of a flip-chip LED chip with anti-ejection pin provided in the first embodiment of the present invention; Figure 6 : A top view of a flip-chip LED chip with anti-pop-off provided in the second embodiment of the present invention.

[0018] Figure numerals: 1-substrate; 2-epitaxial layer; 21-N-type semiconductor layer; 22-multi-quantum well layer; 23-P-type semiconductor layer; 3-current blocking layer; 4-transparent conductive layer; 5-P-type electrode; 6-N-type electrode; 7-passivation layer; 8-pad; 81-P-type pad; 82-N-type pad; 9-anti-top-pin layer; 91-metal layer; 10-protective layer. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail with specific embodiments below.

[0020] In order to solve the above problems, the present invention provides a flip-chip LED chip with an anti-ejection pin, such as Figure 2 and Figure 3 As shown, it includes a substrate 1 and an epitaxial layer 2 stacked in sequence; a groove is provided on the epitaxial layer 2, an N-type electrode 6 is provided in the groove, a current blocking layer 3 and a transparent conductive layer 4 are also provided on the epitaxial layer 2, the transparent conductive layer 4 covers the current blocking layer 3 and exposes the groove, a P-type electrode 5, a passivation layer 7 and a pad 8 are provided on the transparent conductive layer 4, the passivation layer 7 covers the P-type electrode 5 and the groove, the pad 8 includes a P-type pad 81 and an N-type pad 82, the P-type pad 81 and the N-type pad 82 penetrate the passivation layer 7 and are electrically connected to the corresponding P-type electrode 5 and N-type electrode 6, and the anti-top-pin flip-chip LED chip also includes an anti-top-pin layer 9 in contact with the passivation layer 7.

[0021] In the present invention, the anti-ejection layer 9 in contact with the passivation layer 7 is provided on the flip-chip LED chip to play a buffering and isolating role, maintain the structural integrity of the flip-chip LED chip, and reduce the possibility of leakage caused by the ejection pin breaking the chip structure during the packaging and solidification of the flip-chip LED chip. In addition, the anti-ejection layer 9 can cooperate with the passivation layer 7 to reduce the risk of chemical erosion and ensure the stability of the electrical performance of the flip-chip LED chip.

[0022] Specifically, the epitaxial layer 2 includes an N-type semiconductor layer 21, a multi-quantum well layer 22, and a P-type semiconductor layer 23 stacked in sequence, and the groove extends from the P-type semiconductor layer 23 to the N-type semiconductor layer 21, so that the N-type electrode 6 is disposed on the N-type semiconductor layer 21. The current blocking layer 3 and the transparent conductive layer 4 are disposed on the P-type semiconductor layer 23, and the transparent conductive layer 4 covers the current blocking layer 3 and exposes the groove.

[0023] It can be understood that the N-type semiconductor layer 21 can be an N-type GaN layer, an N-type AlGaN layer, or an N-type GaAs layer, but is not limited thereto; the multi-quantum well layer 22 can be an InGaN / GaN multi-quantum well layer, an InGaN / AlGaN multi-quantum well layer, or an AlGaN / AlGaN multi-quantum well layer, but is not limited thereto; the P-type semiconductor layer 23 can be a P-type GaN layer, a P-type AlGaN layer, or a P-type GaAs layer, but is not limited thereto; the current blocking layer 3 includes but is not limited to a SiO2 layer; and the transparent conductive layer 4 includes but is not limited to an ITO layer.

[0024] Optionally, the material of the passivation layer 7 is at least one of SiO2 and Ti3O5; the thickness of the passivation layer 7 is 1μm~6μm; more preferably, the passivation layer 7 is a DBR structure, and the passivation layer 7 is a multilayer structure obtained by repeatedly stacking SiO2 layers and Ti3O5 layers, which can not only play a role in insulation protection, but also serve as a high reflector to allow more light to pass through the chip surface. In some specific and preferred embodiments, the thickness of each SiO2 layer is 1 / 4 optical thickness~1 / 3 optical thickness, and the thickness of each Ti3O5 layer is 1 / 4 optical thickness~1 / 3 optical thickness.

[0025] Wherein, the P-type electrode 5 and the N-type electrode 6 are both metal electrodes, which can be a single-layer structure or a multi-layer structure. Preferably, the raw material composition of the P-type electrode 5 and the N-type electrode 6 is the same and both are multi-layer structures. Specifically, the P-type electrode 5 and the N-type electrode 6 each include an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etching barrier layer and an adhesion layer stacked in sequence. A low-resistance ohmic contact is formed between the ohmic contact layer and the semiconductor layer to ensure that the current can be efficiently conducted between the semiconductor and the electrode. The reflective layer arranged above it can not only reflect light back to the light-emitting surface, but also prevent the external environment from corroding and oxidizing the ohmic contact layer to a certain extent, thereby extending the service life of the ohmic contact layer and maintaining its good ohmic contact performance. The conductive layer is the key layer in the electrode responsible for transmitting current, ensuring that the current can be efficiently transmitted in the electrode, while the coating layer set between the reflective layer and the conductive layer plays a transition and protective role, preventing the metal in the reflective layer from directly contacting the metal in the conductive layer and then diffusing or reacting with each other, thereby protecting the performance of the reflective layer and the conductive layer so that they can work independently. Finally, an etching barrier layer and an adhesion layer are set on the conductive layer to protect the conductive layer and enhance the adhesion of the protective layer on the electrode.

[0026] Furthermore, the ohmic contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, which can effectively reduce the contact resistance between the electrode and the semiconductor, reduce the scattering and energy loss of carriers at the interface, and has good contact performance with the transparent conductive layer 4 and the N-type semiconductor layer 21. The reflective layer includes at least one of an Al layer and an Ag layer, which not only has good reflective performance, but also has excellent electrical and thermal conductivity. The coating layer includes at least two of a Ti layer, a Ni layer, and a Pt layer, which can protect the internal reflective layer, prevent the metal atoms in the reflective layer from migrating under the action of an electric field or other factors, and avoid electrical anomalies, short circuits, and other problems caused by metal migration, thereby improving the stability and service life of the electrode and the entire device; more preferably, the coating layer is a periodic structure with a period number of 2 to 5. While enhancing the mechanical properties of the coating layer, it can realize the regulation of functions such as reflection, absorption or scattering of light of a specific wavelength, and further optimize the optical performance of the chip. The conductive layer includes at least one of an Au layer and a Cu layer, has a low resistivity, can effectively transmit current, reduce energy loss during the conduction process, and ensure that the electrode can still stably transmit current under high current working conditions. The etching barrier layer includes a Pt layer; and the adhesion layer includes a Ti layer.

[0027] In some embodiments, the thickness of the ohmic contact layer is 5Å~100Å; the thickness of the reflective layer is 100nm~300nm; the thickness of the coating layer is 100nm~1000nm; the thickness of the conductive layer is 200nm~1500nm; the thickness of the etch stop layer is 200nm~600nm; and the thickness of the adhesion layer is 30Å~150Å.

[0028] Furthermore, the anti-thrust layer 9 is disposed between the P-type pad 81 and the N-type pad 82, and the anti-thrust layer 9 is composed of a plurality of metal layers 91 arranged at a preset gap, such as Figure 4~Figure 6 As shown. The metal layer 91 is used as the anti-ejection layer 9, and the ductility of the metal is used to play a buffering role to prevent the ejection pin from directly breaking the transparent conductive layer 4 and the epitaxial layer 2. The metal layer 91 is arranged in a gap arrangement. After the passivation layer 7 is broken by the ejection pin, the solder paste of the N-type pad 82 and the P-type pad 81 overflows and contacts the anti-ejection layer 9, it can also ensure that the N-type pad 82 and the P-type pad 81 remain in an open circuit state, which will not cause a short circuit in the chip. At the same time, the heat can be evenly distributed to reduce the occurrence of local overheating.

[0029] The length and width of the anti-ejection layer 9 need to be determined according to the size of the ejection pins used and the possible contact area of ​​the ejection pins on the flip-chip LED chip. Figure 4 The gap between adjacent metal layers 91 is L1, and the width of the metal layer 91 is L2, satisfying L2=0.35L1~10L1, so that the anti-ejection pin layer 9 has a good protection effect on the chip, preventing the ejection pin from contacting the sensitive area of ​​the chip during operation, and can effectively avoid short circuits between adjacent metal layers 91, optimize the light emission path, and improve the luminous uniformity and luminous efficiency of the flip chip. If L2 is less than 0.35L1, the metal layer 91 is relatively small and discontinuous in the entire anti-push pin layer 9, and the shading of the anti-push pin layer 9 is reduced. However, the structure of the anti-push pin layer 9 is relatively loose, and the metal layer 91 is prone to displacement or deformation, which affects the protective effect of the anti-push pin layer 9 and even causes leakage. It will also increase the opacity of the anti-push pin layer 9, and increase the probability of light scattering and absorption in the anti-push pin layer 9, thereby reducing the light extraction efficiency and optical uniformity of the chip. If L2 is greater than 10L1, the anti-push pin effect is good, but the width of the metal layer 91 is relatively wide, which will cause a certain degree of shading, thereby reducing the luminous efficiency. At the same time, the stresses between adjacent metal layers 91 may affect each other. During long-term use, the metal layer 91 is prone to fatigue, cracks and other problems. It may also cause heat to accumulate locally and cannot be effectively dissipated to the surrounding environment, which also causes the problem of chip overheating.

[0030] In some specific embodiments, L1=3μm~15μm, exemplarily 3μm, 5μm, 7μm, 9μm, 11μm, 13μm, 15μm, but not limited thereto; L2=5μm~30μm, exemplarily 5μm, 10μm, 15μm, 20μm, 25μm, 30μm, but not limited thereto.

[0031] For further information, see Figure 5 and Figure 6 , the distance between the anti-thrust layer 9 and the P-type pad 81 is a1, and the distance between the anti-thrust layer 9 and the N-type pad 82 is a2, satisfying a1=a2=1.5L2~33L2. If a1=a2<1.5L2, the distance between the anti-pickup layer 9 and the pad 8 is short, the area of ​​the anti-pickup layer 9 is large, and the anti-pickup effect is good, but the shading area is increased. When the chip is subjected to external force, the stress may be concentrated locally, which may easily lead to mechanical damage such as cracks and fractures in the anti-pickup layer 9 or the pad 8, and the anti-pickup layer 9 will have a strong reflection and absorption effect on the light near the pad 8, thereby reducing the luminous flux emitted from the front of the chip; if a1=a2>33L2, the distance between the anti-pickup layer 9 and the pad 8 is long, the area of ​​the anti-pickup layer 9 is small, the shading area is reduced, but the anti-pickup effect is reduced, and relative displacement or deformation is likely to occur between the anti-pickup layer 9 and the pad 8, resulting in leakage, and the heat may be unevenly distributed in the anti-pickup layer 9 during the conduction process, which is also prone to cause local overheating.

[0032] In some specific embodiments, a1=a2=20μm~100μm, exemplified by 20μm, 30μm, 40μm, 50μm, 60μm, 70μm, 80μm, 90μm, 100μm, but not limited thereto; b≥50μm.

[0033] Furthermore, the width of the anti-ejection layer 9 is b, and the width of the P-type pad 81 or the N-type pad 82 is c, satisfying b≤c. At this time, the light shielding area of ​​the anti-ejection layer 9 is small, which can play a better reflective role, resulting in improved luminous efficiency, but correspondingly, the anti-ejection effect will be weakened, and leakage will occur. In some specific embodiments, 50μm≤b≤c.

[0034] Specifically, the metal layer 91 in the anti-throwing layer 9 can be a single-layer structure or a multi-layer structure, and the raw material composition of the anti-throwing layer 9 can be the same as the raw material composition of the P-type electrode 5 and the N-type electrode 6, or it can be different from the raw material composition of the P-type electrode 5 and the N-type electrode 6.

[0035] In some specific and preferred embodiments, Figure 5As shown, the anti-ejection layer 9 is arranged on the transparent conductive layer 4, and the passivation layer 7 covers the anti-ejection layer 9. At this time, the anti-ejection layer 9 can directly protect the transparent conductive layer 4 below to avoid ejection damage, and the passivation layer 7 is covered thereon, which can help it further block the erosion of the internal structure by external water vapor and impurities. If the anti-ejection layer 9 is in direct contact with the outside world, it may suffer from wear and corrosion and fail in long-term use, and the transparent conductive layer 4 will be exposed to the harsh environment quickly, reducing the life of the flip-chip LED chip. Moreover, the formed layer structure is simple, which simplifies the production difficulty to a certain extent.

[0036] More preferably, the raw material composition of the anti-top-pin layer 9 is the same as the raw material composition of the P-type electrode 5 and the N-type electrode 6, that is, the anti-top-pin layer 9 is a multilayer structure, including an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etching barrier layer, and an adhesion layer stacked in sequence, wherein the ohmic contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer; the reflective layer includes at least one of an Al layer and an Ag layer; the coating layer includes at least two of a Ti layer, a Ni layer, and a Pt layer, more preferably, the coating layer is a periodic structure with a period number of 2 to 5; the conductive layer includes at least one of an Au layer and a Cu layer; the etching barrier layer includes a Pt layer; and the adhesion layer includes a Ti layer. At this time, the passivation layer 7 is in direct contact with the ejector pin, and the anti-ejector layer 9 has good adhesion on the transparent conductive layer 4. The overall structure and performance are consistent. When facing the ejector pin operation, it can more effectively resist the pressure of the ejector pin, reduce the risk of being injured or punctured, and protect the circuit structure and functional integrity inside the chip. Combined with the metal ductility in the anti-ejector layer 9, the flip-chip LED chip will not break under the action of the ejector pin, thereby protecting the layer structure below the anti-ejector layer 9 and avoiding leakage. It can be understood that the anti-ejector layer 9 and the P-type electrode 5 and N-type electrode 6 can be completed in the same process step.

[0037] Optionally, the thickness of the ohmic contact layer is 5Å~100Å; the thickness of the reflective layer is 100nm~300nm; the thickness of the coating layer is 100nm~1000nm; the thickness of the conductive layer is 200nm~1500nm; the thickness of the etching stop layer is 200nm~600nm; and the thickness of the adhesion layer is 30Å~150Å.

[0038] In other specific and preferred embodiments, Figure 6As shown, the anti-ejection layer 9 is arranged on the passivation layer 7, and a protective layer 10 is also arranged on the passivation layer 7, and the protective layer 10 covers the anti-ejection layer 9, and the P-type pad 81 and the N-type pad 82 penetrate the protective layer 10 and the passivation layer 7 and are electrically connected to the corresponding P-type electrode 5 and the N-type electrode 6. At this time, the passivation layer 7 provides basic protection for the transparent conductive layer 4 to block chemical corrosion, while the anti-ejection layer 9 specifically prevents physical damage caused by the ejection operation, and the outermost protective layer 10 further isolates the external mechanical friction and chemical pollution. The multi-layer protection synergy can provide a more lasting and comprehensive protection effect, reducing the probability of chip failure due to various damages. In addition, the anti-push layer 9 is located on the passivation layer 7 and will not cause shading problems, so the luminous efficiency of the flip-chip LED chip will be correspondingly improved. However, compared with the anti-push layer 9 being arranged on the transparent conductive layer 4, the passivation layer 7 is relatively easy to be damaged, resulting in damage to the transparent conductive layer 4 and the epitaxial layer 2, thereby causing the leakage rate of the flip-chip LED chip to increase.

[0039] Optionally, the raw material composition of the anti-ejection layer 9 is different from that of the P-type electrode 5 and the N-type electrode 6, and the anti-ejection layer 9 includes a contact layer, a buffer layer and an adhesion layer stacked in sequence. At this time, the adhesion layer contacts the ejection pin through the protective layer 10, and can use its good adhesion properties to ensure close fit with the ejection pin, and use its own elasticity and adhesion to perform preliminary buffering, protect the buffer layer and the contact layer, and prevent delamination and peeling between the layers. The subsequent force is further dispersed through the buffer layer and transmitted to the contact layer, effectively reducing the external force on the passivation layer 7, and having a good protective effect on the flip-chip LED chip.

[0040] Among them, the contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, has strong adhesion on the passivation layer 7, and exhibits a certain mechanical strength, thereby protecting the passivation layer 7; the buffer layer includes at least one of an Au layer, an Al layer, and a Cu layer, which can effectively absorb and disperse pressure; the adhesion layer includes a Ti layer, which enhances the adhesion between the protective layer 10 and the anti-throwing layer 9, and also has good corrosion resistance, which can prevent external chemicals from corroding the anti-throwing layer 9 to a certain extent, thereby ensuring the long-term stability of the anti-throwing layer 9.

[0041] Furthermore, the thickness of the contact layer is 30Å~500Å; the thickness of the buffer layer is 200nm~1500nm; and the thickness of the adhesion layer is 30Å~150Å.

[0042] Optionally, the material composition of the anti-ejection layer 9 is the same as that of the P-type electrode 5 and the N-type electrode 6. At this time, the structure of the anti-ejection layer 9 contains a reflective layer, which can form an ODR reflection with the underlying passivation layer 7, thereby further improving the luminous efficiency of the flip-chip LED chip.

[0043] Preferably, the protective layer 10 includes at least one of a SiO2 layer and an Al2O3 layer, has excellent wear resistance, hardness and insulation, can effectively resist the force and wear of the ejector pin, and has high transparency and will not affect the emission of light inside the chip.

[0044] Further, the thickness of the protective layer 10 is 200 nm to 1000 nm, and exemplary thicknesses are 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, and 1000 nm, but are not limited thereto.

[0045] There are many embodiments for setting the anti-thrust layer 9, for example Figure 2 In the first embodiment provided, the anti-thrust layer 9 is disposed on the transparent conductive layer 4, and the passivation layer 7 covers the anti-thrust layer 9; Figure 3 In the second embodiment provided, the anti-top-pin layer 9 is arranged on the passivation layer 7, and a protective layer 10 is also arranged on the passivation layer 7, the protective layer 10 covers the anti-top-pin layer 9, and the P-type pad 81 and the N-type pad 82 penetrate the protective layer 10 and the passivation layer 7 and are electrically connected to the corresponding P-type electrode 5 and the N-type electrode 6.

[0046] The present invention will be further described below with specific embodiments: First embodiment This embodiment provides a flip-chip LED chip that is anti-pop-off. Figure 2 and Figure 5 As shown, it includes a substrate 1 and an epitaxial layer 2 stacked in sequence; A groove is provided on the epitaxial layer 2, and an N-type electrode 6 is provided in the groove. A current blocking layer 3 and a transparent conductive layer 4 are also provided on the epitaxial layer 2, and the transparent conductive layer 4 covers the current blocking layer 3 and exposes the groove. A P-type electrode 5, a passivation layer 7 and a pad 8 are provided on the transparent conductive layer 4, and the passivation layer 7 covers the P-type electrode 5 and the groove. The pad 8 includes a P-type pad 81 and an N-type pad 82, and the P-type pad 81 and the N-type pad 82 penetrate the passivation layer 7 and are electrically connected to the corresponding P-type electrode 5 and N-type electrode 6.

[0047] The P-type electrode 5 and the N-type electrode 6 both include an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etch barrier layer and an adhesion layer stacked in sequence, wherein the ohmic contact layer is a Cr layer, the reflective layer is an Al layer, the coating layer is a Ti layer / Pt layer / Ti layer / Pt layer, the conductive layer is an Au layer, the etch barrier layer is a Pt layer, and the adhesion layer is a Ti layer, that is, the P-type electrode 5 and the N-type electrode 6 are both Cr layer / Al layer / Ti layer / Pt layer / Ti layer / Pt layer / Au layer / Pt layer / Ti layer stacked in sequence from bottom to top, with thicknesses of 30Å / 100nm / 100nm / 200nm / 100nm / 200nm / 500nm / 300nm / 50Å, respectively.

[0048] An anti-top-pin layer 9 is also provided on the transparent conductive layer 4. The anti-top-pin layer 9 is provided between the P-type pad 81 and the N-type pad 82. The passivation layer 7 covers the anti-top-pin layer 9. The anti-top-pin layer 9 is composed of a plurality of metal layers 91 arranged according to a preset gap, wherein the gap between adjacent metal layers 91 is L1, and the width of the metal layer 91 is L2, L1=7μm, L2=10μm; the distance between the anti-top-pin layer 9 and the P-type pad 81 is a1, and the distance between the anti-top-pin layer 9 and the N-type pad 82 is a2, a1=a2=20μm; the width of the anti-top-pin layer 9 is b, and the width of the P-type pad 81 or the N-type pad 82 is c, b=c.

[0049] The structure of the anti-throwing layer 9 is the same as that of the P-type electrode 5 and the N-type electrode 6, including an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etching barrier layer and an adhesion layer stacked in sequence, wherein the ohmic contact layer is a Cr layer, the reflective layer is an Al layer, the coating layer is a Ti layer / Pt layer / Ti layer / Pt layer, the conductive layer is an Au layer, the etching barrier layer is a Pt layer, and the adhesion layer is a Ti layer, that is, the anti-throwing layer 9 is a Cr layer / Al layer / Ti layer / Pt layer / Ti layer / Pt layer / Au layer / Pt layer / Ti layer stacked in sequence from bottom to top, with thicknesses of 30Å / 100nm / 100nm / 200nm / 100nm / 200nm / 500nm / 300nm / 50Å, respectively.

[0050] Accordingly, the method for preparing the anti-ejection flip-chip LED chip comprises: (1) providing a substrate 1, preparing an epitaxial layer 2 on the substrate 1, and etching the epitaxial layer 2 to form a groove for arranging an N-type electrode 6; Preferably, the substrate 1 may be a sapphire substrate, a GaAs substrate, a silicon substrate or a SiC substrate, but is not limited thereto.

[0051] Furthermore, the epitaxial layer 2 includes an N-type semiconductor layer 21, a multi-quantum well layer 22 and a P-type semiconductor layer 23 arranged in sequence, and is etched downward from the surface of the P-type semiconductor layer 23 to the N-type semiconductor layer 21 to form a groove, and the etching includes but is not limited to dry etching.

[0052] (2) preparing a current blocking layer 3 and a transparent conductive layer 4 on the epitaxial layer 2, so that the transparent conductive layer 4 covers the current blocking layer 3 and leaks out of the groove; Specifically, a current blocking layer 3 and a transparent conductive layer 4 are provided on the P-type semiconductor layer 23, including: (21) depositing the material of the current blocking layer 3 on the P-type semiconductor layer 23, and then preparing the current blocking layer 3 through photolithography and etching processes, and leaking out the groove; Optionally, the thickness of the current blocking layer 3 is determined according to actual conditions, and the present invention does not specifically limit this. The material of the current blocking layer 3 is deposited by a plasma enhanced chemical vapor deposition (PECVD) process, and the etching process includes but is not limited to wet etching.

[0053] (22) depositing the material of the transparent conductive layer 4 on the P-type semiconductor layer 23 and the current blocking layer 3, and then preparing the transparent conductive layer 4 through photolithography and etching processes, and leaking the groove; Optionally, the material of the current blocking layer 3 is deposited by a PECVD process, and the etching process includes but is not limited to wet etching.

[0054] (3) preparing a P-type electrode 5 on the transparent conductive layer 4 and preparing an N-type electrode 6 in the groove; Optionally, the P-type electrode 5 and the N-type electrode 6 can be prepared by using a yellow light process and a coating process.

[0055] It can be understood that the process of forming the groove can also be carried out in this step, that is, etching downward from the surface of the transparent conductive layer 4 to leak out the N-type semiconductor layer 21 to form a groove, and then setting the P-type electrode 5 and the N-type electrode 6 on the transparent conductive layer 4 and in the formed groove respectively. The P-type electrode 5 and the N-type electrode 6 can be formed using the same process or in two steps using two processes. The present invention is not limited to this, and any corresponding structural implementation form is within the protection scope of the present invention.

[0056] (4) Preparing an anti-thrust layer 9 on the transparent conductive layer 4; Preferably, the anti-thrust layer 9 is located between the P-type electrode 5 and the N-type electrode 6 , and the anti-thrust layer 9 is composed of a plurality of metal layers 91 arranged at preset intervals, and can be prepared by a yellow light process and a coating process.

[0057] (5) preparing a passivation layer 7 on the transparent conductive layer 4; Specifically, the material of the passivation layer 7 is deposited on the transparent conductive layer 4 and the anti-thrust layer 9 to prepare the passivation layer 7 covering the anti-thrust layer 9. It can be understood that the deposition process of the passivation layer 7 includes but is not limited to physical vapor deposition (PVD).

[0058] (6) Etching the passivation layer 7 until the P-type electrode 5 and the N-type electrode 6 are exposed, thereby forming a P-type through hole and an N-type through hole; It can be understood that the P-type through hole and the N-type through hole can be prepared by photolithography and etching processes, wherein the etching process includes but is not limited to dry etching.

[0059] (7) Preparing a P-type pad 81 and an N-type pad 82 at the P-type through hole and the N-type through hole, and electrically connecting the P-type pad 81 and the N-type pad 82 to the corresponding P-type electrode 5 and the N-type electrode 6 through the P-type through hole and the N-type through hole.

[0060] Specifically, a P-type pad 81 and an N-type pad 82 are prepared on the passivation layer 7, that is, materials of the P-type pad 81 and the N-type pad 82 are plated at positions corresponding to the P-type through holes and the N-type through holes on the protective layer 10 to form the P-type pad 81 and the N-type pad 82, preferably prepared by a yellow light process and a coating process.

[0061] Second embodiment This embodiment provides a flip-chip LED chip that is anti-pop-off. Figure 3 and Figure 6 As shown, it includes a substrate 1 and an epitaxial layer 2 stacked in sequence; A groove is provided on the epitaxial layer 2, and an N-type electrode 6 is provided in the groove. A current blocking layer 3 and a transparent conductive layer 4 are also provided on the epitaxial layer 2, and the transparent conductive layer 4 covers the current blocking layer 3 and exposes the groove. A P-type electrode 5, a passivation layer 7 and a pad 8 are provided on the transparent conductive layer 4, and the passivation layer 7 covers the P-type electrode 5 and the groove. The pad 8 includes a P-type pad 81 and an N-type pad 82.

[0062] The P-type electrode 5 and the N-type electrode 6 both include an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etch barrier layer and an adhesion layer stacked in sequence, wherein the ohmic contact layer is a Cr layer, the reflective layer is an Al layer, the coating layer is a Ti layer / Pt layer / Ti layer / Pt layer, the conductive layer is an Au layer, the etch barrier layer is a Pt layer, and the adhesion layer is a Ti layer, that is, the P-type electrode 5 and the N-type electrode 6 are both Cr layer / Al layer / Ti layer / Pt layer / Ti layer / Pt layer / Au layer / Pt layer / Ti layer stacked in sequence from bottom to top, with thicknesses of 30Å / 100nm / 100nm / 200nm / 100nm / 200nm / 500nm / 300nm / 50Å, respectively.

[0063] An anti-top-pin layer 9 and a protective layer 10 are provided on the passivation layer 7, the anti-top-pin layer 9 is provided between the P-type pad 81 and the N-type pad 82, the protective layer 10 covers the anti-top-pin layer 9, the P-type pad 81 and the N-type pad 82 penetrate the protective layer 10 and the passivation layer 7 and are electrically connected to the corresponding P-type electrode 5 and the N-type electrode 6, the anti-top-pin layer 9 is composed of a plurality of metal layers 91 arranged according to a preset gap, wherein the gap between adjacent metal layers 91 is L1, the width of the metal layer 91 is L2, L1=7μm, L2=10μm; the distance between the anti-top-pin layer 9 and the P-type pad 81 is a1, the distance between the anti-top-pin layer 9 and the N-type pad 82 is a2, a1=a2=20μm; the width of the anti-top-pin layer 9 is b, the width of the P-type pad 81 or the N-type pad 82 is c, b=c.

[0064] The structure of the anti-throwing layer 9 is different from that of the P-type electrode 5 and the N-type electrode 6, and includes a contact layer, a buffer layer and an adhesion layer stacked in sequence, wherein the contact layer is a Cr layer, the buffer layer is an Al layer / Cu layer / Au layer, and the adhesion layer is a Ti layer, that is, the anti-throwing layer 9 is a Cr layer / Al layer / Cu layer / Au layer / Ti layer stacked in sequence on the passivation layer 7, with thicknesses of 50Å / 200nm / 300nm / 300nm / 50Å, respectively.

[0065] Accordingly, the method for preparing the anti-ejection flip-chip LED chip comprises: (1) providing a substrate 1, preparing an epitaxial layer 2 on the substrate 1, and etching the epitaxial layer 2 to form a groove for arranging an N-type electrode 6; Preferably, the substrate 1 may be a sapphire substrate, a GaAs substrate, a silicon substrate or a SiC substrate, but is not limited thereto.

[0066] Furthermore, the epitaxial layer 2 includes an N-type semiconductor layer 21, a multi-quantum well layer 22 and a P-type semiconductor layer 23 arranged in sequence, and is etched downward from the surface of the P-type semiconductor layer 23 to the N-type semiconductor layer 21 to form a groove, and the etching includes but is not limited to dry etching.

[0067] (2) preparing a current blocking layer 3 and a transparent conductive layer 4 on the epitaxial layer 2, so that the transparent conductive layer 4 covers the current blocking layer 3 and leaks out of the groove; Specifically, a current blocking layer 3 and a transparent conductive layer 4 are provided on the P-type semiconductor layer 23, including: (21) depositing the material of the current blocking layer 3 on the P-type semiconductor layer 23, and then preparing the current blocking layer 3 through photolithography and etching processes, and leaking the groove; Optionally, the thickness of the current blocking layer 3 is determined according to actual conditions, and the present invention does not specifically limit this. The material of the current blocking layer 3 is deposited by a PECVD process, and the etching process includes but is not limited to wet etching.

[0068] (22) depositing the material of the transparent conductive layer 4 on the P-type semiconductor layer 23 and the current blocking layer 3, and then preparing the transparent conductive layer 4 through photolithography and etching processes, and leaking the groove; Optionally, the material of the current blocking layer 3 is deposited by a PECVD process, and the etching process includes but is not limited to wet etching.

[0069] (3) preparing a P-type electrode 5 on the transparent conductive layer 4 and preparing an N-type electrode 6 in the groove; Optionally, the P-type electrode 5 and the N-type electrode 6 can be prepared by using a yellow light process and a coating process.

[0070] It can be understood that the process of forming the groove can also be carried out in this step, that is, etching downward from the surface of the transparent conductive layer 4 to leak out the N-type semiconductor layer 21 to form a groove, and then setting the P-type electrode 5 and the N-type electrode 6 on the transparent conductive layer 4 and in the formed groove respectively. The P-type electrode 5 and the N-type electrode 6 can be formed using the same process or in two steps using two processes. The present invention is not limited to this, and any corresponding structural implementation form is within the protection scope of the present invention.

[0071] (4) preparing a passivation layer 7 on the transparent conductive layer 4; Specifically, the material of the passivation layer 7 is deposited on the transparent conductive layer 4 to prepare the passivation layer 7. It can be understood that the deposition process of the passivation layer 7 includes but is not limited to PVD.

[0072] (5) Preparing an anti-thrust layer 9 and a protective layer 10 on the passivation layer 7; Specifically include: (51) Preparing an anti-thrust layer 9 on the passivation layer 7; Preferably, the anti-thrust layer 9 is located between the P-type electrode 5 and the N-type electrode 6 , and the anti-thrust layer 9 is composed of a plurality of metal layers 91 arranged at preset intervals, and can be prepared by a yellow light process and a coating process.

[0073] (52) depositing a protective layer 10 on the passivation layer 7 and the anti-thrust layer 9; Specifically, the material of the protection layer 10 is deposited on the passivation layer 7 and the anti-thrust layer 9, and the deposition process includes but is not limited to PECVD.

[0074] (6) Etching the passivation layer 7 and the anti-thrust layer 9 until the P-type electrode 5 and the N-type electrode 6 are exposed, thereby forming a P-type through hole and an N-type through hole; Preferably, the P-type through hole and the N-type through hole can be prepared by a photolithography process and an etching process, wherein the etching process includes but is not limited to dry etching.

[0075] (7) Preparing a P-type pad 81 and an N-type pad 82 at the P-type through hole and the N-type through hole, and electrically connecting the P-type pad 81 and the N-type pad 82 to the corresponding P-type electrode 5 and the N-type electrode 6 through the P-type through hole and the N-type through hole.

[0076] Specifically, a P-type pad 81 and an N-type pad 82 are prepared on the protective layer 10, that is, materials of the P-type pad 81 and the N-type pad 82 are plated at positions corresponding to the P-type through holes and the N-type through holes on the protective layer 10 to form the P-type pad 81 and the N-type pad 82, preferably prepared by a yellow light process and a coating process.

[0077] Third embodiment This embodiment provides a flip-chip LED chip with an anti-pop-off feature, which is basically the same as the first embodiment, except that: The gap between adjacent metal layers 91 is L1, and the width of the metal layer 91 is L2, where L1=7 μm and L2=15 μm.

[0078] Fourth embodiment This embodiment provides a flip-chip LED chip with an anti-pop-off feature, which is basically the same as the first embodiment, except that: The gap between adjacent metal layers 91 is L1, and the width of the metal layer 91 is L2, where L1 = 12 μm and L2 = 10 μm.

[0079] Fifth embodiment This embodiment provides a flip-chip LED chip with an anti-pop-off feature, which is basically the same as the first embodiment, except that: The distance between the anti-thrust layer 9 and the P-type pad 81 is a1, and the distance between the anti-thrust layer 9 and the N-type pad 82 is a2, where a1=a2=40 μm.

[0080] Sixth embodiment This embodiment provides a flip-chip LED chip with an anti-pop-off feature, which is basically the same as the first embodiment, except that: The width of the anti-thrust layer 9 is b, the width of the P-type pad 81 or the N-type pad 82 is c, and cb=30 μm.

[0081] Seventh embodiment This embodiment provides a flip-chip LED chip with an anti-pop-off feature, which is basically the same as the second embodiment, except that: The structure of the anti-top-pin layer 9 is the same as that of the P-type electrode 5 and the N-type electrode 6. The anti-top-pin layer 9 includes an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etching barrier layer and an adhesion layer stacked in sequence, wherein the ohmic contact layer is a Cr layer, the reflective layer is an Al layer, the coating layer is a Ti layer / Pt layer / Ti layer / Pt layer, the conductive layer is an Au layer, the etching barrier layer is a Au / Pt layer, and the adhesion layer is a Ti layer, that is, the anti-top-pin layer 9 is a Cr layer / Al layer / Ti layer / Pt layer / Ti layer / Pt layer / Au layer / Pt layer / Ti layer stacked in sequence from bottom to top, with thicknesses of 30Å / 100nm / 100nm / 200nm / 100nm / 200nm / 500nm / 300nm / 50Å, respectively.

[0082] The first comparison This comparative example provides a flip-chip LED chip with an anti-pop-off feature, which is basically the same as the first embodiment, except that: The flip-chip LED chip does not contain the anti-thrust layer 9, and the structure is as follows Figure 1 shown.

[0083] Performance Testing The leakage rate and luminous efficiency of the anti-ejection flip-chip LED chips obtained in the embodiment and the comparative example were tested. The test results are shown in Table 1 below, where the luminous efficiency was calculated based on the first comparative example.

[0084] Table 1 Performance test results of examples and comparative examples

[0085] From the above results, it can be seen that the anti-ejection layer in contact with the passivation layer on the flip-chip LED chip can play a buffering and isolating role, improve its luminous efficiency, and reduce the possibility of leakage caused by the ejection pin breaking the chip structure during the packaging and solidification of the flip-chip LED chip. In addition, the anti-ejection layer is composed of several metal layers arranged according to a preset gap, which can further reduce the leakage rate of the flip-chip LED chip.

[0086] The above disclosure is only a preferred embodiment of the present invention, which certainly cannot be used to limit the scope of the present invention. Therefore, equivalent changes made according to the claims of the present invention are still within the scope of the present invention.

Claims

1. A flip-chip LED chip with an anti-ejection feature, characterized in that: comprising a substrate and an epitaxial layer stacked in sequence; The epitaxial layer is provided with a groove, an N-type electrode is provided in the groove, a current blocking layer and a transparent conductive layer are further provided on the epitaxial layer, the transparent conductive layer covers the current blocking layer and exposes the groove, a P-type electrode, a passivation layer and a pad are provided on the transparent conductive layer, the passivation layer covers the P-type electrode and the groove, the pad includes a P-type pad and an N-type pad, the P-type pad and the N-type pad penetrate the passivation layer and are electrically connected to the corresponding P-type electrode and N-type electrode; The anti-push-pin flip-chip LED chip further comprises an anti-push-pin layer in contact with the passivation layer, the anti-push-pin layer is arranged between the P-type pad and the N-type pad, and the anti-push-pin layer is composed of a plurality of metal layers arranged at a preset gap; The anti-thrust layer is disposed on the transparent conductive layer, and the passivation layer covers the anti-thrust layer; Alternatively, the anti-throwing layer is arranged on the passivation layer, a protective layer is further arranged on the passivation layer, the protective layer covers the anti-throwing layer, and the P-type pad and the N-type pad penetrate the protective layer and the passivation layer and are electrically connected to the corresponding P-type electrode and N-type electrode; The preset gap between adjacent metal layers is L1, and the width of the metal layer is L2, satisfying: L2=0.35L1~10L1.

2. The anti-thrust flip-chip LED chip according to claim 1, characterized in that: The P-type electrode and the N-type electrode each include an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etching stop layer and an adhesion layer stacked in sequence, wherein: The ohmic contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, and the thickness of the ohmic contact layer is 5Å to 100Å; The reflective layer includes at least one of an Al layer and an Ag layer, and the thickness of the reflective layer is 100nm to 300nm; The coating layer comprises at least two of a Ti layer, a Ni layer, and a Pt layer, and the thickness of the coating layer is 100 nm to 1000 nm; The conductive layer includes at least one of an Au layer and a Cu layer, and the thickness of the conductive layer is 200nm to 1500nm; The etch stop layer comprises a Pt layer, and the thickness of the etch stop layer is 200nm-600nm; The adhesion layer includes a Ti layer, and the thickness of the adhesion layer is 30Å~150Å.

3. The anti-thrust flip-chip LED chip according to claim 2, characterized in that: The anti-thrust layer includes an ohmic contact layer, a reflective layer, a coating layer, a conductive layer, an etching barrier layer and an adhesion layer stacked in sequence, wherein: The ohmic contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, and the thickness of the ohmic contact layer is 5Å to 100Å; The reflective layer includes at least one of an Al layer and an Ag layer, and the thickness of the reflective layer is 100nm to 300nm; The coating layer comprises at least two of a Ti layer, a Ni layer, and a Pt layer, and the thickness of the coating layer is 100 nm to 1000 nm; The conductive layer includes at least one of an Au layer and a Cu layer, and the thickness of the conductive layer is 200nm to 1500nm; The etch stop layer comprises a Pt layer, and the thickness of the etch stop layer is 200nm-600nm; The adhesion layer includes a Ti layer, and the thickness of the adhesion layer is 30Å~150Å.

4. The anti-thrust flip-chip LED chip according to claim 2, characterized in that: The anti-thrust layer includes a contact layer, a buffer layer and an adhesion layer stacked in sequence, wherein: The contact layer includes at least one of a Cr layer, a Ni layer, and a Ti layer, and the thickness of the contact layer is 30Å to 500Å; The buffer layer includes at least one of an Au layer, an Al layer, and a Cu layer, and the thickness of the buffer layer is 200nm to 1500nm; The adhesion layer includes a Ti layer, and the thickness of the adhesion layer is 30Å~150Å.

5. The anti-thrust flip-chip LED chip according to claim 1, characterized in that: The distance between the anti-ejection layer and the P-type pad is a1, and the distance between the anti-ejection layer and the N-type pad is a2, which satisfies: a1=a2=1.5L2~33L2; The width of the anti-thrust layer is b; the width of the P-type pad or the N-type pad is c, satisfying: b≤c.

6. The anti-thrust flip-chip LED chip according to claim 1, characterized in that: The protective layer includes at least one of a SiO2 layer and an Al2O3 layer, and the thickness of the protective layer is 200nm~1000nm.

7. A method for preparing a flip-chip LED chip with anti-ejection properties as claimed in any one of claims 1 to 6, characterized in that: include: Providing a substrate, preparing an epitaxial layer on the substrate, and etching the epitaxial layer to form a groove for arranging an N-type electrode; Preparing a current blocking layer and a transparent conductive layer on the epitaxial layer, so that the transparent conductive layer covers the current blocking layer and leaks out of the groove; Preparing a P-type electrode on the transparent conductive layer and preparing an N-type electrode in the groove; preparing a passivation layer on the transparent conductive layer; Preparing an anti-thrust layer on the transparent conductive layer or the passivation layer, so that the anti-thrust layer and the passivation layer are in contact with each other; Etching the passivation layer until the P-type electrode and the N-type electrode are exposed to form a P-type through hole and an N-type through hole; Preparing a P-type pad and an N-type pad at the upper ends of the P-type through hole and the N-type through hole, and electrically connecting the P-type pad and the N-type pad to the corresponding P-type electrode and the N-type electrode through the P-type through hole and the N-type through hole; Wherein, the anti-thrust layer is arranged between the P-type pad and the N-type pad, and the anti-thrust layer is composed of a plurality of metal layers arranged according to a preset gap.

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