Display panel and electronic equipment

Abstract

The embodiment of the invention provides a display panel and electronic equipment, and relates to the technical field of display. In the display panel, first wires are connected with a gate drive circuit and provide gate drive voltage for the gate drive circuit, and the first wires are located in at least two sub-frame areas. Compared with the prior art, the display panel has the advantages that the wire originally used for transmitting the power supply voltage signal in the frame area of the display panel is used as the first wire to provide the gate driving voltage, the wire for providing the gate driving voltage in the gate driving circuit can be canceled, the layout space of the gate driving circuit is further compressed, and the width of the frame area is reduced; the screen-to-body ratio of the display panel is further improved, the use experience of a user is improved, and the market competitiveness of a product is enhanced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and an electronic device. Background Art

[0002] Organic Light Emitting Diode (OLED) is considered to be the next generation of flat panel display technology after liquid crystal. It has many unique advantages such as self-luminescence, full solid state, light weight, flexibility, etc. As users' requirements for display continue to increase, the requirements for the screen-to-body ratio of display panels are also getting higher and higher. Summary of the invention

[0003] In order to overcome the technical problems mentioned in the above technical background, the present application provides a display panel and an electronic device.

[0004] In a first aspect of the present application, a display panel is provided, comprising:

[0005] substrate;

[0006] A first wiring, the first wiring is located at one side of the substrate, and the first wiring is located in a frame area of ​​the display panel;

[0007] A gate driving circuit, wherein the gate driving circuit is located in the border area;

[0008] The first routing line is connected to the gate driving circuit and is used to provide a gate driving voltage for the gate driving circuit, wherein the border area includes a plurality of sub-border areas, and the first routing line is located in at least two sub-border areas.

[0009] In a possible implementation of the present application, an orthographic projection of the first routing line on the substrate is outside an orthographic projection of the gate driving circuit on the substrate.

[0010] In a possible implementation of the present application, the display panel further includes a first area and a second area, the first area and the second area are both located in the frame area, and the first area is arranged around the display area of ​​the display panel.

[0011] At least part of the first wiring is located in the first area, and the gate driving circuit is located in the second area;

[0012] Preferably, the second area is located in the frame areas on two opposite sides of the display area, and the second area is located on a side of the first area facing the display area.

[0013] In a possible implementation of the present application, in the first area, the display panel includes a first dam structure and a second dam structure located on one side of the substrate, and the first dam structure and the second dam structure are arranged around a display area of ​​the display panel;

[0014] The orthographic projection shapes of the first dam structure and the second dam structure on the substrate include rings;

[0015] The first dam structure is located on a side of the second dam structure close to the display area;

[0016] An orthographic projection of at least part of the first trace on the substrate is located between an orthographic projection of the first dam structure and an orthographic projection of the second dam structure on the substrate.

[0017] In a possible implementation of the present application, the display panel further includes a second wiring, and the second wiring is located in the frame area;

[0018] The first wiring and the second wiring are insulated from each other, and the second wiring is electrically connected to an isolation structure in a display area of ​​the display panel;

[0019] Preferably, the display panel further comprises a light emitting device, wherein in a direction away from the substrate, the light emitting device comprises a first electrode, a light emitting material layer and a second electrode which are stacked, and at least part of the isolation structure is located between the light emitting devices, wherein the second electrode is electrically connected to the isolation structure around the light emitting device;

[0020] Preferably, the second wiring is used to transmit a first power supply voltage signal.

[0021] In a possible implementation of the present application, the display panel further includes a pixel defining layer, the pixel defining layer is located on one side of the substrate, and the isolation structure is located on a side of the pixel defining layer away from the substrate;

[0022] The pixel defining layer encloses a pixel opening on the substrate, the isolation structure encloses an isolation opening on the substrate, at least part of the light-emitting device is located in the pixel opening, and the orthographic projection of the pixel opening on the substrate is located within the orthographic projection of the isolation opening on the substrate.

[0023] In a possible implementation of the present application, the isolation structure includes a first isolation portion and a second isolation portion, and in a direction away from the substrate, the first isolation portion and the second isolation portion are stacked in sequence;

[0024] An orthographic projection of the first isolation portion on the substrate is located within an orthographic projection of the second isolation portion on the substrate.

[0025] In a possible implementation of the present application, the isolation structure further includes a third isolation portion, and in a direction away from the substrate, the third isolation portion, the first isolation portion, and the second isolation portion are stacked in sequence;

[0026] The orthographic projection of the first isolation portion on the substrate is located within the orthographic projection of the third isolation portion on the substrate;

[0027] Preferably, the material of the first isolation portion includes aluminum, silver or copper, and / or the material of the second isolation portion includes titanium or molybdenum, and / or the material of the third isolation portion includes molybdenum or titanium.

[0028] In a possible implementation of the present application, the display panel further includes a first encapsulation layer, the first encapsulation layer includes a plurality of encapsulation units, different encapsulation units are used to encapsulate light-emitting devices in different isolation openings, and two adjacent encapsulation units are disconnected on a side of the isolation structure away from the substrate;

[0029] Preferably, the packaging unit comprises an inorganic packaging unit.

[0030] In a possible implementation of the present application, the display panel further includes a second encapsulation layer;

[0031] The second encapsulation layer is located on a side of the first encapsulation layer away from the substrate, and the second encapsulation layer at least covers the first encapsulation layer;

[0032] Preferably, the second encapsulation layer has a flat surface on a side away from the substrate.

[0033] In a possible implementation of the present application, the display panel further includes a third encapsulation layer, and the third encapsulation layer is located on a side of the second encapsulation layer away from the substrate;

[0034] Preferably, the third encapsulation layer comprises an inorganic encapsulation layer, and the second encapsulation layer comprises an organic encapsulation layer;

[0035] Preferably, the third packaging layer covers a side of the first trace away from the substrate.

[0036] In a possible implementation of the present application, the display panel further includes a third wiring, the first wiring, the second wiring and the third wiring are insulated from each other, and the third wiring is electrically connected to a pixel circuit in the display panel and is used to transmit a second power supply voltage signal;

[0037] Preferably, the voltage value of the first power supply voltage signal is less than the voltage value of the second power supply voltage signal;

[0038] Preferably, the third wiring is located in the border area.

[0039] In a possible implementation of the present application, the display panel further includes:

[0040] A plurality of conductive layers, wherein the plurality of conductive layers are sequentially stacked and arranged between the substrate and the film layer where the light-emitting device is located, and an insulating layer is arranged between adjacent conductive layers;

[0041] Preferably, the display panel further comprises: an active layer;

[0042] The active layer includes a source region, a channel region and a drain region, the transistor in the pixel circuit includes a gate, a source and a drain formed by the conductive layer, the orthographic projection of the gate on the substrate overlaps the orthographic projection of the channel region on the substrate, the source is connected to the source region, and the drain is connected to the drain region;

[0043] Preferably, the first electrode is connected to the source or drain of the transistor;

[0044] Preferably, at least part of the first routing lines is arranged on the same layer as the second routing lines and the third routing lines.

[0045] In a possible implementation of the present application, the insulating layer includes a planarization layer, the number of the planarization layers is multiple, and the dam structure in the first region is disposed in the same layer as at least part of the planarization layer;

[0046] Preferably, at least a portion of the first wiring is arranged in the same layer as the conductive layer between adjacent planarization layers.

[0047] In a possible implementation of the present application, in a display area of ​​the display panel, a pixel row extends along a first direction, and a plurality of the pixel rows are distributed along a second direction, wherein the first direction and the second direction intersect;

[0048] The frame area includes a first sub-frame area, a second sub-frame area, a third sub-frame area and a fourth sub-frame area, wherein the first sub-frame area and the third sub-frame area are arranged opposite to each other in the second direction, and the second sub-frame area and the fourth sub-frame area are arranged opposite to each other in the first direction;

[0049] Preferably, the first routing line is distributed along the second sub-frame area, the third sub-frame area and the fourth sub-frame area, and distributed in a partial area of ​​the first sub-frame area; the second routing line and the third routing line are distributed in the first sub-frame area; the gate driving circuit is distributed in the second sub-frame area and the fourth sub-frame area;

[0050] Preferably, part of the first routing lines are distributed in the second sub-frame area, the third sub-frame area and the first area in the fourth sub-frame area;

[0051] Preferably, in the first sub-frame area, the display panel further includes a third area, and the third area is located on a side of the first area close to the display area;

[0052] Preferably, the second routing line, the third routing line and part of the first routing line are located in the third area;

[0053] Preferably, the second routing line, the third routing line and part of the first routing line are distributed along the first direction in the third area, the second routing line is located on opposite sides of the third routing line, and part of the first routing line is located on a side of the second routing line away from the third routing line.

[0054] In a possible implementation of the present application, the display panel further includes a first signal line, a second signal line, and a third signal line;

[0055] The first signal line is connected to the first routing line distributed in the third area via the first area, the second signal line is connected to the second routing line distributed in the third area via the first area, and the third signal line is connected to the third routing line distributed in the third area via the first area;

[0056] Preferably, the first signal line, the second signal line, the third signal line, the second routing line, the third routing line, and the first routing line distributed in the third area are arranged on the same layer.

[0057] In a possible implementation of the present application, the gate driving circuit includes a plurality of gate driving units, each of which includes a light emitting control subunit and two scanning subunits;

[0058] Preferably, the display panel further comprises connecting wires, and the first wires are electrically connected to the light emitting control subunit and the scanning subunit in each of the gate driving units through the connecting wires.

[0059] In a possible implementation of the present application, in a display area of ​​the display panel, a pixel row extends along a first direction, and a plurality of the pixel rows are distributed along a second direction, wherein the first direction and the second direction intersect;

[0060] The first wiring extending along the second direction provides a gate driving voltage to the gate driving unit through the connecting wiring;

[0061] Preferably, the connecting line extends along the first direction.

[0062] In a possible implementation of the present application, two adjacent gate driving units are connected to the first wiring through the same connecting wiring;

[0063] The orthographic projections of two adjacent gate driving units on the substrate do not overlap with the orthographic projection of the same connecting line on the substrate;

[0064] Preferably, the orthographic projection of the connecting wire on the substrate is located in a gap between the orthographic projections of two adjacent gate driving units on the substrate.

[0065] In a possible implementation of the present application, the gate drive voltage provided by the first wiring is a high-level gate drive voltage or a low-level gate drive voltage.

[0066] In a second aspect, the present application further provides an electronic device, the electronic device comprising the display panel of any one of the first aspects.

[0067] The present application provides a display panel and an electronic device, in which a first line and a gate driving circuit are located in a frame area, the first line is connected to the gate driving circuit, and provides a gate driving voltage for the gate driving circuit, the frame area includes a plurality of sub-frame areas, and the first line is located in at least two sub-frame areas. Compared with the related art, the line originally used for transmitting a power supply voltage signal in the frame area of ​​the display panel is used as the first line to provide a gate driving voltage, and the line providing the gate driving voltage in the gate driving circuit can be cancelled, thereby further compressing the layout space of the gate driving circuit and reducing the width of the frame area, further improving the screen-to-body ratio of the display panel, improving the user experience, and enhancing the market competitiveness of the product. BRIEF DESCRIPTION OF THE DRAWINGS

[0068] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0069] Figure 1 One of the schematic diagrams of regional distribution of the display panel provided by this embodiment is illustrated;

[0070] Figure 2 The first trace and gate drive circuit are shown in Figure 1 Distribution diagram of ;

[0071] Figure 3 Example Figure 2 A schematic diagram of a local cross section of the first region and the second region in the MM direction;

[0072] Figure 4 Example of a dam in Figure 1 One of the distribution diagrams in;

[0073] Figure 5 Example Figure 4 One of the schematic partial cross-sectional views of the first region in the MM direction;

[0074] Figure 6 Example Figure 4 The second schematic diagram of the local cross section of the first region in the MM direction;

[0075] Figure 7 The first trace, the second trace and the gate drive circuit are shown in FIG. Figure 1 Distribution diagram of ;

[0076] Figure 8 One of the schematic diagrams of the partial film layer structure of the display area is illustrated;

[0077] Fig. 9 The second schematic diagram of the partial film layer structure of the display area is illustrated;

[0078] Fig.10 The third schematic diagram of the partial film layer structure of the display area is illustrated;

[0079] Fig.11 The fourth schematic diagram of the partial film layer structure of the display area is illustrated;

[0080] Fig.12 The fifth schematic diagram of the partial film layer structure of the display area is illustrated;

[0081] Fig.13 The first trace, the second trace, the third trace and the gate drive circuit are illustrated in FIG. Figure 1 One of the distribution diagrams in;

[0082] Fig.14 The sixth schematic diagram of the partial film layer structure of the display area is illustrated;

[0083] Fig.15 Example Figure 4 The third schematic diagram of the local cross section of the first region in the MM direction;

[0084] Fig.16 The first trace, the second trace, the third trace and the gate drive circuit are illustrated in FIG. Figure 1 The second distribution diagram in ;

[0085] Fig.17 This example shows the signal line and Fig.16 Schematic diagram of the connection of the middle wiring;

[0086] Fig.18 The schematic diagram of the structure of the gate drive circuit is illustrated;

[0087] Fig.19 One of the connection diagrams of the first wiring and the gate driving unit is illustrated;

[0088] Fig. 20 The second schematic diagram of connection between the first wiring and the gate driving unit is illustrated.

[0089] Main icons: 1-display panel; 111-transistor; 1101-substrate; 1102-buffer layer; 1103-active layer; 1104-gate insulating layer; 1105-gate; 1106-source; 1107-drain; 1108-capacitor dielectric layer; 1109-interlayer insulating layer; 111-transistor; 1110-first capacitor electrode; 1111-second capacitor electrode; 1201-first routing line; 1202-second routing line; 1203-third routing line; 1204-first signal line; 1205-second signal line; 1206-third signal line; 1207-connecting routing line; 130-gate drive circuit; 131-gate drive unit; 1311-light-emitting control subunit; 1312-scanning subunit; 141- First dam structure; 142-second dam structure; 15-isolation structure; 151-isolation opening; 152-first isolation portion; 153-second isolation portion; 154-third isolation portion; 16-light-emitting device; 161-first electrode; 162-light-emitting material layer; 163-second electrode; 17-pixel defining layer; 171-pixel opening; 181-first encapsulation layer; 1811-encapsulation unit; 182-second encapsulation layer; 183-third encapsulation layer; 19-planarization layer; 10-display area; 20-border area; 201-first area; 202-second area; 203-third area; 210-first sub-border area; 220-second sub-border area; 230-third sub-border area; 240-fourth sub-border area; 40-pixel row. DETAILED DESCRIPTION

[0090] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0091] Hereinafter, although terms such as "first", "second", etc. may be used to describe various components, these components are not necessarily limited to the above terms. The above terms are only used to distinguish one component from another. It will also be understood that expressions used in the singular include plural expressions unless the expression in the singular has an obviously different meaning in the context.

[0092] In the description of the present application, it should be noted that the terms "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0093] In some display panels, in order to reduce the difficulty of the evaporation process of the light-emitting material, an isolation structure is arranged on the first insulating layer between the pixel openings. When the light-emitting material layer and the cathode layer are evaporated throughout the entire layer, the light-emitting material layer and the cathode layer between adjacent pixel openings can be disconnected at the position of the isolation structure. Through multiple evaporation and multiple etching processes, corresponding pixel unit film layers can be formed in the pixel openings corresponding to light-emitting devices of different colors, and different light-emitting devices are packaged using separate packaging units.

[0094] Patent PCT / CN2023 / 134518, patent 202310759370.2, patent 202310740412.8, patent 202310707209.0, patent 202311499823.9, and patent 202311346196.5 record relevant technical solutions of isolation structure and encapsulation layer, and their contents are incorporated into this application by reference for reference.

[0095] The inventors have found that the above-mentioned display panel can achieve pixel-level packaging by using a photolithography process, and at this time, the power supply voltage signal (for example, ELVSS) can be transmitted through the isolation structure. For example, the power supply voltage signal can be provided by connecting the conductive traces of the lower frame to the isolation structure of the display area. However, in this display panel, the winding originally designed in the frame area for transmitting the power supply voltage signal has no practical function, which will cause a waste of space in the frame area, which is not conducive to achieving a narrow frame design and an increase in the screen-to-body ratio.

[0096] In order to further narrow the border of the display panel, the inventor innovatively designed the following technical solution to solve the above technical problems. The specific implementation scheme of this application will be described in detail below in conjunction with the accompanying drawings. It should be noted that the defects in the above solutions in the prior art are the results obtained by the inventor after practice and careful research. Therefore, the discovery process of the above technical problems and the solutions proposed in this embodiment below for the above problems should all be the contributions made by the inventor to this application in the process of invention and creation, and should not be understood as technical contents known to those skilled in the art.

[0097] Please refer to Figure 1 , Figure 2 and Figure 3 , Figure 1 The schematic diagram of the regional distribution of the display panel provided by this embodiment is illustrated. Figure 1 is a top view, Figure 2 The first trace and gate drive circuit are shown in Figure 1 The distribution diagram of Figure 3 for Figure 2 A partial cross-sectional schematic diagram of the first area and the second area in the MM direction. In the present embodiment, exemplarily, the display panel 1 includes a display area 10 and a frame area 20, the frame area 20 is arranged around at least a portion of the display area 10, the display area 10 is used to display an image, and the frame area 20 can be set to provide various signal routings for the light-emitting devices in the display area 10 to provide electrical signals and arrange a gate drive circuit (Gate in panel, GIP circuit). Exemplarily, taking the shape of the display panel 1 as a rectangle as an example, the display area 10 can be a rectangle, the frame area 20 can be a rectangular ring surrounding the display area 10, and the frame area 20 can be formed by enclosing an upper frame area, a lower frame area, a left frame area and a right frame area. The frame area 20 may be located in a non-display area of ​​the display panel.

[0098] The display panel 1 includes a substrate 1101, a first wiring 1201 and a gate drive circuit 130, wherein the first wiring 1201 is located on one side of the substrate 1101, the first wiring 1201 is located in the frame area 20, and the gate drive circuit 130 is also located in the frame area 20. The first wiring 1201 is a wiring that at least partially surrounds the display area 10, the first wiring 1201 is connected to the gate drive circuit 130, and the first wiring 1201 provides a gate drive voltage for the gate drive circuit 130. The frame area 20 includes a plurality of sub-frame areas, and the first wiring 1201 is located in at least two sub-frame areas, wherein at least two of the plurality of sub-frame areas have different extension directions, and the plurality of sub-frame areas can be connected in sequence. In the present embodiment, the first wiring 1201 is a wiring originally used to transmit a power supply voltage signal (e.g., an ELVSS signal).

[0099] In the above structure, the wiring originally used to transmit the power supply voltage signal in the display panel border area 20 is used as the first wiring 1201 to provide the gate drive voltage, and the wiring providing the gate drive voltage in the gate drive circuit 130 can be cancelled. In this way, the layout space of the gate drive circuit 130 can be further compressed to reduce the width of the border area 20, further improve the screen-to-body ratio of the display panel 1, improve the user experience, and enhance the market competitiveness of the product.

[0100] Specifically, the orthographic projection of the first routing line 1201 on the substrate 1101 may not overlap with the orthographic projection of the gate driving circuit 130 on the substrate 1101 (that is, the orthographic projection of the first routing line 1201 on the substrate 1101 is outside the orthographic projection of the gate driving circuit 130 on the substrate 1101), and the orthographic projection of the first routing line 1201 on the substrate 1101 may also overlap with the orthographic projection of the gate driving circuit 130 on the substrate 1101.

[0101] Further, please refer again to Figure 1 and Figure 2 The display panel 1 further includes a first area 201 and a second area 202, both of which are located in the frame area 20, wherein the first area 201 can be arranged around the display area 10 of the display panel 1. At least part of the first wiring 1201 is located in the first area 201, and the gate driving circuit 130 is located in the second area 202. Optionally, in this embodiment, the second area 202 is located in the frame area 20 on opposite sides of the display area 10, and the second area 202 is located on the side of the first area 201 facing the display area 10.

[0102] Please refer to Figure 4 , Figure 5 and Figure 6 In the first area 201, the display panel includes a first dam structure 141 and a second dam structure 142 located on one side of the substrate 1101, and the first dam structure 141 and the second dam structure 142 are arranged around the display area 10. The orthographic projections of the first dam structure 141 and the second dam structure 142 on the substrate 1101 are annular, and the specific shape of the annular can be similar to the outline shape of the display area 10. For example, when the outline shape of the display area 10 is rectangular, the orthographic projections of the first dam structure 141 and the second dam structure 142 on the substrate 1101 are rectangular rings. The first dam structure 141 is located on the side of the second dam structure 142 close to the display area 10, that is, the first dam structure 141 is located on the inner side of the annular structure enclosed by the second dam structure 142. In this embodiment, the orthographic projections of at least part of the first wiring 1201 on the substrate 1101 are located between the orthographic projections of the first dam structure 141 and the second dam structure 142 on the substrate 1101.

[0103] In one possible implementation, Figure 5 As shown, the orthographic projection of the first wiring 1201 on the substrate 1101 may be located between the orthographic projections of the first dam structure 141 and the second dam structure 142 on the substrate 1101. In this case, the orthographic projection of the first wiring 1201 on the substrate 1101 does not overlap with the orthographic projections of the first dam structure 141 and the second dam structure 142 on the substrate 1101. In another possible implementation, as Figure 6 As shown, the orthographic projection of part of the first wiring 1201 on the substrate 1101 may be located between the orthographic projections of the first dam structure 141 and the second dam structure 142 on the substrate 1101. In this case, the orthographic projection of the first wiring 1201 on the substrate 1101 overlaps with the orthographic projections of the first dam structure 141 and the second dam structure 142 on the substrate 1101. In this embodiment, the first wiring 1201 is arranged in the first area 201 where the dam structure is located, which can save the wiring space of the first wiring 1201 in the border area 20, and is conducive to narrowing the border.

[0104] For further information, please refer to Figure 7 The display panel 1 also includes a second wiring 1202, the second wiring 1201 is located in the frame area 20, the first wiring 1201 and the second wiring 1202 are insulated from each other, and the second wiring 1202 is electrically connected to the isolation structure 15 distributed in the display area 10, wherein the isolation structure 15 is a conductive isolation structure.

[0105] Please refer to Figure 8 , Figure 8 Example Figure 7 Schematic diagram of a partial film layer structure of the middle display area 10, the display panel 1 includes a light-emitting device 16, in the direction away from the substrate 1101, the light-emitting device 16 includes a first electrode 161, a light-emitting material layer 162 and a second electrode 163 arranged in a stacked manner, at least part of the isolation structure 15 is located between the light-emitting devices 16, specifically, the isolation structure 15 is surrounded by an isolation opening 151 on the substrate 1101, at least part of the light-emitting device 16 can be located in the isolation opening 151, and the second electrode 163 is electrically connected to the isolation structure 15 around the light-emitting device 16. The second wiring 1202 is used to transmit a first power supply voltage signal (for example, an ELVSS signal). Exemplarily, the second wiring 1202 provides a first power supply voltage signal to the second electrode 163 of the light-emitting device 16 through the isolation structure 15.

[0106] In this embodiment, the isolation structure 15 is provided so that the light-emitting material layer 162 and the second electrode 163 can be respectively formed in different isolation openings 151 defined by the isolation structure 15 without the need for a fine metal mask, so that light-emitting devices 16 of different colors can be formed in different isolation openings 151, thereby reducing the manufacturing cost of the display panel. In addition, the isolation structure 15 can isolate the light-emitting material layer 162 and the second electrode 163 in the light-emitting device 16, so that different light-emitting devices 16 are independent of each other, so as to improve the crosstalk between adjacent light-emitting devices 16 and enhance the display effect. And the adjacent light-emitting devices 16 can be independently packaged to improve the packaging yield. At the same time, due to the existence of the isolation structure 15, the light-emitting material layer 162 and the second electrode 163 in the light-emitting device 16 of each color in the display panel 1 can be first prepared on the entire surface and then patterned, without the need for a fine metal mask, so as to save the manufacturing cost of the display panel. At least part of the isolation structure 15 can be located between adjacent light-emitting devices 16.

[0107] Further, please refer again to Figure 8 The display panel 1 further includes a pixel defining layer 17, which is located on one side of the substrate 1101, and the isolation structure 15 is located on the side of the pixel defining layer 17 away from the substrate 1101. The pixel defining layer 17 encloses a pixel opening 171 on the substrate 1101, and at least part of the light emitting device 16 is located in the pixel opening 171. The opening size of the pixel opening 171 is smaller than the opening size of the isolation opening 151, and the orthographic projection of the pixel opening 171 on the substrate 1101 is located within the orthographic projection of the isolation opening 151 on the substrate 1101. That is, the orthographic projection area of ​​the pixel opening 171 on the substrate 1101 is smaller than the orthographic projection area of ​​the isolation opening 151 on the substrate 1101.

[0108] Please refer to Fig. 9 In this embodiment, the isolation structure 15 includes a first isolation portion 152 and a second isolation portion 153. In a direction away from the substrate 1101, the first isolation portion 152 and the second isolation portion 153 are stacked in sequence, for example, the second electrode 163 of the light-emitting device 16 overlaps the first isolation portion 152. The orthographic projection of the first isolation portion 152 on the substrate 1101 is located within the orthographic projection of the second isolation portion 153 on the substrate 1101. Optionally, the orthographic projection area of ​​the first isolation portion 152 on the substrate 1101 is smaller than the orthographic projection area of ​​the second isolation portion 153 on the substrate 1101. The cross-section of the isolation structure 15 may be T-shaped. The first isolation portion 152 includes a conductive material. The first isolation portion 152 is electrically connected to the second electrode 163.

[0109] In this embodiment, please refer to Fig.10, the isolation structure 15 further includes a third isolation portion 154. In the direction away from the substrate 1101, the third isolation portion 154, the first isolation portion 152 and the second isolation portion 153 are stacked in sequence, for example, the second electrode 163 of the light-emitting device 16 is also overlapped with the third isolation portion 154. The orthographic projection of the first isolation portion 152 on the substrate 1101 is located within the orthographic projection of the third isolation portion 154 on the substrate 1101. Optionally, the orthographic projection area of ​​the first isolation portion 152 on the substrate 1101 is smaller than the orthographic projection area of ​​the third isolation portion 154 on the substrate 1101. In this embodiment, the orthographic projection area of ​​the third isolation portion 154 on the substrate 1101 is also smaller than the orthographic projection area of ​​the second isolation portion 153 on the substrate 1101. The cross section of the isolation structure 15 may be in an I-shape. At least one of the third isolation portion 154, the first isolation portion 152 and the second isolation portion 153 may include a conductive material. At least one of the third isolation portion 154 and the first isolation portion 152 is electrically connected to the second electrode 163.

[0110] In this embodiment, the material of the first isolation portion 152 includes aluminum, silver or copper, and / or the material of the second isolation portion 153 includes titanium or molybdenum, and / or the material of the third isolation portion 154 includes molybdenum or titanium.

[0111] Optionally, the second electrodes 163 of the plurality of light emitting devices 16 are electrically connected via the isolation structure 15. Optionally, the second electrodes 163 of the plurality of light emitting devices 16 are electrically connected to the second trace 1202 via the isolation structure 15.

[0112] For further information, please refer to Fig.11 The display panel 1 further includes a first encapsulation layer 181, the first encapsulation layer 181 includes a plurality of encapsulation units 1811, different encapsulation units 1811 are used to encapsulate the light-emitting devices 16 in different isolation openings 151, two adjacent encapsulation units 1811 are disconnected at a side of the isolation structure 15 away from the substrate 1101, and the encapsulation units 1811 include inorganic encapsulation units. In this embodiment, the encapsulation units 1811 can be distributed in the display area 10.

[0113] For further information, please refer to Fig.12 The display panel 1 further includes a second encapsulation layer 182, which is located on a side of the first encapsulation layer 181 away from the substrate 1101, and the second encapsulation layer 182 at least covers the first encapsulation layer 181. For example, the second encapsulation layer 182 has a flat surface on a side away from the substrate 1101, and the second encapsulation layer 182 can be distributed in the display area 10 and the frame area 20.

[0114] In some embodiments, please refer again to Fig.12The display panel 1 further includes a third encapsulation layer 183 . The third encapsulation layer 183 is located on a side of the second encapsulation layer 182 away from the substrate 1101 . The third encapsulation layer 183 may be distributed in the display area 10 and the frame area 20 .

[0115] In some embodiments, the third encapsulation layer 183 includes an inorganic encapsulation layer, and the second encapsulation layer 182 includes an organic encapsulation layer.

[0116] In some embodiments, the third encapsulation layer 183 covers a side of the first trace 1201 away from the substrate 1101 .

[0117] For further information, please refer to Fig.13 The display panel 1 further includes a third wiring 1203. The first wiring 1201, the second wiring 1202 and the third wiring 1203 are insulated from each other. The third wiring 1203 is electrically connected to the pixel circuit in the display panel 1 for transmitting a second power supply voltage signal (e.g., an ELVDD signal). In this embodiment, the voltage value of the first power supply voltage signal is different from the voltage value of the second power supply voltage signal. Optionally, the voltage value of the first power supply voltage signal is less than the voltage value of the second power supply voltage signal. Optionally, the third wiring 1203 is located in the border area 20.

[0118] For further information, please refer to Fig.14 The display panel 1 further includes a plurality of conductive layers, which are sequentially stacked between the substrate 1101 and the film layer where the light-emitting device 16 is located, and an insulating layer is disposed between adjacent conductive layers.

[0119] Please refer again Fig.14 The display panel 1 further includes an active layer 1103, the active layer 1103 includes a source region (S region), a channel region (P-si region) and a drain region (D region), the transistor 111 in the pixel circuit includes a gate 1105, a source 1106 and a drain 1107 formed by a conductive layer, the orthographic projection of the gate 1105 on the substrate 1101 overlaps the orthographic projection of the channel region on the substrate 1101, the source 1106 is connected to the source region, and the drain 1107 is connected to the drain region. In this embodiment, the first electrode 161 is connected to the source 1106 or the drain 1107 of the transistor 111.

[0120] Please refer again Fig.14 , the specific film layer structure of the array substrate forming the pixel circuit is described in detail below. Fig.14 It is the film layer structure of the display area 20.

[0121] The array substrate may include a substrate 1101 , a buffer layer 1102 , an active layer 1103 , a plurality of conductive layers, and an insulating layer between adjacent conductive layers.

[0122] The substrate 1101 may be a rigid substrate (e.g., a glass substrate) or a flexible substrate (e.g., including a polyimide layer). The buffer layer 1102 is located on one side of the substrate 1101. The active layer 1103 is located on the side of the buffer layer 1102 away from the substrate 1101. In this embodiment, the buffer layer 1102 may be formed of an inorganic material, such as silicon oxide, silicon nitride, silicon oxynitride, etc. In this embodiment, the buffer layer 1102 may be a double-layer structure of a silicon nitride (SiNx) layer and a silicon oxide (SiOx) layer sequentially formed on the substrate 1101.

[0123] The active layer 1103 is formed on the buffer layer 1102 and partially covers the buffer layer 1102. The active layer 1103 can be formed of an inorganic semiconductor (e.g., amorphous silicon or polycrystalline silicon), an organic semiconductor or an oxide semiconductor. The active layer 1103 can include a source region (S), a drain region (D) and a channel region (e.g., P-Si).

[0124] A plurality of conductive layers and insulating layers between adjacent conductive layers form a gate insulating layer 1104, a gate 1105, a source 1106, a drain 1107, a capacitor dielectric layer 1108, an interlayer insulating layer 1109, and a first capacitor electrode 1110 and a second capacitor electrode 1111 for forming a capacitor. The storage capacitor may include the first capacitor electrode 1110 and the second capacitor electrode 1111.

[0125] The gate insulating layer 1104 is formed on the active layer 1103 and the buffer layer 1102 not covered by the active layer 1103 to insulate and isolate the active layer 1103 from the gate 1105. The gate insulating layer 1104 may be made of materials such as silicon oxide or silicon nitride, but is not limited thereto.

[0126] The gate 1105 is formed on one side of the gate insulating layer 1104 at a corresponding position of the active layer 1103. The gate 1105 can be formed using one or more of metals such as Al, Mo, Cu, Ti or other metal materials with low resistivity. At the same time, a first capacitor electrode 1110 of a capacitor is also formed on the gate insulating layer 1104. The first capacitor electrode 1110 is formed on the gate insulating layer 1104 and partially covers the gate insulating layer 1104. The first capacitor electrode 1110 and the gate 1105 can be made of the same material. A first conductive layer (e.g., a first metal layer M1) can be made on the gate insulating layer 1104 to achieve the purpose of simultaneously making the gate 1105 and the first capacitor electrode 1110.

[0127] The capacitor dielectric layer 1108 is formed on the gate insulating layer 1104 and covers the gate 1105 and the first capacitor electrode 1110. The second capacitor electrode 1111 is located on the side of the capacitor dielectric layer 1108 corresponding to the first capacitor electrode 1110 that is away from the substrate 1101. The orthographic projection of the second capacitor electrode 1111 on the substrate 1101 overlaps with the orthographic projection of the first capacitor electrode 1110 on the substrate 1101. The capacitor dielectric layer 1108 is used to insulate and isolate the gate 1105 from the source 1106 and the drain 1107, and to insulate and isolate the first capacitor electrode 1110 from the second capacitor electrode 1111. The capacitor dielectric layer 1108 electrically insulates the gate 1105 from the source 1106 and the drain 1107, respectively, and forms a storage capacitor with the first capacitor electrode 1110 and the second capacitor electrode 1111. The capacitor dielectric layer 1108 can also be formed of inorganic materials, such as silicon nitride and silicon oxide. The second capacitor electrode 1111 is located in a second conductive layer (eg, a second metal layer M2 ) formed above the capacitor dielectric layer 1108 .

[0128] The interlayer insulating layer 1109 is formed on the capacitor dielectric layer 1108 and covers the second capacitor electrode 1111, and is used to isolate the source electrode 1106, the drain electrode 1107 and the second capacitor electrode 1111, so that the source electrode 1106, the drain electrode 1107 and the second capacitor electrode 1111 are insulated from each other. The interlayer insulating layer 1109 can also be formed of an inorganic material (such as silicon nitride and silicon oxide). The structure of the interlayer insulating layer 1109 can be a double layer or a triple layer structure formed of silicon nitride and silicon oxide.

[0129] The source electrode 1106 and the drain electrode 1107 are formed on the interlayer insulating layer 1109, the source electrode 1106 is electrically connected to the source region (S) in the active layer 1103 through a through hole, and the drain electrode 1107 is electrically connected to the drain region (D) in the active layer 1103 through a through hole. The electrode materials of the gate electrode 1105, the source electrode 1106, the drain electrode 1107, the first capacitor electrode 1110, and the second capacitor electrode 1111 can be one or more of metal Al, Mo, Cu, Ti or other metal materials with low resistivity. The source electrode 1106 and the drain electrode 1107 are located in the third conductive layer (third metal layer M3) made on the interlayer insulating layer 1109. In this embodiment, the driving layer includes a TFT (Thin Film Transistor) structure formed by the gate electrode 1105, the source electrode 1106, the drain electrode 1107 and the active layer 1103.

[0130] The film layer structure of the above-mentioned array substrate is only an example provided in this embodiment. In other embodiments, the array substrate may include more film layers or only include part of the above-mentioned film layers.

[0131] Please combine Fig.14 And refer to Fig.15The insulating layer in the display panel 1 may include a planarization layer 19, and the number of the planarization layers 19 is multiple, for example, the number of the planarization layers 19 is 3 layers, as shown in FIG. Fig.14 As shown, the planarization layer 19 includes PLN1, PLN2 and PLN3, and the dam structure (the first dam structure 141 and the second dam structure 142) in the first region 201 can be arranged in the same layer as at least part of the planarization layer, for example, it can be arranged in the same layer as the planarization layers PLN2 and PLN3, that is, the dam structure in the first region 201 is formed by the planarization layers PLN2 and PLN3. In this embodiment, at least part of the first trace 1201 is arranged in the same layer as the conductive layer between adjacent planarization layers 19, for example, when the number of planarization layers 19 is 3 and PLN2 and PLN3 are used to form the dam structure, as shown in FIG. Fig.15 As shown, the first wiring 1201 may include a portion of the same layer as the conductive layer M4 and the conductive layer M5, wherein the conductive layer M4 is located between the planarization layer PLN1 and the planarization layer PLN2, and the conductive layer M5 is located between the planarization layer PLN2 and the planarization layer PLN3. The conductive layer M4 and the conductive layer M5 may be a three-layer conductive structure of titanium, aluminum and titanium, so that the resistance of the first wiring 201 can be reduced. It can be understood that when the number of planarization layers 19 is 2 layers (PLN1 and PLN2), and PLN1 and PLN2 are used to form a dam structure, the first wiring 1201 may also include a portion of the same layer as the conductive layer M3 and the conductive layer M4.

[0132] In this embodiment, the side of the dam structure in the first region 201 away from the substrate 1101 can also cover the pixel defining layer 17. Furthermore, in the first region 201, the side of the pixel defining layer 17 away from the substrate 1101 can also cover the second encapsulation layer 182 and the third encapsulation layer 183.

[0133] In the display area 10, the light emitting devices 16 are arranged in an array, each light emitting device 16 may correspond to a pixel, and a plurality of light emitting devices 16 arranged in sequence along the row direction form a pixel row 40, such as Fig.16 As shown, the pixel row 40 extends along a first direction (X direction in the figure), and multiple pixel rows 40 are distributed along a second direction (Y direction in the figure), wherein the first direction and the second direction intersect, and preferably, the first direction and the second direction are perpendicular to each other.

[0134] The border area 20 includes a first sub-border area 210, a second sub-border area 220, a third sub-border area 230 and a fourth sub-border area 240, wherein the first sub-border area 210 and the third sub-border area 230 are arranged relative to each other in the second direction (Y direction in the figure), and the second sub-border area 220 and the fourth sub-border area 240 are arranged relative to each other in the first direction (X direction in the figure).

[0135] In some embodiments, the first trace 1201 is distributed along the second sub-frame area 220, the third sub-frame area 230 and the fourth sub-frame area 240, and is distributed in a partial area of ​​the first sub-frame area 210, such as Fig.16 As shown, the first routing line 1201 is also distributed in the area of ​​the first sub-frame area 210 close to the second sub-frame area 220 and the area of ​​the first sub-frame area 210 close to the fourth sub-frame area 240. The second routing line 1202 and the third routing line 1203 are distributed in the first sub-frame area 210. The gate driving circuit 130 is distributed in the second sub-frame area 220 and the fourth sub-frame area 240.

[0136] Furthermore, part of the first routing lines 1201 are distributed in the first area 201 in the second sub-frame area 220 , the third sub-frame area 230 , and the fourth sub-frame area 240 .

[0137] In some embodiments, in the first sub-frame area 210, the display panel 1 further includes a third area 203, and the third area 203 is located on a side of the first area 201 close to the display area 10. The second routing line 1202, the third routing line 1203, and a portion of the first routing line 1201 are distributed in the third area 203. The second routing line 1202, the third routing line 1203, and a portion of the first routing line 1201 are distributed in the third area 203 along the first direction (the X direction in the figure), wherein the second routing line 1202 is located on opposite sides of the third routing line 1203, and a portion of the first routing line 1201 is located on a side of the second routing line 1202 away from the third routing line 1203. For example, Fig.16 As shown, in the third area 203 , the number of the third routing line 1203 may be one, and the number of the second routing lines 1202 may be two. Two parts of the first routing line 1201 are located in the third area 203 .

[0138] For further information, please refer to Fig.17 , the display panel 1 further includes a first signal line 1204, a second signal line 1205, and a third signal line 1206. The first signal line 1204 is connected to the first routing line 1201 distributed in the third area 203 via the first area 201. The second signal line 1205 is connected to the second routing line 1202 distributed in the third area 203 via the first area 201. The third signal line 1206 is connected to the third routing line 1203 distributed in the third area 203 via the first area 201. Exemplarily, the first signal line 1204 provides a gate drive voltage (VGH or VGL) signal to the first routing line 1201, the second signal line 1205 provides a first power supply voltage (ELVSS) signal to the second routing line 1202, and the third signal line 1206 provides a second power supply voltage (ELVDD) signal to the second routing line 1203.

[0139] In one embodiment, the first signal line 1204, the second signal line 1205, the third signal line 1206, the second routing line 1202, the third routing line 1203, and the first routing line 1201 distributed in the third region 203 are arranged in the same layer. In order to reduce the resistance of the above-mentioned wires, illustratively, the above-mentioned wires can be made in the same layer using a conductive layer having a titanium-aluminum-titanium structure, for example, the above-mentioned wires can be made using a fourth conductive layer M4.

[0140] Please refer to Fig.18 The gate driving circuit 130 includes a plurality of gate driving units 131, and each gate driving unit 131 includes a light-emitting control subunit 1311 and two scanning subunits 1312. The specific circuit structures of the light-emitting control subunit 1311 and the scanning subunit 1312 are the same as those in the prior art, and will not be described in detail here.

[0141] In one embodiment, the light control subunit 1311 and the scanning subunit 1312 in a gate driving unit 131 respectively provide a light control signal (EM signal) and a row scanning signal (Scan signal) for the same pixel row, wherein the row scanning signal includes signals such as Scan1 (S1), Scan2 (S2) and Scan3 (S3).

[0142] Please refer to Fig.19 In one embodiment, the display panel 1 further includes a connecting wire 1207 , and the first wire 1201 is electrically connected to the light emitting control subunit 1311 and the scanning subunit 1312 in each gate driving unit 131 through the connecting wire 1207 .

[0143] The first traces 1201 located in the second sub-frame area 220 and the fourth sub-frame area 240 are distributed along the second direction (the Y direction in the figure), and the first traces 1201 located in the second sub-frame area 220 and the fourth sub-frame area 240 provide a gate driving voltage to the gate driving unit 131 through the connecting traces 1207. Exemplarily, in this embodiment, the connecting traces 1207 may extend along the first direction (the X direction in the figure), wherein the orthographic projection of the connecting traces 1207 on the substrate 1101 is located in the gap between the orthographic projections of adjacent gate driving units 131 on the substrate 1101.

[0144] Please refer to Fig. 20 In one embodiment, two adjacent gate driving units 131 are connected to the first wiring 1201 through the same connecting wiring 1207, and the orthographic projections of the two adjacent gate driving units 131 on the substrate 1101 do not overlap with the orthographic projections of the same connecting wiring 1207 on the substrate 1101. Exemplarily, the orthographic projection of the connecting wiring 1207 on the substrate 1101 is located in the gap between the orthographic projections of the two adjacent gate driving units 131 on the substrate 1101. Fig.19The design can reduce the number of connecting wires 1207, thereby saving the wiring space of the gate driving circuit 130 in the second direction (Y direction in the figure).

[0145] In this embodiment, the first routing 1201 and the connecting routing 1207 can be made of different conductive layers. For example, the first routing 1201 can be formed by a third conductive layer (e.g., a third metal layer M3) and / or a fourth conductive layer (e.g., a fourth metal layer M4), and the connecting routing 1207 can be formed by a first conductive layer (e.g., a first metal layer M1) or a second conductive layer (e.g., a second metal layer M2).

[0146] In this embodiment, the gate driving voltage provided by the first wiring 1201 may be a high-level gate driving voltage (VGH) or a low-level gate driving voltage (VGL).

[0147] Based on the same inventive concept, this embodiment also provides an electronic device, which uses the display panel in the above embodiment. Since the above display panel can have a narrower frame area, the display panel has a higher screen-to-body ratio, which helps to improve the user experience and the market competitiveness of electronic products. The electronic device may include a mobile phone, a wearable device, a notebook, a tablet computer, etc.

[0148] The present application provides a display panel and an electronic device, in which a first line and a gate drive circuit are located in a frame area, the first line is connected to the gate drive circuit and provides a gate drive voltage for the gate drive circuit, and the orthographic projection of the first line on the substrate is located outside the orthographic projection of the gate drive circuit on the substrate, or the orthographic projection of the first line on the substrate overlaps with the orthographic projection of the gate drive circuit on the substrate. Compared with the related art, the line originally used for transmitting the power supply voltage signal in the frame area of ​​the display panel is used as the first line to provide the gate drive voltage, and the line providing the gate drive voltage in the gate drive circuit can be cancelled, thereby further compressing the layout space of the gate drive circuit and reducing the width of the frame area, further improving the screen-to-body ratio of the display panel, improving the user experience, and enhancing the market competitiveness of the product.

[0149] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0150] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, combination, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A display panel, characterized in that: The display panel further includes: substrate; A first wiring, the first wiring is located at one side of the substrate, and the first wiring is located in a frame area of ​​the display panel; A gate driving circuit, wherein the gate driving circuit is located in the border area; The first routing line is connected to the gate driving circuit and is used to provide a gate driving voltage for the gate driving circuit, wherein the border area includes a plurality of sub-border areas, and the first routing line is located in at least two sub-border areas.

2. The display panel according to claim 1, wherein: The orthographic projection of the first wiring on the substrate is outside the orthographic projection of the gate driving circuit on the substrate.

3. The display panel according to claim 1, wherein: The display panel further includes a first area and a second area, the first area and the second area are both located in the frame area, and the first area is arranged around the display area of ​​the display panel. At least part of the first wiring is located in the first area, and the gate driving circuit is located in the second area; Preferably, the second area is located in the frame areas on two opposite sides of the display area, and the second area is located on a side of the first area facing the display area.

4. The display panel according to claim 3, wherein: In the first area, the display panel includes a first dam structure and a second dam structure located on one side of the substrate, and the first dam structure and the second dam structure are arranged around a display area of ​​the display panel; The orthographic projection shapes of the first dam structure and the second dam structure on the substrate include rings; The first dam structure is located on a side of the second dam structure close to the display area; An orthographic projection of at least part of the first trace on the substrate is located between an orthographic projection of the first dam structure and an orthographic projection of the second dam structure on the substrate.

5. The display panel according to claim 3, wherein: The display panel further includes a second wiring, and the second wiring is located in the frame area; The first wiring and the second wiring are insulated from each other, and the second wiring is electrically connected to an isolation structure in a display area of ​​the display panel; Preferably, the display panel further comprises a light emitting device, wherein in a direction away from the substrate, the light emitting device comprises a first electrode, a light emitting material layer and a second electrode which are stacked, and at least part of the isolation structure is located between the light emitting devices, wherein the second electrode is electrically connected to the isolation structure around the light emitting device; Preferably, the second wiring is used to transmit a first power supply voltage signal.

6. The display panel according to claim 5, wherein: The display panel further comprises a pixel defining layer, wherein the pixel defining layer is located on one side of the substrate, and the isolation structure is located on a side of the pixel defining layer away from the substrate; The pixel defining layer encloses a pixel opening on the substrate, the isolation structure encloses an isolation opening on the substrate, at least part of the light-emitting device is located in the pixel opening, and the orthographic projection of the pixel opening on the substrate is located within the orthographic projection of the isolation opening on the substrate.

7. The display panel according to claim 6, wherein: The isolation structure comprises a first isolation portion and a second isolation portion, and in a direction away from the substrate, the first isolation portion and the second isolation portion are stacked in sequence; An orthographic projection of the first isolation portion on the substrate is located within an orthographic projection of the second isolation portion on the substrate.

8. The display panel according to claim 7, wherein: The isolation structure further includes a third isolation portion, and in a direction away from the substrate, the third isolation portion, the first isolation portion and the second isolation portion are stacked in sequence; The orthographic projection of the first isolation portion on the substrate is located within the orthographic projection of the third isolation portion on the substrate; Preferably, the material of the first isolation portion includes aluminum, silver or copper, and / or the material of the second isolation portion includes titanium or molybdenum, and / or the material of the third isolation portion includes molybdenum or titanium.

9. The display panel according to claim 7, wherein: The display panel further comprises a first encapsulation layer, the first encapsulation layer comprises a plurality of encapsulation units, different encapsulation units are used to encapsulate light-emitting devices in different isolation openings, and two adjacent encapsulation units are disconnected at a side of the isolation structure away from the substrate; Preferably, the packaging unit comprises an inorganic packaging unit.

10. The display panel according to claim 9, wherein: The display panel further includes a second encapsulation layer; The second encapsulation layer is located on a side of the first encapsulation layer away from the substrate, and the second encapsulation layer at least covers the first encapsulation layer; Preferably, the second encapsulation layer has a flat surface on a side away from the substrate.

11. The display panel according to claim 10, wherein: The display panel further comprises a third encapsulation layer, wherein the third encapsulation layer is located on a side of the second encapsulation layer away from the substrate; Preferably, the third encapsulation layer comprises an inorganic encapsulation layer, and the second encapsulation layer comprises an organic encapsulation layer; Preferably, the third packaging layer covers a side of the first trace away from the substrate.

12. The display panel according to claim 5, characterized in that: The display panel further includes a third wiring, the first wiring, the second wiring and the third wiring are insulated from each other, and the third wiring is electrically connected to a pixel circuit in the display panel and is used to transmit a second power supply voltage signal; Preferably, the voltage value of the first power supply voltage signal is less than the voltage value of the second power supply voltage signal; Preferably, the third wiring is located in the border area.

13. The display panel according to claim 12, wherein: The display panel further includes: A plurality of conductive layers, wherein the plurality of conductive layers are sequentially stacked and arranged between the substrate and the film layer where the light-emitting device is located, and an insulating layer is arranged between adjacent conductive layers; Preferably, the display panel further comprises: an active layer; The active layer includes a source region, a channel region and a drain region, the transistor in the pixel circuit includes a gate, a source and a drain formed by the conductive layer, the orthographic projection of the gate on the substrate overlaps the orthographic projection of the channel region on the substrate, the source is connected to the source region, and the drain is connected to the drain region; Preferably, the first electrode is connected to the source or drain of the transistor; Preferably, at least part of the first routing lines is arranged on the same layer as the second routing lines and the third routing lines.

14. The display panel according to claim 13, wherein: The insulating layer includes a planarization layer, the number of the planarization layers is multiple, and the dam structure in the first region is arranged in the same layer as at least part of the planarization layer; Preferably, at least a portion of the first wiring is arranged in the same layer as the conductive layer between adjacent planarization layers.

15. The display panel according to claim 12, wherein: In a display area of ​​the display panel, a pixel row extends along a first direction, and a plurality of the pixel rows are distributed along a second direction, wherein the first direction intersects with the second direction; The frame area includes a first sub-frame area, a second sub-frame area, a third sub-frame area and a fourth sub-frame area, wherein the first sub-frame area and the third sub-frame area are arranged opposite to each other in the second direction, and the second sub-frame area and the fourth sub-frame area are arranged opposite to each other in the first direction; Preferably, the first routing line is distributed along the second sub-frame area, the third sub-frame area and the fourth sub-frame area, and distributed in a partial area of ​​the first sub-frame area; the second routing line and the third routing line are distributed in the first sub-frame area; the gate driving circuit is distributed in the second sub-frame area and the fourth sub-frame area; Preferably, part of the first routing lines are distributed in the second sub-frame area, the third sub-frame area and the first area in the fourth sub-frame area; Preferably, in the first sub-frame area, the display panel further includes a third area, and the third area is located on a side of the first area close to the display area; Preferably, the second routing line, the third routing line and part of the first routing line are located in the third area; Preferably, the second routing line, the third routing line and part of the first routing line are distributed in the third area along the first direction, the second routing line is located at two opposite sides of the third routing line, and part of the first routing line is located at a side of the second routing line away from the third routing line; Preferably, the display panel further comprises a first signal line, a second signal line and a third signal line; The first signal line is connected to the first routing line distributed in the third area via the first area, the second signal line is connected to the second routing line distributed in the third area via the first area, and the third signal line is connected to the third routing line distributed in the third area via the first area; Preferably, the first signal line, the second signal line, the third signal line, the second routing line, the third routing line, and the first routing line distributed in the third area are arranged on the same layer.

16. The display panel according to any one of claims 1 to 13, characterized in that: The gate driving circuit includes a plurality of gate driving units, each of which includes a light emitting control subunit and two scanning subunits; Preferably, the display panel further comprises connecting wires, and the first wires are electrically connected to the light emitting control subunit and the scanning subunit in each of the gate driving units through the connecting wires.

17. The display panel according to claim 16, wherein: In a display area of ​​the display panel, a pixel row extends along a first direction, and a plurality of the pixel rows are distributed along a second direction, wherein the first direction intersects with the second direction; The first wiring extending along the second direction provides a gate driving voltage to the gate driving unit through the connecting wiring; Preferably, the connecting line extends along the first direction.

18. The display panel according to claim 16, wherein: Two adjacent gate driving units are connected to the first wiring through the same connecting wiring; The orthographic projections of two adjacent gate driving units on the substrate do not overlap with the orthographic projection of the same connecting line on the substrate; Preferably, the orthographic projection of the connecting wire on the substrate is located in a gap between the orthographic projections of two adjacent gate driving units on the substrate.

19. The display panel according to claim 16, wherein: The gate driving voltage provided by the first wiring is a high-level gate driving voltage or a low-level gate driving voltage.

20. An electronic device, characterized in that: The electronic device comprises the display panel according to any one of claims 1-19.

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