Capacitor

Abstract

The problem is to increase capacitance. The silicon substrate (2) has a first region (A1), a second region (A2), a third region (A3), and an eave portion (27) that protrudes inward from the third region (A3) and overlaps the second porous portion (23B) in plan view. The capacitor (1) satisfies at least one of a first condition and a second condition with respect to the eave portion (27). The first condition is that a first distance (H1) measured in a thickness direction (D1) defined with respect to the silicon substrate (2) should be longer than a second distance (H2) between a plane (VP1) including the main surface (21) in the third region (A3) and a surface (27B) of the eave portion (27) facing the second porous portion (23B) measured in the thickness direction (D1) defined with respect to the silicon substrate (2), the first distance (H1) is the shortest distance between the plane (VP1) and the first porous portion (23A). The second condition is a condition in which the tip (272) of the eave portion (27) should be located outside the inner peripheral edge of the second region (A2) in plan view.

Description

Technical Field

[0001] The present disclosure relates generally to capacitors, and more particularly to capacitors including silicon substrates. Background Art

[0002] Patent document 1 discloses a capacitor, including a silicon substrate, a conductor layer and a dielectric layer. The silicon substrate has a first main surface and a second main surface. The first main surface of the silicon substrate has a capacitance performance region and a non-capacitance performance region. The silicon substrate has a porous portion formed along the thickness direction in the capacitance performance region of the first main surface. The porous portion has a plurality of micropores.

[0003] Sometimes a capacitor is needed to increase its capacitance.

[0004] Patent document 1: WO2020 / 184517A1 Summary of the invention

[0005] An object of the present disclosure is to provide a capacitor that can have increased capacitance.

[0006] A capacitor according to one aspect of the present disclosure includes a silicon substrate, a dielectric layer, and a conductor layer. The silicon substrate has: a first region in which a first porous portion is formed; a second region in which a second porous portion is formed and the second porous portion surrounds the first region; a third region in which the third region surrounds the second region; and an eaves portion, when viewed from above, the eaves portion protrudes inward from the third region and overlaps with the second porous portion. The dielectric layer is arranged to cover the surface of the first porous portion, the surface of the second porous portion, the surface of the eaves portion, and the main surface in the third region in the silicon substrate. The conductor layer is stacked on the dielectric layer. The first porous portion has a plurality of first micropores extending in a thickness direction defined relative to the silicon substrate. In the first porous portion, each pair of first micropores located adjacent to each other belonging to the plurality of first micropores has an uneven spacing in the thickness direction defined relative to the silicon substrate. The second porous portion has a plurality of second micropores. The spacing between each of the plurality of second micropores and the eaves portion measured in the thickness direction defined relative to the silicon substrate increases its length as the distance from the first region increases and the distance from the third region decreases. The capacitor satisfies at least one of a first condition or a second condition with respect to the eaves portion. The first condition is a condition that a first distance measured in a thickness direction defined relative to the silicon substrate should be longer than a second distance measured in a thickness direction defined relative to the silicon substrate between a plane including the main surface in the third region and a surface of the eaves portion facing the second porous portion, wherein the first distance is the shortest distance between the plane and the first porous portion. The second condition is a condition that a tip of the eaves portion should be located outside an inner peripheral edge of the second region when viewed from above. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a schematic cross-sectional view of a capacitor according to a first embodiment;

[0008] Figure 2 is a cross-sectional view showing the main parts of the capacitor on a larger scale;

[0009] Figure 3 is a top view of the capacitor;

[0010] Figure 4A and 4B is a cross-sectional view showing corresponding process steps of a method for manufacturing a capacitor;

[0011] Figure 5A and 5B is a cross-sectional view showing corresponding process steps of a method for manufacturing a capacitor;

[0012] Fig. 6A and 6B is a cross-sectional view showing corresponding process steps of a method for manufacturing a capacitor;

[0013] Figure 7 is a top view showing a method for manufacturing a capacitor; and

[0014] Figure 8 is a cross-sectional view showing a main portion of a capacitor according to a second embodiment on a larger scale. DETAILED DESCRIPTION

[0015] In the following description of the first and second embodiments, reference will be made to Figures 1 to 8 , and their variations are schematically represented. Therefore, the ratios of sizes (including thickness) of the various constituent elements shown in the drawings do not always reflect their actual size ratios.

[0016] (First embodiment)

[0017] (1) Overview

[0018] Will refer to Figure 1-3 The capacitor 1 according to the first embodiment is described. Note that Figure 1 is along Figure 3 Cross-sectional view taken along plane XX.

[0019] The capacitor 1 includes a silicon substrate 2, a dielectric layer 4, and a conductor layer 5. The silicon substrate 2 has a first region A1, a second region A2, a third region A3, and an eaves portion 27, the first region A1 having a first porous portion 23A formed therein, the second region A2 having a second porous portion 23B formed therein and the second region A2 surrounding the first region A1, the third region A3 surrounding the second region A2, and the eaves portion 27 protruding inward from the third region A3 and overlapping with the second porous portion 23B when viewed from above. The dielectric layer 4 is arranged to cover the surface 231A of the first porous portion 23A, the surface 231B of the second porous portion 23B, the surface 270 of the eaves portion 27, and the main surface 21 in the third region A3 in the silicon substrate 2. The conductor layer 5 is stacked on the dielectric layer 4.

[0020] The silicon substrate 2 also has a doping layer 3 containing a p-type dopant, such as boron or indium.

[0021] In the capacitor 1, the doped layer 3 serves as a first electrode of the capacitor 1, and the conductor layer 5 serves as a second electrode of the capacitor 1. Therefore, in the capacitor 1, the dielectric layer 4 is interposed between the first electrode and the second electrode.

[0022] The capacitor 1 further comprises a first external connection electrode 7 and a second external connection electrode 8. The first external connection electrode 7 is connected to the doped layer 3. The second external connection electrode 8 is connected to the conductor layer 5.

[0023] (2) Components of capacitors

[0024] The respective components of the capacitor 1 will be described in further detail.

[0025] (2.1) Silicon substrate

[0026] like Figure 1 and 2 As shown, the silicon substrate 2 has a main surface 21 (hereinafter also referred to as "first main surface 21") and a second main surface 22 opposite to the first main surface 21. The silicon substrate 2 has an outer edge of a rectangular shape when viewed from above in a thickness direction D1 defined relative to the silicon substrate 2. For example, the silicon substrate 2 has a thickness equal to or greater than 300 μm and equal to or less than 1 mm.

[0027] The silicon substrate 2 has a first area A1, a second area A2, a third area A3 and an eaves portion 27. In the first area A1, a first porous portion 23A is formed. The second area A2 has a second porous portion 23B and surrounds the first area A1. The third area A3 surrounds the second area A2. When viewed from above, the eaves portion 27 protrudes inward from the third area A3 and overlaps with the second porous portion 23B. When viewed from above in the thickness direction D1 defined relative to the silicon substrate 2, the first area A1 is a rectangular area and is surrounded by the second area A2. When viewed from above in the thickness direction D1 defined relative to the silicon substrate 2, the first area A1 does not necessarily have to be a rectangular area, but may also be, for example, a circular area, a polygonal area other than a rectangle, or an area of ​​a polygonal shape other than a convex polygon.

[0028] The first porous portion 23A has a plurality of first micropores 24 extending along a thickness direction D1 defined relative to the silicon substrate 2. In the first porous portion 23A, an interval L1 (refer to Figure 2 ) is non-uniform in a thickness direction D1 defined relative to the silicon substrate 2.

[0029] The plurality of first micropores 24 pass through a plane VP1 (refer to FIG. 1 ) including the first main surface 21 of the silicon substrate 2. Figure 2) is formed closer to the third main surface 28 of the second main surface 22. Each of the plurality of first micropores 24 is a hole, the depth of which measured from the third main surface 28 of the silicon substrate 2 in the thickness direction D1 defined relative to the silicon substrate 2 is greater than the width of the opening of the hole through the third main surface 28 of the silicon substrate 2. Each of the plurality of first micropores 24 extends from the third main surface 28 of the silicon substrate 2 in the thickness direction D1 defined relative to the silicon substrate 2, but does not reach the second main surface 22 of the silicon substrate 2. In other words, the plurality of first micropores 24 do not penetrate the silicon substrate 2 in the thickness direction D1 defined relative to the silicon substrate 2. That is, the plurality of first micropores 24 do not contact the second main surface 22 of the silicon substrate 2. Each of the plurality of first micropores 24 has an opening width equal to or greater than 0.1 μm and equal to or less than 10 μm at the third main surface 28 of the silicon substrate 2, for example. In addition, each of the plurality of first micropores 24 has a depth less than the thickness of the silicon substrate 2. The depth of the plurality of first micropores 24 measured in the thickness direction D1 defined relative to the silicon substrate 2 is, for example, equal to or greater than 20 μm and equal to or less than 300 μm, more preferably equal to or greater than 30 μm and equal to or less than 100 μm. Note that the upper limit value of the depth of the plurality of first micropores 24 can be appropriately determined by, for example, the opening width of the plurality of first micropores 24 and the corresponding method of forming the doping layer 3, the dielectric layer 4, and the conductor layer 5. The opening width and depth of the first micropores 24 in the first porous portion 23A of the silicon substrate 2 are values ​​determined based on, for example, a cross-sectional scanning electron microscope (SEM) image of the capacitor 1.

[0030] The surface 231A of the first porous portion 23A is constituted by the respective inner surfaces of the plurality of first micropores 24 formed through the third major surface 28 of the silicon substrate 2 and the third major surface 28 of the silicon substrate 2 .

[0031] In the capacitor 1, the deeper the plurality of first micropores 24 of the first porous portion 23A are, the more significant the surface area of ​​the surface 231A of the first porous portion 23A is, and thus the capacitance of the capacitor 1 can be increased accordingly. Also, in the capacitor 1, the greater the number of first micropores 24 in the first porous portion 23A is, the more significant the surface area of ​​the surface 231A of the first porous portion 23A is, and thus the capacitance of the capacitor 1 can be increased accordingly.

[0032] In the capacitor 1, the interval L1 between two adjacent first micropores 24 among the plurality of first micropores 24 is not uniform in the thickness direction D1 defined with respect to the silicon substrate 2, as shown in FIG. Figure 22. In the capacitor 1, the surface area of ​​the surface 231A of the first porous portion 23A can be increased compared to the case where the interval L1 between two adjacent first micropores 24 among the plurality of first micropores 24 is uniform in the thickness direction D1 defined relative to the silicon substrate 2. Note that when the plurality of first micropores 24 are formed by, for example, dry etching, the interval L1 between two adjacent first micropores 24 among the plurality of first micropores 24 is uniform in the thickness direction D1 defined relative to the silicon substrate 2. In addition, in the capacitor 1, each of the plurality of first micropores 24 has a non-uniform opening width in the thickness direction D1 defined relative to the silicon substrate 2.

[0033] In a second direction D2 (see FIG. 1 ) perpendicular to the thickness direction D1 (hereinafter also referred to as “first direction D1”) defined relative to the silicon substrate 2 Figure 3 ), the inner side surface of one of the two adjacent first micropores 24 and the inner side surface of the other of the two adjacent first micropores 24 do not have a straight line shape, but each of these inner side surfaces has a profile with concave portions and convex portions. The height difference between the troughs and the crests of the concave portions and the convex portions is smaller than the opening width of the first micropore 24. The height difference between the troughs and the crests of the concave portions and the convex portions is a value determined based on, for example, a cross-sectional SEM image of the capacitor 1. The height difference between the troughs and the crests of the concave portions and the convex portions may vary depending on, for example, the impurity concentration of the p-type silicon wafer 20 from which the silicon substrate 2 is cut and the conditions of the anodizing treatment (see Figure 4A ).

[0034] The second porous portion 23B has a plurality of second micropores 25. As the distance from the first area A1 increases (i.e., the distance from the third area A3 decreases), the interval between each of the plurality of second micropores 25 and the eaves portion 27 measured along the thickness direction D1 defined with respect to the silicon substrate 2 increases in length. In other words, the plurality of second micropores are formed along a diagonal direction inclined with respect to the thickness direction D1 defined with respect to the silicon substrate 2.

[0035] In the cross section viewed along the second direction D2 (see Figure 3), the inner side surface of one of the two adjacent second micropores 25 and the inner side surface of the other of the two adjacent second micropores 25 do not have a straight line shape, but each of these inner side surfaces has a profile with concave portions and convex portions. The height difference between the troughs and the crests of the concave portions and the convex portions is smaller than the opening width of the second micropore 25. The height difference between the troughs and the crests of the concave portions and the convex portions is a value determined based on, for example, a cross-sectional SEM image of the capacitor 1. The height difference between the troughs and the crests of the concave portions and the convex portions may vary depending on, for example, the impurity concentration of the p-type silicon wafer 20 from which the silicon substrate 2 is cut and the conditions of the anodizing treatment (see Figure 4A ).

[0036] Silicon substrate 2 has a porous region including first porous portion 23A and second porous portion 23B. The porous region decreases in width as the distance from third major surface 28 increases in thickness direction D1 defined relative to silicon substrate 2 (ie, the distance from second major surface 22 decreases).

[0037] When viewed from above, the eaves portion 27 protrudes inward from the third area A3 and overlaps the second porous portion 23B. Figure 2 As shown, the surface 270 of the eaves portion 27 includes a surface 27B (hereinafter also referred to as "lower surface 27B") facing the second porous portion 23B and an upper surface 27A opposite to the lower surface 27B. The eaves portion 27 has a proximal end 271 connected to the third area A3 and a tip 272 adjacent to the first area A1. At the proximal end 271 of the eaves portion 27, the upper surface 27A of the eaves portion 27 is located on the same plane as the first main surface 21 of the silicon substrate 2. In other words, the upper surface 27A of the eaves portion 27 is located on the plane VP1.

[0038] The capacitor 1 satisfies both the first condition and the second condition with respect to the eaves portion 27 .

[0039] The first condition is a condition that the first distance H1 should be longer than the second distance H2. The first distance H1 is the shortest distance between the plane VP1 including the first main surface 21 in the third area A3 and the first porous portion 23A. The second distance H2 is the distance between the plane VP1 and the surface 27B of the eaves portion 27 facing the second porous portion 23B.

[0040] The second condition is a condition that the tip 272 of the eaves portion 27 is located outside the inner peripheral edge of the second area A2 when viewed from above.

[0041] Capacitor 1 has body region 26 located between doping layer 3 and second main surface 22 of silicon substrate 2 and having impurity concentration as high as p-type silicon wafer 20. In addition, body region 26 of silicon substrate 2 has carrier concentration as high as p-type silicon wafer 20.

[0042] If the silicon substrate 2 is cut out from the p-type silicon wafer 20 (see Figure 4A ), the main body region 26 of the silicon substrate 2 contains, for example, boron (B) as a dopant, but this should not be construed as limiting. Alternatively, the main body region 26 may contain indium (In) as a dopant. The impurity concentration of the main body region 26 in the silicon substrate 2 is, for example, equal to or higher than 1×10 13 cm -3 and equal to or less than 1x10 17 cm -3 , more preferably equal to or higher than 5x10 13 cm -3 and equal to or less than 5x10 16 cm -3 The impurity concentration of the bulk region 26 in the silicon substrate 2 is a value determined by, for example, secondary ion mass spectrometry (SIMS) analysis.

[0043] The doping layer 3 of the silicon substrate 2 is a diffusion layer. The conductivity type of the doping layer 3 is the same as the conductivity type of the main region 26 of the silicon substrate 2. In addition, the impurity concentration of the doping layer 3 is higher than the impurity concentration of the main region 26 of the silicon substrate 2. Therefore, if the conductivity type of the main region 26 of the silicon substrate 2 is p-type, the doping layer 3 is a p-type silicon region (p+ silicon region) having a higher concentration than the main region 26 of the silicon substrate 2. The dopant in the doping layer 3 can be, for example, the same type as the dopant in the main region 26 of the silicon substrate 2. More specifically, if the dopant introduced into the main region 26 is boron, the dopant in the doping layer 3 is boron. The impurity concentration of the doping layer 3 is equal to or higher than 1x10 18 cm -3 and equal to or less than 1x10 21 cm -3 , more preferably equal to or higher than 5x10 18 cm -3 and equal to or less than 1x10 20 cm -3 The impurity concentration of the doping layer 3 is a value determined by, for example, SIMS analysis.

[0044] Furthermore, the carrier concentration of the doped layer 3 is higher than that of the body region 26. The carrier concentration of the doped layer 3 and the carrier concentration of the body region 26 are values ​​determined by, for example, carrier concentration profile observation by scanning microwave impedance microscopy (sMIM).

[0045] When discussing the respective carrier concentration levels of the doping layer 3 and the main region 26 to determine which level is higher than the other, the carrier concentration is not limited to the value determined by the carrier concentration distribution observation of the sMIM. Alternatively, the carrier concentration of the doping layer 3 and the carrier concentration of the main region 26 can be values ​​determined by, for example, the carrier concentration distribution observation by a scanning capacitance microscope (SCM). Still alternatively, the carrier concentration of the doping layer 3 and the carrier concentration of the main region 26 can be values ​​determined by, for example, the carrier concentration distribution observation by scanning nonlinear dielectric microscopy (SNDM).

[0046] The thickness of doping layer 3 is preferably 10 nm or more and 10,000 nm or less, more preferably 50 nm or more and 5,000 nm or less. The thickness of doping layer 3 is a value determined by observing the cross section of capacitor 1 by sMIM, for example.

[0047] The doping layer 3 is formed in the silicon substrate 2 along the first main surface 21 of the silicon substrate 2, the surface 231A of the first porous portion 23A, the surface 231B in the second porous portion 23B, the surface 270 of the eaves portion 27 and the first main surface 21 of the silicon substrate 2 in the third area A3.

[0048] (2.2) Dielectric layer

[0049] The dielectric layer 4 is arranged to cover the surface 231A of the first porous portion 23A, the surface 231B of the second porous portion 23B, the surface 270 of the eaves portion 27, and the first main surface 21 in the third area A3 in the silicon substrate 2. More specifically, the dielectric layer 4 is formed on the doping layer 3, and has a shape that conforms to the shapes of the surface 231A of the first porous portion 23A, the surface 231B of the second porous portion 23B, the surface 270 of the eaves portion 27, and the first main surface 21 in the third area A3 of the silicon substrate 2. The dielectric layer 4 has a portion between the doping layer 3 and the conductor layer 5 in the thickness direction D1 defined relative to the silicon substrate 2, a portion between the doping layer 3 and the conductor layer 5 inside the plurality of first micropores 24 of the first porous portion 23A, and a portion between the doping layer 3 and the conductor layer 5 inside the plurality of second micropores 25 of the second porous portion 23B.

[0050] For example, the dielectric layer 4 has a thickness of 10 nm or more and 500 nm or less. The upper limit of the thickness of the dielectric layer 4 is limited by, for example, the opening width of the first micropores 24 in the first porous portion 23A in one direction aligned with the first main surface 21 of the silicon substrate 2, the thickness of the conductor layer 5 inside the first micropores 24 in the first porous portion 23A measured in the one direction, and the opening width of the second micropores 25 in the second porous portion 23B.

[0051] The dielectric layer 4 has a multilayer structure including a plurality of dielectric films stacked one on top of another, but this should not be construed as limiting. The dielectric layer 4 may also be a single dielectric film. If the dielectric layer 4 has a multilayer structure, the dielectric layer 4 includes, for example: a first dielectric film (for example, a first silicon oxide film) on the doping layer 3; a second dielectric film (for example, a silicon nitride film) on the first dielectric film; and a third dielectric film (for example, a second silicon oxide film) on the second dielectric film. The materials of the first silicon oxide film and the second silicon oxide film may be, for example, silicon dioxide (SiO 2 The first silicon oxide film and the second silicon oxide film do not necessarily have to be composed of SiO 2 . Optionally, the composition of the first silicon oxide film may be different from the composition of the second silicon oxide film. If the dielectric layer 4 is configured as a single dielectric film, the material for the dielectric film may be, for example, silicon oxide. The material for the dielectric film is not limited to silicon oxide, and may be, for example, titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, tungsten oxide, niobium oxide, tantalum oxide, or aluminum oxide.

[0052] (2.3) Conductor layer such as Figure 1 As shown, the conductor layer 5 is stacked on the dielectric layer 4. The conductor layer 5 is formed on the dielectric layer 4. When viewed in a top view in a thickness direction D1 defined relative to the silicon substrate 2, the conductor layer 5 overlaps the first area A1, the second area A2, the third area A3 and the eaves portion 27 of the silicon substrate 2.

[0053] The conductor layer 5 may be, for example, a conductive polysilicon layer. The impurity concentration of the conductive polysilicon layer may be, for example, equal to or higher than 1×10 18 cm -3 and equal to or less than 1×10 21 cm -3 , more preferably equal to or higher than 5×10 18 cm -3 and equal to or less than 1×10 20 cm -3 . The dopant introduced into the conductive polysilicon layer includes one selected from the group consisting of, for example, boron, indium, phosphorus, arsenic and antimony. The conductor layer 5 is not limited to the conductive polysilicon layer, but may be, for example, a metal electrode layer. The material for the metal electrode layer includes at least one selected from the group consisting of, for example, ruthenium (Ru), titanium (Ti), tantalum (Ta), tungsten (W) and aluminum (Al). More specifically, the material for the metal electrode layer may be, for example, ruthenium, titanium, tantalum, tungsten, aluminum or an alloy including one of these metals as a main component.

[0054] The conductor layer 5 includes a first conductive portion 51, a second conductive portion 52, a third conductive portion 53, and a fourth conductive portion 54. The first conductive portion 51 covers the surface 231A of the first porous portion 23A. Therefore, the first conductive portion 51 includes a plurality of first columnar portions 511 located within a plurality of first micropores 24 in the first porous portion 23A. The second conductive portion 52 covers the surface 231B of the second porous portion 23B. Therefore, the second conductive portion 52 includes a plurality of second columnar portions 521 located inside a plurality of second micropores 25 in the second porous portion 23B. The third conductive portion 53 covers the main surface 21 in the third area A3. The fourth conductive portion 54 covers the eaves portion 27. Preferably, the fourth conductive portion 54 is connected to at least one of the first conductive portion 51 or the second conductive portion 52 at at least a portion of the inner peripheral edge 541 of the fourth conductive portion 54 in the conductor layer 5, so as to improve the electrical characteristics of the capacitor 1. More preferably, the fourth conductive portion 54 is connected to at least one of the first conductive portion 51 or the second conductive portion 52 over the entire inner peripheral edge 541 of the fourth conductive portion 54 in the conductor layer 5 so as to improve the electrical characteristics of the capacitor 1. In the conductor layer 5 of the capacitor 1 according to the first embodiment, the fourth conductive portion 54 is connected to the first conductive portion 51 and the second conductive portion 52 over the entire inner peripheral edge 541 of the fourth conductive portion 54.

[0055] (2.4) First external connection electrode and second external connection electrode

[0056] The first external connection electrode 7 is connected to the doped layer 3 of the silicon substrate 2, such as Figure 1 and 2 More specifically, the first external connection electrode 7 passes through the portion 42 (refer to Figure 2 ) formed contact hole 47 (reference Figure 2 ) is connected to the first main surface 21 of the silicon substrate 2 and the doped layer 3. The portion 42 is located in the third area A3 of the first main surface 21 of the silicon substrate 2. In the capacitor 1, the first external connection electrode 7 is electrically connected to the doped layer 3 of the silicon substrate 2. As used herein, “the first external connection electrode 7 is electrically connected to the doped layer 3 of the silicon substrate 2” means that the first external connection electrode 7 is in ohmic contact with the doped layer 3 of the silicon substrate 2.

[0057] When viewed in plan view in the thickness direction D1 defined with respect to the silicon substrate 2, the first external connection electrode 7 has, for example, an outer edge in a quadrilateral shape (see Figure 3 ), but this should not be construed as limiting. The outer edge may have, for example, a circular shape. When viewed from above in the thickness direction D1 defined relative to the silicon substrate 2, the first external connection electrode 7 overlaps a portion of the third area A3 of the silicon substrate 2, but does not overlap the first area A1 and the second area A2 of the silicon substrate 2.

[0058] The second external connection electrode 8 is connected to the conductor layer 5. In the capacitor 1, the second external connection electrode 8 is electrically connected to the conductor layer 5. As used herein, “the second external connection electrode 8 is electrically connected to the conductor layer 5” means that the second external connection electrode 8 is in ohmic contact with the conductor layer 5. When viewed from above in the thickness direction D1 defined relative to the silicon substrate 2, the first external connection electrode 8 overlaps a portion of the third area A3 of the silicon substrate 2, but does not overlap the first area A1 and the second area A2 of the silicon substrate 2.

[0059] Examples of materials for the first external connection electrode 7 and the second external connection electrode 8 include, but are not limited to, aluminum, but may also include gold, platinum, and ruthenium. The material for the second external connection electrode 8 may be the same as the material for the first external connection electrode 7, but this should not be construed as limiting. The material for the second external connection electrode 8 may also be different from the material for the first external connection electrode 7.

[0060] The thickness of the first external connection electrode 7 and the second external connection electrode 8 is, for example, equal to or greater than 1 μm and equal to or less than 3 μm. The second external connection electrode 8 may be as thick as the first external connection electrode 7, but this should not be interpreted as limiting. The thickness of the second external connection electrode 8 may be different from the thickness of the first external connection electrode 7.

[0061] (2) Method for manufacturing capacitor

[0062] The method for manufacturing the capacitor 1 includes, for example, a first step, a second step, a third step, a fourth step, a fifth step, a sixth step, a seventh step, and an eighth step. Figure 4A , 4B , 5A, 5B, 6A, 6B and 7 describe a method for manufacturing capacitor 1.

[0063] The first step includes providing a p-type silicon wafer 20 from which the silicon substrate 2 is cut, and then forming an insulating layer 9 on a first main surface 201 of the p-type silicon wafer 20 (see Figure 4A). The p-type silicon wafer 20 has a first main surface 201 and a second main surface 202 opposite to the first main surface 201. The first main surface 201 of the p-type silicon wafer 20 can be, for example, a (100) plane, but this should not be construed as limiting. The first main surface 201 can also be, for example, a (110) plane or a (111) plane. The first main surface 201 of the p-type silicon wafer 20 can be, for example, a crystal plane whose off-axis angle defined relative to the (100) plane is greater than 0 degrees and equal to or less than 5 degrees. As used herein, "off-axis angle" is an inclination angle defined by the first main surface 201 relative to the (100) plane. Therefore, if the off-axis angle is 0 degrees, the first main surface 201 is a (100) plane. When forming the insulating layer 9, a silicon oxide layer is formed on the entire first main surface 201 of the p-type silicon wafer 20 by, for example, thermal oxidation; and then a silicon nitride layer is formed on the silicon oxide layer by, for example, chemical vapor deposition (CVD).

[0064] The second step includes patterning the insulating layer 9 into a predetermined pattern by photolithography and etching techniques (see Figure 4B ). 4B). In this step, the first main surface 201 of the p-type silicon wafer 20 corresponds to the first main surface 21 of the silicon substrate 2. The insulating layer 9 in the predetermined pattern, for example, covers the first main surface 201 of the p-type silicon wafer 20 corresponding to the second area A2 and the third area A3 of the silicon substrate 2, but does not cover the area thereof corresponding to the first area A1.

[0065] The third step includes etching the p-type silicon wafer 20 to a predetermined depth from the first main surface 201 of the p-type silicon wafer 20 using the insulating layer 9 as an etching mask to form a groove, thereby defining the third main surface 28 as the inner bottom surface of the groove (see Figure 5A ). In the third step, dry etching is used to etch the p-type silicon substrate 20, but this should not be construed as limiting. Alternatively, wet etching may also be used.

[0066] The fourth step includes anodizing the p-type silicon wafer 20 using the p-type silicon wafer 20 as an anode to form the p-type silicon wafer 20 having the first porous portion 23A, the second porous portion 23B and the eaves portion 27 and then removing the insulating layer 9 (refer to Figure 5B and 7). In anodization, a platinum electrode is arranged to face the third main surface 28 of the p-type silicon wafer 20 and the insulating layer 9 in an electrolytic solution, and a current having a specified current density is allowed to flow for a predetermined amount of time, wherein the p-type silicon wafer 20 serves as an anode and the platinum electrode serves as a cathode. As a result of the anodizing, the p-type silicon wafer 20 is made porous, thereby forming a first porous portion 23A, a second porous portion 23B and an eaves portion 27. The electrolytic solution may be, for example, a mixture of hydrofluoric acid and ethanol. Note that, before the anodizing, an electrode for anodizing is formed on the second main surface 202 of the p-type silicon wafer 20. The electrode is removed after the anodizing. The electrode may be, for example, a metal film.

[0067] In the fourth step, changing at least one of the concentration of hydrogen fluoride in the electrolytic solution, the prescribed current density, or the predetermined amount of time allows the shape and depth of the plurality of first micropores 24 and the shape and depth of the plurality of second micropores 25 to be controlled. The concentration of hydrogen fluoride in the electrolytic solution may be, for example, equal to or higher than 1 wt% and equal to or lower than 80 wt%, preferably equal to or higher than 20 wt% and equal to or lower than 40 wt%. In addition, according to the method for manufacturing the capacitor 1, the shapes of the plurality of first micropores 24 and the plurality of second micropores 25 may also be changed by changing the resistivity of the p-type silicon wafer 20, which is determined by the impurity concentration of the p-type silicon wafer 20 from which the silicon substrate 2 is cut.

[0068] Note that when wet etching is used as the etching method in the third step, the third step and the fourth step can be performed continuously.

[0069] The fifth step includes forming a doping layer 3 outside the diffusion layer in the p-type silicon wafer 20 (see Fig. 6A ). 6A). That is, the fifth step includes a diffusion step. The diffusion step includes thermally diffusing a p-type dopant (e.g., boron) into the p-type silicon wafer 20, thereby forming the doped layer 3. Thus, the silicon substrate 2 having the first porous portion 23A, the second porous portion 23B, the eaves portion 27, and the doped layer 3 is formed.

[0070] The sixth step includes forming a dielectric layer 4 on the doped layer 3, such as Fig. 6A In the sixth step, a first silicon oxide film of the dielectric layer 4 is formed by, for example, CVD, a silicon nitride film of the dielectric layer 4 is formed by, for example, CVD, and a second silicon oxide film of the dielectric layer 4 is formed by, for example, CVD. Alternatively, the first silicon oxide film may also be formed by thermal oxidation.

[0071] The seventh step includes forming a conductor layer 5 on the dielectric layer 4, such as Figure 6BMore specifically, the seventh step includes first forming a conductor material layer on the dielectric layer 4 as a prototype of the conductor layer 5. In the seventh step, the conductor material layer is formed by, for example, CVD, and then patterned by, for example, photolithography and etching techniques, thereby forming the conductor layer 5 from a portion of the conductor material layer.

[0072] The eighth step includes forming the first external connection electrode 7 and the second external connection electrode 8 (see Figure 1 ). More specifically, the eighth step includes first forming a contact hole 47 through the dielectric layer 4 (refer to Figure 2 ), thereby exposing a portion of the first main surface 21 of the silicon substrate 2. In the eighth step, a contact hole 47 is formed by, for example, photolithography and etching techniques. Thereafter, a first external connection electrode 7 and a second external connection electrode 8 are formed by combining, for example, a thin film forming method, a photolithography technique, and an etching technique. The thin film forming method may be, for example, evaporation, sputtering, or CVD. The eighth step may include heat treatment to allow the first external connection electrode 7 to be in ohmic contact with the doped layer 3.

[0073] In the method for manufacturing the capacitor 1, a second wafer including a plurality of capacitors 1 can be obtained by providing a first wafer (e.g., a silicon wafer) as a p-type silicon wafer 20 in the first step and thereafter performing the first step to the eighth step on the first wafer. In the method for manufacturing the capacitor 1, a plurality of capacitors 1 can be obtained by cutting the second wafer in the eighth step using, for example, a dicing saw or a laser cutting device.

[0074] (4) Advantages

[0075] In the capacitor 1 according to the first embodiment, the silicon substrate 2 has a first region A1, a second region A2, a third region A3, and an eaves portion 27, the first region A1 having a first porous portion 23A formed therein, the second region A2 having a second porous portion 23B formed therein and the second region A2 surrounding the first region A1, the third region A3 surrounding the second region A2, and the eaves portion 27 protruding inward from the third region A3 and overlapping with the second porous portion 23B when viewed from above. In addition, in the capacitor 1 according to the first embodiment, the dielectric layer 4 is arranged to cover the surface 231A of the first porous portion 23A, the surface 231B of the second porous portion 23B, the surface 270 of the eaves portion 27, and the main surface 21 in the third region A3 of the silicon substrate 2. The capacitor 1 satisfies both the first condition and the second condition with respect to the eaves portion 27. The first condition is that the first distance H1, which is the shortest distance between the plane VP1 including the main surface 21 in the third area A3 and the first porous portion 23A in the thickness direction D1 defined relative to the silicon substrate 2, should be longer than the second distance H2, which is the distance between the plane VP1 and the surface 27B of the eaves portion 27 facing the second porous portion 23B in the thickness direction D1 defined relative to the silicon substrate 2. The second condition is a condition that the tip 272 of the eaves portion 27 should be located outside the inner peripheral edge of the second area A2 when viewed from above. Therefore, the capacitance of the capacitor 1 according to the first embodiment can be increased accordingly. More specifically, in the capacitor 1 according to the first embodiment, the capacitance of the capacitor 1 can be increased without increasing the size of the chip because the silicon substrate 2 includes not only the first porous portion 23A but also the second porous portion 23B, and because the dielectric layer 4 and the conductor layer 5 are also formed inside the plurality of second micropores 25 in the second porous portion 23B. Furthermore, the capacitor 1 according to the first embodiment satisfies both the first condition and the second condition with respect to the eaves portion 27, thereby reducing the chance that the openings of the plurality of second micropores 25 of the second porous portion 23B are closed by the eaves portion 27 that is bent during the manufacturing process. Therefore, the capacitor 1 according to the first embodiment makes it easier to form the dielectric layer 4 and the conductor layer 5 within the plurality of second micropores 25 in the second porous portion 23B according to the design, thereby further increasing the capacitance of the capacitor 1.

[0076] Preferably, the first distance H1 is equal to or greater than twice the thickness of the eaves portion 27 so as to reduce the chance that the openings of the plurality of second micropores 25 of the second porous portion 23B are closed by the eaves portion 27. In addition, preferably, the first distance H1 is equal to or less than ten times the thickness of the eaves portion 27 so as to reduce the degree of capacitance reduction.

[0077] In addition, the conductor layer 5 and the fourth conductive portion 54 of the capacitor 1 according to the first embodiment are connected to the first conductive portion 51 and the second conductive portion 52 in at least a portion of the inner peripheral edge 541 of the fourth conductive portion 54. As a result, the capacitor 1 according to the first embodiment can more significantly reduce the resistance of the conductor layer 5, thereby improving the characteristics of the capacitor 1.

[0078] In the conductor layer 5 of the capacitor 1 according to the first embodiment, preferably, the fourth conductive portion 54 is connected to the first conductive portion 51 and the second conductive portion 52 over the entire inner peripheral edge 541 of the fourth conductive portion 54. Therefore, the capacitor 1 according to the first embodiment can reduce the pressure change in the gap under the eaves portion 27 in a step after the conductor layer 5 has been formed during the manufacturing process (for example, during a vacuum process such as evaporation, sputtering, or CVD in the eighth step described above), and thereby reduce the chance of damage to the eaves portion 27.

[0079] Furthermore, the capacitor 1 according to the first embodiment achieves the following advantages: since the silicon substrate 2 includes the doping layer 3, the surface area of ​​the surface 231A of the first porous portion 23A and the surface area of ​​the surface 231B of the second porous portion 23B can be easily increased. More specifically, before forming the doping layer 3, the surface area of ​​the surface 231A of the first porous portion 23A and the surface area of ​​the surface 231B of the second porous portion 23B can be increased by forming the first porous portion 23A and the second porous portion 23B by performing anodizing on the p-type silicon wafer 20 having a lower impurity concentration than the doping layer 3.

[0080] (Second embodiment)

[0081] Will refer to Figure 8 The capacitor 1A according to the second embodiment is described. The capacitor 1A according to the second embodiment has the same structure as the capacitor 1 according to the first embodiment (refer to Figures 1 to 3 ) will be designated by the same figure mark as the counterpart, and its description will be appropriately omitted in this document.

[0082] (1) Configuration

[0083] In the capacitor 1A according to the second embodiment, the eaves portion 27 thereof is shorter than the eaves portion 27 of the capacitor 1 according to the first embodiment when viewed from above, and the distance between the inner peripheral edge of the second area A2 and the tip 272 of the eaves portion 27 is longer than that in the capacitor 1 according to the first embodiment. Therefore, in the capacitor 1A according to the second embodiment, the plurality of second micropores 25 include at least one second micropore 25 having an opening that does not overlap with the eaves portion 27 when viewed from above.

[0084] (2) Manufacturing method

[0085] The manufacturing method of the capacitor 1A according to the second embodiment is substantially the same as the manufacturing method of the capacitor 1 according to the first embodiment. For the manufacturing method of the capacitor 1A according to the second embodiment, descriptions of the same process steps as those of the manufacturing method of the capacitor 1 according to the first embodiment will be omitted.

[0086] The method for manufacturing the capacitor 1A according to the second embodiment includes a first step, a second step, a third step, a fourth step, a fifth step, a sixth step, a seventh step, and an eighth step as well as the method for manufacturing the capacitor 1 according to the first embodiment.

[0087] In the manufacturing method of the capacitor 1A according to the second embodiment, after the anodic treatment has been performed in the fourth step, the eaves portion 27 is patterned to reduce its length, which is different from the manufacturing method of the capacitor 1 according to the first embodiment. For example, when patterning the eaves portion 27, photolithography and etching techniques can be used.

[0088] advantage

[0089] The capacitor 1A according to the second embodiment can improve the ability to form the dielectric layer 4 and the conductor layer 5 inside the plurality of second micropores 25 in the second porous portion 23B, compared with the capacitor 1 according to the first embodiment.

[0090] (Variant)

[0091] Note that the above-mentioned first embodiment and second embodiment and its variants are merely exemplary embodiments among various embodiments and their variants of the present disclosure and should not be interpreted as limiting. On the contrary, the exemplary embodiments and their variants can be easily modified in various ways according to design selection or any other factors without departing from the scope of the present disclosure.

[0092] For example, the conductivity type of the main region 26 and the doping layer 3 of the silicon substrate 2 is not limited to p-type, but may also be n-type. If the conductivity type of the main region 26 and the doping layer 3 of the silicon substrate 2 is n-type, the main region 26 and the doping layer 3 contain, for example, phosphorus (P) as an n-type dopant, but this should not be interpreted as a limitation. Alternatively, the main region 26 and the doping layer 3 may contain arsenic (As) or antimony (Sb) as a dopant. In addition, even in the case where the conductivity type of the main region 26 and the doping layer 3 of the silicon substrate 2 is n-type, the impurity concentration of the doping layer 3 is higher than the impurity concentration of the main region 26. In addition, the carrier concentration of the doping layer 3 is higher than the carrier concentration of the main region 26.

[0093] In the case where the conductivity type of the doping layer 3 and the body region 26 is n-type, the method for manufacturing the capacitor 1 is substantially the same as the method for manufacturing the capacitor 1 according to Embodiment 1. However, in this case, the first step includes providing an n-type silicon wafer instead of the p-type silicon wafer 20. In addition, in the anodizing process, the number of pores inside the n-type silicon wafer is increased by irradiating the n-type silicon wafer with light, and the n-type silicon wafer is cut with light to form the silicon substrate 2, so as to form the first porous portion 23A and the second porous portion 23B.

[0094] Moreover, the capacitor 1 only needs to satisfy at least one of the first condition or the second condition with respect to the eaves portion 27. Therefore, in the capacitor 1, when viewed from above, the tip 272 of the eaves portion 27 can, for example, overlap with or be located within the inner periphery of the second area A2.

[0095] The silicon substrate 2 may be provided with a plurality of circuit components (such as MOSFETs) in addition to the capacitor 1, 1A. That is, the capacitor 1, 1A according to the present disclosure may be applied to a semiconductor device (such as an integrated circuit (IC) chip) including the capacitor 1, 1A.

[0096] (All aspects)

[0097] The first embodiment and the second embodiment and their modifications described above are specific implementations of the following aspects of the present disclosure.

[0098] A capacitor (1; 1A) according to a first aspect includes a silicon substrate (2), a dielectric layer (4) and a conductor layer (5). The silicon substrate (2) has: a first region (A1) in which a first porous portion (23A) is formed; a second region (A2) in which a second porous portion (23B) is formed and the second region (A2) surrounds the first region (A1); a third region (A3) in which the third region (A3) surrounds the second region (A2); and an eaves portion (27) which protrudes inward from the third region (A3) and overlaps with the second porous portion (23B) when viewed from above. The dielectric layer (4) is arranged to cover a surface (231A) of the first porous portion (23A), a surface (231B) of the second porous portion (23B), a surface (270) of the eaves portion (27) and a main surface (21) in the third region (A3) in the silicon substrate (2). A conductor layer (5) is stacked on a dielectric layer (4). A first porous portion (23A) has a plurality of first micropores (24) extending in a thickness direction (D1) defined relative to a silicon substrate (2). In the first porous portion (23A), each pair of first micropores (24) located adjacent to each other belonging to the plurality of first micropores (24) has an uneven spacing (L1) in the thickness direction (D1) defined relative to the silicon substrate (2). A second porous portion (23B) has a plurality of second micropores (25). The spacing between each of the plurality of second micropores (25) and the eaves portion (27) measured in the thickness direction (D1) defined relative to the silicon substrate (2) increases its length as the distance from the first region (A1) increases and the distance from the third region (A3) decreases. The capacitor (1; 1A) satisfies at least one of the first condition or the second condition relative to the eaves portion (27). The first condition is a condition that a first distance (H1) measured in a thickness direction (D1) defined relative to the silicon substrate (2) should be longer than a second distance (H2) measured in a thickness direction (D1) defined relative to the silicon substrate (2) between a plane (VP1) including the main surface (21) in the third region (A3) and a surface (27B) of the eaves portion (27) facing the second porous portion (23B), wherein the first distance is the shortest distance between the plane (VP1) and the first porous portion (23A). The second condition is a condition that a tip (272) of the eaves portion (27) should be located outside the inner peripheral edge of the second region (A2) when viewed from above.

[0099] This aspect allows for increased capacitance.

[0100] In a capacitor (1; 1A) according to the second aspect which can be implemented in combination with the first aspect, the conductor layer (5) includes a first conductive portion (51), a second conductive portion (52), a third conductive portion (53) and a fourth conductive portion (54). The first conductive portion (51) covers a surface (231A) of the first porous portion (23A). The second conductive portion (52) covers a surface (231B) of the second porous portion (23B). The third conductive portion (53) covers the main surface (21) in the third area (A3). The fourth conductive portion (54) covers the eaves portion (27). In the conductor layer (5), the fourth conductive portion (54) is connected to at least one of the first conductive portion (51) or the second conductive portion (52) in at least a portion of an inner peripheral edge (541) of the fourth conductive portion (54).

[0101] This aspect can more significantly reduce the resistance of the conductor layer (5), and thus allows the characteristics of the capacitor (1; 1A) to be improved.

[0102] In a capacitor (1; 1A) according to the third aspect which can be implemented in combination with the second aspect, the fourth conductive portion (54) is connected to at least one of the first conductive portion (51) or the second conductive portion (52) over the entire inner peripheral edge of the fourth conductive portion (54) in the conductor layer (5).

[0103] This aspect can more significantly reduce the resistance of the conductor layer (5), and thus allows the characteristics of the capacitor (1; 1A) to be improved.

[0104] In a capacitor (1; 1A) according to the fourth aspect which can be implemented in combination with any one of the first to third aspects, the distance between the tip (272) of the eaves portion (27) and the second porous portion (23B) measured in the thickness direction (D1) defined relative to the silicon substrate (2) is shorter than the distance between the proximal end (271) of the eaves portion (27) and the second porous portion (23B) measured in the thickness direction (D1) defined relative to the silicon substrate (2).

[0105] This aspect makes it easier to form a conductor layer (5) in which the fourth conductive portion (54) is connected to at least one of the first conductive portion (51) or the second conductive portion (52) at least in a portion of the inner peripheral edge of the fourth conductive portion (54).

[0106] According to the capacitor (1; 1A) of the fifth aspect, it can be implemented in combination with any one of the first to fourth aspects while satisfying the first condition and the second condition.

[0107] This aspect allows for a further increase in capacitance.

[0108] In the capacitor (1; 1A) according to the sixth aspect which can be implemented in combination with any one of the first to fifth aspects, the first distance (H1) is equal to or greater than twice the thickness of the eaves portion (27) and equal to or less than ten times the thickness of the eaves portion (27).

[0109] In the capacitor (1; 1A) according to the seventh aspect which can be implemented in combination with any one of the first to sixth aspects, the silicon substrate (2) has a doping layer (3) containing a p-type dopant or an n-type dopant. The doping layer (3) is formed to have a shape that conforms to the respective shapes of the first porous portion (23A), the second porous portion (23B), the eaves portion (27), and the main surface (21) in the third region (A3).

[0110] This aspect makes it easier to increase the surface area of ​​the surface ( 231A) of the first porous portion ( 23A) and the surface area of ​​the surface ( 231B) of the second porous portion ( 23B).

[0111] In a capacitor (1; 1A) according to the eighth aspect which can be implemented in combination with the seventh aspect, when the doping layer (3) contains a p-type dopant, the p-type dopant is boron or indium, and when the doping layer (3) contains an n-type dopant, the n-type dopant is phosphorus, arsenic or antimony.

[0112] Reference numerals list

[0113] 1. 1A: Capacitor

[0114] 2: Silicon substrate

[0115] 21: First main surface

[0116] 22: Second main surface

[0117] 23: First porous part

[0118] 231A: Surface

[0119] 23B: Second porous portion

[0120] 231B: Surface

[0121] 24: First micropore

[0122] 25: Second micropore

[0123] 27: Easy Parts

[0124] 27B: Surface

[0125] 270: Surface

[0126] 271: Proximal

[0127] 272: Cutting Edge

[0128] 3: Doping layer

[0129] 4: Dielectric layer

[0130] 5: Conductor layer

[0131] 7: First external connection electrode

[0132] 8: Second external connection electrode

[0133] A1: First Area

[0134] A2: Second Area

[0135] A3: The third area

[0136] D1: thickness direction

[0137] H1: First Distance

[0138] H2: Second distance

[0139] L1: Interval

[0140] VP1: Flat

Claims

1. A capacitor, comprising: A silicon substrate having: a first region in which a first porous portion is formed; a second region in which a second porous portion is formed and which surrounds the first region; a third area, the third area surrounding the second area; and an eaves portion which, when viewed from above, protrudes inwardly from the third region and overlaps the second porous portion, a dielectric layer arranged to cover a surface of the first porous portion, a surface of the second porous portion, a surface of the eave portion, and a main surface in the third region in the silicon substrate; as well as a conductor layer, the conductor layer being stacked on the dielectric layer, The first porous portion has a plurality of first micropores extending in a thickness direction defined relative to the silicon substrate, each pair of first micropores adjacent to each other belonging to the plurality of first micropores in the first porous portion has a non-uniform interval in the thickness direction defined with respect to the silicon substrate, The second porous portion has a plurality of second micropores, The interval between each of the plurality of second microholes and the eaves portion measured in the thickness direction defined with respect to the silicon substrate increases in length as the distance from the first region increases and the distance from the third region decreases, and The capacitor satisfies at least one of the first condition or the second condition with respect to the eaves portion, the first condition being a condition that a first distance measured in the thickness direction defined relative to the silicon substrate is longer than a second distance measured in the thickness direction defined relative to the silicon substrate between a plane including the main surface in the third region and a surface of the eaves portion facing the second porous portion, wherein the first distance is the shortest distance between the plane and the first porous portion, The second condition is a condition that the tip of the eaves portion is located outside the inner peripheral edge of the second area when viewed from above.

2. The capacitor according to claim 1, wherein: The conductor layer comprises: a first conductive portion covering the surface of the first porous portion, a second conductive portion covering the surface of the second porous portion, a third conductive portion covering the main surface in the third region, and a fourth conductive portion covering the eaves portion, and In the conductor layer, the fourth conductive portion is connected to at least one of the first conductive portion or the second conductive portion in at least a portion of the inner peripheral edge of the fourth conductive portion.

3. The capacitor according to claim 2, wherein: In the conductor layer, the fourth conductive portion is connected to at least one of the first conductive portion or the second conductive portion over the entire inner peripheral edge of the fourth conductive portion.

4. The capacitor according to any one of claims 1 to 3, wherein: A distance between the tip of the eave portion and the second porous portion measured in the thickness direction defined relative to the silicon substrate is shorter than a distance between the proximal end of the eave portion and the second porous portion measured in the thickness direction defined relative to the silicon substrate.

5. The capacitor according to any one of claims 1 to 4, wherein: The capacitor satisfies both the first condition and the second condition.

6. The capacitor according to any one of claims 1 to 5, wherein: The first distance is equal to or greater than twice the thickness of the eaves portion and equal to or less than ten times the thickness of the eaves portion.

7. The capacitor according to any one of claims 1 to 6, wherein: The silicon substrate has a doping layer including a p-type dopant or an n-type dopant, and The doping layer is formed to have a shape that conforms to respective shapes of the first porous portion, the second porous portion, the eaves portion, and the main surface in the third region.

8. The capacitor according to claim 7, wherein: When the doping layer includes the p-type dopant, the p-type dopant is boron or indium; and When the doping layer includes the n-type dopant, the n-type dopant is phosphorus, arsenic or antimony.

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