Semiconductor device and method of manufacturing semiconductor device

Abstract

Provided is a semiconductor device having an annular trench formed around a through hole, in which reliability is improved. In the present invention, a semiconductor device includes a semiconductor substrate, a through wiring, a back surface insulating film, and a ring-shaped trench. The wiring layer is formed on a surface of the semiconductor substrate. The through hole penetrates through the semiconductor substrate. The through wiring is formed along a side surface of the through hole. The back surface insulating film covers the back surface of the semiconductor substrate with respect to the front surface. The annular trench surrounds the through-hole when viewed from a direction perpendicular to the back surface, and has formed therein a hollow portion blocked by the back surface insulating film when viewed from a direction parallel to the back surface.

Description

Technical Field

[0001] The present technology relates to a semiconductor device. Specifically, the present invention relates to a semiconductor device having a through electrode formed therein and a method of manufacturing the semiconductor device. Background Art

[0002] In recent years, in various semiconductor devices, for the purpose of further higher integration, research and development of three-dimensional integration technology using through electrodes has been developed. In the case where the through electrodes are formed on a semiconductor substrate such as silicon, parasitic capacitance is formed between the through electrodes and the semiconductor substrate, and signal transmission performance may be degraded. Therefore, a semiconductor device is proposed in which an annular groove is formed around a through hole in the through electrode to separate the conductor in the through hole from the surroundings (for example, see Patent Document 1).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-251539 Summary of the invention

[0006] Problems to be solved by the present invention

[0007] In the above conventional technology, the conductors in the through hole are separated by the ring-shaped groove, thereby reducing the parasitic capacitance and improving the reliability of the through electrode. However, in the above semiconductor device, it is difficult to further improve the reliability represented by the yield rate and the like.

[0008] The present invention has been made in view of such circumstances, and an object thereof is to improve the reliability of a semiconductor device having a ring-shaped trench formed around a through hole.

[0009] Solution to the problem

[0010] The present technology has been made to solve the above-mentioned problems, and its first aspect is a semiconductor device and a method for manufacturing the semiconductor device, the semiconductor device including: a semiconductor substrate having a wiring layer formed on the front surface of the semiconductor substrate; a through hole penetrating the semiconductor substrate; a through wiring formed along the side surface of the through hole; and an annular groove surrounding the periphery of the through hole as viewed from a direction perpendicular to the rear surface of the semiconductor substrate relative to the front surface. This brings about an effect of improving reliability.

[0011] In addition, in the first aspect, a cavity may be formed inside the annular groove when viewed from a direction parallel to the rear surface, which results in an effect of reducing parasitic capacitance.

[0012] In addition, the first aspect may further include a rear surface insulating film covering the rear surface of the semiconductor substrate relative to the front surface, wherein the rear surface insulating film may include a first rear surface insulating film and a second rear surface insulating film stacked, and the second rear surface insulating film may cover the rear surface and cover the sidewall of at least one of the through hole and the annular groove. This brings about the effect of improving the insulation characteristics and the tolerance to mechanical stress.

[0013] Furthermore, the first aspect may further include a first element isolation region formed around the bottom of the through hole. This brings about an effect of suppressing the formation of a notch or a tailing shape.

[0014] In addition, in the first aspect, the second rear surface insulating film may include a fixed charge film. This brings about an effect of reducing the influence of defects on the interface and the front surface.

[0015] In addition, in the first aspect, the through hole may include a first through hole and a second through hole, an annular groove may be formed around the first through hole, and no annular groove may be formed around the second through hole. This brings about the effect of achieving signal transmission performance and integration.

[0016] In addition, in the first aspect, the through hole may include a first through hole and a second through hole arranged adjacent to each other in a direction parallel to the rear surface, the annular groove may include a first annular groove formed around the first through hole and a second annular groove formed around the second through hole, and the first annular groove may share a portion with the second annular groove. This brings about an effect of reducing the pitch of the through electrodes.

[0017] Furthermore, in the first aspect, the width of the portion shared by the first and second annular grooves may be substantially the same as the width of the portion not shared. This brings about the effect of reducing variations in the amount of entry of the rear surface insulating film into the annular groove.

[0018] In addition, the first aspect may further include: a rear surface insulating film covering the rear surface of the semiconductor substrate relative to the front surface; and a rear surface rewiring formed in the rear surface along the periphery of the through hole and the rear surface insulating film. This brings about an effect that the through electrode is electrically connected via the rear surface rewiring.

[0019] In addition, in the first aspect, the outer periphery of the rear surface rewiring formed around the through hole can be larger than the outer periphery of the ring-shaped groove. This brings about the effect of improving the reliability of the wiring.

[0020] In addition, in the first aspect, the width of the portion of the rear surface rewiring that crosses the annular groove can be thicker than the other portions. This brings about the effect of improving the reliability of the wiring.

[0021] In addition, in the first aspect, an opening having a larger periphery than the periphery of the through hole can be formed in the rear surface insulating film, and the rear surface rewiring around the through hole can cover the rear surface inside the opening. This brings about the effects of reducing stress and increasing yield.

[0022] Furthermore, the first aspect may further include: an on-chip lens; a photoelectric conversion unit; and an external terminal. This brings about an effect that the semiconductor device functions as a solid-state imaging device.

[0023] Furthermore, the first aspect may further include a rear surface insulating film covering a rear surface of the semiconductor substrate relative to the front surface, wherein an end portion of the rear surface insulating film may include a tapered shape. This brings about an effect of improving reliability.

[0024] In addition, in the first aspect, the diameter of the through hole may be 1.5 to 4.0 times the width of the annular groove. This brings about an effect of reducing the manufacturing cost.

[0025] In addition, in the first aspect, the diameter of the through hole may be 2.0 to 3.0 times the width of the annular groove. This brings about an effect of reducing the manufacturing cost.

[0026] In addition, the first aspect may further include a solder mask covering the insulating film and the through hole, wherein a cavity blocked by the solder mask may be formed inside the through hole when viewed from a direction parallel to the rear surface. This brings about an effect of improving reliability.

[0027] In addition, the first aspect may further include a low-k material formed between the through hole and the annular trench and having a dielectric constant lower than that of the semiconductor substrate. This brings about an effect of facilitating high integration.

[0028] In addition, the first aspect may further include a rear surface insulating film covering the rear surface of the semiconductor substrate relative to the front surface and covering the annular groove, wherein the solder mask may further cover the rear surface insulating film. This brings about the effect of facilitating high integration.

[0029] Furthermore, in the first aspect, the low-k material may cover the rear surface of the semiconductor substrate relative to the front surface, and the solder mask may also cover the low-k material and the ring-shaped groove. This brings about the effect that a rear surface insulating film is not required.

[0030] Furthermore, the first aspect may further include an element isolation region formed between the wiring layer and the ring-shaped trench. This brings about an effect that the degree of freedom in layout of the wiring layer is improved and the integration degree of the semiconductor element is improved.

[0031] In addition, in the first aspect, the wiring layer may include a dummy gate formed between the through hole and the ring-shaped trench. This brings about an effect of reducing the forbidden area of ​​the gate electrode.

[0032] In addition, the first aspect may further include: a rear surface insulating film covering the rear surface of the semiconductor substrate relative to the front surface; and an insulating reinforcement film adjacent to the wiring layer and covering the periphery of the through hole. This brings about an effect of suppressing the peeling of the semiconductor substrate.

[0033] In addition, in the first aspect, the through hole may have a step at a predetermined depth position as viewed from a direction parallel to the rear surface, the rear surface insulating film may cover the periphery of the through hole in a range from the rear surface to the depth position, and the reinforcing film may cover the periphery of the through hole in a range from the depth position to the wiring layer, and is formed between the base material of the semiconductor substrate and the through hole as viewed from a vertical direction. This brings about an effect of suppressing peeling of the semiconductor substrate.

[0034] Furthermore, in the first aspect, the cross-sectional shape of each of the through hole and the reinforcing film viewed from a parallel direction may have a curved taper, which brings about an effect of facilitating adjustment of the cross-sectional shape during back engraving.

[0035] In addition, in the first aspect, the through hole may have a step at a predetermined depth position when viewed from a direction parallel to the rear surface, the reinforcement film may cover the periphery of the through hole in a range from the depth position to the wiring layer, and the rear surface insulating film may cover the periphery of the through hole and the periphery of the reinforcement film. This brings about the effect of suppressing the peeling of the semiconductor substrate.

[0036] In addition, in the first aspect, the shape of the through hole may include a circle or a polygon when viewed in the vertical direction. This brings about an effect of suppressing the peeling of the semiconductor substrate.

[0037] In addition, in the first aspect, the through hole can cover the entire periphery of the through hole when viewed from the vertical direction. This brings about an effect of suppressing the peeling of the semiconductor substrate.

[0038] In addition, in the first aspect, the reinforcing film may cover part of the periphery of the through hole when viewed from the vertical direction. This brings about an effect of suppressing parasitic capacitance.

[0039] In addition, in the first aspect, the base material of the semiconductor substrate may have a step at a predetermined depth position when viewed from a direction parallel to the rear surface, the rear surface insulating film may cover the periphery of the through hole in a range from the rear surface to the depth position, and the reinforcement film may cover the periphery of the through hole in a range from the depth position to the wiring layer. This brings about the effect that there is no need to provide a step in the through hole.

[0040] In addition, the first aspect may further include a first protective member disposed adjacent to the wiring layer in the ring-shaped groove. This brings about an effect of suppressing peeling of the semiconductor substrate.

[0041] In addition, in the first aspect, the first protective member may include an insulating resin or an inorganic film. This brings about an effect of suppressing peeling of the semiconductor substrate.

[0042] In addition, in the first aspect, the shape of the first protective member may be recessed toward the wiring layer side when viewed from a direction parallel to the rear surface. This brings about an effect of facilitating high-speed transmission.

[0043] In addition, in the first aspect, the first protective member may cover both corners on the inner and outer peripheral sides of the annular groove. This brings about an effect of suppressing the separation of the semiconductor substrate.

[0044] In addition, in the first aspect, the first protective member may cover only the corners on the inner peripheral side of the annular groove. This brings about an effect of facilitating high-speed transmission.

[0045] In addition, the first aspect may further include a second protective member disposed adjacent to the wiring layer in the through hole. This brings about an effect of suppressing peeling of the semiconductor substrate.

[0046] In addition, the first aspect may further include a rear surface insulating film covering the rear surface of the semiconductor substrate relative to the front surface, wherein the width of the annular groove on the wiring layer side may be narrower than the width of the annular groove on the rear surface insulating film side. This brings about the effect of not requiring a protective member.

[0047] In addition, in the first aspect, the cross-sectional shape of the annular groove viewed from a direction parallel to the rear surface may have a taper. This brings about an effect that a protective member is not required.

[0048] In addition, in the first aspect, the corners of the annular groove can be rounded when viewed from a direction parallel to the rear surface. This brings about the effect that a protective member is not required.

[0049] Furthermore, in the first aspect, the corner portion may be located in the wiring layer. This brings about an effect of suppressing peeling of the semiconductor substrate.

[0050] In addition, in the first aspect, the corner portion may straddle the boundary between the semiconductor substrate and the wiring layer. This brings about an effect of suppressing the separation of the semiconductor substrate.

[0051] In addition, in the first aspect, only the corners on the inner circumference side of the inner circumference and the outer circumference of the annular groove may be rounded. This brings about an effect of suppressing the separation of the semiconductor substrate.

[0052] In addition, the first aspect may further include: an insulating film formed between the annular trench and the through hole; and an annular depletion layer formed in the insulating film. This brings about an effect of improving the reliability of the device.

[0053] Furthermore, in the first aspect, the insulating film may have a predetermined number of openings formed at the end of the depletion layer. This brings about an effect of removing the ring-shaped silicon.

[0054] In addition, in the first aspect, a hole as an opening may be formed at the end portion. This brings about an effect of removing the ring-shaped silicon.

[0055] In addition, in the first aspect, a slit as an opening may be formed at the end portion. This brings about an effect of removing the ring-shaped silicon.

[0056] In addition, the first aspect may further include a conductive metal embedded in the annular groove. This brings about the effect of improving the strength of the semiconductor substrate.

[0057] In addition, in the first aspect, the potential of the through wiring may be different from the potential of the conductive metal. This brings about an effect of blocking electromagnetic waves from the outside.

[0058] In addition, in the first aspect, a first insulating film covering the side surface of the ring-shaped groove may be further included. This brings about an effect of insulating the conductive metal.

[0059] In addition, the first aspect may further include a second insulating film covering the side surface of the through hole. This brings about an effect of insulating the through wiring.

[0060] In addition, the first aspect may further include: a first barrier metal covering the side surface of the annular groove; and a second barrier metal covering the side surface of the through hole, wherein each of the first barrier metal and the second barrier metal may include any one of titanium, titanium nitride, tantalum, tantalum nitride and ruthenium. This brings about the effect of improving reliability.

[0061] Furthermore, in the first aspect, the conductive metal may include any one of copper, aluminum, tungsten, cobalt, silver, gold, iron, and lead. This brings about an effect of blocking electromagnetic waves from the outside.

[0062] In addition, in the first aspect, the annular trench may include a first annular trench and a second annular trench formed between the first annular trench and the through hole. This brings about an effect of reducing parasitic capacitance.

[0063] In addition, in the first aspect, the conductive metal may include a first conductive metal embedded in the first annular groove and a second conductive metal embedded in the second annular groove, and the second conductive metal may be of a different kind from the first conductive metal. This brings about the effect of blocking various electromagnetic waves. BRIEF DESCRIPTION OF THE DRAWINGS

[0064] Figure 1 is a cross-sectional view showing a configuration example of a semiconductor device according to a first embodiment of the present technology.

[0065] Figure 2 2 is an example of a cross-sectional view and a top view of a semiconductor device according to a first embodiment of the present technology.

[0066] Figure 3 It is a diagram for explaining the manufacturing method until the etching is completed according to the first embodiment of the present technology.

[0067] Figure 4 It is a diagram for explaining the manufacturing method up to the formation of a solder mask according to the first embodiment of the present technology.

[0068] Figure 5 is a flowchart showing a method for manufacturing a semiconductor device according to a first embodiment of the present technology.

[0069] Figure 6 is an example of a cross-sectional view of a semiconductor device in which a taper is formed at an end portion of a rear surface insulating film according to the first embodiment of the present technology.

[0070] Figure 7 is an example of a cross-sectional view of a semiconductor device in which a ring-shaped trench is filled with a rear surface insulating film according to the first embodiment of the present technology.

[0071] Figure 8 is a cross-sectional view showing a configuration example of a semiconductor device according to a second embodiment of the present technology.

[0072] Fig. 9 is a cross-sectional view showing a configuration example of a semiconductor device according to a third embodiment of the present technology.

[0073] Fig.10 It is a diagram for explaining a manufacturing method according to a third embodiment of the present technology.

[0074] Fig.11 is an example of a cross-sectional view of a semiconductor device 100 according to a fourth embodiment of the present technology.

[0075] Fig.12 is a cross-sectional view showing a configuration example of a semiconductor device according to a fifth embodiment of the present technology.

[0076] Fig.13 is an example of a top view of a semiconductor device according to a fifth embodiment of the present technology.

[0077] Fig.14 is an example of a top view of a semiconductor device according to a sixth embodiment of the present technology.

[0078] Fig.15 is a cross-sectional view showing a configuration example of a semiconductor device according to a seventh embodiment of the present technology.

[0079] Fig.16 is an example of a top view of a semiconductor device according to a seventh embodiment of the present technology.

[0080] Fig.17 is a cross-sectional view showing a configuration example of a semiconductor device according to an eighth embodiment of the present technology.

[0081] Fig.18 is a cross-sectional view showing a configuration example of a semiconductor device according to a ninth embodiment of the present technology.

[0082] Fig.19 It is a cross-sectional view of the semiconductor device according to the ninth embodiment of the present technology viewed from another direction.

[0083] Fig. 20 It is a diagram for explaining a method for manufacturing an opening up to a semiconductor substrate according to a ninth embodiment of the present technology.

[0084] Fig.21 It is a diagram for explaining a manufacturing method up to etching back according to a ninth embodiment of the present technology.

[0085] Fig. 22 It is a diagram for explaining a method of manufacturing an opening up to a rear surface insulating film according to a ninth embodiment of the present technology.

[0086] Fig.23 It is a diagram for explaining a manufacturing method up to formation of a solder mask according to a ninth embodiment of the present technology.

[0087] Fig.24 It is a diagram for explaining a manufacturing method up to formation of a groove according to a ninth embodiment of the present technology.

[0088] Fig.25 It is a diagram for explaining a manufacturing method up to formation of a wiring layer according to a ninth embodiment of the present technology.

[0089] Fig.26 It is a diagram for explaining a manufacturing method up to formation of a rear surface insulating film according to a ninth embodiment of the present technology.

[0090] Fig. 27 It is a diagram for explaining a manufacturing method up to rewiring according to a ninth embodiment of the present technology.

[0091] Fig.28 It is a cross-sectional view of a semiconductor device in the case where a ring-shaped trench is provided according to a ninth embodiment of the present technology.

[0092] Fig.29 : is a cross-sectional view showing a configuration example of a semiconductor device in a first modification example of the ninth embodiment of the present technology.

[0093] Fig.30 is a cross-sectional view showing a configuration example of a semiconductor device in a second modification example of the ninth embodiment of the present technology.

[0094] Fig.31 It is a cross-sectional view showing a configuration example of a semiconductor device in a third modification example of the ninth embodiment of the present technology.

[0095] Fig.32 It is a diagram for explaining a method for manufacturing an opening up to a semiconductor substrate in the third modification example of the ninth embodiment of the present technology.

[0096] Fig.33 It is a diagram for explaining a manufacturing method of film formation up to a reinforcement film in the third modification example of the ninth embodiment of the present technology.

[0097] Fig.34 It is a diagram for explaining a method of manufacturing an opening up to a rear surface insulating film in a third modification example of the ninth embodiment of the present technology.

[0098] Fig.35 It is a diagram for explaining the manufacturing method up to the formation of a solder mask in the third modification example of the ninth embodiment of the present technology.

[0099] Fig.36 is a cross-sectional view showing a configuration example of a semiconductor device in a fourth modification example of the ninth embodiment of the present technology.

[0100] Fig.37 is a cross-sectional view showing a configuration example of a semiconductor device in a fifth modification example of the ninth embodiment of the present technology.

[0101] Fig.38 is a cross-sectional view showing a configuration example of a semiconductor device according to a tenth embodiment of the present technology.

[0102] Fig.39 It is a diagram for explaining the effects of the semiconductor device according to the tenth embodiment of the present technology.

[0103] Fig.40 It is a diagram for explaining a manufacturing method until etching is completed according to a tenth embodiment of the present technology.

[0104] Fig.41 It is a diagram for explaining a manufacturing method up to formation of a resin according to a tenth embodiment of the present technology.

[0105] Fig.42 It is a diagram for explaining a manufacturing method up to rewiring according to a tenth embodiment of the present technology.

[0106] Fig.43 is a cross-sectional view showing an arrangement example of resin according to a tenth embodiment of the present technology.

[0107] Fig.44 1 is an example of a cross-sectional view of a semiconductor device provided with an inorganic film according to a tenth embodiment of the present technology.

[0108] Fig.45 is a cross-sectional view showing a configuration example of a semiconductor device in a first modification example of the tenth embodiment of the present technology.

[0109] Fig.46 This is an example of an enlarged view of a semiconductor device in a first modification example of the tenth embodiment of the present technology.

[0110] Fig.47 is a cross-sectional view showing a configuration example of a semiconductor device in a second modification example of the tenth embodiment of the present technology.

[0111] Fig.48 This is an example of an enlarged view of a semiconductor device in a second modification of the tenth embodiment of the present technology.

[0112] Fig.49 This is an example of an enlarged view of a semiconductor device in a comparative example.

[0113] Fig.50 This is another example of the enlarged view of the semiconductor device in the second modification example of the tenth embodiment of the present technology.

[0114] Fig.51 is a cross-sectional view showing a configuration example of a semiconductor device according to an eleventh embodiment of the present technology.

[0115] Fig.52 is an example of a cross-sectional view of the semiconductor device according to the eleventh embodiment of the present technology viewed from another direction.

[0116] Fig.53 It is a diagram for explaining a method for manufacturing an opening up to a semiconductor substrate according to an eleventh embodiment of the present technology.

[0117] Fig.54 It is a diagram for explaining a method of manufacturing an opening up to an insulating film according to an eleventh embodiment of the present technology.

[0118] Fig.55 It is a diagram for explaining a manufacturing method up to coating and exposure of a rear surface insulating film according to an eleventh embodiment of the present technology.

[0119] Fig.56 It is a diagram for explaining a manufacturing method up to rewiring according to the eleventh embodiment of the present technology.

[0120] Fig.57 This is an example of a cross-sectional view of a semiconductor device in a first modification example of the eleventh embodiment of the present technology.

[0121] Fig.58 This is an example of a cross-sectional view of a semiconductor device in a second modification example of the eleventh embodiment of the present technology.

[0122] Fig.59 : is a diagram showing an example of forming an ideal through hole according to the second embodiment of the present technology.

[0123] Fig.60 : is a diagram showing an example of creating a notch according to the second embodiment of the present technology.

[0124] Fig.61 : is a diagram showing an example in which silicon according to the second embodiment of the present technology has a tailing shape.

[0125] Fig.62 is an example of a cross-sectional view of a semiconductor device before formation of a through hole according to a twelfth embodiment of the present technology.

[0126] Fig.63 It is a diagram for explaining a method for manufacturing a semiconductor device until etching back according to a twelfth embodiment of the present technology.

[0127] Fig.64 It is an enlarged view of the vicinity of the element isolation region according to the twelfth embodiment of the present technology.

[0128] Fig.65 This is an example of a cross-sectional view of a semiconductor device in a first modification example of the twelfth embodiment of the present technology.

[0129] Fig.66 This is an example of a cross-sectional view of a semiconductor device in a second modification example of the twelfth embodiment of the present technology.

[0130] Fig.67 is a cross-sectional view showing a configuration example of a semiconductor device according to a thirteenth embodiment of the present technology.

[0131] Fig.68 It is a diagram for explaining a manufacturing method up to exposure according to a thirteenth embodiment of the present technology.

[0132] Fig.69 It is a diagram for explaining a manufacturing method up to ion implantation according to a thirteenth embodiment of the present technology.

[0133] Fig.70 It is a diagram for explaining a manufacturing method up to formation of a solder mask according to a thirteenth embodiment of the present technology.

[0134] Fig.71 It is a cross-sectional view showing a configuration example of a semiconductor device in a modification example of the thirteenth embodiment of the present technology.

[0135] Fig.72 It is a diagram for explaining a manufacturing method up to coating of a low-k material in a modification example of the thirteenth embodiment of the present technology.

[0136] Fig.73 It is a diagram for explaining a method of manufacturing an opening extending to a pad in a modification example of the thirteenth embodiment of the present technology.

[0137] Fig.74 It is a diagram for explaining a manufacturing method up to formation of a solder mask in a modification example of the thirteenth embodiment of the present technology.

[0138] Fig.75 is a cross-sectional view showing a configuration example of a semiconductor device according to a fourteenth embodiment of the present technology.

[0139] Fig.76 is an example of a cross-sectional view of the semiconductor device taken along line segments A1 - A2 and B1 - B2 according to the fourteenth embodiment of the present technology.

[0140] Fig.77 is an example of a cross-sectional view of a semiconductor device taken along a line segment C1 - C2 according to a fourteenth embodiment of the present technology.

[0141] Fig.78 It is a diagram for explaining a method of manufacturing a semiconductor device up to first coating of an insulating film according to a fourteenth embodiment of the present technology.

[0142] Fig.79 It is a diagram for explaining a method for manufacturing a semiconductor device up to the second coating of an insulating film according to a fourteenth embodiment of the present technology.

[0143] Fig.80 It is a diagram for explaining a method for manufacturing a semiconductor device until formation of a solder mask according to a fourteenth embodiment of the present technology.

[0144] Fig.81 It is a cross-sectional view showing a configuration example of a semiconductor device in a first modification example of the fourteenth embodiment of the present technology.

[0145] Fig.82 It is an example of a cross-sectional view of the semiconductor device taken along line segments A1 - A2 and B1 - B2 in the first modification example of the fourteenth embodiment of the present technology.

[0146] Fig.83This is an example of a cross-sectional view of the semiconductor device taken along the line segment C1 - C2 in the first modification example of the fourteenth embodiment of the present technology.

[0147] Fig.84 It is a cross-sectional view showing a configuration example of a semiconductor device in a second modification example of the fourteenth embodiment of the present technology.

[0148] Fig.85 It is an example of a cross-sectional view of the semiconductor device taken along line segments A1 - A2 and B1 - B2 in the second modification example of the fourteenth embodiment of the present technology.

[0149] Fig.86 This is an example of a cross-sectional view of the semiconductor device taken along the line segment C1 - C2 in the second modification example of the fourteenth embodiment of the present technology.

[0150] Fig.87 is a block diagram depicting a schematic configuration example of a vehicle control system.

[0151] Fig.88 is a diagram to help explain an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0152] Modes for carrying out the present technology (hereinafter referred to as embodiments) will be described below. The description will be given in the following order.

[0153] 1. First Embodiment (Example in which the Cavity is Provided in an Annular Groove)

[0154] 2. Second Embodiment (Example in which a cavity is provided in an annular groove and a rear surface insulating film is formed in two layers)

[0155] 3. Third Embodiment (Examples of Arranging Through Electrodes Having Cavities in Annular Grooves and Through Electrodes Without Annular Grooves)

[0156] 4. Fourth Embodiment (Example in which the cavity is provided in the annular groove and the adjacent through-electrodes share a common portion)

[0157] 5. Fifth Embodiment (Example in which a cavity is provided in an annular groove and the annular groove is covered with rear surface rewiring)

[0158] 6. Sixth Embodiment (Example in which a cavity is provided in an annular groove and a portion of the rear surface is rewired to be thicker)

[0159] 7. Seventh Embodiment (Example in which a cavity is provided in an annular groove and the rear surface redistribution wiring covers the inner side of the rear surface insulating film)

[0160] 8. Eighth Embodiment (Example in which a structure in which a cavity is provided in an annular groove is applied to a solid-state imaging device)

[0161] 9. Ninth Embodiment (Example in which the cavity is provided in the annular groove and the through hole is covered with the reinforcement film)

[0162] 10. Tenth Embodiment (Example in which the cavity is provided in the annular groove and the resin is arranged in the annular groove)

[0163] 11. Eleventh Embodiment (Example in which a cavity is provided in a ring-shaped trench and a depletion layer is formed in an insulating film)

[0164] 12. Twelfth Embodiment (Example in which the cavity is provided in the annular groove and the element isolation region is arranged in an annular shape)

[0165] 13. Thirteenth Embodiment (Example in which the cavity is provided in an annular groove and an annular low-k material is arranged)

[0166] 14. Fourteenth Embodiment (Example in which a conductive metal is embedded in an annular groove)

[0167] 15. Application examples of mobile objects

[0168] <1. First Embodiment>

[0169] [Configuration Example of Semiconductor Device]

[0170] Figure 1 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to an embodiment of the present technology. The cross-sectional view is an enlarged view near the through electrode 149 of the semiconductor device 100. The semiconductor device 100 includes a semiconductor substrate 140. A semiconductor element (not shown) and a wiring layer 150 are formed on one of the two surfaces of the semiconductor substrate 140. Of the two surfaces of the semiconductor substrate 140, the surface on which the wiring layer 150 is formed is hereinafter referred to as the "front surface", and the other surface is hereinafter referred to as the "rear surface". The direction from the front surface to the rear surface is defined as the "upward" direction. In addition, the semiconductor device 100 is used as a signal processing circuit, a memory, an image sensor, etc., and its type is not limited.

[0171] Hereinafter, an axis perpendicular to the substrate plane (front surface or rear surface) of the semiconductor substrate 140 is referred to as a "Z axis", and a predetermined axis parallel to the surface is referred to as an "X axis". An axis perpendicular to the X axis and the Z axis is referred to as a "Y axis". The figure is a cross-sectional view viewed from the Y axis direction.

[0172] In addition, the through electrode 149 is formed on the semiconductor substrate 140. The through electrode 149 includes: a through hole 141 penetrating the semiconductor substrate 140; a through wiring 122 formed along the side surface of the through hole 141; and an annular groove 142 surrounding the periphery of the through hole as viewed from the Z-axis direction. In the X-axis direction, coordinates X1 to X8 correspond to the outer diameter of the annular groove 142 (i.e., the diameter of the through electrode 149). In addition, coordinates X2 to X7 correspond to the inner diameter of the annular groove 142. Coordinates X4 to X5 correspond to the diameter of the through hole 141.

[0173] In addition, the through wiring 122 is connected to the pad 152 formed in the wiring layer 150 on the front surface side and the rear surface rewiring 121 wired on the rear surface. As the material of the through wiring 122, copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), nickel (Ni), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc. are used. Note that the through wiring 122 may have a structure in which a plurality of materials are stacked.

[0174] From the viewpoint of reliability and ease of manufacturing, the aspect ratio of the depth to the width of the annular groove 142 as viewed in the X-axis direction or the Y-axis direction is preferably about 3 to 20. In addition, the diameter of the through hole 141 is preferably 1.5 to 4.0 times, and most preferably 2.0 to 3.0 times, the width of the annular groove 142. As a result, since the through hole 141 and the annular groove 142 can be processed at approximately the same speed during dry etching, they can be formed in the same process.

[0175] In addition, the annular groove 142 and the through hole 141 may not have the same size in the semiconductor device 100. In the signal wiring where the parasitic capacitance is desired to be as small as possible, the width of the annular groove 142 may be increased, and in the portion where it is desired to increase the integration of the through electrode 149, the width of the annular groove 142 may be reduced. This makes it possible to achieve the performance and integration of the through electrode 149.

[0176] In addition, a notch 144 is formed at the bottom of the through hole 141 and a notch 145 is formed at the bottom of the annular groove 142 , with the ends of the through hole 141 and the annular groove 142 on the front surface side serving as the bottom.

[0177] The processing shapes of the through hole 141 and the annular groove 142, such as the processing angle and the notch size of the bottom, can be different. In the case where the through hole 141 has a smaller forward taper or notch, it is beneficial to form the through wiring 122. On the other hand, reducing the forward taper or notch of the annular groove 142 is beneficial to the mechanical stress applied to the annular groove 142. In addition, the processing angle can be changed from the middle of the annular groove 142 or the through hole 141.

[0178] The rear surface insulating film 131 is formed to cover the entire rear surface of the semiconductor substrate 140 and a portion of the through electrode 149. A cavity blocked by the rear surface insulating film 131 is formed inside the annular groove 142 when viewed from the Y-axis direction.

[0179] As the rear surface insulating film 131, a photosensitive insulating film consisting of an organic material having a skeleton of polyimide, acrylic acid, silicone, or epoxy can be formed by photolithography. This makes it possible to simplify the manufacturing process, as will be described later. The rear surface insulating film 131 can be composed of a single material, or multiple materials can be stacked as described later. In addition, it can have a stacked structure of an inorganic film. Observed from the Z-axis direction, the area of ​​the rear surface insulating film 131 covering the through electrode 149 is preferably about 20% to 80% (percentage) of the through electrode, and is expected to be 30% to 65% (percentage).

[0180] In order to adjust the area of ​​the through-electrode 149 covered by the rear surface insulating film 131, an opening slightly larger than the diameter of the through-hole 141 is formed at a portion of the through-hole 141 in the rear surface insulating film 131 as viewed from the Z-axis direction. With this structure, a step is generated in the rear surface insulating film 131 as viewed from the Y-axis direction. In the figure, a step is generated between the coordinates X3 and X6.

[0181] In addition, part of the rear surface insulating film 131 may enter the interior of the annular groove 142. In addition, the entered rear surface insulating film 131 may have a dome shape when viewed from the X-axis direction or the Y-axis direction. For example, from the viewpoints of yield, reliability, and parasitic capacitance, the entry depth of the groove is preferably 5% to 40% (percentage).

[0182] The rear surface rewiring 121 is formed along the periphery of the through hole 141 and the side surface and the upper surface of the rear surface insulating film 131. Since there is a step on the rear surface insulating film 131, the rear surface rewiring 121 also generates a step. The through wiring 122 and the rear surface rewiring 121 can be formed by the same process. In the case of being formed by the same process, there is no bonding surface with the through wiring 122, which is advantageous from the viewpoint of resistance and reliability. As the material of the rear surface rewiring 121, copper (Cu), titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), nickel (Ni), ruthenium (Ru), cobalt (Co), titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), etc. are used. Note that the rear surface rewiring 121 can have a structure in which multiple materials are stacked.

[0183] In addition, a solder mask 110 is formed as a protective film on the upper surfaces of the rear surface redistribution wiring 121 and the rear surface insulating film 131. Part of the solder mask 110 enters the through hole 141, and a cavity blocked by the solder mask 110 is formed inside the through hole 141. As shown in the figure, from the viewpoint of yield and reliability, the penetration depth of the part of the through hole 141 is preferably about 5% to 40% (percentage).

[0184] In addition, on the front surface side of the semiconductor substrate 140, an element isolation region 143 (shallow trench isolation (STI)) is formed between the annular groove 142 and the wiring layer 150 as needed. Note that the element isolation region 143 is an example of a second element isolation region described in the claims. In the figure, the STI is only arranged directly below the annular groove 142, but the present disclosure is not limited to this configuration. For example, the STI can be further arranged between the annular groove 142 and the through hole 141 (coordinates X2 to X4 and coordinates X5 to X7). Thus, the through hole 141 can be formed by self-alignment. The STI can also be formed between the annular groove 142 and the through hole 141. In addition, in the wiring layer 150, a dummy gate 151 is formed near the annular groove 142 as needed. For example, the dummy gate 151 is formed in the lower part of the annular groove 142 and between the through hole 141 and the annular groove 142. When the STI is arranged at the bottom of the annular trench 142 , the STI functions as an etching stopper, so that the layout freedom of the wiring layer 150 is improved and the integration degree of the semiconductor element is improved.

[0185] Furthermore, the pad 152 in the wiring layer 150 may be formed only inside the ring-shaped groove 142. As a result, the parasitic capacitance between the pad 152 and the semiconductor substrate 140 can be reduced.

[0186] In addition, the pseudo gate 151 is arranged between the through hole 141 and the annular groove 142, so that the forbidden area of ​​the gate electrode can be reduced. This improves the flatness when the wiring layer 150 is formed on the front surface, and specifically, in the whole process, fine wiring can be arranged near the through electrode 149. The pseudo gate 151 can be composed of polysilicon, amorphous silicon or other materials.

[0187] In summary, the through hole 141 penetrates the semiconductor substrate 140 having the wiring layer 150 formed on the front surface, and the through wiring 122 is formed along the side surface of the through hole 141. When viewed from the Z-axis direction perpendicular to the rear surface, the annular groove 142 is formed to surround the periphery of the through hole 141. The rear surface insulating film 131 covers the rear surface of the semiconductor substrate 140, and when viewed from the X-axis direction and the Y-axis direction parallel to the rear surface, a cavity blocked by the rear surface insulating film 131 is formed inside the annular groove 142.

[0188] Here, as a comparative example, it is assumed that the structure of filling the through hole 141 and the annular groove 142 with the solder mask 110 and the rear surface insulating film 131 to eliminate the cavity. In the comparative example, since the parasitic capacitance increases and the solder mask 110 and the rear surface insulating film 131 flow into the through hole 141 and the annular groove 142, the flatness of the upper surface may deteriorate. In addition, once the rear surface insulating film 131 enters the through hole 141 during manufacturing, it is necessary to remove the rear surface insulating film 131 by photolithography, but it is difficult to completely remove the rear surface insulating film 131. Due to these factors, the yield may be reduced. In addition, the exclusion zone (KOZ) as the design exclusion zone around the through electrode for device characteristic assurance becomes larger, which increases stress and manufacturing costs.

[0189] On the other hand, in the figure, since the cavity remains inside the through hole 141 or the annular groove 142, the yield can be increased and the reliability can be improved compared with the comparative example. In addition, the KOZ can be reduced to reduce stress and manufacturing cost.

[0190] Figure 2 1 is an example of a cross-sectional view and a top view of the semiconductor device 100 according to the first embodiment of the present technology. Figure 1 1 is a cross-sectional view of the semiconductor device 100 taken along the alternating long and short dashed lines in FIG. Figure 2 FIG. 2 b shows a top view of the semiconductor device 100 before being covered with the solder mask 110 .

[0191] like Figure 2 As shown in a, the cross-sectional shape of the through hole 141 is circular, and the annular groove 142 surrounding the through hole 141 has a ring shape.

[0192] Figure 2 The circular dotted line in b indicates the outer periphery of the through electrode 149, that is, the outer periphery of the annular groove 142. As shown in b of the figure, the rear surface insulating film 131 covers the periphery of the circular opening having an outer diameter larger than that of the through hole 141. In addition, the through wiring 122 is formed in the through hole 141, and the rear surface redistribution wiring 121 is formed along the periphery of the through hole 141 and the upper surface of the rear surface insulating film 131. In addition, the rear surface redistribution wiring 121 on the upper surface of the rear surface insulating film 131 is formed along a straight path.

[0193] The inside of a circle whose diameter is from coordinate X4 to coordinate X5 indicates the region of the through wiring 122 , and the circle whose diameter is from coordinate X3 to X6 indicates the step of the rear surface rewiring 121 caused by the step of the rear surface insulating film 131 .

[0194] [Method for manufacturing a semiconductor device]

[0195] Figure 3 and Figure 4 A method of manufacturing the semiconductor device 100 according to the first embodiment of the present technology is shown.

[0196] First, if Figure 3 As shown in a, on the front surface side of the semiconductor substrate 140, the pad 152 is formed at the position of the subsequent through wiring 122, and the element isolation region 143 is formed at the position of the annular groove 142. In addition, the dummy gate 151 is formed to the position of the annular groove 142. In addition, the semiconductor substrate 140 is thinned from the rear surface side, and a resist mask 190 is formed at a position other than the position where the through hole 141 and the annular groove 142 are processed by photolithography.

[0197] Next, as shown in b of the figure, the through hole 141 and the annular groove 142 are formed by dry etching. b of the figure shows a state in the middle of processing, and is an example of a case where the processing speed on the groove side is higher than the etching speed of the through hole 141. The etching speed of the through hole 141 and the annular groove 142 depends on the aspect ratio and processing conditions.

[0198] Next, as shown in c of the figure, dry etching is performed until the through hole 141 penetrates the semiconductor substrate 140. Thereafter, the resist mask 190 is removed by ashing or the like. When the through hole 141 penetrates the semiconductor substrate 140, the end point detection of etching can be performed by changes in the plasma emission state or the like. For example, the end point detection is performed when the through hole 141 penetrates, and the plasma etching conditions can be changed to conditions in which it is difficult to produce notches, or conditions in which processing is performed with a positive taper. Specifically, as a manufacturing method for reducing notches, there are methods of increasing sidewall protection elements, methods of reducing the amount of processing per cycle when processing is performed by the Bosch process, and the like. As a result, the processing shape of the bottom of the through hole 141 can be controlled more stably and accurately, so that the through wiring 122 can be easily formed in subsequent processes. In addition, the shapes of the annular groove 142 and the through hole 141 can be optimized.

[0199] Then, if Figure 4 As shown in a, after forming a photosensitive insulating resin on the entire surface as the rear surface insulating film 131, the portion of the through electrode 149 on the side of the through hole 141 and the photosensitive resin of the through hole 141 are removed by photolithography, and it is made into a permanent resin by annealing. In addition, the entire surface is etched back, and the through hole 141 is connected to the pad 152 on the front surface side. As a method for forming the rear surface insulating film 131, a lamination method or a coating method can be used. For example, in the case of the coating method, the penetration depth into the annular groove 142 can be controlled by optimizing the viscosity of the resin.

[0200] Next, as shown in b of the figure, the rear surface rewiring 121 and the through wiring 122 are simultaneously formed by a semi-additive method. As an example of the semi-additive method, the following method is used: a barrier metal film and a seed metal film are formed, and then a resist mask is formed by photolithography, and wiring is formed by electroplating at a portion where the resist mask is not arranged. Thereafter, the resist mask is removed, and the barrier metal film and the seed metal film are removed by full-surface etching, thereby forming the rear surface rewiring 121.

[0201] Next, as shown in c of the figure, a solder mask 110 is formed. Although not shown, a portion of the solder mask 110 may be removed so that the rear surface redistribution wiring 121 is exposed, and external connection terminals may be connected to the rear surface redistribution wiring 121.

[0202] Figure 5 1 is a flowchart showing a method for manufacturing a semiconductor device 100 according to a first embodiment of the present technology. The manufacturing system of the semiconductor device 100 forms a pad 152, etc. (step S901), and forms an annular groove 142 together with a through hole 141 by dry etching (step S902). At the end of the dry etching, the manufacturing system removes the resist mask (step S903) and forms a rear surface insulating film 131 (step S904). Then, the manufacturing system forms the rear surface rewiring 121 together with the through wiring 122 (step S905), and forms a solder mask 110 (step S906). After step S906, the manufacturing system performs other necessary steps and ends the manufacturing process.

[0203] Note that Figure 6 As shown, the end of the rear surface insulating film 131 can have a shape with a positive taper. At this time, from the viewpoint of yield and reliability, the upper end (solder mask 110 side) and the lower end (semiconductor substrate 140 side) of the rear surface insulating film 131 preferably fall within the width of the annular groove 142.

[0204] In addition, if Figure 7 As shown, the annular groove 142 may also be filled with the rear surface insulating film 131. As a result, depending on the size, manufacturing becomes easy and the insulating property is also improved. In addition, there is also a case where the resistance to mechanical stress is increased.

[0205] As described above, according to the first embodiment of the present technology, since the cavity remains inside the annular groove 142, the yield can be improved. In addition, stress and manufacturing cost can be reduced.

[0206] <2. Second Embodiment>

[0207] In the first embodiment described above, the rear surface insulating film is a single layer, but in this configuration, it is difficult to further improve the insulating properties and resistance to mechanical stress of the annular groove 142. The semiconductor device 100 according to the second embodiment is different from the semiconductor device of the first embodiment in that the rear surface insulating film has two layers.

[0208] Figure 8 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to a second embodiment of the present technology. The second embodiment is characterized in that a plurality of rear surface insulating films are stacked. For example, a rear surface insulating film 132 is stacked on a rear surface insulating film 131.

[0209] It is preferred that the rear surface insulating film 132 is formed to the rear surface of the semiconductor substrate 140, the annular groove 142 or the through hole 141, or the inside of both. The rear surface insulating film 131 is formed in the same region as the first embodiment. Each of the rear surface insulating films 131 and 132 can be formed by stacking a plurality of materials. Note that the rear surface insulating film 131 is an example of the first rear surface insulating film described in the claims, and the rear surface insulating film 132 is an example of the second rear surface insulating film described in the claims.

[0210] As the rear surface insulating film 132, silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON) or a fixed charge film is used. As the fixed charge film, HfO2 (hafnium oxide), Al2O3 (aluminum oxide), ZrO (zirconium oxide), Ta2O5 (tantalum oxide), titanium oxide (TiO2 (titanium oxide), LaO3 (lanthanum oxide), Pr6O 11 (praseodymium oxide), CeO2 (cerium oxide), Nd2O3 (neodymium oxide), Pm2O3 (praseodymium oxide), Sm2O3 (samarium oxide), Eu2O3 (europium oxide), GdO3 (gadolinium oxide), Tb2O3 (terbium oxide), Dy2O3 (dysprosium oxide), Ho2O3 (holmium oxide), Tm2O3 (thulium oxide), Yb2O3 (ytterbium oxide), Lu2O3 (lutetium oxide), Y2O3 (yttrium oxide), AlN (aluminum nitride), HfON (hafnium oxynitride), AlON (aluminum oxynitride), etc. Similar to the first embodiment, the upper portion of the annular groove 142 can be blocked by the rear surface insulating film 131. As the rear surface insulating film 131, similar to the first embodiment, a photosensitive insulating film composed of an organic material having a skeleton of polyimide, acrylic, silicone, or epoxy can be used.

[0211] In the structure of the second embodiment, the insulating properties of the annular groove 142 can be enhanced by the rear surface insulating film 132. In addition, the tolerance to mechanical stress can be enhanced. Specifically, a superior effect can be obtained by plugging the recess with a film having good coverage. In addition, by introducing a fixed charge film, the influence of defects on the interface and the front surface as noise and leakage sources can be reduced. In addition, by arranging a rear surface insulating film 132 with different films or different film thicknesses in the through hole 141 and the annular groove 142, the balance of mechanical stress can also be controlled.

[0212] As described above, according to the second embodiment of the present technology, since the two layers of the rear surface insulating films 131 and 132 are stacked on the rear surface, the insulating characteristics of the ring-shaped groove 142 and the resistance to mechanical stress can be improved.

[0213] <3. Third Embodiment>

[0214] In the second embodiment described above, an annular groove 142 is formed around the through hole 141 in the through electrode 149, but it is difficult to achieve high integration if all through electrodes are provided with the annular groove 142. The semiconductor device 100 according to the third embodiment is different from the semiconductor device of the second embodiment in that through electrodes with annular grooves 142 and through electrodes without annular grooves are mixed.

[0215] Fig. 9 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to a third embodiment of the present technology. The third embodiment is characterized in that the third embodiment has a structure with multiple through electrodes. In the semiconductor device 100 of the third embodiment, through electrodes 149-1, 149-2, 149-3, etc. are formed.

[0216] The through electrode 149 - 1 has a structure similar to that of the second embodiment, a ring-shaped groove for partitioning the semiconductor substrate 140 is formed, and a through wiring is routed inside the through hole 141 - 1 .

[0217] In the through electrode 149-2, there is no annular groove around the through hole 141-2, and the through wiring is insulated from the semiconductor substrate by the back surface insulating film 132. In addition, the through electrode 149-3 has a structure in which the back surface insulating film 132 and the back surface insulating film 131 are stacked between the side wall of the through hole 141-3 and the semiconductor substrate 140. The structure of the figure is only an example, and other combinations may be adopted.

[0218] In the structure of the third embodiment, the optimal shape can be selected according to the purpose of the through electrode in a bare chip. For example, when the wiring delay is considered important, the through electrode 149-1 provided with an annular groove is used, and when high integration is considered important, the through electrode 149-2 or 149-3 without an annular groove is used, so that a structure with signal transmission performance and integration can be obtained.

[0219] Fig.10 A method for manufacturing the semiconductor device 100 of the third embodiment is shown. Figure 3 However, no annular groove is formed around the through holes 141-2 and 141-3.

[0220] Then, if Fig.10 As shown in b, an inorganic insulating film (e.g., SiO2 film) is formed as a rear surface insulating film 132 on the entire surface including the annular groove and the through hole by an atomic layer deposition (ALD) method or a plasma enhanced chemical vapor deposition (PE-CVD) method.

[0221] Next, as shown in c of the figure, a photosensitive insulating resin is formed on the entire surface as a rear surface insulating film 131, and the photosensitive resin in the portion of the ring-shaped semiconductor substrate and the through hole is removed by photolithography. For the through hole 141-3, the film forming conditions and the mask pattern for photolithography are adjusted so that the rear surface insulating film 131 is also formed on the side surface. In addition, the entire surface is etched back, and each through hole is connected to the pad on the front surface side.

[0222] Thereafter, the Figure 4 Similar to b and c in FIG. 1 , through wiring 122, rear surface rewiring 121 and solder mask 110 are formed, and Fig. 9 structure.

[0223] According to the above-described manufacturing method, a plurality of types of through electrodes can be formed simultaneously without adding manufacturing steps to the second embodiment.

[0224] As described above, according to the third embodiment of the present technology, since the through electrode 149 - 1 formed with the annular groove 142 and the through electrodes 149 - 2 and 149 - 3 without the annular groove are provided, signal transmission performance and integration can be achieved.

[0225] <4. Fourth Embodiment>

[0226] In the first embodiment described above, an annular groove 142 is formed around the through hole 141 in the through electrode 149, but when multiple through electrodes are arranged, the spacing may need to be reduced. The semiconductor device 100 according to the fourth embodiment is different from the semiconductor device of the first embodiment in that two adjacent through electrodes share a portion of the annular groove.

[0227] Fig.11 is an example of a cross-sectional view of the semiconductor device 100 viewed from the Z-axis direction according to the fourth embodiment of the present technology.

[0228] A plurality of through electrodes, such as through electrodes 149-1, 149-2, and 149-3, are arranged in the X-axis direction and the Y-axis direction. Annular grooves, such as annular grooves 142-1, 142-2, and 142-3, are formed around the corresponding through holes of the through electrodes. Two adjacent through electrodes arranged in the X-axis direction share a portion of the annular groove. For example, in the through electrodes 149-1 and 149-2, the annular groove 142-1 and the annular groove 142-2 are partially shared. As a result, the spacing of the through electrodes can be reduced.

[0229] Note that in the drawing, the through electrodes arranged in the X-axis direction share their portions, but the through electrodes arranged in the Y-axis direction may share their portions.

[0230] In addition, the width D1 of the common portion of the annular grooves 142-1 and 142-2 can be made substantially the same as the width D2 of the non-common portion. In the case of a common annular groove, if the size of the common portion is different from that of the other portions, problems such as variation in the amount of intrusion of the insulating film occur when the rear surface insulating film 131 is formed, but as shown in the figure, by making the width substantially the same, the variation is reduced.

[0231] Note that the second embodiment and the third embodiment can be applied to the fourth embodiment.

[0232] As described above, according to the fourth embodiment of the present technology, since the portion of the ring-shaped groove is shared by two adjacent through electrodes, the pitch of the through electrodes can be reduced compared to the case where the through electrodes are not shared.

[0233] <5. Fifth embodiment>

[0234] In the first embodiment described above, the rear surface rewiring 121 covers the inner side of the annular groove 142, but in this configuration, the wiring reliability may be insufficient. The semiconductor device 100 according to the fifth embodiment is different from the semiconductor device of the first embodiment in that the rear surface rewiring 121 covers the entire surface of the annular groove 142.

[0235] Fig.12is a cross-sectional view showing a configuration example of a semiconductor device 100 according to a fifth embodiment of the present technology.

[0236] Fig.13 1 is an example of a top view of a semiconductor device 100 according to a fifth embodiment of the present technology. This figure shows a top view before being covered with a solder mask 110.

[0237] The fifth embodiment is characterized in that the rear surface redistribution wiring 121 opposite to the through wiring 122 is formed to cover the entire ring-shaped groove 142. Fig.12 and Fig.13 In FIG. 1 , coordinates X1 to X8 correspond to the outer periphery of the through electrode 149 (ie, the outer periphery of the annular groove 142). Fig.13 As shown, the outer circumference of the rear surface redistribution 121 is larger than the outer circumference of the annular groove 142 .

[0238] Since the rigidity of the semiconductor substrate 140 is low in the upper portion of the annular groove 142, stress is easily applied to the rear surface redistribution wiring 121. Therefore, wiring reliability is easily deteriorated, but in the fifth embodiment, the thin wiring does not cross the annular groove 142, so that high wiring reliability can be obtained.

[0239] Note that each of the first embodiment, the second embodiment, and the third embodiment can be applied to the fifth embodiment.

[0240] As described above, according to the fifth embodiment of the present technology, since the rear surface redistribution wiring 121 covers the entire ring-shaped groove 142 , wiring reliability is improved.

[0241] <6. Sixth Implementation>

[0242] In the first embodiment described above, the rear surface rewiring 121 is formed linearly from the periphery of the through hole 141, but the width of the rear surface rewiring 121 may not be constant. The semiconductor device 100 according to the sixth embodiment is different from the semiconductor device of the first embodiment in that the width of the rear surface rewiring 121 increases at a position crossing the upper portion of the annular groove 142.

[0243] Fig.14 1 is an example of a top view of a semiconductor device 100 according to a sixth embodiment of the present technology. This figure shows a top view before being covered with a solder mask 110. Between coordinates X6 and X8, the rear surface redistribution wiring 121 crosses the upper portion of the annular groove 142, but the width of this portion is thicker than other portions.

[0244] Since the rigidity of the semiconductor substrate 140 is low in the upper part of the annular groove 142, stress is easily applied to the rear surface redistribution wiring 121. Therefore, the wiring reliability is easily deteriorated, but in the sixth embodiment, high wiring reliability can be obtained by thickening the wiring that crosses the annular groove 142. In addition, since the area of ​​the rear surface redistribution wiring 121 is smaller than that of the fifth embodiment, it is conducive to high integration.

[0245] Note that each of the first to fourth embodiments can be applied to the sixth embodiment.

[0246] As described above, according to the sixth embodiment of the present technology, since the width of the rear surface redistribution wiring 121 at the position crossing the upper portion of the ring-shaped groove 142 is increased, wiring reliability can be improved.

[0247] <7. Seventh Implementation Method>

[0248] In the first embodiment described above, the entire surface of the opening of the rear surface insulating film 131 is covered, but in this structure, the yield may be insufficient. The semiconductor device 100 according to the seventh embodiment is different from the semiconductor device of the first embodiment in that the inside of the opening is covered.

[0249] Fig.15 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to a seventh embodiment of the present technology.

[0250] Fig.16 1 is an example of a top view of a semiconductor device 100 according to a seventh embodiment of the present technology. This figure shows a top view before being covered with a solder mask 110 .

[0251] In the seventh embodiment, the rear surface redistribution wiring 121 surrounding the through hole 141 covers the rear surface inside the opening of the rear surface insulating film 131 . Fig.15 and Fig.16 The range of coordinates X3 to X6 in corresponds to the diameter of the opening formed in the rear surface insulating film 131. The coordinate between the coordinate X3 and the coordinate X4 of the end of the through hole 141 is defined as X3'. In addition, the coordinate between the coordinate X5 and the coordinate X6 of the end of the through hole 141 is defined as X5'. The inner side of the opening from the coordinate X3' to the coordinate X5' is covered by the rear surface redistribution 121.

[0252] Since a material with a large stress is generally used for the rear surface rewiring 121, the reliability of the through electrode 149 can be improved by reducing its area as much as possible. On the other hand, since the exposure accuracy of the photolithography decreases near the step (coordinates X3 and X6) of the rear surface insulating film 131, there is a problem of decreased yield. Fig.15 and Fig.16 The structure shown is patterned in advance so as not to ride on the rear surface insulating film 131, so that stress reduction and high yield can be achieved.

[0253] Note that each of the first to fourth embodiments can be applied to the seventh embodiment.

[0254] As described above, according to the seventh embodiment of the present technology, since the inner side of the rear surface insulating film 131 is covered with the rear surface redistribution wiring 121 , reduction in stress and high yield can be achieved.

[0255] <8. Eighth Implementation Method>

[0256] In the above-mentioned first embodiment, the annular groove 142 is formed around the through hole 141 in the through electrode 149, but an external connection terminal, a circuit, etc. may be connected to the through electrode 149. The semiconductor device 100 according to the eighth embodiment is different from the semiconductor device of the first embodiment in that an external connection terminal, a photoelectric conversion layer, etc. are added to be used as a solid-state imaging device.

[0257] Fig.17 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to an eighth embodiment of the present technology. The eighth embodiment is an example in which the structure of the through electrode 149 of the first embodiment is adopted in a back-illuminated solid-state imaging device.

[0258] The external connection terminal 160 is connected to the through electrode 149 via the rear surface rewiring 121. On the front surface side, the photoelectric conversion layer 170 is formed via the wiring layer 150, and the photoelectric conversion layer 170 includes, for example, a semiconductor substrate such as silicon, a Group 3-5 substrate such as gallium nitride (GaAs), an organic material, or a stack thereof.

[0259] In addition, a light-condensing structure such as an on-chip lens 180 is arranged on the lower surface side of the photoelectric conversion layer 170 via an anti-reflection film (not shown) or the like. In addition, in a solid-state imaging element, for example, in an interface circuit, it is necessary to transmit a signal to the outside at high speed, and by adopting the through-electrode 149 of the present invention having low capacitance and high reliability, higher performance than that of a conventional structure can be obtained.

[0260] Note that each of the second to seventh embodiments can be applied to the eighth embodiment.

[0261] As described above, according to the eighth embodiment of the present technology, since the external connection terminal 160 and the photoelectric conversion layer 170 are formed, the semiconductor device 100 can be used as a solid-state imaging device.

[0262] <9. Ninth Implementation Method>

[0263] In the above-described first embodiment, the through electrode 149 is formed on the semiconductor substrate 140. However, if measures are taken to reduce parasitic capacitance, the film stress of the conductive film (through wiring 122) may cause cracking or peeling on the bottom surface of the through hole 141. The semiconductor device 100 according to the ninth embodiment is different from the semiconductor device of the first embodiment in that a reinforcement film is formed around the through hole 141.

[0264] Fig.18 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to a ninth embodiment of the present technology. The semiconductor device 100 of the ninth embodiment differs from the semiconductor device of the first embodiment in that it further includes a reinforcement film 210. In this figure, it is assumed that no annular groove 142 is formed around the through hole 141.

[0265] In addition, in the ninth embodiment, when viewed from the Y-axis direction or the X-axis direction, the through hole 141 has a step at a predetermined depth position Z1. In addition, as the rear surface insulating film 131, a material with a low dielectric constant such as a low-k film or a resin is used. In addition to the upper surface (i.e., the rear surface) of the semiconductor substrate 140, the rear surface insulating film 131 covers the periphery of the through hole 141 in the range from the upper surface to the depth position Z1. The low dielectric constant rear surface insulating film 131 can reduce the parasitic capacitance of the through electrode 149 and the rear surface rewiring 121. However, in this configuration, in the absence of a reinforcement film 210, the film stress of the conductive film (through wiring 122) may cause cracking or peeling on the bottom surface of the through hole 141.

[0266] In addition, an inorganic insulating film such as silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), or silicon carbide (SiC) is used as the enhancement film 210. The enhancement film 210 covers the periphery of the through hole 141 in the range from the depth position Z1 to the wiring layer 150. The periphery of the enhancement film 210 is in contact with the base material (silicon, etc.) of the semiconductor substrate 140.

[0267] As shown in the figure, by forming the reinforcement film 210 at the lower end of the through hole 141, cracking and peeling of the bottom surface of the through hole 141 due to the film stress of the conductive film and the softness of the rear surface insulating film 131 can be suppressed. In the figure, the white arrow indicates the vector of deformation caused by the film stress under Cu.

[0268] As the thickness T of the enhancement film 210 in the X-axis direction or the Y-axis direction increases, the film stress can be dispersed to suppress cracking and peeling. For example, the thickness T is adjusted to be 5 micrometers (μm) or more. In addition, as shown in the figure, when the periphery of the enhancement film 210 is in contact with the base material (silicon, etc.) of the semiconductor substrate 140, the enhancement effect can be enhanced compared to the case where the periphery is not in contact with the base material.

[0269] Fig.19 This is a cross-sectional view of the semiconductor device 100 according to the ninth embodiment of the present technology as viewed from the Z-axis direction. Fig.18 Cross-sectional view taken along line segment X9-X10.

[0270] As shown in a of the figure, the cross-sectional shape of the through hole 141 as viewed from the Z-axis direction is circular, and the reinforcing film 210 covers the entire periphery of the through hole 141 .

[0271] Note that, as shown in b of the figure, the reinforcing film 210 may cover part of the periphery of the through hole 141. As a result, compared with the case where the entire periphery is covered, parasitic capacitance can be suppressed.

[0272] then, Figure 20 to Figure 23 Detailed Description of the Invention A first method for manufacturing the semiconductor device 100 according to the ninth embodiment of the present technology is shown in FIG.

[0273] like Fig. 20 As shown in a of FIG. 1 , the wiring layer 150 is formed on the front surface of the semiconductor substrate 140. Then, as shown in b of the same figure, the semiconductor substrate 140 is opened.

[0274] Then, if Fig.21 As shown in a of FIG. 1 , the enhancement film 210 is formed. Then, as shown in b of the same figure, the enhancement film 210 is etched back, while the lower portion remains in the through hole.

[0275] Then, if Fig. 22 As shown in a of FIG. 1 , a rear surface insulating film 131 having a low dielectric constant is formed. Then, as shown in b of the same figure, the rear surface insulating film 131 is opened to generate a step.

[0276] Then, if Fig.23 As shown in a of FIG. 1 , a conductive film (rear surface wiring 121 and through wiring 122) is formed. Then, as shown in b of the same figure, a solder mask 110 is applied.

[0277] The manufacturing method of the ninth embodiment is not limited to the above-mentioned first manufacturing method. Figure 24 to Figure 27 A second manufacturing method is shown.

[0278] like Fig.24 As shown in a of FIG. 1 , the semiconductor substrate 140 is placed with the front surface side facing upward before the formation of the wiring layer 150. Then, as shown in b of the same figure, a groove is engraved on the front surface side.

[0279] Then, if Fig.25 As shown in a of FIG. 1 , a reinforcement film 210 is formed in the trench, and STI is obtained. Then, as shown in b of the same figure, a wiring layer 150 is formed.

[0280] Then, if Fig.26 As shown in a of FIG. 1 , the semiconductor substrate 140 is opened, and as shown in b of the same figure, a rear surface insulating film 131 having a low dielectric constant is formed.

[0281] Then, if Fig. 27 As shown in a of FIG. 1 , the rear surface insulating film 131 is opened, and a conductive film is formed as shown in b of the same figure. Then, a solder mask 110 (not shown) is applied.

[0282] Note that although Fig.18 No annular groove 142 is provided, but it can be Fig.28 As shown, an annular groove 142 is further provided. Furthermore, each of the first to eighth embodiments can be applied to the ninth embodiment.

[0283] As described above, according to the ninth embodiment of the present technology, since the periphery of the through hole 141 is covered with the reinforcement film 210 in the range from the depth position Z1 to the wiring layer 150 , cracking and peeling can be suppressed.

[0284] [First Modification]

[0285] In the ninth embodiment, the through hole 141 has a step, but the corner of the step can be rounded when etching back the enhancement film 210. The semiconductor device 100 according to the first modification of the ninth embodiment is different from the semiconductor device of the ninth embodiment in that the cross-sectional shape of the through hole 141 has a curved taper.

[0286] Fig.29 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to a first modification of the ninth embodiment of the present technology. The semiconductor device 100 according to the first modification of the ninth embodiment is different from the semiconductor device of the ninth embodiment in that the cross-sectional shape of each of the through hole 141 and the enhancement film 210 viewed from the X-axis direction or the Y-axis direction has a curved taper. This facilitates adjustment of the cross-sectional shape during back etching.

[0287] Note that each of the first to eighth embodiments can be applied to the first modification example of the ninth embodiment.

[0288] As described above, according to the first modification example of the ninth embodiment of the present technology, since the cross-sectional shape of each of the through hole 141 and the reinforcement film 210 has a curved taper, it is easy to adjust the cross-sectional shape at the time of back engraving.

[0289] [Second Modification]

[0290] In the above-mentioned ninth embodiment, the enhancement film 210 is formed so that the periphery of the enhancement film 210 is in contact with the base material of the semiconductor substrate 140, but as the thickness of the enhancement film increases, the parasitic capacitance also increases. The semiconductor device 100 according to the second modification of the ninth embodiment is different from the semiconductor device of the ninth embodiment in that the rear surface insulating film 131 covers the periphery of the through hole 141 and the enhancement film 210.

[0291] Fig.30 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to a second modification of the ninth embodiment of the present technology. The semiconductor device 100 according to the second modification of the ninth embodiment is different from the semiconductor device of the ninth embodiment in that the rear surface insulating film 131 covers not only the periphery of the through hole 141 but also the periphery of the enhancement film 210.

[0292] As shown in the figure, in the case where the enhancement film 210 does not contact the base material of the semiconductor substrate 140, the optimal value of the thickness T of the enhancement film 210 is within a specific range. If the thickness T is too small, the enhancement effect is insufficient. On the other hand, when the thickness T is too large, it is possible to lift the entire enhancement film 210 and peel off, and only the position where the enhancement film is peeled off changes. In addition, parasitic capacitance increases. For example, the thickness T is preferably adjusted in the range of 5 to 10 micrometers (μm).

[0293] Note that each of the first to eighth embodiments can be applied to the second modification example of the ninth embodiment.

[0294] As described above, according to the second modification of the ninth embodiment of the present technology, since the rear surface insulating film 131 covers the periphery of the through hole 141 and the reinforcement film 210 , the thickness of the reinforcement film 210 can be reduced to reduce parasitic capacitance.

[0295] [Third Modification]

[0296] In the ninth embodiment, the through hole 141 has a step, but the base material of the semiconductor substrate 140 may have a step instead of the through hole 141. The semiconductor device 100 in the third modification of the ninth embodiment is different from the semiconductor device of the ninth embodiment in that the base material of the semiconductor substrate 140 has a step.

[0297] Fig.31 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 in a third modification of the ninth embodiment of the present technology. The semiconductor device 100 according to the third modification of the ninth embodiment is different from the semiconductor device of the ninth embodiment in that the through hole 141 does not have a step, but instead the base material of the semiconductor substrate 140 has a step at a depth position Z1.

[0298] The rear surface insulating film 131 covers the through hole 141 in the range from the rear surface to the depth position Z1. In addition, the reinforcing film 210 covers the through hole 141 in the range from the depth position Z1 to the wiring layer 150. In addition, the reinforcing film 210 is formed along the base material of the semiconductor substrate 140 and is located between the base material and the rear surface insulating film 131 above the depth position Z1.

[0299] then, Figure 32 to Figure 35 A method for manufacturing the semiconductor device 100 according to the third modification example of the ninth embodiment of the present technology is shown.

[0300] like Fig.32 As shown in a of FIG. 1 , a wiring layer 150 is formed on the front surface of a semiconductor substrate 140. Then, as shown in b of the same figure, the semiconductor substrate 140 is opened, and a resist mask 190 is applied to a portion other than a portion where a step is to be provided.

[0301] Then, if Fig.33 As shown in a of FIG. 1 , a step is formed in the opening of the substrate, and the resist mask 190 is removed. Then, as shown in b of the same figure, a reinforcement film 210 is formed.

[0302] Then, if Fig.34 As shown in a of the figure, the rear surface insulating film 131 is formed, and as shown in b of the figure, the rear surface insulating film 131 is opened.

[0303] Then, if Fig.35 As shown in a of FIG. 1 , a conductive film (rear surface wiring 121 and through wiring 122) is formed. Then, as shown in b of the same figure, a solder mask 110 is applied.

[0304] Note that each of the first to eighth embodiments can be applied to the third modification example of the ninth embodiment.

[0305] As described above, according to the third modification example of the ninth embodiment of the present technology, since the base material of the semiconductor substrate 140 has the step, it is not necessary to provide the step in the through hole 141 .

[0306] [Fourth Modification]

[0307] In the ninth embodiment, the cross-sectional shape of the through hole 141 viewed from the Z-axis direction is circular, but may be rectangular. The semiconductor device 100 according to the fourth variation of the ninth embodiment is different from the semiconductor device of the ninth embodiment in that the cross-sectional shape of the through hole 141 is rectangular.

[0308] Fig.36 This is a cross-sectional view of the semiconductor device 100 according to the fourth modification of the ninth embodiment of the present technology as viewed from the Z-axis direction. Fig.18 Cross-sectional view taken along line segment X9-X10.

[0309] like Fig.36 As shown in a, when viewed from the Z-axis direction, the cross-sectional shape of the through hole 141 is rectangular, and the reinforcing film 210 covers the entire periphery of the through hole 141 .

[0310] Note that, as shown in b of the figure, the reinforcing film 210 may cover part of the periphery of the through hole 141. As a result, compared with the case where the entire periphery is covered, parasitic capacitance can be suppressed.

[0311] Note that each of the first to eighth embodiments can be applied to the fourth modification example of the ninth embodiment.

[0312] As described above, according to the fourth modification example of the ninth embodiment of the present technology, cracking and peeling can be suppressed in the semiconductor device 100 in which the cross-sectional shape of the through hole 141 is rectangular.

[0313] [Fifth Modification]

[0314] In the ninth embodiment described above, the cross-sectional shape of the through hole 141 as viewed from the Z-axis direction is circular, but may be a polygon (hexagon) other than a rectangle. The semiconductor device 100 according to the fifth variation of the ninth embodiment is different from the semiconductor device of the ninth embodiment in that the cross-sectional shape of the through hole 141 is a hexagon.

[0315] Fig.37 This is a cross-sectional view of the semiconductor device 100 according to the fifth modification of the ninth embodiment of the present technology as viewed from the Z-axis direction. Fig.18 Cross-sectional view taken along line segment X9-X10.

[0316] like Fig.37 As shown in a, viewed from the Z-axis direction, the cross-sectional shape of the through hole 141 is a polygon other than a rectangle (such as a hexagon), and the reinforcing film 210 covers the entire periphery of the through hole 141. Note that although the cross-sectional shape is a hexagon in this figure, the cross-sectional shape may be a polygon other than a hexagon.

[0317] In addition, as shown in b of the figure, the reinforcing film 210 may cover a portion of the periphery of the through hole 141. As a result, compared with the case where the entire periphery is covered, parasitic capacitance can be suppressed.

[0318] In addition, each of the first to eighth embodiments can be applied to the fifth modification example of the ninth embodiment.

[0319] As described above, according to the fifth modification of the ninth embodiment of the present technology, cracking and peeling can be suppressed in the semiconductor device 100 in which the cross-sectional shape of the through hole 141 is hexagonal.

[0320] <10. Tenth Implementation Method>

[0321] In the first embodiment described above, the annular groove 142 is formed around the through hole 141, but the semiconductor substrate 140 may be peeled off due to the shrinkage of the upper rear surface insulating film 131 during annealing. The semiconductor device 100 according to the tenth embodiment is different from the semiconductor device of the first embodiment in that a protective member is provided at the lower portion of the annular groove 142 to suppress peeling.

[0322] Fig.38 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to a tenth embodiment of the present technology. The semiconductor device 100 according to the tenth embodiment is different from the first embodiment in that a protective member 220 is arranged adjacent to the wiring layer 150 in the annular groove 142. As the protective member 220, for example, an insulating resin is used. The material of the resin may be the same as or different from the material of the rear surface insulating film 131.

[0323] In the manufacturing process, when annealing is performed, the rear surface insulating film 131 entering the upper part of the annular groove 142 shrinks. The black arrow in the figure indicates the direction of shrinkage. Due to this shrinkage, stress that causes the semiconductor substrate 140 to peel off is generated, and specifically, the stress is concentrated on the corner of the inner peripheral side of the bottom of the annular groove 142. The white arrow in the figure indicates the direction of stress.

[0324] Fig.39 This is a diagram for explaining the effect of the semiconductor device according to the tenth embodiment of the present technology. Fig.38 2 is an enlarged view of a portion surrounded by a dotted line in FIG. b of the same figure shows an enlarged view of a case where a protective member 220 is provided.

[0325] By making the annular groove 142 hollow, the dielectric constant can be reduced and high-speed transmission can be achieved. However, as shown in a of the figure, when the protective member 220 is not provided, the semiconductor substrate 140 and the wiring layer 150 are deformed, and the semiconductor substrate 140 may be partially peeled off. Note that in a and b of the figure, the degree of deformation is emphasized more than 100 times.

[0326] On the other hand, as shown in b of the figure, when the protective member 220 is provided, the protective member 220 shrinks, and the deformation of the semiconductor substrate 140 and the wiring layer 150 is suppressed by shrinking. The arrow in b of the figure indicates the shrinking direction. As a result, local peeling is suppressed. For example, by setting the film thickness of the protective member 220 to 5 micrometers (μm) or more, peeling can be sufficiently suppressed. Therefore, high-speed transmission through the hollow annular groove 142 and suppression of peeling can be achieved.

[0327] then, Figure 40 to Figure 42 Detailed Description of the Invention A method of manufacturing the semiconductor device 100 according to the first embodiment of the present technology is shown in FIG.

[0328] like Fig.40 As shown in a of FIG. 1 , a wiring layer 150 is formed on the front surface of a semiconductor substrate 140. Then, as shown in b of the same figure, a through hole 141 and an annular groove 142 are formed by dry etching. Note that the through hole 141 and the annular groove 142 may be formed at once at the same time, or may be formed twice.

[0329] Then, if Fig.41 As shown in a of FIG. 1 , a photosensitive protective member 220 is applied, and a portion of the through hole 141 is removed by photolithography. Then, as shown in b of the same figure, etching back is performed so that the protective member 220 remains only at the bottom of the annular groove 142.

[0330] Then, if Fig.42 As shown in a of the figure, a photosensitive rear surface insulating film 131 is formed, and the inside of the through hole 141 and the portion surrounding the through hole are removed by photolithography. Then, as shown in b of the figure, the rear surface rewiring 121 and the through wiring 122 are formed at the same time. Then, a solder mask 110 (not shown) is formed, and a Fig.38 A semiconductor device 100 in FIG.

[0331] Note that Fig.38 In the embodiment, the protection member 220 is formed to cover the entire bottom surface of the annular groove 142, but the present invention is not limited to this configuration.

[0332] like Fig.43 As shown in a, the protective member 220 may also be arranged to cover the inner and outer corners of the annular groove 142, wherein a portion of the bottom surface of the annular groove 142 remains. Since the amount of back-etching is particularly large in the central portion of the annular groove 142, the protective member 220 can be left only at the corners by adjusting the total amount of back-etching during back-etching.

[0333] In addition, as shown in b of the figure, the protective member 220 may be arranged to cover only the corners of the inner circumference. The dielectric constant of the resin used as the protective member 220 is generally higher than the dielectric constant of air. Therefore, as shown in a and b of the figure, by leaving the resin only at the corners, the volume of the entire resin is reduced, and the dielectric constant can be reduced by that amount, which is conducive to high-speed transmission.

[0334] In addition, Fig.38 In the embodiment, resin is used as the protective member 220, but as Fig.44 As shown, an insulating inorganic film can be used instead of a resin. Specifically, when the film is a stretch film, a stress reduction effect equivalent to that of a resin is produced. In a compression film, a stress reduction equivalent to that of a resin cannot be obtained, but since the inorganic film is harder, there is an effect of suppressing deformation, and it is considered to be effective for anti-peeling measures.

[0335] For example, an inorganic film is formed by an atomic layer deposition (ALD) method, and then the inorganic film in the through hole 141 and the annular groove 142 is removed by etching back. The inorganic film remaining at the corner of the through hole 141 is defined as a protective member 232, and the inorganic film remaining in the annular groove 142 is defined as a protective member 231. Note that the protective member 231 is an example of a first protective member described in the claims, and the protective member 232 is an example of a second protective member described in the claims.

[0336] like Fig.44 As shown in a, the inorganic film (protective member 232) is also retained at the corner of the through hole 141, but since the corner of the through wiring 122 composed of Cu or the like is rounded, the effect of reducing the stress directly below the through hole 141 is produced. In addition, in the annular groove 142, since the back etching starts from the central part, the retained protective member 231 has a shape that is recessed downward (i.e., on the wiring layer 150 side). Even with this shape, since the corner is covered, the effect of suppressing peeling is not affected. In addition, the volume of the protective member 231 is reduced by the recess, and the dielectric constant can be reduced by this amount, which is conducive to high-speed transmission.

[0337] Depending on the degree of etching back, as shown in b of the figure, there is a possibility that part of the bottom surface of the annular groove 142 is exposed and the protection member 231 remains only at the corner. Even in this case, since the corner is rounded, the effect of suppressing peeling is produced.

[0338] Note that each of the first to ninth embodiments can be applied to the tenth embodiment.

[0339] As described above, according to the tenth embodiment of the present technology, since the protection member 220 is disposed adjacent to the wiring layer 150 in the annular groove 142 , peeling can be suppressed.

[0340] [First Modification]

[0341] In the above-described tenth embodiment, the protective member 220 is arranged in the annular groove 142 to suppress peeling, but in this configuration, it is necessary to add a step of forming the protective member 220. The semiconductor device 100 according to the first modification of the tenth embodiment is different from the semiconductor device of the tenth embodiment in that the protective member 220 is not required.

[0342] Fig.45 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 in a first modification of the tenth embodiment of the present technology. In the semiconductor device 100 according to the first modification of the tenth embodiment, the protective member 220 is not formed. Instead, the width dX2 of the annular groove 142 on the wiring layer 150 side is adjusted to be narrower than the width dX1 of the annular groove 142 on the rear surface insulating film 131 side. For example, the cross-sectional shape of the annular groove 142 has a taper that becomes thinner toward the wiring layer 150 at the lower portion of the annular groove.

[0343] Fig.46 This is an example of an enlarged view of a semiconductor device in a first variation of the tenth embodiment of the present technology. Fig.45 An enlarged view of the portion surrounded by the dotted line in FIG.

[0344] like Fig.46 As shown in a of the figure, the annular groove 142 has a taper on both the inner and outer circumferences. In addition, as shown in b of the figure, a structure having a taper only on the inner circumference can be adopted. By setting the taper as exemplified in a and b of the figure, deformation can be suppressed and peeling can be prevented.

[0345] Note that each of the first to ninth embodiments can be applied to the first modification example of the tenth embodiment.

[0346] As described above, according to the first modified example of the tenth embodiment of the present technology, since the cross-sectional shape of the annular groove 142 has a taper, the protection member 220 is not required.

[0347] [Second Modification]

[0348] In the above-described tenth embodiment, the protective member 220 is arranged in the annular groove 142 to suppress peeling, but in this configuration, it is necessary to add a step of forming the protective member 220. The semiconductor device 100 according to the second modification of the tenth embodiment is different from the semiconductor device of the tenth embodiment in that the protective member 220 is not required.

[0349] Fig.471 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to a second modification of the tenth embodiment of the present technology. In the semiconductor device 100 according to the second modification of the tenth embodiment, the protective member 220 is not formed. Instead, the width dX2 of the annular groove 142 on the wiring layer 150 side is adjusted to be narrower than the width dX1 of the annular groove 142 on the rear surface insulating film 131 side. For example, the corner of the bottom of the annular groove 142 is adjusted to have a rounded shape.

[0350] Fig.48 This is an example of an enlarged view of a semiconductor device in a second modification of the tenth embodiment of the present technology. Fig.47 Magnified view of the portion surrounded by the dotted line.

[0351] like Fig.48 As shown in a of the figure, in the first modified example of the tenth embodiment, it is assumed that the two corners of the inner and outer peripheral sides of the annular groove 142 are rounded. Note that, as shown in b of the figure, only the corner of the inner peripheral side may be rounded. As shown in a and b of the figure, the so-called rounded shape can suppress deformation and prevent peeling.

[0352] On the other hand, Fig.49 As shown in a of FIG. 1 , when a notch is formed in the corner, the stress is concentrated in the corner, so the wiring layer 150 is easily peeled off. In addition, as shown in b of the same figure, even if there is no notch in the corner, the effect of suppressing peeling cannot be obtained unless the corner is rounded.

[0353] Note that although Fig.47 In the example, the corner does not reach the wiring layer 150, but Fig.50 As shown in a of FIG. 1 , etching may be performed so that the corner portion crosses the boundary between the semiconductor substrate 140 and the wiring layer 150. Furthermore, as illustrated in b of the same figure, etching may be performed so that the corner portion is located in the wiring layer 150.

[0354] Note that each of the first to ninth embodiments can be applied to the second modification example of the tenth embodiment.

[0355] As described above, according to the second modification of the tenth embodiment of the present technology, since the corners of the annular groove 142 are rounded, the protection member 220 is not required.

[0356] <11. Eleventh Implementation Method>

[0357] In the first embodiment described above, an annular groove 142 is formed around the through hole 141, but in this case, the base material (silicon, etc.) of the semiconductor substrate 140 is kept in an annular shape between the through hole 141 and the annular groove 142. In this configuration, it is necessary to ensure a sufficient width of the cavity in the annular groove 142 to increase the withstand voltage of the rear surface rewiring 121 or to ensure a sufficient ring width to suppress the peeling of the annular silicon. Therefore, there is a problem that high integration of the pattern becomes difficult. The semiconductor device 100 according to the eleventh embodiment is different from the semiconductor device of the first embodiment in that the space between the through hole 141 and the annular groove 142 is exhausted.

[0358] Fig.51 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to an eleventh embodiment of the present technology. The semiconductor device 100 according to the eleventh embodiment is different from the semiconductor device of the first embodiment in that an insulating film 240 is formed on the periphery of the annular groove 142 and between the through hole 141 and the annular groove 142. In addition, the eleventh embodiment is different from the first embodiment in that a depletion layer 250 is formed in the insulating film 240 between the through hole 141 and the annular groove 142. For example, SiO2 is used as the insulating film 240.

[0359] Fig.52 This is an example of a cross-sectional view of the semiconductor device 100 according to the eleventh embodiment of the present technology as viewed from another direction. Fig.51 A cross-sectional view taken along the line segment X11-X12 in FIG. 1 and observed from the Z-axis direction. Fig.52 b is along Fig.51 A cross-sectional view taken along the line segment X13-X14 and observed from the Z-axis direction.

[0360] like Fig.52 As shown in a, the insulating film 240 is opened at the upper end of the ring-shaped groove 142, and a circular or elliptical hole 241 is formed. Note that the hole 241 is an example of an opening described in the claims.

[0361] In addition, if Fig.52 As shown in b, the insulating film 240 between the annular groove 142 and the through hole 141 is completely depleted to form a depletion layer 250. By adopting the structure in which the portion of the annular silicon is completely depleted in the first embodiment, the outer diameter of the annular groove 142 can be reduced while ensuring the insulation width between the through wiring 122 and the semiconductor substrate 140. In addition, since the metal wiring in the wiring layer 150 is not exposed at the bottom of the annular depletion layer 250, pattern collapse such as film peeling and corrosion of the metal wiring is suppressed. As a result, the through electrode 149 with high withstand voltage and low capacitance can be highly integrated, and improvement in device reliability can be expected.

[0362] then, Figure 53 to Figure 56 A method of manufacturing the semiconductor device 100 according to the eleventh embodiment of the present technology is shown in FIG.

[0363] like Fig.53 As shown in a, the semiconductor substrate 140 formed with the circuit is bonded to the support substrate including the wiring layer 150. In the grinder device, the semiconductor substrate 140 is thinned by polishing until the thickness becomes about 80 micrometers (μm). The support substrate may be a silicon substrate or a glass substrate.

[0364] Next, as shown in b of the figure, a through hole 141 and an annular groove 142 are formed. First, a resist pattern of the through hole 141 and the annular groove 142 is formed by photolithography. For example, the diameter of the through hole 141 is 40 microns (μm), and the width of the annular silicon between the through hole 141 and the annular groove 142 is 2 microns (μm). In addition, the width of the annular groove 142 is 5 microns (μm). At this time, it is preferred to set an element isolation region 143 (STI) at the bottom of the annular groove 142, and it is desired that there is no STI at the bottom of the through hole 141. Then, dry etching of silicon is performed using the resist as a mask. For example, a vertical shape is obtained by SF6 (silicon hexafluoride) or C4F8 (octafluorocyclobutane) gas.

[0365] Then, if Fig.54 As shown in a, the insulating film 240 is formed by a CVD method. For example, by forming a tetraethoxysilane (TEOS) film with a thickness of 1 micrometer (μm) on the flat portion, a film with a thickness of 0.5 to 0.7 micrometers (μm) is formed on the side wall or bottom of the through hole 141 or the annular groove 142. Note that the insulating film 240 may be silicon nitride (SiN) or silicon nitride oxide (SiON) in addition to SiO2. In addition, film formation may also be performed by an ALD method.

[0366] Next, as shown in b of the figure, a portion of the insulating film 240 at the upper end of the annular trench 142 is opened by photolithography and dry etching, and a hole 241 is formed.

[0367] Then, if Fig.55 As shown in a, the annular silicon between the through hole 141 and the annular groove 142 is removed through the hole 241 by chemical dry etching using SF6 gas. At this time, the etching selectivity with the insulating film 240 is 500 or more, and the scraping of the insulating film 240 when the semi-circumference of the annular silicon is about 160 microns (μm) is less than 0.3 microns (μm). Note that when removing silicon, for example, wet etching with an aqueous solution of tetramethylammonium hydroxide (TMAH) can also be used. In this case, a pattern of multiple holes 241 that are anisotropically etched considering the orientation of the silicon plane is preferred.

[0368] Next, as shown in b of the figure, a rear surface insulating film 131 is formed. For example, a photosensitive resin material is applied, and the resin material is patterned by photolithography according to the through hole 141. At this time, the annular groove 142 is blocked without being completely filled with the resin material, and becomes hollow.

[0369] Then, if Fig.56 As shown in a, the insulating film 240 at the bottom of the through hole 141 and the interlayer film of the wiring layer 150 are removed by dry etching using the patterned resin material as a mask, and the metal wiring of the wiring layer 150 is exposed.

[0370] Next, as shown in b of the figure, rear surface rewiring 121 and through wiring 122 are formed. For example, Cu wiring (rear surface rewiring 121 and through wiring 122) is formed by a semi-additive method using a resist mask and Cu plating. Then, a solder mask 110 (not shown) is formed.

[0371] Note that each of the first to tenth embodiments can be applied to the eleventh embodiment.

[0372] As described above, according to the eleventh embodiment of the present technology, since the depletion layer 250 is formed in the insulating film 240 between the through hole 141 and the ring-shaped trench 142 , the reliability of the device can be improved.

[0373] [First Modification]

[0374] In the eleventh embodiment, one hole 241 is formed at the upper end of the annular trench 142, but it is difficult to remove the annular silicon having one hole. The semiconductor device 100 according to the first modification of the eleventh embodiment is different from the semiconductor device of the eleventh embodiment in that two or more holes 241 are provided.

[0375] Fig.57 1 is an example of a cross-sectional view of a semiconductor device 100 in a first modification of the eleventh embodiment of the present technology. Fig.51 A cross-sectional view taken along the line segment X11-X12 in FIG. 1 and observed from the Z-axis direction.

[0376] like Fig.57 As shown, in the first modification of the eleventh embodiment, two or more holes 241 are formed. This facilitates the removal of the ring-shaped silicon.

[0377] Note that each of the first to ninth embodiments can be applied to the first modification example of the eleventh embodiment.

[0378] As described above, according to the first modification example of the eleventh embodiment of the present technology, since two or more holes 241 are provided, the ring-shaped silicon can be easily removed.

[0379] [Second Modification]

[0380] In the above eleventh embodiment, a circular or elliptical hole 241 is opened at the upper end of the annular groove 142, but the shape of the opening is not limited to a circle or an ellipse. The semiconductor device 100 according to the second modification of the eleventh embodiment is different from the semiconductor device of the eleventh embodiment in that a slit is formed.

[0381] Fig.58 1 is an example of a cross-sectional view of a semiconductor device 100 in a second modification of the eleventh embodiment of the present technology. Fig.51 A cross-sectional view taken along the line segment X11-X12 in FIG. 1 and observed from the Z-axis direction.

[0382] like Fig.58 As shown, in the second modification of the eleventh embodiment, instead of the hole 241, one or more cutouts are formed as slits 242 along a predetermined direction.

[0383] Note that each of the first to ninth embodiments can be applied to the second modification example of the eleventh embodiment.

[0384] As described above, according to the second modification example of the eleventh embodiment of the present technology, since the slit 242 is formed at the upper end of the annular groove 142 , the annular groove can be removed via the slit 242 .

[0385] <12. Twelfth Implementation>

[0386] In the above-mentioned second embodiment, the rear surface insulating film 132 (SiO2, etc.) is formed on the inner wall of the through hole 141, but in this configuration, when the through hole 141 is formed, the shape of the bottom may be a notch or a tail shape. In this case, the rear surface insulating film 132 becomes thinner at the portion having the notch or the tail shape, and a problem of withstand voltage failure or reduced reliability occurs. The semiconductor device 100 according to the twelfth embodiment is different from the semiconductor device of the second embodiment in that the notch and the tail shape are suppressed.

[0387] Fig.59 1 is a diagram showing an example of forming an ideal through hole according to the second embodiment of the present technology. In this figure, the annular groove 142 is omitted. This similarly applies to the subsequent drawings.

[0388] As shown in a of the figure, a photoresist 191 is formed on the upper surface of the rear surface insulating film 132 except for the processing position. Then, as shown in b of the figure, a through hole 141 is formed to penetrate the semiconductor substrate 140. Then, the photoresist 191 is removed, and the rear surface insulating film 132 is also formed on the inner wall of the through hole 141, as shown in c of the figure. Subsequently, as shown in d of the figure, the rear surface insulating film 132 is etched back. Then, as shown in e of the figure, metal wiring (rear surface rewiring 121 and through wiring 122) is formed. In the case where the through hole 141 has an ideal shape as shown in the figure, problems such as withstand voltage failure and reduced reliability will not occur.

[0389] However, if Fig.60 As shown in FIG. 1 , it is also possible to generate a notch at the bottom of the through hole 141. The silicon processing of the semiconductor substrate 140 is performed to reach the wiring layer 150, but when the processing reaches the wiring layer 150, there is no silicon to be processed. Therefore, as shown in the portion surrounded by the dotted line in b of the figure, the silicon is processed in the lateral direction to form a shape called a notch. In the portion of the notch, the rear surface insulating film 132 formed in c of the figure becomes thinner. Therefore, problems such as withstand voltage failure and reduced reliability may occur.

[0390] In addition, if Fig.61 As shown in FIG. 1 , the bottom of the through hole 141 may have a tailing shape. In the case of insufficient silicon processing, as shown in the portion surrounded by the dotted line in b of the figure, the silicon has a tailing shape. In this case, the back surface insulating film 132 on the silicon side wall becomes thinner by the back etching process in d of the figure, and problems such as withstand voltage failure and reduced reliability occur.

[0391] Specifically, when silicon processing is simultaneously performed on the respective portions of the through hole 141 and the annular groove 142 , etching rates are different, so that the etching amount of the pattern with a fast etching rate increases, and notches are easily generated.

[0392] Fig.62 141 is an example of a cross-sectional view of the semiconductor device 100 before forming the through hole 141 according to the twelfth embodiment of the present technology. In the twelfth embodiment, the element isolation region (STI) 146 and the pseudo polysilicon 153 are further arranged to prevent the above-mentioned notch and tailing shape. The figure a is an example of a cross-sectional view of the semiconductor device 100 observed from the Y-axis direction. The figure b is an example of a cross-sectional view taken along the alternating long and short dashed lines in the figure a and observed from the Z-axis direction. Note that the element isolation region 146 is an example of the first element isolation region described in the claims.

[0393] As shown in a and b of the figure, in the semiconductor substrate 140, the element isolation region 146 is arranged in a ring shape around the region to be the bottom of the through hole 141. In addition, in the wiring layer 150, the pseudo polysilicon 153 is arranged in the region where the silicon processing reaches the wiring layer 150 and becomes the bottom of the through hole 141. As shown in b of the figure, the pseudo polysilicon 153 is circular when viewed from the Z-axis direction, and its diameter is smaller than the inner diameter of the element isolation region 146.

[0394] Fig.63 1 is a diagram for explaining a method of manufacturing a semiconductor device 100 until etching back according to a twelfth embodiment of the present technology. Fig.62 The semiconductor device 100 in the state of Fig.63 As shown in a, silicon processing begins. Fig.63 A shows the state in the middle of processing.

[0395] Then, if Fig.63 As shown in FIG. b, silicon processing is performed until the pseudo polysilicon 153 is removed and the insulating film in the wiring layer 150 on the upper part of the Cu wiring 154 remaining in the wiring layer 150 becomes thinner. After the silicon processing, as shown in FIG. c, the rear surface insulating film 132 is formed to cover the side wall and bottom surface of the through hole 141. Subsequently, as shown in FIG. d, the insulating film is processed by etching back until the Cu wiring 154 is exposed. In FIG. d, processing is required to increase the thickness of each film of the insulating film on the upper part of the Cu wiring 154 retained in FIG. b and the rear surface insulating film 132 formed in FIG. c. Note that in this figure, the process after the wiring of the through wiring 122 is omitted.

[0396] By arranging the element isolation region 146, the occurrence of notches and tailing shapes can be suppressed, and the withstand voltage and reliability can be improved. In addition, since the insulating film on the upper part of the Cu wiring 154 is thinned by the pseudo polysilicon 153, the processing amount of the insulating film that exposes the Cu wiring 154 can be reduced. As a result, the processing amount of the rear surface insulating film 132 on the side wall of the through hole 141 is also reduced, and the withstand voltage and reliability can be improved.

[0397] Note that although the element isolation region 146 and the dummy polysilicon 153 are provided, only the element isolation region 146 may be provided. In addition, although the annular trench 142 (not shown) is formed around the through hole 141, the annular trench 142 may not be formed.

[0398] Fig.64 This is an enlarged view of the vicinity of the element isolation region 146 according to the twelfth embodiment of the present technology. Fig.62 , and Fig.64 b, c, d and e in Fig.63Enlarged views of a, b, c, and d in Fig. Fig.64 As shown in the portion surrounded by the dotted line in c, a minute notch may be generated, but enlargement of the notch is suppressed by the element isolation region 146. In addition, the arrangement position of the pseudo polysilicon 153 is processed deeper than its periphery and becomes a contact position with the metal (through wiring 122) by self-alignment.

[0399] As described above, according to the twelfth embodiment of the present technology, since the ring-shaped element isolation region 146 and the dummy polysilicon 153 are arranged, the occurrence of the notch and the tailing shape can be suppressed, and the withstand voltage and reliability can be improved.

[0400] [First Modification]

[0401] In the twelfth embodiment, the circular dummy polysilicon 153 is arranged when viewed from the Z-axis direction, but the shape of the dummy polysilicon 153 is not limited to this shape. The semiconductor device 100 according to the first variation of the twelfth embodiment is different from the semiconductor device of the twelfth embodiment in that the shape of the dummy polysilicon 153 is changed.

[0402] Fig.65 1 is an example of a cross-sectional view of the semiconductor device 100 in the first modification of the twelfth embodiment of the present technology. This figure is an example of a cross-sectional view viewed from the Z-axis direction. The shape of the pseudo polysilicon 153 is not limited to a circle, and can be formed in various patterns. For example, the pseudo polysilicon 153 is formed in a dot pattern.

[0403] As described above, according to the first modification example of the twelfth embodiment of the present technology, the dummy polysilicon 153 can be formed in various patterns other than the circular shape.

[0404] [Second Modification]

[0405] In the twelfth embodiment, the circular dummy polysilicon 153 is arranged when viewed from the Z-axis direction, but the shape of the dummy polysilicon 153 is not limited to this shape. The semiconductor device 100 according to the second variation of the twelfth embodiment is different from the semiconductor device of the twelfth embodiment in that the shape of the dummy polysilicon 153 is changed.

[0406] Fig.66 1 is an example of a cross-sectional view of the semiconductor device 100 in the second modification of the twelfth embodiment of the present technology. The figure is an example of a cross-sectional view observed from the Z-axis direction. For example, the pattern of the pseudo polysilicon 153 is a dot pattern, and each dot-shaped pseudo polysilicon 153 is arranged in a region corresponding to the Cu wiring 154. The area of ​​each pseudo polysilicon 153 is smaller than the area of ​​the corresponding Cu wiring 154. As a result, a portion of the Cu wiring 154 can be opened by self-alignment when etching back.

[0407] As described above, according to the second modification of the twelfth embodiment of the present technology, since the dot-shaped dummy polysilicon 153 is arranged in the region corresponding to the Cu wiring 154 , the portion of the Cu wiring 154 can be opened by self-alignment at the time of etching back.

[0408] <13. Thirteenth Implementation Method>

[0409] In the first embodiment described above, an annular groove 142 is formed around the through hole 141, but in this case, the base material (silicon, etc.) of the semiconductor substrate 140 is kept in an annular shape between the through hole 141 and the annular groove 142. In this configuration, it is necessary to ensure a sufficient width of the cavity in the annular groove 142 to increase the withstand voltage of the rear surface rewiring 121 or to ensure a sufficient ring width to suppress the peeling of the annular silicon. Therefore, there is a problem that high integration of the pattern becomes difficult. The semiconductor device 100 according to the thirteenth embodiment is different from the semiconductor device of the first embodiment in that a low-k material is arranged between the through hole 141 and the annular groove 142.

[0410] Fig.67 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to a thirteenth embodiment of the present technology. The semiconductor device 100 according to the thirteenth embodiment is different from the semiconductor device of the first embodiment in that a ring-shaped low-k material 147 is arranged between the through hole 141 and the ring-shaped trench 142.

[0411] The low-k material 147 is a material having a lower dielectric constant than the dielectric constant of the base material (silicon, etc.) of the semiconductor substrate 140. As the low-k material 147, silicon dioxide (SiO2), silicon nitride containing carbon (SiOC), etc. are used. By arranging the low-k material 147 between the through hole 141 and the annular groove 142, the dielectric constant can be reduced compared to the first embodiment in which silicon is arranged, and measures for stripping the annular silicon surrounding the through hole 141 are not required. This contributes to high integration.

[0412] Note that in the figure, the rear surface of the semiconductor substrate 140 and the ring-shaped groove 142 are covered with the rear surface insulating film 131, and the rear surface insulating film 131 is covered with the solder mask 110. However, as described later, the rear surface insulating film 131 may not be used.

[0413] then, Figures 68 to 70 A method of manufacturing the semiconductor device 100 according to the thirteenth embodiment of the present technology is shown in FIG.

[0414] First, if Fig.68As shown in a, on the front surface side of the semiconductor substrate 140, the pad 152 is formed at the position of the subsequent through wiring 122, and the element isolation region 143 is formed at the position of the ring-shaped trench 142. In addition, the dummy gate 151 is formed up to the position of the ring-shaped trench 142.

[0415] Next, as shown in b of the figure, a through hole 141 and an annular groove 142 are formed by dry etching. Since the etching rate condition and the generation of the notch are easily a trade-off, it is necessary to use the condition appropriately as needed. Note that the annular groove 142 can also be processed after the through hole 141 is processed and the side surface is hardened.

[0416] Next, as shown in c of the figure, after a photosensitive insulating resin is formed on the entire surface as the rear surface insulating film 131, the photosensitive resin around and within the through hole 141 is removed by photolithography and made into a permanent resin by annealing.

[0417] Then, if Fig.69 As shown in a of FIG. 1 , the entire surface is etched back, and the through hole 141 is connected to the pad 152 on the front surface side. Next, as shown in b of the same figure, a low-k material 147 is formed by implanting oxygen ions.

[0418] Then, if Fig.70 As shown in a of FIG. 1 , the rear surface rewiring 121 and the through-wiring 122 are simultaneously formed by a semi-additive method. Next, as shown in b of the same figure, a solder mask 110 is formed.

[0419] As described above, according to the thirteenth embodiment of the present technology, since the ring-shaped low-k material 147 is arranged between the through hole 141 and the annular trench 142, the dielectric constant is reduced, so measures for silicon peeling are not required and high integration becomes easy.

[0420] [Modifications]

[0421] In the above-mentioned thirteenth embodiment, the rear surface of the semiconductor substrate 140 and the annular groove 142 are covered by the rear surface insulating film 131. However, instead of the rear surface insulating film 131, the rear surface may be covered with a low-k material 147. The semiconductor device 100 according to the modification of the thirteenth embodiment is different from the semiconductor device of the thirteenth embodiment in that the rear surface of the semiconductor substrate 140 is covered with the low-k material 147.

[0422] Fig.711 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to a modification of the thirteenth embodiment of the present technology. In the modification of the thirteenth embodiment, the rear surface insulating film 131 is not provided, and instead, the rear surface of the semiconductor substrate 140 is covered with a low-k material 147. In addition, the low-k material 147 covering the rear surface and the upper end of the annular groove 142 is covered with a solder mask 110.

[0423] then, Figure 72 to Figure 74 A method of manufacturing the semiconductor device 100 according to the modification example of the thirteenth embodiment of the present technology is described.

[0424] First, if Fig.72 As shown in a, on the front surface side of the semiconductor substrate 140, the pad 152 is formed at the position of the subsequent through wiring 122, and the element isolation region 143 is formed at the position of the ring-shaped trench 142. In addition, the dummy gate 151 is formed up to the position of the ring-shaped trench 142.

[0425] Next, as shown in b of the figure, a through hole having substantially the same diameter as the ring-shaped trench 142 is formed by dry etching. Then, as shown in c of the figure, a film of a low-k material 147 is formed.

[0426] Then, if Fig.73 As shown in a of the figure, the through hole 141 and the annular groove 142 are formed by dry etching the low-k material 147 in the through hole. Next, as shown in b of the figure, a resist mask 190 is applied except for the through hole 141, and as shown in c of the figure, the through hole 141 is connected to the pad 152 on the front surface side by back etching.

[0427] Then, if Fig.74 As shown in a of FIG. 1 , the rear surface rewiring 121 and the through-wiring 122 are simultaneously formed by a semi-additive method. Next, as shown in b of the same figure, a solder mask 110 is formed.

[0428] As described above, according to the modification example of the thirteenth embodiment of the present technology, since the rear surface of the semiconductor substrate 140 is covered with the low-k material 147 , the step of forming the rear surface insulating film 131 becomes unnecessary.

[0429] <14. Fourteenth Implementation Method>

[0430] In the first embodiment described above, the parasitic capacitance is reduced by forming a hollow annular groove 142 around the through hole 141. However, when a high-frequency signal is transmitted, the signal may be affected by electromagnetic waves from the outside. In addition, since the annular groove 142 is a cavity, the strength of the semiconductor substrate 140 may be weakened. The semiconductor device 100 according to the fourteenth embodiment is different from the semiconductor device of the first embodiment in that the annular groove 142 is filled with a conductive metal.

[0431] Fig.75 14 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to a fourteenth embodiment of the present technology. The semiconductor device 100 according to the fourteenth embodiment is different from the semiconductor device of the first embodiment in that it further includes insulating films 261 and 262, barrier metals 271 and 272, and a conductive metal 281.

[0432] The side surface of the through hole 141 is covered with a barrier metal 272 via an insulating film 262. The rear surface of the semiconductor substrate 140 is also covered with the barrier metal 272, and the rear surface redistribution wiring 121 on the rear surface and the through wiring 122 on the side surface of the through hole 141 are formed on the barrier metal 272. The through hole 141 and the through wiring 122 serve as through silicon vias (TSVs).

[0433] In addition, the side surface of the annular groove 142 is covered by the barrier metal 271 via the insulating film 261. In addition, the conductive metal 281 is embedded in the annular groove 142. The conductive metal 281 is separated from the rear surface redistribution 121 and the through wiring 122. The annular groove 142 in which the conductive metal 281 is embedded serves as a TSV different from the central TSV. The annular groove 142 filled with the conductive metal 281 is hereinafter referred to as a "annular TSV".

[0434] The dimension of the annular TSV in the X-axis direction (in other words, the width) dX3 is, for example, 3 micrometers (μm). In addition, dZ, which is the dimension of the annular TSV in the Z-axis direction (in other words, the height), is, for example, 30 micrometers (μm). When the aspect ratio (AR) exceeds 10, etching processing becomes difficult. Therefore, the dimensions of the width and height can be freely set within the range of the aspect ratio (AR) being 10 or less.

[0435] In addition, the through wiring 122 of the central TSV is connected to the signal potential and exchanges electrical signals (such as high-frequency signals) with the external electrode. On the other hand, the conductive metal 281 of the ring-shaped TSV is connected to the same potential as the semiconductor substrate 140 (ground potential, etc.), and does not exchange signals. As described above, the potential of the through wiring 122 is different from the potential of the conductive metal 281. With this structure, the ring-shaped TSV exerts a shielding effect for reducing electromagnetic waves from the outside. In addition, the effect of increasing the strength of the semiconductor substrate 140 is produced.

[0436] In addition, dX1, which is the diameter of the inner circumference of the central TSV, is, for example, 15 micrometers (μm). A distance dX2 between the central TSV and the annular TSV in the X-axis direction is, for example, 5 micrometers (μm).

[0437] Note that the insulating films 261 and 262 are examples of the first insulating film and the second insulating film described in the claims. The barrier metals 271 and 272 are examples of the first barrier metal and the second barrier metal described in the claims.

[0438] Fig.76 is an example of a cross-sectional view of the semiconductor device taken along line segments A1 - A2 and B1 - B2 according to the fourteenth embodiment of the present technology. Fig.76 The a is along Fig.75 An example of a cross-sectional view taken along the line segment A1-A2, Fig.76 b is along Fig.75 An example of a cross-sectional view taken along line segment B1 - B2 .

[0439] like Fig.76 As shown in a, viewed from the Z-axis direction, the rear surface redistribution 121 is formed in a ring shape along the inner periphery of the through hole 141, and part of it extends in the X-axis direction and is connected to an external electrode (not shown). In addition, the conductive metal 281 extends in the X-axis direction and is connected to the ground potential.

[0440] As shown in b of the figure, a circular barrier metal 271 is formed on a portion of the upper surface of the ring-shaped TSV when viewed from the Z-axis direction. The thick dotted line in a of the figure indicates the outline of the circular portion in b of the figure.

[0441] Fig.77 1 is an example of a cross-sectional view of a semiconductor device taken along line segment C1-C2 according to the fourteenth embodiment of the present technology. As shown in the figure, the side surface of the through hole 141 is covered with a barrier metal 272, and the through wiring 122 is formed on the barrier metal 272. The barrier metal 272 is separated from the semiconductor substrate 140 by the insulating film 262. In addition, the side surface of the annular groove 142 is covered with the barrier metal 271, and the conductive metal 281 is embedded in the annular groove 142. The barrier metal 271 is separated from the semiconductor substrate 140 by the insulating film 261.

[0442] then, Figures 78 to 80 A method of manufacturing the semiconductor device 100 according to the fourteenth embodiment of the present technology is shown in FIG.

[0443] As shown in a of the figure, the semiconductor substrate 140 is placed so that the rear surface which is one of the two surfaces of the semiconductor substrate 140 on which the wiring layer 150 is not formed is located on the upper side.

[0444] Then, as shown in b of the figure, by photolithography and dry etching, a ring-shaped groove 142 is formed in the semiconductor substrate 140. Thereafter, as shown in c of the figure, an insulating film 261 is formed by a CVD method in order to ensure insulating properties between the conductive metal 281 and the semiconductor substrate 140. As the insulating film 261, silicon oxynitride (SiON) or the like is used.

[0445] Then, if Fig.79 As shown in a, a barrier metal 271 and a seed metal are deposited by sputtering. As the barrier metal 271, for example, any one of titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN) and ruthenium (Ru) is used. Then, the annular groove 142 is filled with a conductive metal 281 by electroplating. As the conductive metal 281, for example, any one of copper (Cu), aluminum (Al), tungsten (W), cobalt (Co), silver (Ag), gold (Au), iron (Fe) and lead (Pb) is used. Here, it is assumed that Cu is filled as the conductive metal 281.

[0446] Then, as shown in b of the figure, extra Cu and SiON on the rear surface of the semiconductor substrate 140 are removed by chemical mechanical polishing (CMP). Next, as shown in c of the figure, a rear surface insulating film 131 such as SiON is formed on the rear surface. In addition, a through hole 141 is formed to pass through the rear surface insulating film 131.

[0447] Then, if Fig.80 As shown in a, a conductive metal 281 is further formed by a second Cu plating to ground the ring-shaped TSV. In addition, an insulating film 262 and a barrier metal 272 are formed, and a rear surface rewiring 121 and a through wiring 122 are formed on the barrier metal 272. As a result, the central TSV is connected to the external electrode, and electrical exchange can be performed.

[0448] Finally, as shown in b of the same figure, the rear surface is covered with the solder mask 110 , and oxidation of the ring TSV, the central TSV, and the rear surface rewiring 121 is prevented.

[0449] As described above, according to the fourteenth embodiment of the present technology, since the conductive metal 281 is embedded in the ring-shaped groove 142 , electromagnetic waves from the outside can be blocked and the strength of the semiconductor substrate 140 can be improved.

[0450] [First Modification]

[0451] In the above-described fourteenth embodiment, the conductive metal 281 is embedded in the annular trench 142, but in this configuration, it is preferable to further reduce the parasitic capacitance. The semiconductor device 100 according to the first variation of the fourteenth embodiment is different from the semiconductor device of the fourteenth embodiment in that the annular trench is double.

[0452] Fig.81 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 in a first modification of the fourteenth embodiment of the present technology. The semiconductor device 100 according to the first modification of the fourteenth embodiment is different from the first embodiment in that a hollow annular groove 290 is further formed between the annular groove 142 and the through hole 141. Note that the annular groove 142 is an example of a first annular groove described in the claims, and the annular groove 290 is an example of a second annular groove described in the claims.

[0453] As shown in the figure, by adding the hollow annular groove 290, the parasitic capacitance can be reduced compared with the fourteenth embodiment.

[0454] Fig.82 It is an example of a cross-sectional view of the semiconductor device taken along line segments A1 - A2 and B1 - B2 in the first modification example of the fourteenth embodiment of the present technology. Fig.82 The a is along Fig.81 An example of a cross-sectional view taken along line segment A1-A2, and Fig.82 b is along Fig.81 An example of a cross-sectional view taken along line segment B1 - B2 .

[0455] like Fig.82 As shown in FIG. 1 , the cross-sectional view taken along line segment A1-A2 in the first variant of the fourteenth embodiment is similar to that in the fourteenth embodiment. As shown in b of the figure, in the first variant of the fourteenth embodiment, a circular barrier metal 271 is also formed on a portion of the upper surface of the annular TSV.

[0456] Fig.83 14 is an example of a cross-sectional view of the semiconductor device taken along the line segment C1 - C2 in the first modification of the fourteenth embodiment of the present technology. As shown in this figure, a hollow annular groove 290 is formed between the annular groove 142 and the through hole 141 .

[0457] As described above, according to the first modification example of the fourteenth embodiment of the present technology, since the hollow annular groove 290 is further formed between the annular groove 142 and the through hole 141 , the parasitic capacitance can be reduced.

[0458] [Second Modification]

[0459] In the above-mentioned fourteenth embodiment, the conductive metal 281 is embedded in the annular groove 142, but with this structure, it is difficult to block various electromagnetic waves. The semiconductor device 100 according to the second variation of the fourteenth embodiment is different from the semiconductor device of the first embodiment in that an annular groove 290 in which the conductive metal 282 is embedded is further formed between the annular groove 142 and the through hole 141.

[0460] Fig.84 1 is a cross-sectional view showing a configuration example of a semiconductor device 100 according to a second modification of the fourteenth embodiment of the present technology. The semiconductor device 100 according to the second modification of the fourteenth embodiment is different from the semiconductor device of the first embodiment in that an annular groove 290 in which a conductive metal 282 is embedded is further formed between the annular groove 142 and the through hole 141.

[0461] The kind of the conductive metal 282 is different from the kind of the conductive metal 281. For example, Cu is used as the conductive metal 281, and Fe is used as the conductive metal 282. Cu blocks β rays, and Fe blocks α rays and γ rays. As described above, by filling the double annular grooves with different kinds of conductive metals 281 and 282, various electromagnetic waves from the outside can be blocked. As a result, the semiconductor device 100 can be applied to devices mounted on aircraft or medical equipment.

[0462] Note that the annular groove 142 is an example of a first annular groove described in the claims, and the annular groove 290 is an example of a second annular groove described in the claims. The conductive metals 281 and 282 are examples of a first conductive metal and a second conductive metal described in the claims.

[0463] Fig.85 It is an example of a cross-sectional view of the semiconductor device taken along line segments A1 - A2 and B1 - B2 in the second modification example of the fourteenth embodiment of the present technology. Fig.85 The a is along Fig.84 An example of a cross-sectional view taken along line segment A1-A2, and Fig.85 b is along Fig.84 An example of a cross-sectional view taken along line segment B1 - B2 .

[0464] like Fig.85 As shown in a of the figure, the cross-sectional view taken along the line segment A1-A2 in the second modification of the fourteenth embodiment is similar to the cross-sectional view of the fourteenth embodiment. As shown in b of the figure, in the second modification of the fourteenth embodiment, the barrier metal 271 is formed in the region spanning the annular grooves 142 and 290. The shape of this portion viewed from the Z-axis direction is a rectangle in b of the figure, but is not limited to a rectangle and may be an ellipse or the like.

[0465] Fig.86 This is an example of a cross-sectional view of the semiconductor device taken along line segment C1-C2 in the second modification of the fourteenth embodiment of the present technology. As shown in this figure, an annular trench 290 in which a conductive metal 282 is embedded is formed between the annular trench 142 and the through hole 141.

[0466] As described above, according to the first modification of the fourteenth embodiment of the present technology, since the annular groove 290 in which the conductive metal 282 is embedded is further formed between the annular groove 142 and the through hole 141 , various electromagnetic waves from the outside can be blocked.

[0467] <15. Application examples of mobile objects>

[0468] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body (such as a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, a personal mobility tool, an airplane, a drone, a ship, and a robot).

[0469] Fig.87 is a block diagram depicting an example of a schematic configuration of a vehicle control system, which is an example of a moving body control system to which the technology according to an embodiment of the present disclosure can be applied.

[0470] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.87 In the depicted example, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an exterior information detection unit 12030, an interior information detection unit 12040, and an integrated control unit 12050. In addition, as a functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound / image output section 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0471] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a drive force of the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, and the like.

[0472] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a backup light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave transmitted from a mobile device as a substitute for a key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0473] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to the imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform a process of detecting an object such as a person, a vehicle, an obstacle, a sign, text on the road surface, etc., or a process of detecting the distance of the object.

[0474] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0475] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0476] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle acquired by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control of functions intended to implement an advanced driver assistance system (ADAS), including collision prevention or shock absorption for the vehicle, follow-up driving based on a following distance, driving to maintain the vehicle speed, warning of vehicle collision, warning of vehicle deviation from a lane, and the like.

[0477] In addition, the microcomputer 12051 can perform coordinated control intended for autonomous driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about the outside or inside of the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, which enables the vehicle to drive automatically without relying on the driver's operation, etc.

[0478] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle acquired by the vehicle exterior information detection unit 12030. For example, the microcomputer 12051 can perform coordinated control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0479] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Fig.87 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and an instrument panel 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0480] Fig.88 is a diagram depicting an example of the installation position of the imaging unit 12031.

[0481] exist Fig.88 In the figure, the imaging unit 12031 includes imaging units 12101, 12102, 12103, 12104 and 12105.

[0482] The imaging units 12101, 12102, 12103, 12104 and 12105 are arranged, for example, at positions on the front nose, side mirrors, rear bumper and rear door of the vehicle 12100 and at positions on the upper part of the windshield inside the vehicle. The imaging unit 12101 arranged at the front nose and the imaging unit 12105 arranged at the upper part of the windshield inside the vehicle mainly acquire images in front of the vehicle 12100. The imaging units 12102 and 12103 arranged at the side mirrors mainly acquire images on the sides of the vehicle 12100. The imaging unit 12104 arranged at the rear bumper or rear door mainly acquires images at the rear of the vehicle 12100. The imaging unit 12105 arranged at the upper part of the windshield inside the vehicle is mainly used to detect vehicles in front, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0483] By the way, Fig.88Depicting examples of the shooting ranges of the imaging units 12101 to 12104. Imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose. Imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the side mirrors. Imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 observed from above is obtained by superimposing image data shot by the imaging units 12101 to 12104.

[0484] At least one of the imaging units 12101 to 12104 may have a function of acquiring distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0485] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information acquired from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object that exists on the driving path of the vehicle 12100 and travels at a predetermined speed (e.g., equal to or greater than 0 km / hour) in the same direction as the vehicle 12100 as the leading vehicle. In addition, the microcomputer 12051 can pre-set the following distance to be maintained in front of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. Thus, coordinated control intended for autonomous driving can be performed, which allows the vehicle to travel automatically without relying on the driver's operation, etc.

[0486] For example, the microcomputer 12051 can classify the three-dimensional object data about the three-dimensional object into three-dimensional object data of two-wheeled vehicles, standard-sized vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. When the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0487] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. This recognition of a pedestrian is performed, for example, by a process of extracting feature points in the captured images of the imaging units 12101 to 12104, which are infrared cameras, and a process of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer 12051 determines that a pedestrian exists in the captured images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed as superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0488] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. For example, the technology according to the present disclosure can be applied to the imaging unit 12031 in the above configuration. Specifically, Figure 1 The semiconductor device 100 in the embodiment can be applied to the imaging portion 12031. By applying the technology according to the present disclosure to the imaging portion 12031, the yield of the semiconductor device 100 can be increased and the reliability of the vehicle control system can be improved.

[0489] Note that the above-mentioned embodiments show examples for embodying the present technology, and the matters in the embodiments and the matters specifying the present invention in the claims have a corresponding relationship. Similarly, the matters specifying the present invention in the claims have a corresponding relationship with the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to these embodiments, and can be embodied by applying various modifications to the embodiments without departing from the gist of the present technology.

[0490] Note that the advantageous effects described in this specification are merely examples and are not limited, and other advantageous effects may be provided.

[0491] Note that the present technology may also have the following configurations.

[0492] (1) A semiconductor device comprising:

[0493] a semiconductor substrate having a wiring layer formed on a front surface of the semiconductor substrate;

[0494] A through hole penetrates through a semiconductor substrate;

[0495] a through wiring formed along a side surface of the through hole; and

[0496] The annular groove surrounds the periphery of the through hole when viewed from a direction perpendicular to the rear surface of the semiconductor substrate relative to the front surface.

[0497] (2) The semiconductor device according to (1),

[0498] When viewed from a direction parallel to the rear surface, a cavity is formed inside the annular groove.

[0499] (3) The semiconductor device according to (2), further comprising:

[0500] a rear surface insulating film covering a rear surface of the semiconductor substrate relative to the front surface,

[0501] wherein the rear surface insulating film includes a first rear surface insulating film and a second rear surface insulating film stacked together, and

[0502] The second rear surface insulating film covers the rear surface and covers a side wall of at least one of the through hole and the ring-shaped trench.

[0503] (4) The semiconductor device according to (3), further comprising:

[0504] A first element isolation region is formed around the bottom of the through hole.

[0505] (5) The semiconductor device according to (3),

[0506] Wherein, the second rear surface insulating film includes a fixed charge film.

[0507] (6) The semiconductor device according to any one of (2) to (5),

[0508] The through hole includes a first through hole and a second through hole.

[0509] An annular groove is formed around the first through hole, and

[0510] No annular groove is formed around the second through hole.

[0511] (7) The semiconductor device according to (2),

[0512] wherein the through hole includes a first through hole and a second through hole arranged adjacent to each other in a direction parallel to the rear surface,

[0513] The annular groove includes a first annular groove formed around the first through hole and a second annular groove formed around the second through hole, and

[0514] The first annular groove and the second annular groove share a common portion.

[0515] (8) The semiconductor device according to (7),

[0516] The width of the shared portion between the first annular groove and the second annular groove is substantially the same as the width of the unshared portion.

[0517] (9) The semiconductor device according to any one of (2) to (8), further comprising:

[0518] a rear surface insulating film covering a rear surface of the semiconductor substrate relative to the front surface; and

[0519] The rear surface rewiring is formed in the rear surface along the periphery of the through hole and the rear surface insulating film.

[0520] (10) The semiconductor device according to (9),

[0521] Here, the outer circumference of the rear surface rewiring formed around the through hole is larger than the outer circumference of the annular groove.

[0522] (11) The semiconductor device according to (9),

[0523] The width of a portion of the rear surface rewiring that crosses the annular groove is thicker than other portions.

[0524] (12) The semiconductor device according to (9),

[0525] wherein an opening having a larger periphery than that of the through hole is formed in the rear surface insulating film, and

[0526] The wiring is then routed around the rear surface of the through hole to cover the rear surface inside the opening.

[0527] (13) The semiconductor device according to any one of (2) to (12), further comprising:

[0528] On-chip lens;

[0529] a photoelectric conversion unit; and

[0530] External terminals.

[0531] (14) The semiconductor device according to any one of (2) to (13), further comprising:

[0532] a rear surface insulating film covering a rear surface of the semiconductor substrate relative to the front surface,

[0533] Here, an end portion of the rear surface insulating film includes a tapered shape.

[0534] (15) The semiconductor device according to any one of (2) to (14),

[0535] The diameter of the through hole is 1.5 to 4.0 times the width of the annular groove.

[0536] (16) The semiconductor device according to (15),

[0537] The diameter of the through hole is 2.0 to 3.0 times the width of the annular groove.

[0538] (17) The semiconductor device according to any one of (2) to (16), further comprising:

[0539] a solder mask covering the insulating film and the through hole,

[0540] When viewed from a direction parallel to the rear surface, a cavity blocked by a solder mask is formed inside the through hole.

[0541] (18) The semiconductor device according to (17), further comprising:

[0542] The low-k material is formed between the through hole and the annular trench and has a dielectric constant lower than that of the semiconductor substrate.

[0543] (19) The semiconductor device according to (18), further comprising:

[0544] a rear surface insulating film covering a rear surface of the semiconductor substrate relative to the front surface and covering the annular groove,

[0545] Here, the solder mask also covers the rear surface insulating film.

[0546] (20) The semiconductor device according to (18),

[0547] wherein the low-k material covers a rear surface of the semiconductor substrate relative to the front surface, and

[0548] The solder mask also covers the low-k material and the annular trench.

[0549] (21) The semiconductor device according to any one of (2) to (20), further comprising:

[0550] The first element isolation region is formed between the wiring layer and the annular trench.

[0551] (22) The semiconductor device according to any one of (2) to (21),

[0552] The wiring layer includes a dummy gate formed between the through hole and the annular trench.

[0553] (23) The semiconductor device according to any one of (2) to (22), further comprising:

[0554] a rear surface insulating film covering a rear surface of the semiconductor substrate relative to the front surface; and

[0555] An insulating reinforcement film is adjacent to the wiring layer and covers the periphery of the through hole.

[0556] (24) The semiconductor device according to (23),

[0557] wherein the through hole has a step at a predetermined depth position when viewed from a direction parallel to the rear surface,

[0558] The rear surface insulating film covers the periphery of the through hole in the range from the rear surface to the depth position, and

[0559] The reinforcement film covers the periphery of the through hole in a range from a depth position to the wiring layer, and is formed between the base material of the semiconductor substrate and the through hole when viewed in the vertical direction.

[0560] (25) The semiconductor device according to (23),

[0561] Here, a cross-sectional shape of each of the through hole and the reinforcement film viewed from a parallel direction has a curved taper.

[0562] (26) The semiconductor device according to (23),

[0563] wherein the through hole has a step at a predetermined depth position as viewed from a direction parallel to the rear surface, the reinforcing film covers the periphery of the through hole in a range from the depth position to the wiring layer, and

[0564] The rear surface insulating film covers the periphery of the through hole and the periphery of the reinforcement film.

[0565] (27) The semiconductor device according to any one of (23) to (26),

[0566] Wherein, when viewed from a vertical direction, the shape of the through hole includes a circle or a polygon.

[0567] (28) The semiconductor device according to any one of (23) to (27),

[0568] Wherein, when viewed from a vertical direction, the through hole covers the entire periphery of the through hole.

[0569] (29) The semiconductor device according to any one of (23) to (27),

[0570] When viewed from a vertical direction, the reinforcing film covers a portion of the periphery of the through hole.

[0571] (30) The semiconductor device according to (23), wherein the base material of the semiconductor substrate has a step at a predetermined depth position when viewed from a direction parallel to the rear surface,

[0572] The rear surface insulating film covers the periphery of the through hole in the range from the rear surface to the depth position, and

[0573] The reinforcement film covers the periphery of the through hole in a range from a depth position to the wiring layer.

[0574] (31) The semiconductor device according to any one of (2) to (30), further comprising:

[0575] The first protection member is disposed adjacent to the wiring layer in the annular groove.

[0576] (32) The semiconductor device according to (31),

[0577] Herein, the first protective member includes an insulating resin or an inorganic film.

[0578] (33) The semiconductor device according to (31) or (32),

[0579] Among them, the shape of the first protective member is recessed toward the wiring layer side when viewed from a direction parallel to the rear surface.

[0580] (34) The semiconductor device according to any one of (31) to (33),

[0581] The first protective member covers two corners on the inner and outer peripheral sides of the annular groove.

[0582] (35) The semiconductor device according to any one of (31) to (33),

[0583] The first protective member covers only the corners on the inner circumference side of the annular groove.

[0584] (36) The semiconductor device according to any one of (31) to (35), further comprising:

[0585] The second protection member is disposed adjacent to the wiring layer in the through hole.

[0586] (37) The semiconductor device according to (2), further comprising:

[0587] a rear surface insulating film covering a rear surface of the semiconductor substrate relative to the front surface,

[0588] Here, the width of the annular groove on the wiring layer side is narrower than the width of the annular groove on the rear surface insulating film side.

[0589] (38) The semiconductor device according to (37),

[0590] When viewed from a direction parallel to the rear surface, the cross-sectional shape of the annular groove has a taper.

[0591] (39) The semiconductor device according to (37),

[0592] Among them, when viewed from a direction parallel to the rear surface, the corners of the annular groove are rounded.

[0593] (40) The semiconductor device according to (39),

[0594] The corner is located in the wiring layer.

[0595] (41) The semiconductor device according to (39),

[0596] The corner portion crosses the boundary between the semiconductor substrate and the wiring layer.

[0597] (42) The semiconductor device according to any one of (39) to (41),

[0598] Among the inner and outer circumferences of the annular groove, only the corners on the inner circumference side are rounded.

[0599] (43) The semiconductor device according to any one of (2) to (42),

[0600] Also includes:

[0601] an insulating film formed between the annular groove and the through hole; and

[0602] A ring-shaped depletion layer is formed in the insulating film.

[0603] (44) The semiconductor device according to (43),

[0604] The insulating film has a predetermined number of openings formed at ends of the depletion layer.

[0605] (45) The semiconductor device according to (44),

[0606] Among them, a hole is formed as an opening at the end.

[0607] (46) The semiconductor device according to (44),

[0608] Among them, a slit is formed as an opening at the end.

[0609] (47) The semiconductor device according to (1) further includes: a conductive metal embedded in the annular groove.

[0610] (48) The semiconductor device according to (47),

[0611] Among them, the potential of the through wiring is different from the potential of the conductive metal.

[0612] (49) The semiconductor device according to (47) or (48), further including: a first insulating film covering a side surface of the ring-shaped trench.

[0613] (50) The semiconductor device according to (49), further including: a second insulating film covering a side surface of the through hole.

[0614] (51) The semiconductor device according to any one of (47) to (50),

[0615] Also includes:

[0616] a first barrier metal covering a side surface of the annular trench; and

[0617] a second barrier metal covering the side surface of the through hole,

[0618] Wherein, each of the first barrier metal and the second barrier metal includes any one of titanium, titanium nitride, tantalum, tantalum nitride and ruthenium.

[0619] (52) The semiconductor device according to any one of (47) to (51),

[0620] The conductive metal includes any one of copper, aluminum, tungsten, cobalt, silver, gold, iron and lead.

[0621] (53) The semiconductor device according to any one of (47) to (52),

[0622] The annular groove includes a first annular groove and a second annular groove formed between the first annular groove and the through hole.

[0623] (54) The semiconductor device according to (53),

[0624] The conductive metal includes a first conductive metal embedded in the first annular groove and a second conductive metal embedded in the second annular groove, and

[0625] The second conductive metal is of a different type from the first conductive metal.

[0626] (55) A method for manufacturing a semiconductor device, comprising:

[0627] an etching step of forming an annular groove together with a through hole penetrating the semiconductor substrate having the wiring layer formed on the front surface by etching, wherein the annular groove surrounds the periphery of the through hole when viewed from a direction perpendicular to the rear surface relative to the front surface; and

[0628] In the wiring process, through wiring is formed along the side surface of the through hole.

[0629] (56) The method for manufacturing a semiconductor device according to (55),

[0630] The semiconductor substrate includes a second element isolation region, which is arranged around a region serving as a bottom of the through hole.

[0631] (57) The method for manufacturing a semiconductor device according to (56),

[0632] wherein the wiring layer includes pseudo polysilicon arranged in a region serving as a bottom of the through hole, and

[0633] The dummy polysilicon is removed during the etching process.

[0634] (58) The method for manufacturing a semiconductor device according to (57),

[0635] The pattern of the pseudo polysilicon includes a dot pattern.

[0636] (59) The method for manufacturing a semiconductor device according to (58), wherein the wiring layer includes a predetermined number of wirings, and

[0637] The dummy polysilicon is arranged in a dot shape at a position corresponding to each of the wirings.

[0638] Reference Symbols List

[0639] 100 Semiconductor devices

[0640] 110 Solder Mask

[0641] 121 Rear Surface Rewiring

[0642] 122 Through wiring

[0643] 131, 132 rear surface insulation film

[0644] 140 Semiconductor substrate

[0645] 141, 141-1, 141-2, 141-3 through holes

[0646] 142, 142-1, 142-2, 142-3, 290 annular groove

[0647] 143, 146 Component isolation area

[0648] 144, 145 Notch

[0649] 147 Low-k Materials

[0650] 149, 149-1, 149-2, 149-3 through-electrodes

[0651] 150 wiring layers

[0652] 151 Pseudo Gate

[0653] 152 pads

[0654] 153 Pseudo polysilicon

[0655] 154 Cu wiring

[0656] 160 External connection terminals

[0657] 170 Photoelectric conversion layer

[0658] 180 On-chip lens

[0659] 190 Resist Mask

[0660] 191 Photoresist

[0661] 210 Enhanced Film

[0662] 220, 231, 232 protection components

[0663] 240, 261, 262 insulation film

[0664] 241 holes

[0665] 242 Slit

[0666] 250 Depletion layer

[0667] 271, 272 Barrier Metal

[0668] 281, 282 Conductive metal

[0669] 12031 Imaging Department.

Claims

1. A semiconductor device comprising: a semiconductor substrate having a wiring layer formed on a front surface of the semiconductor substrate; A through hole penetrating the semiconductor substrate; A through wiring is formed along a side surface of the through hole; as well as The annular groove surrounds the periphery of the through hole when viewed from a direction perpendicular to a rear surface of the semiconductor substrate relative to the front surface.

2. The semiconductor device according to claim 1, in, When viewed from a direction parallel to the rear surface, a cavity is formed inside the annular groove.

3. The semiconductor device according to claim 2, further comprising: a rear surface insulating film covering the rear surface of the semiconductor substrate relative to the front surface, wherein the rear surface insulating film comprises a first rear surface insulating film and a second rear surface insulating film stacked together, and The second rear surface insulating film covers the rear surface and covers a side wall of at least one of the through hole and the annular trench.

4. The semiconductor device according to claim 3, further comprising: A first element isolation region is formed around the bottom of the through hole.

5. The semiconductor device according to claim 3, in, The second rear surface insulating film includes a fixed charge film.

6. The semiconductor device according to claim 2, in, The through hole comprises a first through hole and a second through hole, The annular groove is formed around the first through hole, and The annular groove is not formed around the second through hole.

7. The semiconductor device according to claim 2, in, The through holes include a first through hole and a second through hole arranged adjacent to each other in a direction parallel to the rear surface, The annular groove includes a first annular groove formed around the first through hole and a second annular groove formed around the second through hole, and The first annular groove and the second annular groove share a common portion.

8. The semiconductor device according to claim 7, in, The width of the shared portion of the first annular groove and the second annular groove is substantially the same as the width of the unshared portion.

9. The semiconductor device according to claim 2, further comprising: a rear surface insulating film covering the rear surface of the semiconductor substrate relative to the front surface; as well as A rear surface rewiring is formed in the rear surface along the periphery of the through hole and the rear surface insulating film.

10. The semiconductor device according to claim 9, in, The outer circumference of the rear surface rewiring formed around the through hole is larger than the outer circumference of the annular groove.

11. The semiconductor device according to claim 9, in, The width of a portion of the rear surface rewiring that crosses the annular groove is thicker than other portions.

12. The semiconductor device according to claim 9, in, An opening having a larger periphery than that of the through hole is formed in the rear surface insulating film, and The rear surface surrounding the through hole is rewired to cover the rear surface inside the opening.

13. The semiconductor device according to claim 2, further comprising: On-chip lens; Photoelectric conversion unit; as well as External terminals.

14. The semiconductor device according to claim 2, further comprising: a rear surface insulating film covering the rear surface of the semiconductor substrate relative to the front surface, Wherein, the end portion of the rear surface insulating film includes a tapered shape.

15. The semiconductor device according to claim 2, in, The diameter of the through hole is 1.5 to 4.0 times the width of the annular groove.

16. The semiconductor device according to claim 15, in, The diameter of the through hole is 2.0 to 3.0 times the width of the annular groove.

17. The semiconductor device according to claim 2, further comprising: a solder mask covering the through hole, Wherein, when viewed from a direction parallel to the rear surface, a cavity blocked by the solder mask is formed inside the through hole.

18. The semiconductor device according to claim 17, further comprising: A low-k material is formed between the through hole and the annular trench and has a dielectric constant lower than that of the semiconductor substrate.

19. The semiconductor device according to claim 18, further comprising: a rear surface insulating film covering the rear surface of the semiconductor substrate relative to the front surface and covering the annular groove, Wherein, the solder mask also covers the rear surface insulating film.

20. The semiconductor device according to claim 18, in, The low-k material covers the rear surface of the semiconductor substrate relative to the front surface, and The solder mask also covers the low-k material and the annular trench.

21. The semiconductor device according to claim 2, further comprising: A second element isolation region is formed between the wiring layer and the annular trench.

22. The semiconductor device according to claim 2, in, The wiring layer includes a dummy gate formed between the through hole and the ring-shaped trench.

23. The semiconductor device according to claim 2, further comprising: a rear surface insulating film covering the rear surface of the semiconductor substrate relative to the front surface; as well as An insulating reinforcement film is adjacent to the wiring layer and covers the periphery of the through hole.

24. The semiconductor device according to claim 23, in, The through hole has a step at a predetermined depth position when viewed from a direction parallel to the rear surface. The rear surface insulating film covers the periphery of the through hole in a range from the rear surface to the depth position, and The reinforcement film covers the periphery of the through hole in a range from the depth position to the wiring layer, and is formed between a base material of the semiconductor substrate and the through hole when viewed in a vertical direction.

25. The semiconductor device according to claim 23, in, A cross-sectional shape of each of the through hole and the reinforcement film viewed from a parallel direction has a curved taper.

26. The semiconductor device according to claim 23, in, The through hole has a step at a predetermined depth position when viewed from a direction parallel to the rear surface. The reinforcement film covers the periphery of the through hole in a range from the depth position to the wiring layer, and The rear surface insulating film covers a periphery of the through hole and a periphery of the reinforcement film.

27. The semiconductor device according to claim 23, in, When viewed from a vertical direction, the through hole has a circular or polygonal shape.

28. The semiconductor device according to claim 23, in, When viewed from a vertical direction, the through hole covers the entire periphery of the through hole.

29. The semiconductor device according to claim 23, in, When viewed from a vertical direction, the reinforcement film covers a portion of the periphery of the through hole.

30. The semiconductor device according to claim 23, wherein The base material of the semiconductor substrate has a step at a predetermined depth position when viewed from a direction parallel to the rear surface. The rear surface insulating film covers the periphery of the through hole in a range from the rear surface to the depth position, and The reinforcement film covers the periphery of the through hole in a range from the depth position to the wiring layer.

31. The semiconductor device according to claim 2, further comprising: A first protective member is disposed adjacent to the wiring layer in the annular groove.

32. The semiconductor device according to claim 31, in, The first protective member includes an insulating resin or an inorganic film.

33. The semiconductor device according to claim 31, in, The first protective member has a shape that is recessed toward the wiring layer side when viewed in a direction parallel to the rear surface.

34. The semiconductor device according to claim 31, in, The first protection member covers both corners on the inner and outer peripheral sides of the annular groove.

35. The semiconductor device according to claim 31, in, The first protective member covers only the corners on the inner peripheral side of the annular groove.

36. The semiconductor device according to claim 31, further comprising: A second protection member is disposed in the through hole adjacent to the wiring layer.

37. The semiconductor device according to claim 2, further comprising: a rear surface insulating film covering the rear surface of the semiconductor substrate relative to the front surface, Here, the width of the annular groove on the wiring layer side is narrower than the width of the annular groove on the rear surface insulating film side.

38. The semiconductor device according to claim 37, in, The cross-sectional shape of the annular groove has a taper when viewed from a direction parallel to the rear surface.

39. The semiconductor device according to claim 37, in, The annular groove has rounded corners when viewed from a direction parallel to the rear surface.

40. The semiconductor device according to claim 39, in, The corner portion is located in the wiring layer.

41. The semiconductor device according to claim 39, in, The corner portion straddles a boundary between the semiconductor substrate and the wiring layer.

42. The semiconductor device according to claim 39, in, Of the inner and outer circumferences of the annular groove, only the inner circumference side corners are rounded.

43. The semiconductor device according to claim 2, Also includes: an insulating film formed between the annular groove and the through hole; as well as A ring-shaped depletion layer is formed in the insulating film.

44. The semiconductor device according to claim 43, in, The insulating film has a predetermined number of openings formed at an end portion of the depletion layer.

45. The semiconductor device according to claim 44, in, A hole serving as an opening is formed at the end portion.

46. ​​The semiconductor device according to claim 44, in, A slit serving as an opening is formed at the end portion.

47. The semiconductor device according to claim 1, further comprising: A conductive metal is embedded in the annular groove.

48. The semiconductor device according to claim 47, in, The through wiring has a potential different from that of the conductive metal.

49. The semiconductor device according to claim 47, further comprising: A first insulating film covers a side surface of the annular trench.

50. The semiconductor device according to claim 49, further comprising: A second insulating film covers a side surface of the through hole.

51. The semiconductor device according to claim 47, Also includes: a first barrier metal covering a side surface of the annular groove; as well as a second barrier metal covering the side surface of the through hole, Wherein, each of the first barrier metal and the second barrier metal includes any one of titanium, titanium nitride, tantalum, tantalum nitride and ruthenium.

52. The semiconductor device according to claim 47, in, The conductive metal includes any one of copper, aluminum, tungsten, cobalt, silver, gold, iron and lead.

53. The semiconductor device according to claim 47, in, The annular groove includes a first annular groove and a second annular groove formed between the first annular groove and the through hole.

54. The semiconductor device according to claim 53, in, The conductive metal includes a first conductive metal embedded in the first annular groove and a second conductive metal embedded in the second annular groove, and The second conductive metal is of a different type from the first conductive metal.

55. A method of manufacturing a semiconductor device, comprising: an etching step of forming an annular groove together with a through hole penetrating the semiconductor substrate having the wiring layer formed on the front surface by etching, wherein the annular groove surrounds the periphery of the through hole when viewed from a direction perpendicular to the rear surface relative to the front surface; and The wiring step forms a through wiring along the side surface of the through hole.

56. The method for manufacturing a semiconductor device according to claim 55, in, The semiconductor substrate includes a second element isolation region arranged around a region serving as a bottom of the through hole.

57. The method for manufacturing a semiconductor device according to claim 56, in, The wiring layer includes dummy polysilicon arranged in a region serving as a bottom of the through hole, and The dummy polysilicon is removed in the etching process.

58. The method for manufacturing a semiconductor device according to claim 57, in, The pattern of the pseudo polysilicon includes a dot pattern.

59. The method for manufacturing a semiconductor device according to claim 58, wherein: The wiring layer includes a predetermined number of wirings, and The dummy polysilicon is arranged in a dot shape at a position corresponding to each of the wirings.

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