Semiconductor device and computing device

Abstract

One embodiment of the present invention provides a novel semiconductor device. The semiconductor device includes a flip-flop circuit and a memory circuit, the memory circuit including a first transistor, a second transistor, a first capacitor, and a second capacitor, the semiconductor device further includes a substrate, a first insulator disposed on the substrate, and a second insulator disposed on the first insulator, the first insulator includes a first opening portion and a second opening portion extending in a direction perpendicular to a surface of the substrate, the second insulator includes a third opening portion and a fourth opening portion extending in a direction perpendicular to the surface of the substrate, and the flip-flop circuit is provided on the substrate. At least a portion of each of the first capacitor and the second capacitor is provided in the first opening portion and the second opening portion, and at least a portion of each of the first transistor and the second transistor is provided in the third opening portion and the fourth opening portion.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a computing device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of one embodiment of the invention disclosed in this specification, etc. relates to an object, a method, a driving method or a manufacturing method. One embodiment of the present invention relates to a process, a machine, a product or a composition. Specifically, as an example of the technical field of one embodiment of the present invention disclosed in this specification, etc., there can be cited semiconductor devices, display devices, light-emitting devices, power storage devices, optical devices, camera devices, lighting devices, computing devices, control devices, storage devices, input devices, output devices, input-output devices, signal processing devices, computing processing devices, electronic computers, electronic devices, their driving methods or their manufacturing methods. Background Art

[0003] Technical development of a semiconductor device including a transistor including an oxide semiconductor in a channel formation region (hereinafter, referred to as an OS transistor) and capable of retaining charges corresponding to data is being actively pursued.

[0004] For example, by providing the semiconductor device with a structure for saving (also referred to as saving, storing, or backing up) or loading (also referred to as returning, restoring, or recovering) a program or data held in a flip-flop, etc., low power consumption can be achieved through power gating, etc. Therefore, it is being applied to a CPU (Central Processing Unit) and the like (for example, refer to Patent Document 1).

[0005] In a CPU or the like, a series of processes (tasks) are executed by sequentially executing processes corresponding to a program or data.

[0006] When executing multiple tasks, each task is divided into smaller processing units and the processing units of each task are executed sequentially, so as to pretend to execute multiple tasks simultaneously. In order to execute such processing, multiple register banks (general register groups) capable of maintaining the state of the CPU, etc. (also called context) when executing each task are prepared, and multiple tasks are executed while switching to the register banks corresponding to each task in sequence.

[0007] Furthermore, when the program is transferred from the main routine to the subroutine, the processing of the subroutine is executed after the register bank is switched, and after the processing of the subroutine is completed, the register bank is switched to the original register bank, and then the processing of the main routine is executed.

[0008] [Prior technical literature]

[0009] [Patent Document]

[0010] [Patent Document 1] Japanese Patent Application Publication No. 2013-9297 Summary of the invention

[0011] Technical problem to be solved by the invention

[0012] In a CPU or the like, when switching tasks, the data of the task being executed is saved in the corresponding register library and the processing is interrupted, and the data of the task to be executed next is loaded from the corresponding register library and the processing is restarted. However, when the register library is insufficient for complex processing, the data of the register corresponding to the task is temporarily written to the external memory, and when the task is re-executed, the data needs to be written back to the register from the external memory. In this case, energy is consumed by writing and writing back the data between the external memory and the register. When a large number of register libraries are prepared, although the energy consumption accompanying the writing and writing back of the data between the external memory and the register can be suppressed, this will lead to an increase in the circuit layout area.

[0013] One of the purposes of one embodiment of the present invention is to provide a novel semiconductor device, etc. Another purpose of one embodiment of the present invention is to provide a semiconductor device, etc. having a novel structure capable of suppressing an increase in circuit layout area. Another purpose of one embodiment of the present invention is to provide a semiconductor device, etc. having a novel structure excellent in low power consumption. Another purpose of one embodiment of the present invention is to provide a semiconductor device, etc. having a novel structure excellent in computing performance.

[0014] In addition, the description of the above-mentioned purpose does not prevent the existence of other purposes. Note that one mode of the present invention does not necessarily achieve all of the above-mentioned purposes. Other purposes other than the above-mentioned can be clearly seen and extracted from the description of this specification, drawings, claims, etc.

[0015] Solutions to technical problems

[0016] One embodiment of the present invention is based on the above-mentioned problem. In a CPU or the like, a plurality of memories (also referred to as OS memories) composed of OS transistors and capacitors are stacked on registers, and a function of writing and writing back data of the registers in a manner corresponding to a plurality of tasks is installed. When switching tasks, for example, data of the register corresponding to the first task is written to the first OS memory, and data of the second OS memory corresponding to the second task of the next task is written back to the register. In the OS memory, an OS transistor is stacked on the capacitor, and a portion of the dielectric layer of the capacitor and a portion of the semiconductor layer including the channel formation region of the OS transistor are arranged in a direction perpendicular to the surface of the substrate on which the register is arranged, thereby increasing the storage capacity per unit area. (1)

[0018] One embodiment of the present invention is a semiconductor device, which includes a trigger circuit and a storage circuit, the storage circuit including a first transistor, a second transistor, a first capacitor, and a second capacitor, one of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor, one terminal of the first capacitor, and one terminal of the second capacitor, the other of the source and the drain of the first transistor is electrically connected to the output terminal of the trigger circuit, and the other of the source and the drain of the second transistor is electrically connected to the input terminal of the trigger circuit, the semiconductor device also includes a substrate, a first insulator, and a second insulator, the first insulator is arranged on the substrate, the second insulator is arranged on the first insulator, the first insulator includes a first opening portion and a second opening portion extending in a direction perpendicular to the surface of the substrate, the second insulator includes a third opening portion and a fourth opening portion extending in a direction perpendicular to the surface of the substrate, the trigger circuit is arranged on the substrate, at least a portion of each of the first capacitor and the second capacitor is arranged in the first opening portion and the second opening portion, and at least a portion of each of the first transistor and the second transistor is arranged in the third opening portion and the fourth opening portion. (2)

[0020] In the above (1), preferably, at least a portion of the dielectric layer of each of the first capacitor and the second capacitor is arranged along the side walls of each of the first opening portion and the second opening portion, and at least a portion of the semiconductor layer including the channel formation region of each of the first transistor and the second transistor is arranged along the side walls of each of the third opening portion and the fourth opening portion. (3)

[0022] In the above (2), the semiconductor layer preferably includes an oxide semiconductor. (4)

[0024] One embodiment of the present invention is a computing device, which includes a semiconductor device described in any one of (1) to (3) above and a control unit, the control unit having a function of generating a signal for controlling the operation of the semiconductor device, and the semiconductor device having a function of controlling the conductive state or non-conductive state of a first transistor to store data held by a trigger circuit in a storage circuit and a function of controlling the conductive state or non-conductive state of a second transistor to load data held by the storage circuit into the trigger circuit. (5)

[0026] In the above (4), preferably, the semiconductor device includes multiple storage circuits, and the control unit has the following function: when switching tasks, the first data held by the trigger circuit is saved in any one of the multiple storage circuits, and the second data held by any one of the multiple storage circuits is loaded into the trigger circuit.

[0027] Effects of the Invention

[0028] One embodiment of the present invention can provide a novel semiconductor device, etc. Another embodiment of the present invention can provide a semiconductor device with a novel structure that can suppress the increase in circuit layout area, etc. Another embodiment of the present invention can provide a semiconductor device with a novel structure that is excellent in low power consumption, etc. Another embodiment of the present invention can provide a semiconductor device with a novel structure that is excellent in computing performance, etc.

[0029] In addition, the description of the above effects does not prevent the existence of other effects. Note that one mode of the present invention does not necessarily have all the above effects. Other effects other than the above can be clearly seen and extracted from the description of this specification, drawings, or claims, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1A is a circuit diagram illustrating a structural example of a semiconductor device. Figure 1B It is a schematic diagram for explaining a structural example of a semiconductor device.

[0031] Figure 2A It is a schematic diagram for explaining an operation example of a semiconductor device. Figure 2B It is a timing chart for explaining an operation example of a semiconductor device.

[0032] FIG. 3A to FIG. 3E It is a schematic diagram for explaining an operation example of a semiconductor device.

[0033] Figure 4 It is a schematic diagram for explaining a configuration example of a computing device.

[0034] Figure 5It is a schematic diagram for explaining an operation example of the computing device.

[0035] Figure 6 A diagram illustrating a structural example of a semiconductor device.

[0036] Figure 7 A diagram illustrating a structural example of a semiconductor device.

[0037] FIG. 8A to FIG. 8C A diagram illustrating a structural example of a semiconductor device.

[0038] Fig. 9A and Fig. 9B A diagram illustrating a structural example of a semiconductor device.

[0039] Fig.10 A diagram illustrating a structural example of a semiconductor device.

[0040] Fig.11A and Fig. 11B A diagram illustrating a structural example of a semiconductor device.

[0041] Fig. 12A and Fig. 12B It is a diagram showing an example of an electronic component.

[0042] Fig.13A and Fig. 13B is a diagram showing an example of an electronic device. FIG. 13C to FIG. 13E This is a diagram showing an example of a large computer.

[0043] Fig.14 is a diagram showing an example of space equipment.

[0044] Fig.15 is a diagram showing an example of a storage system that can be used in a data center. DETAILED DESCRIPTION

[0045] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, for example, a circuit including a semiconductor element (such as a transistor or a diode, etc.) or a device including the circuit, etc. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. For example, as examples of semiconductor devices, there are integrated circuits including semiconductor elements, chips including integrated circuits, electronic components containing chips in packages, or electronic devices equipped with electronic components, etc. In addition, for example, display devices, light-emitting devices, power storage devices, optical devices, camera devices, lighting devices, computing devices, control devices, storage devices, input devices, output devices, input-output devices, signal processing devices, electronic computers or electronic devices, etc., are themselves semiconductor devices, and sometimes include semiconductor devices.

[0046] Hereinafter, the embodiments are described with reference to the accompanying drawings. Note that the embodiments can be implemented in a plurality of different forms. Thus, a person skilled in the art can easily understand that the embodiments and details can be transformed into various forms without departing from the purpose and scope thereof. Therefore, one embodiment of the present invention should not be interpreted as being limited to the contents described in the embodiments.

[0047] In addition, in this specification, the structure shown in each embodiment can be appropriately combined with the structure shown in other embodiments to constitute one mode of the present invention. In addition, when multiple structures are shown in one embodiment, these structures can be appropriately combined and regarded as one mode of the present invention.

[0048] Note that, with respect to the drawings illustrating the embodiments, in the structure of the invention, the same symbols are sometimes used in common in different drawings to represent the same parts or parts with the same function, thereby omitting repeated descriptions. In addition, in the drawings, when representing parts with the same function, for example, the same hatching lines are sometimes used without adding special symbols. For example, in a stereogram or a top view (also called a "plan view"), for the sake of clarity, the illustration of some constituent elements is sometimes omitted. For example, the description of some hidden lines in the drawings is sometimes omitted. In addition, for example, the description of hatching lines in the drawings is sometimes omitted.

[0049] In the drawings, dimensions, layer thicknesses, or regions are sometimes exaggerated for the sake of clarity. Therefore, the drawings are not limited to, for example, the dimensions or aspect ratios in the drawings. In addition, in the drawings, ideal examples are schematically shown, so the present invention is not limited to, for example, the shapes or values ​​shown in the drawings. For example, in actual manufacturing processes, layers or resist masks are sometimes unintentionally thinned due to processes such as etching, but this is sometimes not reflected in the drawings for ease of understanding. In addition, in actual circuit operation, for example, voltage or current may be uneven due to noise or timing deviation, but this is sometimes not reflected in the drawings for ease of understanding.

[0050] In this specification and the drawings, the components are classified according to their functions and are represented as components that are independent of each other. However, it is difficult to classify the components according to their functions, and sometimes one component involves multiple functions or multiple components involve one function. Therefore, the components shown in this specification and the drawings are not limited to the description thereof, and the words and phrases may be appropriately changed according to the circumstances.

[0051] In this specification and the drawings, when the same symbol is used for a plurality of components and it is necessary to distinguish them, an identification symbol such as "A", "b", "_1", "[n]", or "[m, n]" may be added to the symbol. In addition, when the common content between a plurality of components to which identification symbols are added is described or it is not necessary to distinguish them, they may be described without adding identification symbols.

[0052] Note that in this specification, etc., the "conductive state" or "open state" of a transistor refers to, for example, a state in which the source and drain of the transistor are electrically short-circuited or a state in which current can flow between the source and drain. For example, the following states are sometimes referred to as "conductive state" or "open state": in an n-channel transistor, the voltage between the gate and the source is higher than the threshold voltage; or in a p-channel transistor, the voltage between the gate and the source is lower than the threshold voltage. In addition, the "non-conductive state", "disconnected state" or "off state" of a transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically disconnected. For example, the following states are sometimes referred to as "non-conductive state", "disconnected state" or "off state": in an n-channel transistor, the voltage between the gate and the source is lower than the threshold voltage; or in a p-channel transistor, the voltage between the gate and the source is higher than the threshold voltage.

[0053] In addition, in this specification, etc., the voltage between the gate and the source (gate-source) is sometimes referred to as the "gate voltage", the voltage between the drain and the source (drain-source) is referred to as the "drain voltage", and the voltage between the back gate and the source (back gate-source) is referred to as the "back gate voltage". In addition, the current flowing between the drain and the source is sometimes referred to as the "drain current". Note that the records of high gate voltage, high drain voltage and high back gate voltage of n-channel transistors can be appropriately converted to records of low gate voltage, low drain voltage and low back gate voltage of p-channel transistors. In addition, the records of low gate voltage, low drain voltage and low back gate voltage of n-channel transistors can be appropriately converted to records of high gate voltage, high drain voltage and high back gate voltage of p-channel transistors.

[0054] In addition, in this specification, etc., unless otherwise specified, the "off-state current" of a transistor refers to the drain current when the transistor is in the off state. Note that in this specification, etc., the off-state current and the current flowing between the gate and the source and drain (also called gate leakage current) are sometimes referred to as leakage current.

[0055] (Implementation Method 1)

[0056] A semiconductor device according to one embodiment of the present invention is described with reference to the accompanying drawings. In addition, a semiconductor device according to one embodiment of the present invention can also be used as a part of a register included in a computing processing device such as a CPU (Central Processing Unit), an MPU (Micro Processing Unit) or an MCU (Micro Controller Unit).

[0057] <Register Structure Example>

[0058] Figure 1A and Figure 1B FIG. 1 is a schematic diagram for explaining a configuration example of a register according to one embodiment of the present invention.

[0059] Figure 1A and Figure 1B The register 110 shown includes a scan flip-flop 120 (volatile register) and a data holding circuit 130. The scan flip-flop 120 includes a selector 121 and a flip-flop 122. The data holding circuit 130 includes storage circuits 131[1] to 131[k] (k is an integer greater than or equal to 2). The storage circuits 131[1] to 131[k] all include a transistor 132, a transistor 133, a transistor 134, a capacitor 135, and a capacitor 136.

[0060] Note that Figure 1A and Figure 1B In order to facilitate the understanding of the description of the positional relationship of each component constituting the register 110, the X direction, the Y direction, and the Z direction are defined. Figure 1A and Figure 1B In the embodiment, the Z direction is a direction perpendicular to the surface of the substrate on which the register 110 is provided. In this specification, etc., perpendicular refers to a state in which the angle formed by two components of an object is greater than 85 degrees and less than 95 degrees. In this specification, etc., for ease of understanding, the Z direction is sometimes referred to as a vertical direction. In addition, the surface of the substrate on which the register 110 is provided corresponds to a surface formed by the X direction defined as a direction perpendicular to the Z direction and the Y direction defined as a direction perpendicular to both the X direction and the Z direction.

[0061] The scan trigger 120 is provided in the element layer 20. The element layer 20 is provided on a substrate including silicon, for example. Therefore, the scan trigger 120 can be configured using, for example, a Si transistor (a transistor including silicon in a channel formation region).

[0062] The data holding circuit 130 is provided in the element layer 30 stacked on the element layer 20 in the vertical direction (Z direction). The element layer 30 includes an element layer 30a and an element layer 30b stacked on the element layer 30a in the vertical direction (Z direction). The element layer 30a is provided with a capacitor. That is, the capacitor 135 and the capacitor 136 included in the data holding circuit 130 are provided. The element layer 30b is provided with a transistor. That is, the transistor 132, the transistor 133, and the transistor 134 included in the data holding circuit 130 are provided.

[0063] In addition, a portion of the dielectric layer of the capacitor provided in the element layer 30a and a portion of the semiconductor layer including the channel formation region of the transistor provided in the element layer 30b are both extended in a direction (Z direction) perpendicular to the surface of the substrate provided with the element layer 20. Thus, the layout area of ​​the memory circuits 131[1] to 131[k] can be reduced.

[0064] The transistor provided in the element layer 30 b is, for example, an OS transistor (a transistor including an oxide semiconductor in a channel formation region).

[0065] Since the band gap of the oxide semiconductor forming the channel is 2 eV or more, the OS transistor has the characteristic of extremely small off-state current. The off-state current value of the OS transistor with a channel width of 1 μm at room temperature can be 1 aA (1×10 -18 A) or less, 1zA(1×10 -21 A) or less or 1yA(1×10 -24 Note that the off-state current value of a Si transistor with a channel width of 1 μm at room temperature is 1 fA (1×10 -15 A) or more and 1pA (1×10 -12 Therefore, it can be said that the off-state current of the OS transistor is about 10 bits smaller than the off-state current of the Si transistor.

[0066] In addition, even in a high temperature environment, the off-state current of the OS transistor hardly increases. Specifically, even at an ambient temperature above room temperature and below 200°C, its off-state current hardly increases. In addition, even in a high temperature environment, the on-state current of the OS transistor is not easy to drop. On the other hand, in a high temperature environment, the on-state current of the Si transistor drops. That is, in a high temperature environment, the on-state current of the OS transistor is larger than that of the Si transistor. In addition, even at an ambient temperature above 125°C and below 150°C, the ratio of the on-state current to the off-state current of the OS transistor is large, so good switching operation can be performed. Therefore, a semiconductor device including an OS transistor operates stably and has high reliability even in a high temperature environment.

[0067] Note that specific structural examples of the element layer 20 and the element layer 30 will be described later.

[0068] like Figure 1A As shown, various signals (signals BK[ 1 ] to BK[k], signals RE[ 1 ] to RE[k], signal SE, and signal CLK) for controlling the operation of register 110 are supplied to register 110 .

[0069] In this specification, for example, each signal is a high level or a low level potential, and the high level is a potential higher than the low level. For example, the potential difference between the high level and the low level is preferably greater than the threshold voltage of the transistor to which each signal is supplied. Note that being at a high level or at a low level may also vary depending on the signal.

[0070] In this specification, a high level is sometimes expressed as "H" or "High", and a low level is sometimes expressed as "L" or "Low". In addition, a signal is sometimes set to a high level as "set the signal to "H" or "signal = "H", and a signal is sometimes set to a low level as "set the signal to "L" or "signal = "L".

[0071] Each of the signals BK[1] to BK[k] is a signal that controls the saving (also referred to as saving, storing, or backing up) of the data held by the flip-flop 122 in the scan flip-flop 120. By saving the data, the data held by the flip-flop 122 is held after being written to any one of the storage circuits 131[1] to 131[k] in the data holding circuit 130.

[0072] Each of the signals RE[1] to RE[k] is a signal that controls loading (also referred to as returning, restoring, or recovering) of data held by any one of the storage circuits 131[1] to 131[k] in the data holding circuit 130. By loading the data, the data held by any one of the storage circuits 131[1] to 131[k] is held after being written back to the flip-flop 122 in the scan flip-flop 120.

[0073] The signal SE is a switching signal for selecting the output of the selector 121 .

[0074] The signal CLK is a clock signal for operating the flip-flop 122 .

[0075] The register 110 stores and holds the data input from the terminal D or the terminal SD in the flip-flop 122 in the scan flip-flop 120 in synchronization with the signal CLK, and outputs the data from the terminal Q. The data held by the flip-flop 122 is held from the terminal Q in any one of the storage circuits 131[1] to 131[k] in the data holding circuit 130 by the control signals BK[1] to BK[k]. The data held by any one of the storage circuits 131[1] to 131[k] is loaded from the terminal SD into the flip-flop 122 by the control signals RE[1] to RE[k].

[0076] The selector 121 has a function of transmitting a signal of the terminal D or the terminal SD to the flip-flop 122 by the control signal SE. The terminal D is a terminal to which data input from the outside of the register 110 is supplied. The terminal SD is a terminal to which data held by any one of the storage circuits 131[1] to 131[k] in the data holding circuit 130 or data input from the terminal SD_IN is supplied. The terminal SD_IN is a terminal to which scan test data is supplied.

[0077] The flip-flop 122 can use a flip-flop circuit prepared in a standard circuit library. The flip-flop 122 can use, for example, a positive edge-triggered D flip-flop. The flip-flop 122 can hold a data by, for example, including a circuit such as an inverter loop. The flip-flop 122 holds the data of the input terminal Df in synchronization with the signal CLK, and outputs the held data from the output terminal Qf to the terminal Q.

[0078] The data holding circuit 130 can hold the state of the scan flip-flop 120 for each task resulting from switching between a plurality of tasks in a one-to-one correspondence with each of the storage circuits 131[1] to 131[k]. In the data holding circuit 130, when saving data, any one of the storage circuits 131[1] to 131[k] is selected by the control signals BK[1] to BK[k]. In addition, when loading data, any one of the storage circuits 131[1] to 131[k] is selected by the control signals RE[1] to RE[k].

[0079] like Figure 1A As shown, each of the signals BK[1] to BK[k] and each of the signals RE[1] to RE[k] are supplied in a one-to-one correspondence with each of the storage circuits 131[1] to 131[k].

[0080] Note that in this specification, “storage circuit 131” may be used to describe common contents among storage circuits 131[1] to 131[k]. In this case, signals BK[1] to BK[k] may be described as signals BK, and signals RE[1] to RE[k] may be described as signals RE.

[0081] like Figure 1A As shown, the storage circuit 131 is connected to the terminal Q and the terminal SD. In the storage circuit 131, the terminal (wiring) connected to the terminal Q is an input terminal, and the terminal (wiring) connected to the terminal SD is an output terminal. That is, in the register 110, the output terminal Qf of the flip-flop 122 is electrically connected to the input terminal of the storage circuit 131, and the input terminal Df of the flip-flop 122 is electrically connected to the output terminal of the storage circuit 131 through the selector 121.

[0082] In the memory circuit 131, one of the source and the drain of the transistor 133 is electrically connected to one terminal of the capacitor 135. One of the source and the drain of the transistor 134 is electrically connected to one terminal of the capacitor 136. In addition, one terminal of the capacitor 135 and one terminal of the capacitor 136 are electrically connected to each other. The other terminal of the capacitor 135 and the other terminal of the capacitor 136 are electrically connected to the wiring CL.

[0083] The other of the source and the drain of the transistor 133 is electrically connected to the input terminal (ie, terminal Q) of the storage circuit 131. The other of the source and the drain of the transistor 134 is electrically connected to the output terminal (ie, terminal SD) of the storage circuit 131.

[0084] One of the source and the drain of the transistor 132 is electrically connected to the terminal SD. The other of the source and the drain of the transistor 132 is electrically connected to the terminal SD_IN.

[0085] Note that in each of the storage circuits 131[1] to 131[k], a node (wiring) at which one terminal of the capacitor 135 and one terminal of the capacitor 136 are electrically connected to each other may be described as a node SN[1] to a node SN[k]. In addition, when describing the common contents among the storage circuits 131[1] to 131[k], the nodes SN[1] to SN[k] may be described as nodes SN.

[0086] OS transistors are preferably used as the transistor 132, the transistor 133, and the transistor 134. As described above, the off-state current of the OS transistor is extremely small, and the off-state current hardly increases even in a high-temperature environment.

[0087] Therefore, the memory circuit 131 can hold one data in the node SN for a long period of time by turning off the transistor 133 and the transistor 134 (in a non-conductive state).

[0088] That is, the storage circuit 131 can be used as a nonvolatile memory. For example, data can be retained even in a power gating state (a state in which power is not supplied to the scan flip-flop 120).

[0089] As another example of the structure of the register 110, a structure in which the transistor 132 is provided in the element layer 20 and a Si transistor is used as the transistor 132 may be employed. Alternatively, a structure in which one transistor 132 is provided for a plurality of storage circuits 131 may be employed.

[0090] The signal BK is supplied to the gate of the transistor 133 and the gate of the transistor 132. The signal BK is a signal for storing the data held by the flip-flop 122 in the storage circuit 131.

[0091] The transistor 133 and the transistor 132 are in a conducting state or a non-conducting state according to the signal BK. For example, the transistor 133 and the transistor 132 are in a conducting state when the signal BK is set to "H" or in a non-conducting state when the signal BK is set to "L".

[0092] The signal RE is supplied to the gate of the transistor 134. The signal RE is a signal for loading the data held by the storage circuit 131 into the flip-flop 122.

[0093] The transistor 134 is in a conducting state or a non-conducting state according to the signal RE. For example, the transistor 134 is in a conducting state when the signal RE is set to "H" or is in a non-conducting state when the signal RE is set to "L".

[0094] The selector 121 selects and outputs a signal of the terminal SD or the terminal D according to the signal SE. For example, the selector 121 selects and outputs a signal of the terminal SD when the signal SE is set to "H" or selects and outputs a signal of the terminal D when the signal SE is set to "L".

[0095] For example, when the signal BK is set to "H" and the signal RE is set to "L", the storage circuit 131 can write the data held by the flip-flop 122 to the node SN. In addition, when the signal BK is set to "L", the signal RE is set to "H", and the signal SE is set to "H", the storage circuit 131 can write the data held by the node SN back to the flip-flop 122.

[0096] When any one of the signals BK[1] to BK[k] is "H" and the signals RE[1] to RE[k] are all "L", the data holding circuit 130 can store the data held by the flip-flop 122 in any one of the storage circuits 131[1] to 131[k]. For example, by setting the signal BK[1] = "H" when the signals RE[1] to RE[k] are all "L", the data held by the flip-flop 122 can be written to the node SN[1] of the storage circuit 131[1]. Similarly, by setting the signal BK[k] = "H", the data held by the flip-flop 122 can be written to the node SN[k] of the storage circuit 131[k].

[0097] When the signals BK[1] to BK[k] are all "L" and any one of the signals RE[1] to RE[k] is "H", the data holding circuit 130 can load the data held in any one of the storage circuits 131[1] to 131[k] into the flip-flop 122. For example, by setting the signal RE[1] = "H" and the signal SE = "H" in a state where the signals BK[1] to BK[k] are all "L", the data held in the node SN[1] of the storage circuit 131[1] can be written back to the flip-flop 122. Similarly, by setting the signal RE[k] = "H" and the signal SE = "H", the data held in the node SN[k] of the storage circuit 131[k] can be written back to the flip-flop 122.

[0098] One embodiment of the present invention has a structure in which a data holding circuit 130 including a plurality of storage circuits 131 is stacked on a scan flip-flop 120 in a register 110 .

[0099] Therefore, the distance of the wiring electrically connecting the scan flip-flop 120 and the data holding circuit 130 can be shortened. Thus, the time and power required for charging and discharging the wiring can be reduced. In other words, the energy (access energy) required for data storage and loading can be reduced.

[0100] In addition, the data holding circuit 130 can be provided in the register 110 without changing the circuit structure and layout of the scan flip-flop 120. That is, the versatility of the data holding circuit 130 is very high.

[0101] Furthermore, by providing the data holding circuit 130, parasitic capacitance generated by, for example, wiring and the transistor 133 is added to the terminal Q, but this parasitic capacitance is smaller than parasitic capacitance generated by other circuits connected to the terminal Q, and therefore does not affect the operation of the scan flip-flop 120. In other words, by providing the data holding circuit 130, the performance of the register 110 is not substantially degraded.

[0102] In addition, in the register 110, the layout area of ​​the data holding circuit 130 is preferably smaller than the layout area of ​​the scan flip-flop 120. Thus, the area overhead caused by providing the data holding circuit 130 can be reduced, preferably reduced to zero.

[0103] One embodiment of the present invention has the following structure: in the storage circuit 131 stacked on the scan trigger 120, a transistor is stacked on the capacitor. In addition, a part of the dielectric layer of the capacitor and a part of the semiconductor layer including the channel formation region of the transistor are arranged in a direction perpendicular to the surface of the substrate on which the scan trigger 120 is arranged. Therefore, the layout area of ​​the storage circuit 131 can be reduced. As a result, in the register 110, the number of storage circuits 131 (the number k) that can be configured in the data holding circuit 130 can be increased without increasing the area cost. In other words, the storage capacity per unit area of ​​the data holding circuit 130 can be increased while suppressing the increase in process cost.

[0104] Furthermore, in order to further increase the number of storage circuits 131 that can be arranged in the register 110 without increasing the area cost, a plurality of element layers 30 may be stacked and the data holding circuit 130 may be provided in each element layer 30 .

[0105] <Register working example>

[0106] Next, the operation of the register 110 will be described.

[0107] exist Figure 2A 2 , as an example for explaining the operation of the register 110 , a configuration is shown in which the number of storage circuits 131 included in the data holding circuit 130 is 4 (k=4). Figure 2A Nodes SN[1] to SN[4] for holding data in the storage circuits 131[1] to 131[4] included in the data holding circuit 130 are shown. Signals BK[1] to BK[4] and signals RE[1] to RE[4] for controlling the storage circuits 131[1] to 131[4] are shown.

[0108] Figure 2B Yes Description Figure 2A A timing diagram of an example of the operation of register 110 is shown.

[0109] Figure 2BThe state (high level (High) or low level (Low)) of each signal CLK, signal BK[1], signal BK[2], signal RE[1], signal RE[2], and signal SE during the period from time T1 to time T8 is shown (the signal BK[3], signal BK[4], signal RE[3], and signal RE[4] are omitted). In addition, the state of data (any of data D1 to data D8) supplied to terminal D, terminal Q, terminal SD, node SN[1], and node SN[2] is shown (the node SN[3] and node SN[4] are omitted).

[0110] During the period from time T1 to time T8 , the flip-flop 122 stores the data of the input terminal Df in synchronization with the timing (positive edge) when the signal CLK switches from “L” to “H” and outputs the data from the output terminal Qf.

[0111] FIG. 3A to FIG. 3E Yes Description Figure 2B A schematic diagram of the state of register 110 in the timing diagram shown.

[0112] Figure 3A The scan flip-flop 120 and the storage circuit 131 [ 1 ] to the storage circuit 131 [ 4 ] included in the data holding circuit 130 are shown. Figure 3B , Figure 3C , Figure 3D and Figure 3E Shown respectively in Figure 2B The timing diagram shown in FIG. 1 shows the input and output of data by the storage circuits 131 [ 1 ] to 131 [ 4 ] included in the scan flip-flop 120 and the data holding circuit 130 at times T3 , T4 , T6 , and T7 .

[0113] At time T1, signals BK[1] to BK[4], signals RE[1] to RE[4], and signal SE are all "L". In addition, the states of the data supplied to nodes SN[1] and SN[2] are uncertain (data D1 to D8 are not shown). In addition, the potential supplied to wiring CL is a constant potential (for example, ground potential). Note that in the following description, when each signal is not referred to, the previous state is maintained.

[0114] At time T2 , data D1 supplied to the terminal D is stored in the scan flip-flop 120 and output to the terminal Q in synchronization with the positive edge of the signal CLK.

[0115] At time T3, data D2 supplied to terminal D is stored in scan flip-flop 120 in synchronization with the positive edge of signal CLK and output to terminal Q. Here, by setting signal BK[1] = "H", data D2 output to terminal Q is stored in node SN[1] of storage circuit 131[1] (refer to Figure 3B ).

[0116] Then, by setting the signal BK[1] to "L", the data D2 stored in the node SN[1] is retained.

[0117] At time T4, data D3 supplied to terminal D is stored in scan flip-flop 120 in synchronization with the positive edge of signal CLK and output to terminal Q. Here, by setting signal BK[2] = "H", data D3 output to terminal Q is stored in node SN[2] of storage circuit 131[2] (refer to Figure 3C ).

[0118] Then, by setting the signal BK[2] to "L", the data D3 stored in the node SN[2] is maintained.

[0119] At time T5 , data D4 supplied to the terminal D is stored in the scan flip-flop 120 and output to the terminal Q in synchronization with the positive edge of the signal CLK.

[0120] Then, by setting the signal RE[1] = "H", the data D2 stored in the node SN[1] of the storage circuit 131[1] is supplied to the terminal SD. Note that although the data D5 is supplied to the terminal D, the terminal SD is selected by setting the signal SE = "H".

[0121] At time T6, data D2 supplied to the terminal SD is stored in the scan flip-flop 120 in synchronization with the positive edge of the signal CLK and output to the terminal Q (see Figure 3D ).

[0122] Then, by setting the signal RE[1] = "L" and the signal RE[2] = "H", the data D3 stored in the node SN[2] of the storage circuit 131[2] is supplied to the terminal SD. Note that although the data D6 is supplied to the terminal D, the terminal SD is selected by setting the signal SE = "H".

[0123] At time T7, data D3 supplied to the terminal SD is stored in the scan flip-flop 120 in synchronization with the positive edge of the signal CLK and output to the terminal Q (see Figure 3E ).

[0124] Then, the signal RE[2] is set to "L" and the signal SE is set to "L".

[0125] At time T8 , data D7 supplied to the terminal D is stored in the scan flip-flop 120 and output to the terminal Q in synchronization with the positive edge of the signal CLK.

[0126] As described above, register 110 may be referenced Figure 2B and FIG. 3B to FIG. 3E Description of the work.

[0127] One embodiment of the present invention can save the data of the interrupted task and load the data of the restarted task in a CPU or the like using the register 110. That is, in the register 110, when switching between multiple tasks, the data of the scan trigger 120 can be written, retained, and written back to any of the multiple storage circuits 131.

[0128] <Configuration Example of Computing Device>

[0129] Figure 4 1 is a block diagram for explaining a configuration example of a computing device including the register 110. The computing device according to one embodiment of the present invention can be used as a part of a CPU or the like, for example.

[0130] Figure 4 The computing device 100 shown includes a control unit 101 and a CPU core 102. The CPU core 102 includes a register unit 103 and a computing unit 104. The register unit 103 includes a plurality of register banks 105. The register banks 105 include a plurality of general registers 106. The general registers 106 include a plurality of registers 110.

[0131] The computing device 100 can execute a series of processes (tasks) by sequentially executing processes corresponding to a program or data. The computing device 100 can execute a plurality of tasks.

[0132] The control unit 101 has a function of outputting a control signal for switching between multiple tasks based on, for example, an interrupt signal (Interrupts) input from outside the computing device 100 or a sleep signal generated by the CPU core 102. For example, the control unit 101 has a function of generating various signals (signals BK[1] to BK[k], signals RE[1] to RE[k], signal SE, and signal CLK) for controlling the operation of the register 110 in the CPU core 102 when switching between multiple tasks and supplying the signals to the register 110.

[0133] The control unit 101 may have a function of outputting a signal for controlling power gating of the CPU core 102 , for example.

[0134] The CPU core 102 has a function of performing arithmetic processing in the arithmetic unit 104 according to the program data held in the register unit 103. The CPU core 102 is sometimes referred to as a processor core. The arithmetic device 100 may have one (single-core) CPU core 102, or may have two or more (e.g., dual-core or multi-core) CPU cores 102.

[0135] The register unit 103 includes, for example, a register bank 105 provided with pipeline registers and a register file, etc. The register unit 103 has a function of temporarily holding program data for operation processing by the operation unit 104, data used for operation processing, and data obtained by operation processing.

[0136] The operation unit 104 has a function of performing various operations such as arithmetic operations and logic operations based on the program data stored in the register unit 103. The operation unit 104 is sometimes referred to as an ALU (Arithmetic logic unit). The CPU core 102 may include, for example, a program counter or a control circuit in addition to the register unit 103 and the operation unit 104.

[0137] The register bank 105 is provided for each of the plurality of tasks executed by processing corresponding to the program data. Each of the plurality of general registers 106 in the register bank 105 has the function of holding program data used for calculation processing when executing each task, data used for calculation processing, or data obtained by calculation processing.

[0138] In the computing device 100, the register banks 105 provided for each task respectively hold the state (also referred to as context) of the computing device 100 when executing each task. When switching between multiple tasks, the control unit 101 controls the operation so as to switch to the register banks 105 corresponding to each task.

[0139] In other words, the computing device 100 is controlled by the control unit 101 as follows: when switching tasks, the context of the task being executed is saved (also called saved, stored or backed up) in the corresponding register library 105 to interrupt the processing, and the context of the next task to be executed is loaded (also called returned, restored or recovered) from the corresponding register library 105, and then the processing is restarted. In this way, by executing multiple tasks while switching the register library 105, it is not necessary to exchange data used to execute each task between the external memory (for example, cache memory (for example, SRAM (Static Random Access Memory)) or main memory (for example, DRAM (Dynamic Random Access Memory)) provided in the computing device 100. Therefore, the operating speed of the computing device 100 can be improved. In other words, the computing performance of the computing device 100 can be improved.

[0140] <Operation Example of Computing Device>

[0141] Next, an example of the operation of the register 110 during task switching of the computing device 100 will be described.

[0142] Figure 5 is a schematic diagram illustrating an example of the following operation: Figure 4 The computing device 100 shown in FIG. Figure 2A The register 110 shown and referenced Figure 2B Instructions for working with multiple tasks.

[0143] Figure 5 The diagram shows how the three tasks, Task 1, Task 2, and Task 3, are sequentially switched and executed at each of time Ta, time Tb, and time Tc. In addition, arrows are used to indicate how the data for executing each of Tasks 1 to 3 is stored in each of the storage circuits 131[1] to 131[3] from the scan flip-flop 120 when the tasks are switched, and how the data is loaded from each of the storage circuits 131[1] to 131[3] to the scan flip-flop 120. Note that it is assumed that Task 1 is executed before time Ta.

[0144] At time Ta, task 1 is interrupted and task 2 is started. That is, the data in the scan flip-flop 120 is stored in the storage circuit 131[1] while task 1 is being executed. Then, by loading the data of the storage circuit 131[2] into the scan flip-flop 120, the state can be switched to one in which task 2 can be executed.

[0145] At time Tb, task 2 is interrupted and task 3 is started. That is, the data in the scan flip-flop 120 is stored in the storage circuit 131[2] while task 2 is being executed. Then, by loading the data of the storage circuit 131[3] into the scan flip-flop 120, the state can be switched to one in which task 3 can be executed.

[0146] At time Tc, task 3 is interrupted and task 1 is restarted. That is, the data in the scan flip-flop 120 is stored in the storage circuit 131[3] in the state of executing task 3. Then, by loading the data of the storage circuit 131[1] into the scan flip-flop 120, it is possible to switch to a state in which task 3 can be executed. Therefore, task 1 interrupted at time Ta is restarted.

[0147] As described above, the computing device 100 can resume the task interrupted by switching tasks by performing the above operations.

[0148] In one embodiment of the present invention, for example, a large number of registers can be provided in the CPU or the like using the computing device 100 while reducing power consumption. Also, when switching tasks, processing can be restarted from the continuous processing when the task was last executed, so computing performance can be improved.

[0149] For example, even if an interruption of another task occurs during the execution of a task and there are other tasks such as interruption, the data of the task that is interrupted due to the interruption is also maintained, so the processing can be restarted from the original task interruption. At this time, the data of the task that is interrupted due to the interruption is maintained in the register included in the computing device. Therefore, when saving and loading the data of the task, it is not necessary to access the stack area of ​​the external memory (for example, SRAM or DRAM, etc.). Therefore, even if the task is switched due to the interruption, there is no time lag when accessing the external memory, so the interrupt processing can be performed efficiently.

[0150] <Structural Example of Element Layer>

[0151] Next, a configuration example of the element layer 20 and the element layer 30 (element layer 30 a and element layer 30 b ) provided with the register 110 described above will be described.

[0152] Figure 6 It is a part of the cross-sectional structure of a semiconductor device which can be used for the register 110 . Figure 6 The semiconductor device shown includes transistor 550 , transistor 37 , capacitor 38 , via 35 , and via 36 . Figure 7 is a cross-sectional view of the transistor 550 in the channel width direction. Figure 6 1 shows a cross-sectional view of the channel length direction of the transistor 550. In addition, Fig. 8A is a top view of transistor 37 and capacitor 38, Figure 8B and Figure 8C It is a cross-sectional view of the transistor 37 and the capacitor 38.

[0153] exist Figure 6 In the embodiment, transistor 550 corresponds to a Si transistor included in element layer 20 (e.g., a transistor constituting scan trigger 120 in FIG. 1 ). Transistor 37 corresponds to an OS transistor included in element layer 30b (e.g., transistor 133 and transistor 134 in FIG. 1 ). Capacitor 38 corresponds to a capacitor included in element layer 30a (e.g., capacitor 135 and capacitor 136 in FIG. 1 ).

[0154] In addition, Figure 6 1 , symbols such as the terminal Q, the terminal SD, the node SN, and the wiring CL respectively correspond to the terminal Q, the terminal SD, the node SN, and the wiring CL of the register 110 shown in FIG. 1 .

[0155] like Figure 6 As shown, transistor 37, capacitor 38, via 35, and via 36 are disposed above transistor 550. Transistor 37 is disposed above capacitor 38 or above via 35. Via 36 is disposed above via 35.

[0156] The through hole 35 is provided in the element layer 30a and is formed by a conductor used as a plug or wiring. The through hole 36 is provided in the element layer 30b and is formed by a conductor used as a plug or wiring. The transistor 37 can be electrically connected to the transistor 550 provided in the element layer 20 through the through hole 35 or through the through hole 36 and the through hole 35.

[0157] Note that in this specification, the capacitor 38 and the transistor 37 disposed above the capacitor 38 are sometimes collectively referred to as the memory cell 32. Also, the through hole 35 and the transistor 37 disposed above the through hole 35 are sometimes collectively referred to as the functional element 33. Figure 6 The semiconductor device shown includes two memory cells 32 and one functional element 33 .

[0158] exist Figure 6 In the embodiment, the transistor 37 and the capacitor 38 included in the storage unit 32 connected to the terminal Q correspond to the transistor 133 and the capacitor 135 shown in FIG. 1 , respectively. In addition, the transistor 37 and the capacitor 38 included in the storage unit 32 connected to the terminal SD correspond to the transistor 134 and the capacitor 136 shown in FIG. 1 , respectively. Figure 6 In the embodiment, the transistor 37 included in the functional element 33 is equivalent to the transistor 132 shown in FIG. 1 .

[0159] In the memory cell 32, one of the source and the drain of the transistor 37 is electrically connected to one terminal of the capacitor 38. The memory cell 32 can hold the charge stored in the capacitor 38 by making the transistor 37 non-conductive. Therefore, the memory cell 32 can store binary data by making the high and low potentials corresponding to the amount of charge held in the capacitor 38 correspond to "1" or "0", for example.

[0160] like Figure 6 As shown, in the two storage cells 32, one terminal (equivalent to the node SN) of each capacitor 38 is electrically connected to each other and the other terminal (equivalent to the wiring CL) is also electrically connected to each other. Therefore, the electrostatic capacitance of the capacitor added to the node SN that holds the charge can be increased, and the data retention characteristics can be improved. In addition, the miniaturization or high integration of the storage circuit (equivalent to the storage circuit 131 shown in FIG. 1) including the two storage cells 32 can be promoted.

[0161] 〔Transistor 550〕

[0162] The transistor 550 is provided on the substrate 311 and includes: a conductor 316, an insulator 315, a semiconductor region 313 consisting of a portion of the substrate 311; a low resistance region 314a serving as one of the source region and the drain region; and a low resistance region 314b serving as the other of the source region and the drain region.

[0163] like Figure 7 As shown, in the transistor 550, the conductor 316 covers the top surface and the side surface in the channel width direction of the semiconductor region 313 via the insulator 315. In this way, by making the transistor 550 have a Fin-type structure, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 550. In addition, since the effect of the electric field of the gate electrode can be enhanced, the off-state characteristics of the transistor 550 can be improved.

[0164] In addition, the transistor 550 may be either a p-channel transistor or an n-channel transistor. For example, by electrically connecting the gate of the n-channel transistor 550 to the gate of the p-channel transistor 550, a CMOS circuit (e.g., a circuit that operates complementary, a CMOS logic gate, or a CMOS logic circuit) may be formed.

[0165] For example, in the transistor 550, the channel forming region of the semiconductor region 313, the region near the channel, the low resistance region 314a used as one of the source region and the drain region, and the low resistance region 314b used as the other of the source region and the drain region preferably include semiconductors such as silicon-based semiconductors, and more preferably include single crystal silicon. Alternatively, the transistor 550 may be formed using materials including Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), or GaAlAs (gallium aluminum arsenic). Alternatively, the transistor 550 may also use silicon that applies stress to the lattice, changes the interplanar spacing, and controls the effective mass. Alternatively, the transistor 550 may be a HEMT (High Electron Mobility Transistor) using GaAs and GaAlAs, for example.

[0166] The low resistance regions 314 a and 314 b contain, in addition to the semiconductor material used for the semiconductor region 313 , an element imparting n-type conductivity such as arsenic or phosphorus or an element imparting p-type conductivity such as boron.

[0167] As the conductor 316 used as the gate electrode, for example, a semiconductor material such as silicon containing an element imparting n-type conductivity such as arsenic or phosphorus or an element imparting p-type conductivity such as boron can be used. Alternatively, for example, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

[0168] In addition, since the material of the conductor determines the work function, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, as the conductor, materials such as titanium nitride or tantalum nitride are preferably used. In order to have both conductivity and embedding properties, as the conductor, a stack of metal materials such as tungsten or aluminum is preferably used, and tungsten is particularly preferred in terms of heat resistance.

[0169] The transistor 550 can also be formed using, for example, a SOI (Silicon on Insulator) substrate or the like.

[0170] In addition, as an SOI substrate, the following substrate can also be used: a SIMOX (Separation by Implanted Oxygen) substrate formed by forming an oxide layer in a region at a certain depth from the surface and eliminating defects generated in the surface layer by injecting oxygen ions into a mirror-polished wafer and then heating it at a high temperature. Alternatively, for example, the following substrate can be used: an SOI substrate formed by the smart peeling method or the ELTRAN method (registered trademark: Epitaxial Layer Transfer) in which a semiconductor substrate is split by growing tiny gaps formed by injecting hydrogen ions through heat treatment. A transistor formed using a single crystal substrate contains a single crystal semiconductor in the channel formation region.

[0171] An insulator 320 , an insulator 322 , an insulator 324 , and an insulator 326 are stacked in this order so as to cover the transistor 550 .

[0172] As the insulator 320 , the insulator 322 , the insulator 324 , and the insulator 326 , for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, or aluminum nitride can be used.

[0173] Note that in this specification, etc., silicon oxynitride refers to a material containing more oxygen than nitrogen in its composition, and silicon nitride oxide refers to a material containing more nitrogen than oxygen in its composition. Note that in this specification, etc., aluminum oxynitride refers to a material containing more oxygen than nitrogen in its composition, and aluminum nitride oxide refers to a material containing more nitrogen than oxygen.

[0174] The insulator 322 may also be used as a planarization film for planarizing a step caused by the transistor 550 disposed thereunder, etc. For example, in order to improve the planarity of the top surface of the insulator 322, the top surface may be planarized by a planarization process such as chemical mechanical polishing (CMP).

[0175] As the insulator 324 , for example, a film having a barrier property that can prevent hydrogen, impurities, and the like from diffusing from the substrate 311 , the transistor 550 , and the like into a region where the transistor 37 is provided is preferably used.

[0176] As a film having a barrier property against hydrogen, for example, silicon nitride formed by a CVD method can be used. For example, hydrogen sometimes diffuses into a semiconductor element including an oxide semiconductor such as transistor 37, resulting in a decrease in the characteristics of the semiconductor element. Therefore, it is preferred to provide a film that inhibits hydrogen diffusion between transistor 37 and transistor 550. Specifically, the film that inhibits hydrogen diffusion refers to a film with a small amount of hydrogen released.

[0177] The amount of hydrogen released can be analyzed by, for example, thermal desorption spectroscopy (TDS). For example, when the amount of hydrogen released is converted to the amount per unit area of ​​the insulator 324 when the film surface temperature in the TDS analysis is in the range of 50°C to 500°C, the amount of hydrogen released from the insulator 324 is 1×10 16 atoms / cm 2 Below, preferably 5×10 15 atoms / cm 2 The following is enough.

[0178] Note that the dielectric constant of the insulator 326 is preferably lower than that of the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably lower than 4, more preferably lower than 3. For example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0179] In addition, in insulators 320, 322, 324, and 326, for example, a conductor (e.g., conductor 328 and conductor 330) having a function of electrically connecting transistor 550 to transistor 37 is embedded. In addition, conductor 328 and conductor 330 have a function of a plug or a wiring. Note that the same symbol is sometimes used to represent a plurality of conductors having a function of a plug or a wiring. In addition, in this specification, etc., a wiring and a plug electrically connected to the wiring may also be one component. That is, a part of a conductor is sometimes used as a wiring, and another part of the conductor is sometimes used as a plug.

[0180] As the material of each plug or wiring (for example, conductor 328 or conductor 330, etc.), for example, a single layer or a laminate of a conductive material such as a metal material, an alloy material, a metal nitride material or a metal oxide material can be used. As the material of the plug or wiring, for example, a high melting point material such as tungsten or molybdenum having both heat resistance and conductivity is preferably used. Alternatively, the material of the plug or wiring is preferably formed using a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material for the plug or wiring, the wiring resistance can be reduced.

[0181] Alternatively, a wiring layer may be provided on the insulator 326 and the conductor 330. Figure 6 In the embodiment, an insulator 350, an insulator 352, and an insulator 354 are stacked in this order. In addition, a conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 has, for example, a function of a plug or wiring that electrically connects the transistor 550 and the transistor 37. In addition, the conductor 356 can be formed using, for example, the same material as the conductor 328 or the conductor 330.

[0182] In addition, similar to the insulator 324, the insulator 350 preferably uses an insulator having a barrier property to hydrogen, for example. In addition, the conductor 356 preferably includes a conductor having a barrier property to hydrogen. In particular, the conductor having a barrier property to hydrogen is formed in the opening portion included in the insulator 350 having a barrier property to hydrogen. By adopting this structure, the transistor 550 can be separated from the transistor 37 using a barrier layer. Therefore, the diffusion of hydrogen from the transistor 550 to the transistor 37 can be suppressed.

[0183] Note that as a conductor having a barrier property to hydrogen, for example, tantalum nitride or the like is preferably used. In addition, it is preferable to stack tantalum nitride and tungsten having high conductivity. By using a stack of tantalum nitride and tungsten as the conductor 356, the conductor 356 can not only maintain the conductivity as a wiring but also suppress the diffusion of hydrogen from the transistor 550. At this time, the tantalum nitride layer of the conductor 356 having a barrier property to hydrogen is preferably in contact with the insulator 350 having a barrier property to hydrogen.

[0184] Although the wiring layer including the conductor 356 is described above, the semiconductor device according to one embodiment of the present invention is not limited thereto. The wiring layer similar to the wiring layer including the conductor 356 may have a single layer structure or a stacked structure of two or more layers.

[0185] [Transistor 37 and capacitor 38]

[0186] FIG. 8A to FIG. 8C 1 and 2 are a plan view and a cross-sectional view of a transistor 37 and a capacitor 38 included in a memory cell 32 of each structure that can be used in the device layer 30 . Fig. 8A is a plan view of the storage unit 32. In addition, Figure 8B and Figure 8C is a cross-sectional view of the storage unit 32. Here, Figure 8B It is along Fig. 8A A cross-sectional view of the portion along the dot-dash line A1-A2 in FIG. Figure 8C It is along Fig. 8A The cross-sectional view of the portion along the dashed line A3-A4 in FIG. Fig. 8A In the plan view, some components are omitted for clarity.

[0187] FIG. 8A to FIG. 8C Insulator 440, conductor 410 on insulator 440, memory cell 32 on conductor 410, insulator 480 on conductor 410, insulator 280 on insulator 480, and insulator 283 on memory cell 32 are shown. Insulator 440, insulator 480, insulator 280, and insulator 283 are used as interlayer films. Conductor 410 is used as wiring.

[0188] The memory cell 32 includes a capacitor 38 on a conductor 410 and a transistor 37 on the capacitor 38 .

[0189] like FIG. 8A to FIG. 8C As shown, the transistor 37 is provided in a manner overlapping with the capacitor 38. In addition, the opening 290 in which a part of the structure of the transistor 37 is provided has a region overlapping with the opening 490 in which a part of the constituent element of the capacitor 38 is provided. In particular, the conductor 420 is used as one of the source electrode and the drain electrode of the transistor 37 and is used as one of a pair of electrodes of the capacitor 38, so the transistor 37 and the capacitor 38 share a part of the constituent element. By adopting such a structure, the transistor 37 and the capacitor 38 can be provided in a manner that does not increase the occupied area when viewed from a plane. As a result, the occupied area of ​​the memory cell 32 can be reduced, so the memory cell 32 can be arranged at a high density to increase the storage capacity.

[0190] {Capacitor 38}

[0191] Capacitor 38 includes conductor 415 on conductor 410, insulator 430 on conductor 415, and conductor 420 on insulator 430. Conductor 420 is used as one of a pair of electrodes (sometimes referred to as an upper electrode), conductor 415 is used as the other of the pair of electrodes (sometimes referred to as a lower electrode), and insulator 430 is used as a dielectric layer. That is, capacitor 38 constitutes a MIM (Metal-Insulator-Metal) capacitor.

[0192] like Figure 8B and Figure 8C As shown, the insulator 480 is provided with an opening 490 that reaches the conductor 410. At least a portion of the conductor 415 is disposed in the opening 490. The conductor 415 has a region in contact with the top surface of the conductor 410 in the opening 490, a region in contact with the side surface of the insulator 480 in the opening 490, and a region in contact with at least a portion of the top surface of the insulator 480. The insulator 430 is disposed in such a manner that at least a portion thereof is located in the opening 490. The conductor 420 is disposed in such a manner that at least a portion thereof is located in the opening 490. In addition, as shown in FIG. Figure 8B and Figure 8C As shown, the conductor 420 is preferably provided in a manner embedded in the opening 490 .

[0193] The capacitor 38 has a structure in which the upper electrode and the lower electrode are opposed to each other through a dielectric layer not only on the bottom surface (sometimes referred to as the bottom) but also on the side surface (sometimes referred to as the side wall) in the opening 490, so that the electrostatic capacitance per unit area can be increased. Therefore, the deeper the depth of the opening 490, the larger the electrostatic capacitance of the capacitor 38 can be. In this way, by increasing the electrostatic capacitance per unit area of ​​the capacitor 38, the read operation in the memory cell array can be stabilized. In addition, the miniaturization or high integration of the memory cell can be promoted.

[0194] The side wall of the opening 490 (sometimes referred to as the side wall in the opening 490 of the insulator 480) is preferably perpendicular to the top surface of the conductor 410. In other words, the insulator 480 can also be said to include the opening 490 extending in a direction perpendicular to the top surface of the conductor 410. In this case, the opening 490 has a cylindrical shape. By adopting this structure, the miniaturization or high integration of the memory cell can be achieved.

[0195] In addition, in the present embodiment, an example is shown in which the opening 490 is circular when viewed from a plane, but one embodiment of the present invention is not limited to this. For example, when viewed from a plane, the opening 490 may also be in a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are curved. In this case, the maximum width of the opening 490 is preferably calculated appropriately based on the shape of the uppermost portion of the opening 490. For example, when the opening is a quadrangle when viewed from a plane, the maximum width of the opening 490 is preferably the length of the diagonal line of the uppermost portion of the opening 490.

[0196] The portions of the conductor 415, the insulator 430, and the conductor 420 disposed in the opening 490 reflect the shape of the opening 490. Therefore, the conductor 415 is provided so as to cover the bottom and side walls of the opening 490, the insulator 430 is provided so as to cover the conductor 415, and the conductor 420 is provided so as to fit into the recess of the insulator 430 reflecting the shape of the opening 490.

[0197] That is, a portion of the dielectric layer (equivalent to the insulator 430) of the capacitor 38 is provided along the side wall of the opening 490. In other words, it is provided in a direction perpendicular to the top surface of the conductor 410. In other words, it can be said that the surface where the upper electrode of the capacitor 38 contacts the dielectric layer and the surface where the lower electrode contacts the dielectric layer both have a component in a direction perpendicular to the top surface of the conductor 410.

[0198] Note that Figure 8B and Figure 8C In the embodiment, the opening 490 is provided so that the side wall of the opening 490 is perpendicular to the top surface of the conductor 410, but one embodiment of the present invention is not limited thereto. For example, the side wall of the opening 490 may also be tapered.

[0199] Conductor 415 and insulator 430 are stacked along the sidewalls of opening 490 and the top surface of conductor 410. Conductor 420 is provided on insulator 430 so as to be embedded in opening 490. In this specification, capacitor 38 having such a structure is sometimes referred to as a trench capacitor, a trench capacitor, a deep hole stacked capacitor, or the like.

[0200] The insulator 280 is disposed on the capacitor 38. That is, the insulator 280 is disposed on the conductor 415, the insulator 430, and the conductor 420. In other words, the conductor 420 is disposed under the insulator 280.

[0201] The conductor 410 is used, for example, as Figure 6 The conductor 420 is used as, for example, Figure 6 The node SN is shown.

[0202] The conductor 410 is provided below the conductor 415 . The conductor 415 has a region in contact with the conductor 410 .

[0203] The conductor 410 is provided on the insulator 440. The conductor 410 can be provided in a planar shape, for example. As the conductor 410, a single layer or a stack of conductors can be used. As the conductor 410, for example, a conductive material with high conductivity such as tungsten can be used. By using such a conductive material with high conductivity, the conductivity of the conductor 410 can be improved.

[0204] As the conductor 415, it is preferred to use a single layer or a stack of a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion. For example, titanium nitride or indium tin oxide with silicon added may be used. Alternatively, for example, a structure may be provided in which tantalum nitride is stacked on tungsten. Alternatively, for example, a structure may be provided in which a first titanium nitride, tungsten, and a second titanium nitride are stacked in sequence. By adopting such a structure, when an oxide insulator is used as the insulator 430, oxidation of the conductor 415 due to the insulator 430 can be suppressed. In addition, when an oxide insulator is used as the insulator 480, oxidation of the conductor 415 due to the insulator 480 can be suppressed.

[0205] The insulator 430 is provided on the conductor 415. The insulator 430 is provided in contact with the top surface and the side surface of the conductor 415. In other words, the insulator 430 preferably covers the side end of the conductor 415. Thus, the conductor 415 and the conductor 420 can be prevented from being short-circuited.

[0206] In addition, if Figure 8B and Figure 8C As shown, the insulator 430 may also be extended to contact the top surface of the insulator 480 .

[0207] Alternatively, a structure may be adopted in which the side ends of the insulator 430 are aligned with the side ends of the conductor 415. With such a structure, the insulator 430 and the conductor 415 can be formed using the same mask, thereby simplifying the manufacturing process of the element layer 30.

[0208] A material having a high relative dielectric constant, so-called high-k material, is preferably used as insulator 430. By using a high-k material as insulator 430, insulator 430 can be formed thick enough to suppress gate leakage current, and the electrostatic capacitance of capacitor 38 can be sufficiently ensured.

[0209] In addition, the insulator 430 preferably uses a stack of insulating layers composed of high-k materials, and preferably uses a stacked structure of a high-k material and a material having a dielectric strength greater than that of the high-k material. As the insulator 430, for example, an insulating film in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in sequence can be used. In addition, for example, an insulating film in which zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide are stacked in sequence can be used. In addition, for example, an insulating film in which hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide are stacked in sequence can be used. By stacking an insulator with a relatively large dielectric strength such as aluminum oxide, the dielectric strength can be increased to suppress the electrostatic destruction of the capacitor 38.

[0210] In addition, a material having ferroelectricity may be used for the insulator 430. Examples of the material having ferroelectricity include hafnium oxide, zirconium oxide, HfZrO X (X is a real number greater than 0) and other metal oxides. In addition, as a material that can have ferroelectricity, a material in which an element J1 (herein, the element J1 is one or more selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to hafnium oxide can be cited. In addition, the ratio of the number of atoms of hafnium atoms to the number of atoms of element J1 can be appropriately set. For example, the ratio of the number of atoms of hafnium atoms to the number of atoms of element J1 can be 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, a material in which an element J2 (herein, the element J2 is one or more selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, strontium, etc.) is added to zirconium oxide can be cited. In addition, the ratio of the number of atoms of zirconium atoms to the number of atoms of element J2 can be appropriately set. For example, the ratio of the number of atoms of zirconium atoms to the number of atoms of element J2 can be 1:1 or thereabouts. In addition, as a material that can have ferroelectricity, lead titanate (PbTiO X ), barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), barium titanate and other piezoelectric ceramics with perovskite structure.

[0211] In addition, as a material that can have ferroelectricity, a metal nitride containing an element M1, an element M2 and nitrogen can be cited. Here, the element M1 is, for example, one or more selected from aluminum, gallium, indium, etc. In addition, the element M2 is, for example, one or more selected from boron, scandium, yttrium, lanthanum, cerium, neodymium, europium, titanium, zirconium, hafnium, vanadium, niobium, tantalum, chromium, etc. In addition, the ratio of the number of atoms of the element M1 to the number of atoms of the element M2 can be appropriately set. In addition, a metal nitride containing the element M1 and nitrogen sometimes has ferroelectricity even if it does not contain the element M2. In addition, as a material that can have ferroelectricity, a material in which the element M3 is added to the above-mentioned metal nitride can be cited. Here, the element M3 is, for example, one or more selected from magnesium, calcium, strontium, zinc, cadmium, etc. In addition, the ratio of the number of atoms of the element M1, the number of atoms of the element M2 and the number of atoms of the element M3 can be appropriately set.

[0212] In addition, as a material that can have ferroelectricity, for example, SrTaO 2 N、BaTaO 2 N and other perovskite-type oxynitrides, κ-type alumina GaFeO 3 wait.

[0213] Note that although the above description shows examples of metal oxides and metal nitrides, the present invention is not limited thereto and, for example, metal oxynitrides obtained by adding nitrogen to the above metal oxides or metal nitride oxides obtained by adding oxygen to the above metal nitrides may also be used.

[0214] In addition, as a material that can have ferroelectricity, for example, a mixture or compound composed of a plurality of materials selected from the materials listed above can be used. Alternatively, the insulator 430 can have a stacked structure composed of a plurality of materials selected from the materials listed above. The crystal structure (properties) of the materials listed above and the like may change not only depending on the deposition conditions but also depending on various processes and the like. Therefore, in this specification and the like, sometimes not only a material that exhibits ferroelectricity is referred to as a ferroelectric, but also a material that can have ferroelectricity is also referred to as a ferroelectric.

[0215] In addition, the metal oxide containing one or both of hafnium and zirconium can have ferroelectricity even if it is processed into a thin film of several nm, so it is preferred. Here, the thickness of the insulator 430 can be less than 100nm, preferably less than 50nm, more preferably less than 20nm, and further preferably less than 10nm (typically, more than 2nm and less than 9nm). For example, the thickness of the insulator 430 is preferably more than 8nm and less than 12nm. When the insulator 430 is a ferroelectric layer that can be thin-filmed, for example, the capacitor 38 can be combined with semiconductor elements such as miniaturized transistors to form a semiconductor device. In this specification, etc., a material that can have ferroelectricity in a layered form is sometimes referred to as a ferroelectric layer, a metal oxide film, or a metal nitride film. In addition, in this specification, etc., sometimes such a device including a ferroelectric layer, a metal oxide film, or a metal nitride film is referred to as a ferroelectric device.

[0216] In addition, a metal oxide containing one or both of hafnium and zirconium is preferred because it can have ferroelectricity even when its area is small. For example, even if the area (occupied area) of the ferroelectric layer in top view is 100 μm 2 Below, 10μm 2 Below, 1μm 2 Below or 0.1μm 2 The following can also have ferroelectricity. In addition, sometimes the area is 10000nm 2 Below or 1000nm 2 The following also has ferroelectricity. By forming a ferroelectric layer with a small area, the area occupied by the capacitor 38 can be reduced.

[0217] Ferroelectrics are insulators that are polarized internally when exposed to an external electric field and that maintain polarization even when the electric field is zero. Therefore, a nonvolatile memory element can be formed by using a capacitor (hereinafter sometimes referred to as a ferroelectric capacitor) that uses the material as a dielectric. A nonvolatile memory element using a ferroelectric capacitor is sometimes referred to as a FeRAM (Ferroelectric Random Access Memory) or a ferroelectric memory, etc. For example, a ferroelectric memory includes a transistor and a ferroelectric capacitor, and one of the source and drain of the transistor is electrically connected to a terminal of the ferroelectric capacitor. Thus, in the case where a ferroelectric capacitor is used as the capacitor 38, the memory cell shown in this embodiment is used as a ferroelectric memory.

[0218] In addition, ferroelectricity is considered to be exhibited because oxygen or nitrogen of the crystal contained in the ferroelectric layer is displaced by the action of an external electric field. In addition, the exhibiting of ferroelectricity is presumed to depend on the crystal structure of the crystal contained in the ferroelectric layer. Therefore, in order for the insulator 430 to exhibit ferroelectricity, the insulator 430 needs to include crystals. In particular, the insulator 430 preferably includes crystals having a crystal structure of an orthorhombic system, thereby exhibiting ferroelectricity. In addition, the crystal structure of the crystal contained in the insulator 430 may also be any one or more selected from the group consisting of a cubic system, a tetragonal system, an orthorhombic system, a monoclinic system, and a hexagonal system. In addition, the insulator 430 may also have an amorphous structure. At this time, the insulator 430 may also have a composite structure of an amorphous structure and a crystal structure.

[0219] The conductor 420 is provided in contact with a portion of the top surface of the insulator 430. In addition, the side end of the conductor 420 is preferably located inside the side end of the conductor 415 in both the X direction and the Y direction. In the structure where the insulator 430 covers the side end of the conductor 415, the side end of the conductor 420 may be located outside the side end of the conductor 415.

[0220] A single layer or a stack of conductive materials can be used as the conductor 420. For example, a conductive material that is not easily oxidized or a conductive material that has a function of suppressing oxygen diffusion is preferably used as the conductor 420. For example, titanium nitride or tantalum nitride can be used.

[0221] In addition, if Figure 6 As shown, in two adjacent capacitors 38 , the conductors 420 of both capacitors 38 may be formed integrally so that one terminal of each capacitor 38 is electrically connected to each other.

[0222] Since the insulator 480 is used as an interlayer film, the relative dielectric constant is preferably low. By using a material with a low relative dielectric constant for the interlayer film, the parasitic capacitance generated between the wirings can be reduced. As the insulator 480, a single layer or a stack of insulators containing a material with a low relative dielectric constant can be used. Silicon oxide and silicon oxynitride are preferred because they have thermal stability. In this case, the insulator 480 contains at least silicon and oxygen.

[0223] {Transistor 37}

[0224] Transistor 37 includes conductor 420, conductor 240 on insulator 280, oxide semiconductor 230, insulator 250 on oxide semiconductor 230, and conductor 260 on insulator 250. Oxide semiconductor 230 is used as a semiconductor layer, conductor 260 is used as a gate electrode, insulator 250 is used as a gate insulator, conductor 420 is used as one of a source electrode and a drain electrode, and conductor 240 is used as the other of the source electrode and the drain electrode.

[0225] like Figure 8B and Figure 8C As shown, an opening 290 that reaches the conductor 420 is provided in the insulator 280 and the conductor 240. At least a portion of the oxide semiconductor 230 is disposed in the opening 290. The oxide semiconductor 230 has a region in contact with the top surface of the conductor 420 in the opening 290, a region in contact with the side surface of the conductor 240 in the opening 290, and a region in contact with at least a portion of the top surface of the conductor 240. The insulator 250 is disposed so that at least a portion thereof is located in the opening 290. The conductor 260 is disposed so that at least a portion thereof is located in the opening 290. In addition, as shown in FIG. Figure 8B and Figure 8C As shown, the conductor 260 is preferably provided in a manner embedded in the opening 290 .

[0226] In addition, the conductor 420 may have a structure in which tantalum nitride is stacked on titanium nitride, for example. In this case, the titanium nitride is in contact with the insulator 430, and the tantalum nitride is in contact with the oxide semiconductor 230. By adopting such a structure, it is possible to suppress the conductor 420 from being excessively oxidized by the oxide semiconductor 230. In addition, when an oxide insulator is used as the insulator 430, it is possible to suppress the conductor 420 from being excessively oxidized by the insulator 430. Alternatively, the conductor 420 may have a structure in which tungsten is stacked on titanium nitride, for example.

[0227] In addition, since the conductor 420 has a region in contact with the oxide semiconductor 230, it is preferable to use a conductive material containing oxygen. By using a conductive material containing oxygen as the conductor 420, the conductivity can be maintained even if the conductor 420 absorbs oxygen. In addition, even if an insulator containing oxygen such as zirconium oxide is used as the insulator 430, the conductivity of the conductor 420 can be maintained. As the conductor 420, for example, a single layer or a stack of indium tin oxide (also called ITO), indium tin oxide with added silicon (also called ITSO), or indium zinc oxide (also called IZO (registered trademark)) can be used.

[0228] The oxide semiconductor 230 has a region in contact with the side surface of the conductor 240 and a region in contact with a portion of the top surface of the conductor 240 in the opening 290. In this way, since the oxide semiconductor 230 is in contact with the top surface of the conductor 240 in addition to the side surface, the contact area between the oxide semiconductor 230 and the conductor 240 can be increased.

[0229] in addition, Figure 8CThe structure in which the side end of the oxide semiconductor 230 is located inside the side end of the conductor 240 is shown. Note that one embodiment of the present invention is not limited to this. For example, a structure in which the side end of the oxide semiconductor 230 is aligned with the side end of the conductor 240 in the Y direction may be adopted. Alternatively, a structure in which the side end of the oxide semiconductor 230 is located outside the side end of the conductor 240 may be adopted.

[0230] In addition, if FIG. 8A to FIG. 8C As shown in FIG. 1 , it is preferred that the conductor 260 is extended in the Y direction and the conductor 240 is extended in the X direction. By adopting this structure, the conductor 260 and the conductor 240 are arranged to cross each other. Fig. 8A In the embodiment, the conductor 410 is provided in a planar shape, but one embodiment of the present invention is not limited thereto. For example, the conductor 410 may be parallel to the conductor 260 or parallel to the conductor 240.

[0231] The side wall of the opening 290 (sometimes referred to as the side wall in the opening 290 of the insulator 280) is preferably perpendicular to the top surface of the conductor 410. In other words, the insulator 280 can also be said to include the opening 290 extending in a direction perpendicular to the top surface of the conductor 410. In this case, the opening 290 has a cylindrical shape. By adopting this structure, the miniaturization or high integration of the memory cell can be achieved.

[0232] In addition, in the present embodiment, an example is shown in which the opening 290 is circular when viewed from a plane, but one embodiment of the present invention is not limited to this. For example, when viewed from a plane, the opening 290 may also be in a substantially circular shape such as an ellipse, a polygonal shape such as a quadrangle, or a shape in which the corners of a polygon such as a quadrangle are curved. In this case, the maximum width of the opening 290 is preferably calculated appropriately based on the shape of the uppermost portion of the opening 290. For example, when the opening is a quadrangle when viewed from a plane, the maximum width of the opening 290 is preferably the length of the diagonal line of the uppermost portion of the opening 290.

[0233] The portions of the oxide semiconductor 230, the insulator 250, and the conductor 260 disposed in the opening 290 reflect the shape of the opening 290. Therefore, the oxide semiconductor 230 is provided so as to cover the bottom and sidewalls of the opening 290, the insulator 250 is provided so as to cover the oxide semiconductor 230, and the conductor 260 is provided so as to fit into the recess of the insulator 250 reflecting the shape of the opening 290.

[0234] That is, a portion of the semiconductor layer (equivalent to the oxide semiconductor 230) including the channel formation region of the transistor 37 is arranged along the side wall of the opening 290. In other words, it is arranged in a direction perpendicular to the top surface of the conductor 410. In other words, it can be said that the channel length direction of the transistor 37 has a component in the direction perpendicular to the top surface of the conductor 410. Therefore, a transistor of one embodiment of the present invention can be called, for example, a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, or a vertical channel transistor.

[0235] Note that Figure 8B and Figure 8C In the embodiment, the opening 290 is provided so that the side wall of the opening 290 is perpendicular to the top surface of the conductor 410, but one embodiment of the present invention is not limited thereto. For example, the side wall of the opening 290 may also be tapered.

[0236] Here, Fig. 9A Show Figure 8B An enlarged view of the oxide semiconductor 230 and its vicinity in FIG. Fig. 9B A cross-sectional view including the conductor 240 on the XY plane is shown.

[0237] like Fig. 9A As shown, the oxide semiconductor 230 includes a region 230i and a region 230na and a region 230nb provided so as to sandwich the region 230i.

[0238] The region 230na is a region in the oxide semiconductor 230 that is in contact with the conductor 420. At least a portion of the region 230na is used as one of the source region and the drain region of the transistor 37. The region 230nb is a region in the oxide semiconductor 230 that is in contact with the conductor 240. At least a portion of the region 230nb is used as the other of the source region and the drain region of the transistor 37. Fig. 9B As shown, the conductor 240 is in contact with the entire periphery of the oxide semiconductor 230. Therefore, the other of the source region and the drain region of the transistor 37 may be formed on the entire periphery of the portion of the oxide semiconductor 230 formed in the same layer as the conductor 240.

[0239] The region 230i is a region between the region 230na and the region 230nb of the oxide semiconductor 230. At least a portion of the region 230i is used as a channel formation region of the transistor 37. That is, the channel formation region of the transistor 37 is located in a region between the conductor 420 and the conductor 240 of the oxide semiconductor 230. In addition, it can also be said that the channel formation region of the transistor 37 is located in a region of the oxide semiconductor 230 that contacts the insulator 280 or a region near the insulator 280.

[0240] The channel length of transistor 37 is the distance between the source region and the drain region. That is, the channel length of transistor 37 can be determined according to the thickness of insulator 280 on conductor 420. Fig. 9A , the dotted double arrow indicates the channel length L of the transistor 37. The channel length L corresponds to the distance between the end of the region where the oxide semiconductor 230 contacts the conductor 420 and the end of the region where the oxide semiconductor 230 contacts the conductor 240 when viewed in cross section. In other words, the channel length L corresponds to the length of the side surface of the insulator 280 on the side of the opening 290 when viewed in cross section.

[0241] In the conventional transistor, the channel length is set according to the exposure limit of the photolithography, but in one embodiment of the present invention, the channel length can be set according to the thickness of the insulator 280. Therefore, the channel length of the transistor 37 can be set to a very fine structure below the exposure limit of the photolithography (for example, below 60nm, below 50nm, below 40nm, below 30nm, below 20nm, or below 10nm and above 1nm or above 5nm). Therefore, the on-state current of the transistor 37 becomes larger, so that the frequency characteristics can be improved. Therefore, the read speed and write speed of the memory cell 32 can be improved.

[0242] Furthermore, as described above, a channel formation region, a source region, and a drain region can be formed in the opening 290. Thus, compared with a conventional transistor in which a channel formation region, a source region, and a drain region are respectively provided on the XY plane, the occupied area of ​​the transistor 37 can be reduced. Thus, high integration of the memory cell 32 can be achieved, so that the storage capacity per unit area can be increased.

[0243] In addition, on the XY plane including the channel formation region of the oxide semiconductor 230, the oxide semiconductor 230, the insulator 250, and the conductor 260 are also aligned with each other. Fig. 9BSimilarly, it is arranged in a concentric circle shape. Therefore, the side surface of the conductor 260 arranged in the center is opposite to the side surface of the oxide semiconductor 230 via the insulator 250. In other words, the edge of the oxide semiconductor 230 as a whole becomes a channel formation region when viewed from a plane. At this time, for example, the channel width of the transistor 37 is determined by the length of the outer circumference of the oxide semiconductor 230. In other words, it can also be said that the channel width of the transistor 37 is determined by the maximum width of the opening 290 (the maximum diameter when the opening 290 is circular when viewed from a plane). Fig. 9A and Fig. 9B In FIG. 1 , the double-pointed arrow indicates the maximum width D of the opening 290. Fig. 9B In FIG. 1 , a double-pointed arrow indicates a channel width W of the transistor 37. By increasing the maximum width D of the opening 290, the channel width per unit area can be increased, thereby increasing the on-state current.

[0244] When the opening 290 is formed by photolithography, the maximum width D of the opening 290 is set according to the exposure limit of the photolithography. In addition, the maximum width D of the opening 290 is set according to the thickness of the oxide semiconductor 230, the insulator 250, and the conductor 260 provided in the opening 290. The maximum width D of the opening 290 is preferably 5 nm or more, 10 nm or more, or 20 nm or more and 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, or 30 nm or less. Note that when the opening 290 is circular when viewed from a plane, the maximum width D of the opening 290 is equivalent to the diameter of the opening 290, and the channel width W can be calculated as "D×π".

[0245] In addition, in the memory cell 32 of one embodiment of the present invention, the channel length L of the transistor 37 is preferably at least smaller than the channel width W of the transistor 37. The channel length L of the transistor 37 according to one embodiment of the present invention is greater than or equal to 0.1 times and less than or equal to 0.99 times, and preferably greater than or equal to 0.5 times and less than or equal to 0.8 times, of the channel width W of the transistor 37. By adopting such a structure, a transistor having good electrical characteristics and high reliability can be realized.

[0246] In addition, the opening 290 is formed in a circular shape when viewed from a plane, so that the oxide semiconductor 230, the insulator 250, and the conductor 260 are arranged in a concentric circle shape. As a result, the distance between the conductor 260 and the oxide semiconductor 230 becomes uniform or substantially uniform, so that the gate electric field of the oxide semiconductor 230 can be applied uniformly or substantially uniformly.

[0247] In the channel formation region of a transistor using an oxide semiconductor in the semiconductor layer, it is preferred that the number of oxygen vacancies is smaller or the impurity concentration (for example, the concentration of hydrogen, nitrogen, or a metal element, etc.) is lower than that in the source region and the drain region. In addition, hydrogen near the oxygen vacancy may form a defect in which hydrogen enters the oxygen vacancy (hereinafter, sometimes referred to as V O H) and generate electrons that become carriers, so in the channel formation region V O H is also preferably reduced. Thus, the channel formation region of the transistor is a high resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0248] In addition, the source region and the drain region of a transistor using an oxide semiconductor as a semiconductor layer are regions where V O The resistance is reduced by increasing the carrier concentration due to more H or higher impurity concentration (e.g., concentration of hydrogen, nitrogen, or metal elements, etc.). That is, the source region and drain region of the transistor are n-type regions with higher carrier concentration and lower resistance than the channel formation region.

[0249] The band gap of the metal oxide used as the oxide semiconductor 230 is preferably greater than 2 eV, and more preferably greater than 2.5 eV. By using a metal oxide with a larger band gap as the oxide semiconductor 230, the off-state current of the transistor can be reduced. By using a transistor with a small off-state current for a memory cell, the storage content can be maintained for a long time. In other words, since no refresh operation is required or the frequency of the refresh operation is extremely low, the power consumption of the memory cell array can be substantially reduced. Note that the frequency of the refresh operation of a general DRAM needs to be about 1 time / 60 msec, but the frequency of the refresh operation of a semiconductor device of one embodiment of the present invention can be about 1 time / 10 sec, that is, more than 10 times or more than 100 times the frequency of the refresh operation of a general DRAM. Note that by using a semiconductor device of one embodiment of the present invention, the refresh operation can be performed once every 1 sec or more and less than 100 sec, preferably once every 5 sec or more and less than 50 sec.

[0250] Note that as the oxide semiconductor 230 , a single layer or a stacked layer of a metal oxide can be used.

[0251] The metal oxide preferably contains at least one of indium and zinc. For example, it preferably contains indium, M (M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and cobalt) and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium and tin.

[0252] In particular, as the metal oxide, an oxide containing indium (In), gallium (Ga) and zinc (Zn) (also denoted as IGZO) is preferably used. Alternatively, an oxide containing indium (In), aluminum (Al) and zinc (Zn) (also denoted as IAZO) may be used. Alternatively, an oxide containing indium (In), aluminum (Al), gallium (Ga) and zinc (Zn) (also denoted as IAGZO) may be used. Alternatively, an oxide containing indium (In), tin (Sn) and zinc (Zn) (also denoted as "ITZO (registered trademark)") may be used. Alternatively, an oxide containing indium (In), gallium (Ga), zinc (Zn) and tin (Sn) (also denoted as "IGZTO") may be used.

[0253] When the metal oxide is an In-M-Zn oxide, the atomic number ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic number ratio of M. Examples of the atomic number ratio of the metal elements in such an In-M-Zn oxide include a composition of In:M:Zn=1:1:1 or in the vicinity thereof, a composition of In:M:Zn=1:1:1.2 or in the vicinity thereof, a composition of In:M:Zn=2:1:3 or in the vicinity thereof, a composition of In:M:Zn=3:1:2 or in the vicinity thereof, a composition of In:M:Zn=4:2:3 or in the vicinity thereof, a composition of In:M:Zn=4:2:4.1 or in the vicinity thereof, a composition of In:M:Zn=5:1:3 or in the vicinity thereof, a composition of In:M:Zn=5:1:6 or in the vicinity thereof, a composition of In:M:Zn=5:1:7 or in the vicinity thereof, a composition of In:M:Zn=5:1:8 or in the vicinity thereof, a composition of In:M:Zn=6:1:6 or in the vicinity thereof, or a composition of In:M:Zn=5:2:5 or in the vicinity thereof. In addition, the atomic number ratio of In in the In-M-Zn oxide may be smaller than the atomic number ratio of M in some cases. Examples of the atomic ratio of metal elements in the In-M-Zn oxide include a composition of In:M:Zn=1:3:2 or in the vicinity thereof, and a composition of In:M:Zn=1:3:4 or in the vicinity thereof. Note that the vicinity composition includes a range of ±30% of the desired atomic ratio.

[0254] For example, when the composition is described as having an atomic ratio of In:Ga:Zn=4:2:3 or thereabouts, the content ratio of each element includes the following cases: when In is 4, Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. In addition, when the composition is described as having an atomic ratio of In:Ga:Zn=5:1:6 or thereabouts, the content ratio of each element includes the following cases: when In is 5, Ga is greater than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. In addition, when the composition is described as having an atomic ratio of In:Ga:Zn=1:1:1 or thereabouts, the content ratio of each element includes the following cases: when In is 1, Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0255] In addition, when stacking metal oxides, for example, the following three-layer structure can be cited: a metal oxide having an atomic ratio of metal elements of In:Ga:Zn=1:1:1 is set as the first layer, a metal oxide having an atomic ratio of metal elements of In:Zn=4:1 is set as the second layer, and a metal oxide having an atomic ratio of metal elements of In:Ga:Zn=1:1:1 is set as the third layer. It is preferred that the band gap of the metal oxides of the first layer and the third layer is larger than the band gap of the metal oxide of the second layer. By adopting this structure, the metal oxide of the second layer can be used as the main current path, so the so-called embedded channel structure can be realized.

[0256] The metal oxide can be formed by sputtering or atomic layer deposition (ALD). Note that when the metal oxide is formed by sputtering, the composition of the metal oxide after formation is sometimes different from the composition of the sputtering target. In particular, the zinc content of the metal oxide after formation is sometimes reduced to about 50% of the zinc content of the sputtering target.

[0257] The oxide semiconductor 230 preferably has crystallinity. Examples of crystalline oxide semiconductors include CAAC-OS (c-axis aligned crystalline oxide semiconductor), nc-OS (nanocrystalline oxide semiconductor), polycrystalline oxide semiconductors, and single crystal oxide semiconductors. CAAC-OS or nc-OS is preferably used as the oxide semiconductor 230, and CAAC-OS is particularly preferably used.

[0258] The CAAC-OS preferably has a plurality of layered crystal regions and its c-axis is oriented in the normal direction of the formed surface. For example, the oxide semiconductor 230 preferably has layered crystals parallel to the side walls of the opening 290, especially the side surfaces of the insulator 280. By adopting such a structure, the layered crystals of the oxide semiconductor 230 are formed parallel to the channel length direction of the transistor 37, so that the on-state current of the transistor can be increased.

[0259] Note that although Figure 8B and Figure 8C The oxide semiconductor 230 is shown as a single layer, but one embodiment of the present invention is not limited thereto. The oxide semiconductor 230 may also have a stacked structure of multiple oxide layers with different chemical compositions. For example, a structure in which multiple types selected from the above-mentioned metal oxides are appropriately stacked may also be adopted.

[0260] 〔Deformation Example〕

[0261] Fig.10 yes Figure 6 Here, the following mainly describes the modified examples of the semiconductor device shown in FIG. Figure 6 The semiconductor devices shown are different.

[0262] Fig.10 The semiconductor device shown includes a functional element 34 instead of the functional element 33. The functional element 34 includes a connection portion 39 and a transistor 37 provided above the connection portion 39.

[0263] The connection portion 39 is provided in the element layer 30 a . The transistor 37 can be electrically connected to the transistor 550 provided in the element layer 20 through the connection portion 39 .

[0264] Fig.11A and Fig. 11B 1 and 2 are a plan view and a cross-sectional view of a transistor 37 and a connection portion 39 included in the functional element 34 . Fig.11A is a plan view of the functional element 34. In addition, Fig. 11B is a cross-sectional view of the functional element 34. Here, Fig. 11B It is along Fig.11A The cross-sectional view of the portion along the dashed line A5-A6 in FIG. Fig.11A In the plan view, some components are omitted for clarity.

[0265] Fig.11A and Fig. 11B The functional element 34 shown includes a transistor 37 and a connection portion 39. The functional element 34 is different from the memory cell 32 in that the insulator 430 is structured, the insulator 431 is included, and the conductor 415 is in contact with the conductor 420. The other structures are substantially the same as the memory cell 32.

[0266] In the functional element 34, the insulator 430 is provided with an opening overlapping with the opening 490. The opening of the insulator 430 is preferably provided to include the opening 490. That is, the opening 490 is preferably located inside the opening of the insulator 430 when viewed from a plane.

[0267] In addition, the portion provided along the inner wall of the insulator 480 along the conductor 415 inside the opening 490 includes an insulator 431. The insulator 431 is in contact with the conductor 415 and the conductor 420. The insulator 430 and the insulator 431 are formed by processing the same insulating film and contain the same element. The insulator 431 is formed when a portion of the insulator 430 located at the bottom of the opening 490 is removed by anisotropic etching and a portion of the insulator 430 remains. The insulator 431 may also be called a sidewall insulator.

[0268] Note that the insulator 431 may not be formed depending on a processing method of an insulating film to be the insulator 430. In this case, the area in which the conductor 420 and the conductor 415 are in contact with each other becomes larger, which is preferable.

[0269] That is, the connection portion 39 has a structure in which an opening is formed in a part of the insulator 430 in the capacitor 38, and the conductor 415 and the conductor 420 are in contact with each other through the opening.

[0270] Therefore, the conductor 420 is electrically connected to the conductor 415 , and thus the conductor 420 is electrically connected to the conductor 410 via the conductor 415 . In other words, one of the source electrode and the drain electrode of the transistor 37 is electrically connected to the conductor 410 .

[0271] Note that the semiconductor device and computing device according to one embodiment of the present invention are not limited to the semiconductor device and computing device described in this embodiment. At least a part of the structural examples, working examples, and drawings corresponding to these examples shown in this embodiment can be appropriately combined with other structural examples, other working examples, other drawings, and other embodiments shown in other embodiments of the present invention.

[0272] (Implementation Method 2)

[0273] In this embodiment, a transistor including an oxide semiconductor in a channel formation region (OS transistor) is described. In addition, in the description of the OS transistor, a comparison with a transistor including silicon in a channel formation region (also referred to as a Si transistor) is briefly described.

[0274] 〔OS transistor〕

[0275] It is preferable to use an oxide semiconductor with a low carrier concentration for the OS transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , and more preferably less than 1×10 13 cm -3 , and further preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 In the case of reducing the carrier concentration of the oxide semiconductor, the impurity concentration in the oxide semiconductor can be reduced to reduce the defect state density in the oxide semiconductor. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0276] Since high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes have a low trap state density. In addition, it takes a long time for the charges captured by the trap states of the oxide semiconductor to disappear, and sometimes they act like fixed charges. Therefore, sometimes the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density are unstable.

[0277] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. Examples of impurities include hydrogen and nitrogen. Note that impurities in an oxide semiconductor refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0278] In an OS transistor, when impurities or oxygen vacancies exist in the channel formation region of an oxide semiconductor, the electrical characteristics are easily changed and reliability may be reduced. In addition, in an OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (hereinafter sometimes referred to as V O H), electrons that become carriers may be generated. In addition, in the OS transistor, when V OWhen the gate voltage is 0V, the donor concentration in the channel formation region may increase. Therefore, in the OS transistor, as the donor concentration in the channel formation region increases, the threshold voltage may be uneven. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the OS transistor may have a normally-on characteristic (a characteristic in which the drain current flows when the gate voltage is 0V). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V O H.

[0279] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and more preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0280] For example, in Si transistors, as the miniaturization of transistors progresses, a short channel effect (SCE: Short Channel Effect) occurs. Therefore, miniaturization of Si transistors is difficult. One of the reasons for the occurrence of the short channel effect is that the band gap of silicon is small. On the other hand, in OS transistors, an oxide semiconductor, which is a semiconductor material with a large band gap, is used, so the short channel effect can be suppressed. In other words, an OS transistor is a transistor with no short channel effect or very little short channel effect.

[0281] The short channel effect refers to the degradation of electrical characteristics that occurs with the miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a reduction in threshold voltage, an increase in subthreshold swing value (sometimes recorded as S value), and an increase in leakage current. Here, the S value refers to the change in gate voltage in the subthreshold region that changes the drain current value by one digit with a fixed drain voltage.

[0282] As an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0283] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region and the characteristic length between the drain region and the channel formation region in OS transistors are smaller. Therefore, OS transistors have a higher ability to resist short channel effects than Si transistors. That is, when you want to manufacture transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0284] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor, so the energy difference of the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to more than 0.1 eV and less than 0.2 eV. Thus, the OS transistor can be regarded as having n + / n - / n + The accumulation type junctionless transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel formation region is n - Type region, source region and drain region are both n + Type area.

[0285] When the above structure is used as an OS transistor, good electrical characteristics can be achieved even if miniaturization or high integration is performed. For example, even if the gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm due to the occurrence of a short channel effect. Therefore, compared with Si transistors, OS transistors can be used as transistors with a small channel length. The gate length is the length of the gate electrode in the direction of the carrier movement channel formation region when the transistor is working, and is also the width of the bottom surface of the gate electrode when the transistor is viewed from a plane.

[0286] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cutoff frequency of the transistor can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz.

[0287] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a small channel length.

[0288] The configuration, structure, method, or the like described in this embodiment mode can be used in combination with the configuration, structure, method, or the like described in other embodiments mode, etc. as appropriate.

[0289] (Implementation method 3)

[0290] In this embodiment, electronic components, electronic devices, mainframe computers, space equipment, and data centers (also referred to as DC) that can use the semiconductor device described in the above embodiment are described. Electronic components, electronic devices, mainframe computers, space equipment, and data centers that use a semiconductor device in one embodiment of the present invention are effective for achieving high performance such as low power consumption.

[0291] 〔Electronic components〕

[0292] Fig. 12A It is a perspective view of an electronic component 700 and a substrate (circuit board 704) on which the electronic component 700 is mounted. Fig. 12A The electronic component 700 shown includes a semiconductor device 710 within a mold 711. Fig. 12A 700 is partially omitted to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713. The electrode pad 713 is electrically connected to the semiconductor device 710 through a lead 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of these electronic components and electrically connecting them on the printed circuit board 702, a circuit board 704 is completed.

[0293] In addition, the semiconductor device 710 includes a driving circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driving circuit layer 715 and the storage layer 716 are stacked can adopt a monolithic stacked structure. In the monolithic stacked structure, for example, each layer can be connected without using through-electrode technology such as TSV (Through Silicon Via) and bonding technology such as Cu-Cu direct bonding. When having a monolithic stacked structure of the driving circuit layer 715 and the storage layer 716, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface part between the processor and the memory can be achieved.

[0294] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to the technology using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0295] In addition, it is preferred that multiple memory cell arrays included in the storage layer 716 are formed using OS transistors, and the multiple memory cell arrays are stacked in a monolithic manner. When the multiple memory cell arrays have a monolithic stacked structure, one or both of the bandwidth of the memory and the access delay of the memory can be improved. Bandwidth refers to the amount of data transmitted per unit time. In addition, access delay refers to the time between access and the start of data transmission and reception. When Si transistors are used in the storage layer 716, it is more difficult to implement a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0296] In other words, OS transistors have superior effects compared to Si transistors, such as being able to achieve a wider memory bandwidth.

[0297] Note that the semiconductor device 710 may also be referred to as a bare chip. In this specification, etc., a bare chip refers to a chip obtained by forming a circuit pattern on a disk-shaped substrate (also referred to as a wafer) or the like in the manufacturing process of a semiconductor chip, and cutting it into rectangular small pieces. Examples of semiconductor materials that can be used for bare chips include silicon, silicon carbide, or gallium nitride. For example, a bare chip obtained from a silicon substrate (also referred to as a silicon wafer) is sometimes referred to as a silicon chip.

[0298] Fig. 12B 7 is a perspective view of an electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0299] In the electronic component 730, the semiconductor device 710 can be used as a storage device such as a high bandwidth memory (HBM). In addition, the semiconductor device 735 can be used as an integrated circuit (for example, a computing device, a control device, or a signal processing device) such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0300] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate, etc. The interposer 731 may be, for example, a silicon interposer or a resin interposer, etc.

[0301] The plug board 731 has a plurality of wirings and has a function of electrically connecting each of a plurality of integrated circuits having different terminal spacings through each of the plurality of wirings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the plug board 731 has a function of electrically connecting an integrated circuit disposed on the plug board 731 to an electrode disposed on the package substrate 732. Therefore, the plug board 731 is sometimes also referred to as a "rewiring substrate" or an "intermediate substrate". In addition, sometimes a through electrode is provided in the plug board 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, when a silicon plug board is used as the plug board 731, TSV can also be used as a through electrode.

[0302] A silicon interposer is preferably used as the interposer 731. Since a silicon interposer does not need to be provided with active elements, it can be manufactured at a lower cost than an integrated circuit. In addition, the wiring formation of the silicon interposer can be performed in a semiconductor process, so it is easy to form fine wiring that is difficult to form when using a resin interposer.

[0303] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0304] In addition, for example, in SiP or MCM using a silicon interposer, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not likely to occur. In addition, since the surface flatness of the silicon interposer is high, poor connection between the integrated circuit disposed on the silicon interposer and the silicon interposer is not likely to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and disposed on the interposer.

[0305] On the other hand, when a plurality of integrated circuits with different terminal pitches are electrically connected, for example, by using a silicon interposer and TSV, a space such as the width of the terminal pitch is required. Therefore, when it is desired to reduce the size of the electronic component 730, the width of the terminal pitch becomes a problem, and it is sometimes difficult to set up a large number of wirings required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner may also be used.

[0306] The substrate on which the electronic component 730 is mounted may be provided with a heat sink (heat sink plate) overlapping the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 uniform. For example, in the electronic component 730, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 uniform.

[0307] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig. 12B An example of forming the electrode 733 using solder balls is shown. The electronic component 730 can realize BGA (Ball Grid Array) packaging by arranging solder balls in a matrix at the bottom of the packaging substrate 732. In addition, the electrode 733 can also be formed using conductive needles. The electronic component 730 can realize PGA (Pin Grid Array) packaging by arranging conductive needles in a matrix at the bottom of the packaging substrate 732.

[0308] The electronic component 730 can be mounted on other substrates by various packaging methods, not limited to BGA or PGA. For example, packaging methods such as SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package) can be used.

[0309] 〔Electronic equipment〕

[0310] Fig.13A It is a three-dimensional diagram of the electronic device 6500 . Fig.13A The electronic device 6500 shown is a portable information terminal device that can be used as a smartphone. The electronic device 6500 includes, for example, a frame 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A semiconductor device of one embodiment of the present invention can be used for a display unit 6502 or a control device 6509. By using a semiconductor device of one embodiment of the present invention for the control device 6509, power consumption can be reduced, so it is preferred.

[0311] Fig. 13B It is a three-dimensional diagram of electronic device 6600. Fig. 13BThe electronic device 6600 shown is an information terminal device that can be used as a notebook personal computer. The electronic device 6600 includes, for example, a frame 6611, a keyboard 6612, a pointing device 6613, an external connection port 6614, a display unit 6615, and a control device 6616. The control device 6616 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. A semiconductor device of one embodiment of the present invention can be used for the control device 6509 or the control device 6616. By using a semiconductor device of one embodiment of the present invention for the control device 6616, power consumption can be reduced, so it is preferred.

[0312] 〔Mainframe computer〕

[0313] Fig. 13C This is a three-dimensional diagram of the mainframe computer 5600. Fig. 13C In the illustrated mainframe computer 5600, a plurality of rack-mounted computers 5620 are housed in a rack 5610. The mainframe computer 5600 may also be referred to as a supercomputer.

[0314] Fig.13D 1 is a perspective view illustrating an example of the structure of the computer 5620. Fig.13D In the embodiment, the computer 5620 includes a motherboard 5630. The motherboard 5630 includes a plurality of slots 5631 and a plurality of connection terminals (not shown). A personal computer card 5621 is inserted into the slots 5631. The personal computer card 5621 includes connection terminals 5623, 5624, and 5625, which are connected to the motherboard 5630.

[0315] Fig.13E The personal computer card 5621 shown is an example of a processing board including a CPU, a GPU, a storage device, etc. The personal computer card 5621 has a board 5622. In addition, the board 5622 includes a connection terminal 5623, a connection terminal 5624, a connection terminal 5625, a semiconductor device 5626, a semiconductor device 5627, a semiconductor device 5628, and a connection terminal 5629. Note that Fig.13E Semiconductor devices other than the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 are shown. For description of these semiconductor devices, refer to the description of the semiconductor device 5626, the semiconductor device 5627, and the semiconductor device 5628 described below.

[0316] The connection terminal 5629 has a shape that can be inserted into the slot 5631 of the motherboard 5630, and is used as an interface for connecting the personal computer card 5621 and the motherboard 5630. Examples of the specification of the connection terminal 5629 include PCIe (Peripheral Component Interconnect Express: a high-speed serial computer expansion bus standard).

[0317] Each of the connection terminals 5623, 5624, and 5625 can be used as an interface for supplying power to the personal computer card 5621 or inputting a signal, for example. In addition, for example, it can be used as an interface for outputting a signal calculated by the personal computer card 5621. As examples of the specifications of each of the connection terminals 5623, 5624, and 5625, USB (Universal Serial Bus), SATA (Serial ATA), or SCSI (Small Computer System Interface) can be cited. In addition, when the connection terminals 5623, 5624, and 5625 each output a video signal, as examples of the specifications, HDMI (registered trademark) (High-Definition Multimedia Interface) can be cited.

[0318] The semiconductor device 5626 includes a terminal (not shown) for inputting and outputting a signal. By inserting the terminal into a socket (not shown) included in the board 5622 , the semiconductor device 5626 and the board 5622 can be electrically connected.

[0319] The semiconductor device 5627 includes a plurality of terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. Examples of the semiconductor device 5627 include FPGA, GPU, and CPU. For example, the electronic component 730 described above can be used as the semiconductor device 5627.

[0320] The semiconductor device 5628 includes a plurality of terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, soldering the terminals to wiring included in the board 5622 by reflow soldering. As the semiconductor device 5628, for example, a memory device can be cited. As the semiconductor device 5628, for example, the electronic component 700 described above can be used.

[0321] The mainframe computer 5600 can be used as a parallel computer. By using the mainframe computer 5600 as a parallel computer, for example, large-scale calculations required for learning and inference of artificial intelligence can be performed.

[0322] 〔Space Equipment〕

[0323] For example, the semiconductor device of one embodiment of the present invention can be used in space equipment such as equipment for processing and storing information.

[0324] A semiconductor device according to one embodiment of the present invention may include an OS transistor. The OS transistor has a small change in electrical characteristics due to exposure to radiation. In other words, the OS transistor has high resistance to radiation and is therefore suitable for use in an environment where radiation may be incident. For example, an OS transistor is appropriately used when used in outer space.

[0325] exist Fig.14 In FIG. 6 , an artificial satellite 6800 is shown as an example of a space device. The artificial satellite 6800 includes a main body 6801, a solar cell panel 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. Fig.14 An example is shown in which the outer space includes the planet 6804. Note that the outer space refers to, for example, an altitude of 100 km or more, but the outer space described in this specification and the like may also include the thermosphere, mesosphere, and stratosphere.

[0326] In addition, although Fig.14 Although not shown in the figure, a battery management system (also called BMS) or a battery control circuit may be provided in the secondary battery 6805. When an OS transistor is used for the battery management system or the battery control circuit, power consumption is low and high reliability is achieved even in outer space, so it is preferred.

[0327] In addition, outer space is an environment where the radiation dose is more than 100 times that of the ground. Examples of radiation include: electromagnetic waves (electromagnetic radiation) represented by X-rays and gamma rays; and particle radiation represented by alpha rays, beta rays, neutron rays, proton rays, heavy ion rays, muon rays, etc.

[0328] When sunlight hits the solar panel 6802, the power required for the artificial satellite 6800 to operate is generated. However, for example, when sunlight does not hit the solar panel 6802 or when the amount of sunlight hitting the solar panel 6802 is small, the power generated by the solar panel 6802 decreases. Therefore, there is a possibility that the power required for the artificial satellite 6800 to operate may not be generated. In order to operate the artificial satellite 6800 even when the power generated by the solar panel 6802 is small, it is preferable to provide a secondary battery 6805 in the artificial satellite 6800. In addition, the solar panel 6802 is sometimes referred to as a solar cell module.

[0329] The artificial satellite 6800 can generate a signal. The signal is transmitted through the antenna 6803. In addition, for example, a receiver on the ground or other artificial satellites can receive the signal. For example, by receiving the signal transmitted by the artificial satellite 6800, the receiver can measure the position of the receiver that receives the signal. Thus, the artificial satellite 6800 can constitute a satellite positioning system.

[0330] In addition, the control device 6807 has a function of controlling the artificial satellite 6800. The control device 6807 is configured using, for example, any one or more selected from a CPU, a GPU, and a storage device. In addition, a semiconductor device including an OS transistor of one embodiment of the present invention is preferably used for the control device 6807. Compared with Si transistors, the electrical characteristics of OS transistors due to irradiation with radiation are less changed. Therefore, OS transistors are preferred because they have high reliability even in an environment where radiation may be incident.

[0331] In other words, the OS transistor has excellent effects such as high resistance to radiation rays, etc., compared with the Si transistor.

[0332] In addition, the artificial satellite 6800 may include a sensor. For example, by including a visible light sensor, the artificial satellite 6800 may have a function of detecting sunlight reflected from an object on the ground. Or, by including a thermal infrared sensor, the artificial satellite 6800 may have a function of detecting thermal infrared rays released from the ground. Thus, the artificial satellite 6800 may be used as an earth observation satellite, for example.

[0333] Note that although an artificial satellite is described as an example of space equipment in this embodiment, the present invention is not limited to this. For example, a semiconductor device according to one embodiment of the present invention can be used for space equipment such as a spacecraft, a space capsule, and a space probe.

[0334] 〔Data Center〕

[0335] For example, a semiconductor device according to one embodiment of the present invention can be used in a storage system used in a data center or the like. A data center is required to ensure data invariance and to manage data over a long period of time. When managing data over a long period of time, for example, it is necessary to set up storage and servers for storing large amounts of data, ensure a stable power supply to maintain data, or ensure cooling equipment required for maintaining data. Therefore, for example, it is necessary to enlarge the facilities of a data center.

[0336] By using a semiconductor device of one embodiment of the present invention in a storage system used in a data center, it is possible to reduce the power required for data retention and to miniaturize the semiconductor device for retaining data. Therefore, for example, it is possible to miniaturize the storage system, miniaturize the power supply for retaining data, and reduce the size of the cooling equipment. As a result, it is possible to save space in the data center.

[0337] In addition, the power consumption of the semiconductor device of one embodiment of the present invention is low, so the heat generation of the circuit can be reduced. As a result, the negative impact of the heat generation on the circuit itself, the peripheral circuits and the peripheral modules can be reduced. In addition, by using the semiconductor device of one embodiment of the present invention, a data center that can operate stably even in a high temperature environment can be realized. Therefore, the reliability of the data center can be improved.

[0338] Fig.15 A storage system that may be used in a data center is shown. Fig.15 The storage system 7000 shown includes a plurality of servers 7001sb as hosts 7001 (shown as host computers). In addition, a plurality of storage devices 7003md are included as storage 7003 (shown as storage). In addition, the host 7001 and the storage 7003 are shown to be connected via a storage area network 7004 (shown as SAN: Storage Area Network) and a storage control circuit 7002 (shown as a storage controller).

[0339] The host 7001 is equivalent to a computer that accesses data stored in the storage 7003. The hosts 7001 may be connected to each other via a network.

[0340] In the storage 7003, the speed of accessing data is shortened by using a flash memory, that is, the time required for writing or reading data is shortened, but this time is much longer than the time required for a DRAM that can be used as a cache memory in the storage. In the storage system, in order to solve the problem of the long access speed of the storage 7003, a cache memory is generally provided in the storage to shorten the time required for writing or reading data.

[0341] The cache memory described above is used in the storage control circuit 7002 and the storage 7003. Data exchanged between the host 7001 and the storage 7003 is stored in the cache memory in the storage control circuit 7002 and the storage 7003 and then output to the host 7001 or the storage 7003.

[0342] When an OS transistor is used as a transistor for storing data in the cache memory to hold a potential corresponding to the data, the refresh frequency of the cache memory can be reduced to reduce the power consumption of the cache memory. In addition, the cache memory can be miniaturized by stacking memory cell arrays.

[0343] By using a semiconductor device of one embodiment of the present invention for any one or more selected from electronic components, electronic devices, large computers, space equipment, and data centers, power consumption can be reduced. Therefore, it is currently believed that as the energy demand for high performance or high integration of semiconductor devices increases, by using a semiconductor device of one embodiment of the present invention, carbon dioxide (CO 2 ) is a representative greenhouse gas emission. In addition, a semiconductor device according to one embodiment of the present invention has low power consumption and is therefore also effective as a measure against global warming.

[0344] The configuration, structure, method, or the like described in this embodiment mode can be used in combination with the configuration, structure, method, or the like described in other embodiments mode, etc. as appropriate.

[0345] (Additional Notes on the Descriptions in This Manual, etc.)

[0346] Hereinafter, comments will be added to the description of the above-mentioned embodiment and each configuration in the embodiment.

[0347] In this specification, when it is stated that "X is connected to Y", it means that the following cases are disclosed in this specification, etc.: a case where X is electrically connected to Y; a case where X is functionally connected to Y; and a case where X is directly connected to Y. Therefore, the connection relationship is not limited to the connection relationship shown in the drawings or the text, and other connection relationships are also described within the scope described in the drawings or the text. X and Y are both objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films or layers, etc.).

[0348] Here, the description of "X and Y are electrically connected" means that when an object having some kind of electrical effect exists between X and Y, an electrical signal can be transmitted and received between X and Y. As an example of a case where X and Y are electrically connected, one or more elements (for example, switches, transistors, capacitors, inductors, resistors, diodes, display devices, light-emitting devices, or loads) that can electrically connect X and Y can be connected between X and Y.

[0349] As an example of a case where X and Y are functionally connected, one or more circuits capable of functionally connecting X and Y (for example, a logic circuit (for example, an inverter, a NAND circuit, or a NOR circuit), a signal conversion circuit (for example, a digital-to-analog conversion circuit, an analog-to-digital conversion circuit, or a gamma correction circuit), a potential level conversion circuit (for example, a power supply circuit (for example, a step-up circuit or a step-down circuit) or a level shift circuit that changes the potential level of a signal), a voltage source, a current source, a switching circuit, an amplifier circuit (for example, a circuit capable of increasing signal amplitude or current, an operational amplifier, a differential amplifier circuit, a source follower circuit, or a buffer circuit), a signal generation circuit, a storage circuit, or a control circuit, etc.) may be connected between X and Y. In addition, as an example, even if another circuit is included between X and Y, when a signal output from X is transmitted to Y, it can be said that X and Y are functionally connected.

[0350] Furthermore, when it is clearly stated that “X is electrically connected to Y”, the following cases are included: a case where X is electrically connected to Y (in other words, a case where X and Y are connected with another element or another circuit interposed therebetween); and a case where X and Y are directly connected (in other words, a case where X and Y are connected without another element or another circuit interposed therebetween).

[0351] In addition, for example, it can be expressed as "X, Y, the source of the transistor (sometimes referred to as one of the first terminal and the second terminal in this specification, etc.) and the drain (sometimes referred to as the other of the first terminal and the second terminal in this specification, etc.) are electrically connected to each other, and are electrically connected in the order of X, the source of the transistor, the drain of the transistor, and Y". Alternatively, it can be expressed as "the source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence". Alternatively, it can be expressed as "X is electrically connected to Y through the source of the transistor and the drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are arranged in sequence". By specifying the connection order in the circuit structure using the same expression method as these examples, the source and drain of the transistor can be distinguished to determine the technical scope. Note that this expression method is an example and is not limited to the above expression method. Here, X and Y are both objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films or layers, etc.).

[0352] In addition, even if independent components are electrically connected to each other on a circuit diagram, one component may have the functions of multiple components. For example, when a part of a wiring is used as an electrode, one conductive film has the functions of both wiring and electrode. Therefore, the category of "electrically connected" in this specification and the like also includes the case where one conductive film has the functions of multiple components.

[0353] In this specification, etc., "resistor" includes, for example, a circuit element having a resistance value higher than 0Ω or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, etc., "resistor" includes, for example, a wiring having a resistance value, a transistor through which current flows between a source and a drain, a diode, or a coil. Therefore, the word "resistor" can be transformed into, for example, "resistance", "load" or "region having a resistance value". On the contrary, for example, the word "resistance", "load" or "region having a resistance value" can be transformed into the word "resistor". The resistance value is, for example, preferably greater than 1 mΩ and less than 10 Ω, more preferably greater than 5 mΩ and less than 5 Ω, and even more preferably greater than 10 mΩ and less than 1 Ω. In addition, for example, it can also be greater than 1 Ω and 1×10 9 Ω or less.

[0354] When a wiring is used as a resistor, the resistance value of the resistor sometimes depends on the length of the wiring. In addition, a conductor having a resistivity different from that of the conductor used as the wiring is sometimes used as a resistor. Alternatively, when a semiconductor is used as a resistor, the resistance value of the resistor is sometimes determined by doping the semiconductor with impurities.

[0355] In this specification, etc., "capacitor" may include, for example, a circuit element having an electrostatic capacitance value higher than 0F, a region of wiring having an electrostatic capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor. Therefore, in this specification, etc., "capacitor" is not limited to a circuit element including a pair of electrodes and a dielectric between the electrodes. "Capacitor" includes, for example, parasitic capacitance generated between wiring and wiring or gate capacitance generated between one of the source and drain of a transistor and the gate. In addition, for example, words such as "capacitor", "parasitic capacitance" or "gate capacitance" can be transformed into words such as "capacitor". On the contrary, for example, the word "capacitor" can be transformed into words such as "capacitor", "parasitic capacitance" or "gate capacitance". In addition, for example, the word "a pair of electrodes" of "capacitor" can be transformed into words such as "a pair of conductors", "a pair of conductive regions" or "a pair of regions". The electrostatic capacitance value can be, for example, more than 0.05fF and less than 10pF. In addition, for example, it can also be more than 1pF and less than 10μF.

[0356] In addition, in this specification, etc., a transistor includes three terminals called a gate (also called a gate terminal, a gate region, or a gate electrode), a source (also called a source terminal, a source region, or a source electrode), and a drain (also called a drain terminal, a drain region, or a drain electrode). In addition, the transistor has a region (also called a channel formation region) where a channel is formed between the drain and the source. In the transistor, current can flow between the source and the drain through the channel formation region. Note that the channel formation region is the region where the current mainly flows. The gate is a control terminal that controls the amount of current flowing in the channel formation region between the source and the drain. The two terminals used as the source or the drain are the input and output terminals of the transistor.

[0357] Depending on the conductivity type of the transistor (n-channel or p-channel) and the potential applied to the three terminals of the transistor, one of the two input and output terminals is used as a source and the other as a drain. For example, when the direction of the current changes during circuit operation, the function as a source and the function as a drain are sometimes swapped. Therefore, in this specification, etc., the words "source" and "drain" can be interchanged. In this specification, etc., when describing the connection relationship of the transistor, the expression "one of the source and the drain" (the first electrode or the first terminal) or "the other of the source and the drain" (the second electrode or the second terminal) is used.

[0358] In addition, depending on the structure of the transistor, a back gate is sometimes included in addition to the above three terminals. In this case, in this specification, one of the gate and the back gate of the transistor is sometimes referred to as the first gate, and the other of the gate and the back gate of the transistor is sometimes referred to as the second gate. In addition, in a transistor, the words "gate" and "back gate" can sometimes be interchanged. In addition, when the transistor includes more than three gates, in this specification, for example, each gate is sometimes referred to as the first gate, the second gate, or the third gate.

[0359] In this specification, etc., a multi-gate structure transistor having more than two gate electrodes can be used as a transistor. The multi-gate structure transistor has a structure in which multiple transistors are connected in series because the channel forming regions are connected in series. Therefore, the multi-gate structure transistor can reduce the off-state current and can improve the voltage resistance of the transistor (improve reliability). Alternatively, in a multi-gate structure transistor, when the transistor operates in the saturation region, even if the voltage between the drain and the source changes, the change in the current between the drain and the source is not too large, so that a voltage-current characteristic with a flat tilt angle can be obtained. A transistor with a voltage-current characteristic with a flat tilt angle can realize an ideal current source circuit or an active load with an extremely high resistance value. As a result, a transistor with a voltage-current characteristic with a flat tilt angle can realize, for example, a differential circuit or a current mirror circuit with good characteristics.

[0360] In addition, in this specification, etc., a case where a circuit diagram shows a circuit element sometimes includes a case where the circuit element has a plurality of circuit elements. For example, a case where a circuit diagram shows a resistor includes a case where two or more resistors are electrically connected in series. In addition, for example, a case where a circuit diagram shows a capacitor includes a case where two or more capacitors are electrically connected in parallel. In addition, for example, a case where a circuit diagram shows a transistor includes a case where two or more transistors are electrically connected in series and the gates of each transistor are electrically connected to each other. Similarly, for example, a case where a circuit diagram shows a switch includes a case where the switch has two or more transistors, and the two or more transistors are electrically connected in series or in parallel and the gates of each transistor are electrically connected to each other.

[0361] In addition, in this specification, etc., a "node" may be referred to as a "terminal", "wiring", "electrode", "conductive layer", "conductor" or "impurity region", etc., for example, depending on a circuit structure or a device structure. In addition, for example, a "terminal" or "wiring" may be referred to as a "node".

[0362] In addition, in this specification, etc., "voltage" and "potential" can be appropriately interchanged. "Voltage" refers to the potential difference from a reference potential. For example, when the reference potential is a ground potential (ground potential), "voltage" can also be referred to as "potential". The ground potential does not necessarily mean 0V. In addition, potential is relative. That is, for example, the potential supplied to the wiring, the potential applied to the circuit, or the potential output from the circuit also changes according to the change of the reference potential.

[0363] In addition, in this specification, etc., words such as "high-level potential (also referred to as "H potential" or "H")" or "low-level potential (also referred to as "L potential" or "L")" do not mean specific potentials. For example, in the case where two wirings are both recorded as "wirings used to supply high-level potentials", the high-level potentials supplied by the two wirings may be different from each other. Similarly, in the case where two wirings are both recorded as "wirings used to supply low-level potentials", the low-level potentials supplied by the two wirings may be different from each other.

[0364] In addition, in this specification, "electric current" refers to the migration phenomenon (conduction) of electric charge. For example, the record of "conduction of a positively charged body" can be replaced by the record of "conduction of a negatively charged body in the opposite direction". Therefore, in this specification, unless otherwise stated, "electric current" refers to the migration phenomenon (conduction) of electric charge when carriers migrate. Here, as carriers, for example, electrons, holes, anions, cations or complex ions can be cited. In addition, the carriers are different according to the system through which the current flows (for example, semiconductors, metals, electrolytes or vacuum, etc.). In addition, for example, the "direction of electric current" in wiring, etc. is the direction of migration of positive carriers, which is recorded as a positive current amount. In other words, the direction of migration of negative carriers is opposite to the direction of electric current, and is recorded as a negative current amount. Therefore, in this specification, etc., in the absence of special instructions, about the positive and negative of the electric current (or the direction of the electric current), for example, the record of "the electric current flows from element A to element B" can be replaced by the record of "the electric current flows from element B to element A". Furthermore, for example, a description such as “current is input to element A” may be replaced with a description such as “current is output from element A”.

[0365] In addition, in this specification, etc., ordinal numbers such as "first", "second" or "third" are added to avoid confusion between constituent elements. Therefore, the ordinal numbers do not limit the number of constituent elements. In addition, the ordinal numbers do not limit the order of the constituent elements. For example, in this specification, etc., a constituent element with the number "first" in one embodiment may be regarded as a constituent element with the number "second" in other embodiments or claims. In addition, for example, in this specification, etc., a constituent element with the number "first" in one embodiment may be omitted in other embodiments or claims.

[0366] In addition, in this specification, etc., for the sake of convenience, words such as "upper", "lower", "above" or "below" that indicate configuration are sometimes used to illustrate the positional relationship of constituent elements with reference to the drawings. In addition, the positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, the words indicating configuration described in this specification, etc. are not limited, and the words and phrases can be appropriately replaced according to the circumstances. For example, by rotating the direction of the illustrated drawing by 180 degrees, the expression "the insulator located on the top surface of the conductor" can be replaced with "the insulator located on the bottom surface of the conductor". In addition, by rotating the direction of the illustrated drawing by 90 degrees, the expression "the insulator located on the top surface of the conductor" can be replaced with "the insulator located on the left (or right) of the conductor".

[0367] In addition, the words "above" or "below" are not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, the expression "electrode B on insulating layer A" does not necessarily mean that electrode B is formed on insulating layer A in direct contact, but may also include the case where other components are included between insulating layer A and electrode B.

[0368] In addition, in this specification, for example, words such as "row" or "column" are sometimes used to describe components configured in a matrix and their positional relationship. In addition, the positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, for example, words such as "row" or "column" are not limited to the words and phrases described in this specification, and can be appropriately replaced according to the situation. For example, by rotating the direction of the drawing by 90 degrees, the expression of "row direction" can sometimes be replaced by "column direction".

[0369] In addition, in this specification, for example, the word "overlap" is not limited to the state of the stacking order of the components. For example, the expression "electrode B overlapping with the insulating layer A" does not necessarily mean that the electrode B is formed on the insulating layer A. The expression "electrode B overlapping with the insulating layer A" may also include, for example, the state in which the electrode B is formed under the insulating layer A or the state in which the electrode B is formed on the right side (or left side) of the insulating layer A.

[0370] In addition, in this specification, the words "adjacent" or "close to" are not limited to the case where the components are in direct contact. For example, the expression "electrode B adjacent to insulating layer A" does not necessarily mean that the insulating layer A and the electrode B are formed in direct contact, and may also include the case where other components are included between the insulating layer A and the electrode B.

[0371] In addition, in this specification, etc., depending on the situation, for example, words such as "film" or "layer" may sometimes be interchanged with each other. For example, the word "conductive layer" may sometimes be replaced by the word "conductive film". For example, the word "insulating film" may sometimes be replaced by the word "insulating layer". In addition, depending on the situation, for example, other words may sometimes be used instead of words such as "film" or "layer". For example, the words such as "conductive layer" or "conductive film" may sometimes be replaced by the word "conductor". In addition, the word "conductor" may sometimes be replaced by words such as "conductive layer" or "conductive film". For example, the words such as "insulating layer" or "insulating film" may sometimes be replaced by the word "insulator". In addition, the word "insulator" may sometimes be replaced by words such as "insulating layer" or "insulating film".

[0372] Note that, for example, in this specification, the words such as "electrode", "wiring" or "terminal" do not functionally limit their constituent elements. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, the words such as "electrode" or "wiring" also include, for example, a case where a plurality of "electrodes" or "wirings" are formed as one. In addition, for example, sometimes a "terminal" is used as a part of a "wiring" or "electrode", and vice versa. Furthermore, the word "terminal" also includes, for example, a case where a plurality of "electrodes", "wiring" or "terminals" are formed as one. Therefore, for example, an "electrode" can be a part of a "wiring" or a "terminal". In addition, for example, a "terminal" can be a part of a "wiring" or an "electrode". In addition, for example, the words such as "electrode", "wiring" or "terminal" are sometimes replaced with words such as "region".

[0373] In this specification, etc., depending on the situation, for example, the words such as "wiring", "signal line" or "power line" can sometimes be interchanged with each other. For example, the word "wiring" can sometimes be converted to the word "signal line". In addition, for example, the word "wiring" can sometimes be converted to the word "power line". Vice versa, for example, the word "signal line" or "power line" can sometimes be converted to the word "wiring". In addition, for example, the word "power line" can sometimes be converted to the word "signal line". Vice versa, for example, the word "signal line" can sometimes be converted to the word "power line". In addition, depending on the situation, for example, the word "potential" applied to the wiring can be converted to the word "signal". Vice versa, for example, the word "signal" can sometimes be converted to the word "potential".

[0374] In addition, in this specification, etc., a "switch" includes a plurality of terminals and has a function of switching (selecting) conduction or non-conduction between the terminals. For example, when a switch includes two terminals and conduction between the two terminals occurs, the switch is in a "conducting state" or "open state". In addition, when non-conduction between the two terminals occurs, the switch is in a "non-conducting state" or "closed state". Note that "the switch is switched to one of the conducting state and the non-conducting state" or "the switch maintains one of the conducting state and the non-conducting state" is sometimes referred to as "controlling the conducting state".

[0375] That is, a switch refers to a component that has the function of controlling whether or not to allow current to flow. Alternatively, a switch refers to a component that has the function of selecting and switching the current path. As a switch, for example, an electric switch or a mechanical switch can be used. In other words, a switch is not limited to a specific component as long as it can control current.

[0376] In addition, as a type of switch, there is a switch that is normally in a non-conducting state and becomes a conducting state by controlling the conducting state, and this switch is sometimes called an "A contact". In addition, there is a switch that is normally in a conducting state and becomes a non-conducting state by controlling the conducting state, and this switch is sometimes called a "B contact".

[0377] As an electric switch, for example, there are transistors (such as bipolar transistors or MOS transistors), diodes (such as PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM: Metal Insulator Metal) diodes, metal-insulator-semiconductor (MIS: Metal Insulator Semiconductor) diodes, or diode-connected transistors, etc.), or logic circuits combining these elements, etc. When a transistor is used only as a switch, there is no particular restriction on the polarity (conductivity type) of the transistor.

[0378] As a mechanical switch, for example, a switch using MEMS (micro-electromechanical system) technology can be cited. This switch has a mechanically movable electrode, and a conductive state or a non-conductive state is selected by moving the electrode.

[0379] In this specification, etc., the "channel length" of a transistor sometimes refers to, for example, the distance between the source and the drain in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on state) and the gate overlap, or the distance between the source and the drain in the region where the channel is formed.

[0380] In addition, in this specification, etc., the "channel width" of a transistor sometimes refers to, for example, the length of the opposing portions of the source and drain in the region where the semiconductor (or the portion of the semiconductor through which current flows when the transistor is in an on state) and the gate overlap, or the length of the opposing portions of the source and drain in the region where the channel is formed.

[0381] In this specification, for example, the words "substrate", "wafer" or "bare chip" do not limit the functions of the components. For example, the words "substrate", "wafer" or "bare chip" may be interchanged depending on the situation.

[0382] In this specification, "parallel" does not necessarily mean completely parallel. Therefore, the word "parallel" can be appropriately replaced by words such as "almost parallel", "roughly parallel" or "substantially parallel". "Parallel", "almost parallel", "roughly parallel" or "substantially parallel" can also include, for example, a state in which two straight lines or planes are configured at an angle of more than -5° and less than 5°. Alternatively, it can also include a state in which two straight lines or planes are configured at an angle of more than -10° and less than 10°. Alternatively, it sometimes includes a state in which two straight lines or planes are configured at an angle of more than -30° and less than 30°. Therefore, "parallel" sometimes means "parallel or roughly parallel". In addition, "vertical" does not necessarily mean completely vertical. Therefore, the word "vertical" can be appropriately replaced by words such as "almost vertical", "roughly vertical" or "substantially vertical". "Vertical", "almost vertical", "roughly vertical" or "substantially vertical" can also include, for example, a state in which two straight lines or planes are configured at an angle of more than 85° and less than 95°. Alternatively, it can also include a state in which two straight lines or planes are configured at an angle of more than 80° and less than 100°. Alternatively, it may include a state where two straight lines or planes are arranged at an angle of 60° or more and 120° or less. Therefore, “perpendicular” may mean, for example, “perpendicular or substantially perpendicular”.

[0383] In addition, in this specification, etc., "high consistency or approximately consistency" means that the height from a reference plane (for example, a flat surface such as a substrate surface) is equal when viewed in cross section. For example, in the manufacturing process of a semiconductor device, a flattening treatment is sometimes performed to expose the surface of a single layer or multiple layers. In this case, the height of the processed surface treated by the flattening treatment is equal from the reference plane. However, depending on the processing device, processing method or material of the processed surface used in the flattening treatment, the heights of the multiple layers of the processed surface are sometimes not completely equal. In this specification, etc., this situation is also regarded as "high consistency or approximately consistency". For example, the following situation is also referred to as "high consistency or approximately consistency": including two layers (here, the first layer and the second layer) with different heights from the reference plane, wherein the difference between the top surface height of the first layer and the top surface height of the second layer is less than 20nm.

[0384] In this specification, etc., "ends are aligned or roughly aligned" means that at least a portion of the outline of each layer in the stack overlaps when viewed from above. For example, it refers to a case where the upper layer and the lower layer are processed by the same mask pattern or a portion of the same mask pattern in the manufacturing process of the semiconductor device. However, strictly speaking, sometimes the outlines do not overlap and the outline of the upper layer is located inside the end of the lower layer or the outline of the upper layer is located outside the end of the lower layer. In this specification, etc., these cases are also included in the case of "ends are roughly aligned".

[0385] In this specification, for example, regarding count values ​​or measurement values, objects, methods, and phenomena that can be converted into count values ​​or measurement values, when mentioning "same", "identical", "equal", or "uniform" (including synonyms of these words), unless otherwise stated, an error of ±20% is included.

[0386] In this specification, etc., impurities of a semiconductor refer to substances other than the main components constituting the semiconductor. For example, an element with a concentration lower than 0.1 atomic% is an impurity. When a semiconductor contains impurities, for example, the defect state density in the semiconductor may increase, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components of the oxide semiconductor. In particular, for example, there are hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, or nitrogen. For example, sometimes oxygen vacancies (also called V O : oxygen vacancy) is formed in the oxide semiconductor.

[0387] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified, for example, into oxide insulators, oxide conductors (including transparent oxide conductors) and oxide semiconductors (Oxide Semiconductor, also referred to as OS). For example, in the case where a metal oxide is used for a semiconductor including a channel formation region of a transistor, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when a metal oxide is used as a material capable of constituting a channel formation region of a transistor including at least one of an amplification function, a rectification function and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. In addition, an OS transistor can be referred to as a transistor including a metal oxide or an oxide semiconductor.

[0388] In addition, in this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride).

[0389] In addition, arrows indicating the X direction, Y direction, and Z direction are sometimes attached in the drawings and the like according to this specification. In this specification and the like, the "X direction" refers to the direction along the X axis, and sometimes the positive direction and the negative direction are not distinguished except for the cases clearly indicated. The same is true for the "Y direction" and the "Z direction". In addition, the X direction, the Y direction, and the Z direction are directions that intersect each other. Specifically, the X direction, the Y direction, and the Z direction are directions that are orthogonal to each other. In this specification and the like, sometimes one of the X direction, the Y direction, and the Z direction is referred to as the "first direction". In addition, sometimes the other one is referred to as the "second direction". In addition, sometimes the remaining one is referred to as the "third direction".

[0390] [Explanation of symbols]

[0391] 110: register, 120: scan trigger, 121: selector, 122: trigger, 130: data holding circuit, 131: storage circuit, 132: transistor, 133: transistor, 134: transistor, 135: capacitor, 136: capacitor, 20: element layer, 30: element layer, 30a: element layer, 30b: element layer, BK: signal, RE: signal, SE: signal, CLK: signal, D: terminal, SD: terminal, Q: terminal, SD_IN: terminal, Df: input terminal, Qf: output terminal, CL: wiring, SN: node, T1: time, T2: time, T3: time, T4: time, T5: time, T6: time, T7: time, T8: time, D1: data, D2: data, D3: data, D4: data, D5: data, D6: data, D7: data, D8: data, 100: computing device, 101: control unit, 102: CPU core, 103: register unit, 105: register bank, 106: general register, Ta: time, Tb: time, Tc: time, 550: transistor, 37: transistor, 38: capacitor, 35: through hole, 36: through hole, 32: memory cell, 33: functional element, 311: substrate, 316: conductor, 315: insulator, 313: semiconductor region, 314a: low resistance region, 314b: low resistance region, 320: insulator, 322: insulator, 324: insulator, 326: insulator, 328: conductor, 330: conductor, 350: insulator, 352: insulator , 354: insulator, 356: conductor, 440: insulator, 410: conductor, 480: insulator, 280: insulator, 283: insulator, 290: opening, 490: opening, 415: conductor, 430: insulator, 420: conductor, 240: conductor, 230: oxide semiconductor, 250: insulator, 260: conductor, 230i: region, 230na: region, 230nb: region, 34: functional element, 39: connection portion, 431: insulator

Claims

1. A semiconductor device comprising: Trigger circuit; as well as Storage circuits, The storage circuit includes a first transistor, a second transistor, a first capacitor and a second capacitor. One of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the second transistor, one terminal of the first capacitor, and one terminal of the second capacitor, the other of the source and the drain of the first transistor is electrically connected to the output terminal of the trigger circuit, The other of the source and the drain of the second transistor is electrically connected to the input terminal of the trigger circuit, The semiconductor device further includes a substrate, a first insulator and a second insulator. The first insulator is disposed on the substrate, The second insulator is disposed on the first insulator, The first insulator includes a first opening and a second opening extending in a direction perpendicular to the surface of the substrate. The second insulator includes a third opening and a fourth opening extending in a direction perpendicular to the surface of the substrate. The trigger circuit is arranged on the substrate, At least a portion of each of the first capacitor and the second capacitor is disposed in the first opening and the second opening, Furthermore, at least a portion of each of the first transistor and the second transistor is disposed in the third opening and the fourth opening.

2. The semiconductor device according to claim 1, wherein at least a portion of the dielectric layer of each of the first capacitor and the second capacitor is disposed along a side wall of each of the first opening and the second opening, Furthermore, at least a portion of the semiconductor layer including the channel formation region of each of the first transistor and the second transistor is provided along the side walls of each of the third opening and the fourth opening.

3. The semiconductor device according to claim 2, The semiconductor layer includes an oxide semiconductor.

4. A computing device, comprising: The semiconductor device according to any one of claims 1 to 3; as well as Control Department, wherein the control unit has a function of generating a signal for controlling the operation of the semiconductor device, Furthermore, the semiconductor device has: a function of controlling the conductive state or non-conductive state of the first transistor to save the data held by the trigger circuit in the storage circuit; and a function of controlling the conductive state or non-conductive state of the second transistor to load the data held by the storage circuit into the trigger circuit.

5. The computing device according to claim 4, wherein the semiconductor device comprises a plurality of the memory circuits, And the semiconductor device has the following function: when switching tasks, the first data held by the flip-flop circuit is saved in any one of the plurality of storage circuits, and the second data held by any one of the plurality of storage circuits is loaded into the flip-flop circuit.

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