Method for manufacturing optical semiconductor element

Abstract

Provided is a method for manufacturing an optical semiconductor element that suppresses wafer breakage due to grinding and has good yield. This method for manufacturing an optical semiconductor element comprises: a step for forming a laminate of compound semiconductor layers on one main surface of a compound semiconductor substrate having cleavage properties; and a grinding step for grinding the other main surface of the substrate, in which the skewness (Ssk) in the surface roughness measurement of the ground surface of the substrate immediately after the completion of the grinding step is set to be positive.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing an optical semiconductor element including a step of grinding a substrate of a compound semiconductor having cleavage properties, for an optical semiconductor element such as a light emitting element or a light receiving element. Background Art

[0002] Light-emitting elements and light-receiving elements obtained by using an InP substrate, which is a substrate of a compound semiconductor having cleavage like a GaAs substrate and is widely used in optical fibers, various infrared sensors, etc. by emitting or receiving infrared rays, are widely used.

[0003] For example, Patent Document 1 discloses that since an InP substrate is brittle, if the InP substrate is excessively ground to less than 200 μm, for example, 150 μm or less, breakage may occur.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2018-6495 Summary of the invention

[0007] Problem that the invention aims to solve

[0008] As infrared light-emitting and light-receiving devices are miniaturized, it is required to reduce the overall thickness of the components. The substrate occupies the vast majority of the thickness of the component, so if the substrate thickness is reduced, the component thickness will be reduced. However, during epitaxial growth and subsequent electrode formation, if the substrate does not have a sufficient thickness of, for example, more than 300 μm, the warping becomes larger or it is easy to break. Therefore, in order to reduce the thickness of the substrate, after using a sufficiently thick substrate, it is necessary to grind the substrate in a subsequent process before cutting into individual chips to reduce the thickness to less than 200 μm.

[0009] As described in Patent Document 1, cleavable compound semiconductor substrates such as InP substrates are very brittle and easily damaged during thinning by grinding. Therefore, an object of the present invention is to provide a method for manufacturing optical semiconductor elements with good yield while suppressing wafer damage caused by grinding.

[0010] Solutions for solving problems

[0011] The present inventors have conducted intensive studies to achieve the above-mentioned objects, and as a result, have completed the present invention described below.

[0012] That is, the gist of the present invention is as follows.

[0013] (1) A method for manufacturing an optical semiconductor element, comprising:

[0014] A step of forming a laminate of compound semiconductor layers on one main surface of a cleavable compound semiconductor substrate; and

[0015] A grinding step of grinding the other main surface of the substrate, wherein:

[0016] The skewness (Ssk) in the surface roughness measurement of the ground surface of the substrate immediately after the grinding step is completed is set to be positive.

[0017] (2) The method for manufacturing an optical semiconductor element according to (1) above, wherein a maximum height (Sz) of the ground surface in surface roughness measurement immediately after the grinding step is completed is set to 1.9 μm or more.

[0018] (3) The method for manufacturing an optical semiconductor element according to (1) or (2) above, wherein in the grinding step, only a medium-sized grindstone having a grit size of #800 to #2000 is used.

[0019] (4) The method for producing an optical semiconductor element according to any one of (1) to (3) above, wherein the compound semiconductor substrate is an InP substrate.

[0020] (5) The method for manufacturing an optical semiconductor element according to any one of (1) to (4) above, further comprising, after the grinding step:

[0021] an etching step of etching the ground surface; and

[0022] A back electrode forming step is to form an electrode on the ground surface and perform heat treatment.

[0023] (6) The method for manufacturing an optical semiconductor element according to (5) above, wherein the etching step comprises:

[0024] A first etching process using a diluted sulfuric acid-hydrogen peroxide solution; and

[0025] The second etching step uses a mixed solution of hydrochloric acid and acetic acid.

[0026] Effects of the Invention

[0027] According to the present invention, it is possible to provide a method for manufacturing an optical semiconductor element with a good yield while suppressing wafer breakage due to grinding. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 This is a schematic diagram of a method for manufacturing an optical semiconductor element.

[0029] Figure 2This is a diagram for explaining the outer peripheral shape of the substrate used in the present invention.

[0030] Figure 3 It is a figure which shows the roughness profile of the Example of this invention. DETAILED DESCRIPTION

[0031] Before describing the embodiments of the present invention, the following aspects will be described.

[0032] <Compound semiconductor substrate with cleavage properties>

[0033] The compound semiconductor substrate with cleavage in this embodiment (hereinafter sometimes abbreviated as "substrate") is a compound semiconductor substrate with a cubic zinc blende crystal structure, and can be any one of GaAs, InP, GaP, InAs, GaSb, InSb, and ZnSe. From the perspective of ease of manufacturing optical semiconductor elements, it is preferably GaAs or InP. Compared with GaAs substrates, InP substrates are more easily broken, so the present invention is particularly useful when InP is used.

[0034] <Surface Roughness Measurement>

[0035] The surface roughness parameters such as skewness (Ssk) and maximum height (Sz) based on the surface roughness measurement can be measured using a non-stylus type shape analysis laser microscope (VK-X1000 / 1100 manufactured by KEYENCE Co., Ltd.) The surface roughness parameters are based on ISO25178-2:2012.

[0036] Below, refer to Figure 1 , a method for manufacturing an optical semiconductor element according to the present invention is described in detail.

[0037] <Substrate>

[0038] Figure 1 The substrate 100 used in S10 is a cleavage-type compound semiconductor substrate as described above, which is a compound semiconductor substrate having a cubic zinc blende crystal structure. The conductivity type and impurity concentration of the substrate 100 are not particularly limited. The thickness of the substrate 100 and the diameter of the substrate 100 can be selected from commonly commercially available substrates. For example, the thickness of the substrate 100 before grinding is 300μm to 2mm, and the diameter of the substrate 100 is 2 to 6 inches. The surface orientation and deviation angle of the substrate 100 are not particularly limited. The substrate 100 can be a double-sided mirror or a single-sided mirror, and a double-sided mirror substrate is preferably used.

[0039] Here, for Figure 1 The outer peripheral shape of the substrate 100 shown in S10 is used Figure 2In general, the peripheral shape of the substrate 100 (also referred to as the inclined surface shape) may be as follows: when the periphery of the substrate 100 is observed from the direction perpendicular to the cross section of the substrate 100, a straight line inclined relative to the main surface (also referred to as the main surface) is formed by chamfering, a curved line is formed, and a combination of a straight line and a curved line inclined relative to the main surface is formed. Furthermore, in the vertical cross-sectional view, the straight line inclined is formed on both the surface side 100A and the back side 100B, and is formed only on one side. The shape formed by chamfering has Figure 2 In the case where the curved portion 100a shown in FIG. 1 is not included, it is preferable for the purpose of preventing damage, sliding during crystal growth, etc., and in order to alleviate the impact with the grindstone and prevent damage in the initial stage of the back grinding step S40, it is also preferable that the shape formed by chamfering has the straight portion 100b inclined with respect to the main surface only on the back side 100B. Similarly, when the shape formed by chamfering has straight portions inclined with respect to the main surface on both the front side 100A and the back side 100B, the length of the straight portion inclined with respect to the main surface is preferably longer on the back side 100B than on the front side 100A.

[0040] <Epitaxial Growth Step S20>

[0041] Back to Figure 1 . In the epitaxial growth step S20, a stack 110 of compound semiconductor layers having a composition capable of epitaxial growth is formed on the surface side 100A of the above-mentioned substrate 100. The stacked compound semiconductor layers may be of a known composition known to be formed on the substrate according to the material of the substrate 100, and are preferably lattice-matched systems with a small lattice mismatch. It should be noted that even in the case of a large lattice mismatch, epitaxial growth can be performed by forming an appropriate buffer layer on the substrate. On a GaAs substrate, in the epitaxial growth step S20, for example, a stack of AlGaAs-based semiconductor layers, a stack of AlInGaP-based semiconductor layers, and a stack mixed with these layers are formed. On an InP substrate, in the epitaxial growth step S20, for example, a stack of InGaAs-based semiconductor layers, a stack of InGaAsP-based semiconductor layers, a stack of InGaAlAs-based semiconductor layers, and a stack mixed with these layers are formed.

[0042] -Thickness and Warpage-

[0043] The thickness of the laminate 110 is preferably 1 to 20 μm. The substrate 100 is warped due to the difference in lattice constant and thermal expansion coefficient between the substrate 100 and the laminate 110. Therefore, the substrate 100 on which the laminate 110 is formed contains stress inside, and is therefore more likely to be broken during grinding than the substrate 100 alone.

[0044] In the top surface electrode forming step S30, the back grinding step S40, the etching step S50, the back electrode forming step S60, and the singulation step S70 described later, if the warping of the substrate 100 is too large, the substrate will be damaged when it is fixed to the base by suction in each step to be flat. Therefore, the thickness of the stacked body 110 in the epitaxial growth step S20 is preferably such a size and shape that the stacked body 110 is not damaged before the grinding in the back grinding step S40 that follows.

[0045] <Top Surface Electrode Forming Step S30>

[0046] As the top surface electrode 130, it is sufficient to use an appropriate known electrode according to the layer forming the top surface electrode 130. As the metal, it is preferably a combination of a noble metal such as Au (gold) and Pt (platinum) and a metal such as Ti (titanium), Zn (zinc), and Ni (nickel). For example, Ti (titanium), Pt (platinum), and Au (gold) can be used in a stacked manner. Regarding the formation of the top surface electrode 130, in addition to a stripping method in which a metal layer that becomes the top surface electrode 130 is formed by evaporation, sputtering, etc. after forming a top surface electrode pattern in advance using a photoresist, and then the photoresist is removed, a method in which a top surface electrode pattern is formed using a photoresist after the metal layer is formed, and the useless metal layer is removed by etching, etc. can also be used. As an example, the diagram shown in the figure Figure 1 In the embodiment, the top surface electrode 130 is formed in a dot shape.

[0047] <Back grinding step S40>

[0048] In the back grinding step S40 of the present invention, the back grinding is performed so that the skewness (Ssk) in the surface roughness measurement of the ground surface immediately after the grinding is completed is positive. In addition, it is preferred that the maximum height (Sz) in the surface roughness measurement of the ground surface immediately after the back grinding step S40 is 1.9 μm or more, and it is preferred that only a medium grindstone with a particle size of #800 to #2000 is used in the grinding step S40.

[0049] It is believed that the reason why the substrate 100 does not break during grinding by such operation is that, in the case of a surface with a positive skewness (Ssk) and many fine peaks, the cutting slag of the substrate 100 generated during grinding can be discharged from the back of the substrate 100 and the grindstone through the gaps between the peaks, so the cutting slag does not accumulate between the back of the substrate 100 and the grindstone, but in the case of a surface with a negative skewness (Ssk) and many fine valleys, the cutting slag cannot be discharged from the back of the substrate 100 and the grindstone and accumulates, which may apply a load in the direction of valley expansion. When the maximum height (Sz) is large, it is easy to ensure the discharge path of the cutting slag, so it is preferred.

[0050] In addition, it can be considered that: when only a medium grindstone with a particle size of #800 to #2000 is used, there is a discharge path for the cutting slags of the grindstone itself, and it is easy to form a state where the skewness (Ssk) is positive as described above, so it is preferred. As a grindstone, if a finishing grindstone with a particle size of #3000 or later is used, although it becomes flat, it is easy to form a state where the skewness (Ssk) is negative, so it is easy to be damaged. The thickness of the substrate 160 after back grinding is preferably less than 200μm. The thickness of the substrate 160 after back grinding is preferably set to 60 to 180μm.

[0051] - Fixing of the substrate on the grinding base -

[0052] In order to grind the back side of the substrate, the surface side of the substrate needs to be fixed to the grinding base. On the surface side of the substrate, in addition to the stack of semiconductor layers, a top surface electrode and the like are also formed, and it is necessary to fix them while preventing them from being damaged. In order to prevent damage, it is preferred to perform one or more of the following operations on the surface side of the substrate:

[0053] · Apply resist to the epitaxial surface as a protective film;

[0054] ·Paste UV curing film;

[0055] A support plate having a shape similar to that of the base plate and capable of being peeled off after bonding is attached.

[0056] Regarding fixation to the grinding base, there are cases where suction fixation is performed, fixation to a plate such as ceramics using resin (wax), and the like.

[0057] -Use of slurry-

[0058] During grinding, preferably, a grinding fluid is circulated to the surface of the compound semiconductor substrate to be ground. The grinding fluid not only discharges the cutting slag outside the system, but also cools the ground surface. In general grinding and polishing, abrasive grains and abrasives are sometimes mixed into the grinding fluid, but in the present invention, if abrasive grains and abrasives are included, clogging and damage may occur. Therefore, as the grinding fluid, water or pure water is preferably used, and a surfactant may be mixed.

[0059] - Post-grinding treatment -

[0060] After grinding, the substrate is released from the grinding base. The resist, UV curing sheet, support plate, etc. provided on the surface side of the substrate to prevent damage to the substrate may be maintained until the subsequent steps are completed, or may be removed immediately after the back grinding step S40.

[0061] <Etching Step S50>

[0062] After the back grinding step S40, impurities such as oxides are sometimes attached to the grinding surface 165. If an electrode is formed directly, the contact resistance sometimes becomes high or the electrode is easily peeled off. Therefore, the grinding surface 165 after the back grinding step S40 is preferably lightly etched to remove impurities. The etching liquid can be appropriately selected according to the type of substrate. As the etching amount, for example, the thickness is 1 to 100 nm. The portion in which the skewness (Ssk) is positive and a protrusion is formed is preferentially etched in the etching step S50, so that the fragmentation in the subsequent steps (back electrode formation step S60, etc.) can be suppressed. If the case of using an InP substrate is used as an example, the etching conditions in the etching step S50 preferably include: a first etching step using a diluted sulfuric acid hydrogen peroxide aqueous solution, and a second etching step using a mixed solution of hydrochloric acid and acetic acid.

[0063] <<First etching step for removing impurities>>

[0064] It is preferred to use a diluted sulfuric acid hydrogen peroxide solution, and the volume ratio of sulfuric acid (96% concentration) to hydrogen peroxide solution (30.0% to 35.5% concentration, also known as hydrogen peroxide) can be set in the range of 1:10 to 10:1, for example, preferably 1:1. When only sulfuric acid and hydrogen peroxide are mixed, the etching rate is fast, so it is easy to prevent excessive etching when the concentration is dilute, and it is further diluted with pure water to more than 5 times and less than 15 times. For example, sulfuric acid: hydrogen peroxide: pure water is preferably set to 1:1:7 in terms of volume ratio.

[0065] <<Second etching step for removing the altered layer>>

[0066] It is preferred to use a mixed solution of hydrochloric acid and acetic acid. The volume ratio of hydrochloric acid (concentration of 35-37%) to acetic acid (concentration of 99.7%) can be set in the range of 1:10 to 10:1, for example, preferably 1:1. When only hydrochloric acid and acetic acid are mixed, the etching rate is fast. Therefore, it is easy to prevent excessive etching when the concentration is dilute, and it is further diluted with pure water to more than 1 times and less than 5 times. For example, the volume ratio of hydrochloric acid: acetic acid: pure water is preferably set to 1:1:2.

[0067] <Back electrode forming step S60>

[0068] As the back electrode 190, it can be appropriately selected according to the type of substrate on which the back electrode 190 is formed. For example, for an InP substrate, metals such as Au (gold), Al (aluminum), Pd (palladium), Ge (germanium), Ni (nickel) and Mo (molybdenum) are preferably used. For example, an AuGe alloy can be used. The back electrode 190 can be formed on the entire surface or a portion of the back side of the substrate. After the back electrode is formed, it is preferably subjected to ohmic heat treatment at a temperature and time suitable for the top surface electrode 130 and the back electrode 190. In the ohmic heat treatment, considering the heat resistance of protective agents such as resists on the surface side, it is preferably carried out after removing the resists, etc. as needed.

[0069] <Single-piece process S70>

[0070] As the singulation step S70, a blade cutter, a laser cutter, a scriber, etc. can be used. The chip size can be set to 200 μm to 3000 μm on one side. The chip shape is arbitrary, but for a substrate with cleavage, a square or rectangular shape is preferably used as a shape that is easy to singulate.

[0071] <Other steps (forming the terrace, roughening the surface, forming a protective film)>

[0072] Before or after the epitaxial growth step S20 and any subsequent steps, any of a mesa formation step, a roughening step, and a protective film formation step may be included. The mesa formation step is a step of etching the stack of compound semiconductor layers at a predetermined portion to be separated in the singulation step S70, the roughening step is a step of roughening the surface through which light mainly passes by etching, and the protective film formation step is a step of forming a dielectric film such as SiO2 on the surface of the element other than the electrode to prevent element degradation caused by external gas or to form a film to suppress surface leakage current.

[0073] Hereinafter, the present invention will be described in more detail using examples, but the present invention is not limited to the following examples at all.

[0074] Example

[0075] <Example>

[0076] An n-type InP substrate (3 inches, thickness: 625 μm, carrier density: 3.0×10 18 / cm 3) are sequentially formed on the substrate to form a stacked body that functions as a light receiving element in an optical semiconductor element. The total thickness of the stacked body is 4.4 μm.

[0077] Next, a mask is formed on the cap layer and it is etched, and then a SiN film (thickness: 0.1 μm) is formed by CVD, and patterning is performed by photolithography using a resist, and Zn is diffused by MOCVD, so that Zn diffuses from the cap layer to the undoped InP window layer and the undoped InGaAs light absorption layer.

[0078] Thereafter, a top surface electrode (Ti (titanium) / Pt (platinum) / Au (gold)) was formed on the cap layer by a vapor deposition method so as to have an opening portion to be a light receiving portion.

[0079] Then, after forming a protective film on the side where the top surface electrode is formed by using a photoresist, an ultraviolet curing tape is pasted, and the side where the top surface electrode is formed is adsorbed and fixed to the grinding base of the grinder by means of the ultraviolet curing tape. After that, the circular grindstone is pushed to the back side of the InP substrate by a load while circulating pure water, and the thickness of the back side of the InP substrate is ground from 625μm to 150μm by the rotation of the substrate and the rotation of the circular grindstone. The grinding uses a manual grinder (DAG810) manufactured by DISCO, and the grinding conditions are as follows: the particle size of the grindstone is #2000 (manufactured by DISCO, GF01-SD2000-BR440-100), the spindle is 2000rpm, the chuck table is 97rpm, and the grinding speed is 1.50μm / sec. Thereafter, when the suction fixation to the grinding base was released, the presence or absence of wafer damage was visually checked, and the wafer damage rate was evaluated for 10 wafers produced under the same conditions.

[0080] The surface roughness of any nine points of the ground surface immediately after grinding was measured using a shape analysis laser microscope (VK-X1000 / 1100 manufactured by KEYENCE) to obtain the average value. The measurement conditions were:

[0081] Lens magnification: 150 times

[0082] Pixel count: 2048×1536

[0083] Use Gaussian filter

[0084] Specific input parameters of the surface roughness measuring device are as follows.

[0085] Sal, Str: s = 0.20

[0086] Sxp: p = 2.5%

[0087] Vvv: p = 80.0%

[0088] ·Vvc: p=10.0%, q=80.0%

[0089] Vmp: p = 10.0%

[0090] ·Vmc: p=10.0%, q=80.0%

[0091] In addition, the surface roughness parameters automatically calculated according to ISO25178-2:2012, namely Sa (arithmetic mean height), Sz (maximum height), Sq (root mean square height), Sdr (expanded area ratio of the interface), Spc (arithmetic mean curvature of the peak apex), Ssk (skewness: deviation), and Sku (kurtosis: sharpness) are respectively recorded in Table 1. It should be noted that the values ​​of the comparative examples and reference examples described later are also recorded in Table 1. In addition, as a representative example, the surface roughness measurement results of the embodiment obtained by using a shape analysis laser microscope at any one point of the ground surface immediately after grinding are shown in Figure 3 .

[0092] [Table 1]

[0093]

[0094] Thereafter, in a state where the surface side is coated with a resist, as the first etching process, for the ground surface, an etching solution of sulfuric acid (96%): hydrogen peroxide (35%): pure water in a volume ratio of 1:1:7 is used, and etching is performed at 22°C for 3 minutes. As the second etching process, an etching solution of hydrochloric acid (36%): acetic acid (99.7%): pure water in a volume ratio of 1:1:2 is used, and etching is performed at 22°C for 30 seconds, and the back surface is etched by about 6nm to remove impurities generated by grinding. For the back of the etched substrate, an AuGe alloy film is formed by sputtering to form a back electrode. In addition, after removing the resist on the surface side, a heat treatment is performed at 320°C for 5 minutes as an ohmic heat treatment as a back electrode formation process. A laser cutting machine is used to perform a singulation process to obtain an infrared light receiving element.

[0095] <Comparative Example>

[0096] An optical semiconductor element of the comparative example was produced in the same manner as in Example 1 except that the grain size of the grindstone was changed to #4800 (GF01-SD4800-BR440-100 manufactured by DISCO Corporation) and the grinding conditions were set to: spindle 2000 rpm, chuck table 99 rpm, and grinding speed 0.30 μm / sec.

[0097] <Reference example>

[0098] For the n-type InP substrate of the single-sided mirror (thickness: 625 μm, carrier density: 3.0×10 18 / cm 3 ) was ground on the back surface and the surface roughness was measured.

[0099] As shown in Table 1, it is found that the wafer breakage rate can be reduced by performing back grinding so that the skewness (Ssk) in the surface roughness measurement of the ground surface immediately after grinding is positive and the maximum height (Sz) is 1.9 μm or more.

[0100] Industrial Applicability

[0101] The method for producing an optical semiconductor element of the present invention is useful in suppressing damage to a substrate and producing an optical semiconductor element with a good yield.

[0102] Description of Reference Numerals

[0103] 100 substrates

[0104] 110 laminated body

[0105] 130 Top electrode

[0106] 160 Back grinding substrate

[0107] 165 back grinding surface

[0108] 190 back electrode

Claims

1. A method for manufacturing an optical semiconductor element, comprising: A step of forming a laminate of compound semiconductor layers on one main surface of a cleavable compound semiconductor substrate; and A grinding step of grinding the other main surface of the substrate, wherein: The skewness (Ssk) in the surface roughness measurement of the ground surface of the substrate immediately after the grinding step is completed is set to be positive.

2. The method for manufacturing an optical semiconductor element according to claim 1, wherein: The maximum height (Sz) of the ground surface in the surface roughness measurement immediately after the grinding step is completed is set to 1.9 μm or more.

3. The method for manufacturing an optical semiconductor element according to claim 1, wherein: In the grinding process, only medium grinding stones with a grit size of #800 to #2000 are used.

4. The method for manufacturing an optical semiconductor element according to any one of claims 1 to 3, wherein: The compound semiconductor substrate is an InP substrate.

5. The method for manufacturing an optical semiconductor element according to claim 1, wherein: After the grinding process, the method further comprises: an etching step of etching the grinding surface; and A back electrode forming step is to form an electrode on the ground surface and perform heat treatment.

6. The method for manufacturing an optical semiconductor element according to claim 5, wherein: The etching process comprises: A first etching process using a diluted sulfuric acid-hydrogen peroxide solution; and The second etching step uses a mixed solution of hydrochloric acid and acetic acid.

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