Preparation method of display panel, MicroLED connection structure, driving backboard and display panel

Abstract

The invention discloses a preparation method of a display panel, a MicroLED connection structure, a driving backboard and the display panel. The preparation method of the display panel comprises the following steps: providing a growth substrate with an epitaxial layer; forming an insulating layer on one side of the second epitaxial layer; exposing and etching a preset position, corresponding to the second epitaxial layer, of the insulating layer to form a communicating hole; filling the communicating hole with a third conductive layer; a backplane substrate provided with a driving circuit layer; exposing and etching the position, corresponding to the communication hole, of one side of the driving circuit layer to form a fourth communication hole, and filling the fourth communication hole with a fourth conductive layer; the driving circuit layer is bonded with the insulating layer, so that the third conductive layer is electrically connected with the fourth conductive layer; stripping the growth substrate; and exposing and etching the epitaxial layer to form a light-emitting mesa structure. Therefore, the problems of poor contact or contact dislocation of the micro LED array structure and the driving back plate caused by non-uniform bonding due to metal thermal expansion in the bonding process of the existing eutectic bonding technology can be effectively solved.

Description

Display panel manufacturing method, MicroLED connection structure, driving backplane and display panel Technical Field

[0001] The present invention relates to the field of micro-display technology, and in particular to a method for preparing a display panel, a MicroLED connection structure, a driving backplane, and a display panel. Background Art

[0002] Inorganic micro-light-emitting diodes, also known as "micro-LEDs" or microLEDs, are gaining increasing attention for applications in a variety of fields, including self-luminous microdisplays, visible light communications, and optogenetics. Compared to traditional organic LEDs (OLEDs) or liquid crystal display (LCD)-based microdisplays, micro-LEDs offer higher wall plug efficiency, higher brightness, lower efficiency droop, better thermal stability, longer lifespan, faster response rate, higher resolution, wider color gamut, and higher contrast.

[0003] Micro-LED display panels integrate an array of thousands or even millions of micro-LEDs with a driver backplane. Each pixel in a micro-LED display panel is composed of one or more micro-LEDs. Micro-LED display panels can be either monochrome or multi-color. In multi-color micro-LED display panels, each pixel can further include multiple sub-pixels formed by multiple micro-LEDs, each corresponding to a different color. For example, three micro-LEDs corresponding to red, green, and blue can be stacked to form a pixel. Different colors can be mixed to produce a variety of colors.

[0004] In the existing technology, the commonly used technology for bonding between the micro LED array structure and the driver backplane is eutectic bonding technology; however, as the display panel continues to shrink, the metal expands during the eutectic bonding process, and the bonding between the micro LED array structure and the driver backplane is uneven, resulting in poor contact and contact dislocation between the micro LED array structure and the driver backplane, affecting the pixel luminescence effect.

[0005] Summary of the Invention

[0006] In order to solve the above technical problems, the purpose of the present invention is to provide a method for preparing a display panel, a MicroLED connection structure, a driving backplane and a display panel, which can solve the problems of uneven bonding due to metal thermal expansion during the bonding process of the existing eutectic bonding technology, resulting in poor contact or contact dislocation between the micro LED array structure and the driving backplane, and can increase the alignment area, improve the alignment rate, and improve the product quality rate.

[0007] In order to achieve the above object, the present invention discloses a method for preparing a display panel, which is characterized by comprising the following steps:

[0008] Providing a growth substrate, on which an epitaxial layer is formed, wherein the epitaxial layer includes a first epitaxial layer, a light-emitting layer, and a second epitaxial layer stacked in sequence from bottom to top;

[0009] forming an insulating layer on a side of the second epitaxial layer away from the growth substrate;

[0010] exposing and etching a predetermined position of the insulating layer corresponding to the second epitaxial layer to form a connecting hole, and filling the connecting hole with a third conductive layer so that the third conductive layer is electrically connected to the second epitaxial layer;

[0011] Providing a backplane substrate, wherein a driving circuit layer is formed on the backplane substrate;

[0012] exposing and etching a position corresponding to the communication hole on a side of the driving circuit layer away from the backplane substrate to form a fourth communication hole, and filling the fourth communication hole with a fourth conductive layer;

[0013] bonding the driving circuit layer to the insulating layer so that the third conductive layer is electrically connected to the fourth conductive layer;

[0014] peeling off the growth substrate; and

[0015] The epitaxial layer is exposed and etched to form a light-emitting mesa structure.

[0016] Before the step of bonding the driving circuit layer to the insulating layer, the method further includes the following steps:

[0017] At least one of the third conductive layer and the fourth conductive layer is exposed and etched to form at least one groove.

[0018] Before the step of bonding the driving circuit layer to the insulating layer, the method further includes the following steps:

[0019] exposing and etching a side of the third conductive layer away from the second epitaxial layer to form a first groove; and

[0020] The side of the fourth conductive layer away from the backplane substrate is exposed and etched to form a second groove.

[0021] The steps include:

[0022] The third conductive layer is filled in the communication hole and is flush with the surface of the insulating layer away from the second epitaxial layer; and

[0023] The fourth conductive layer is filled in the fourth connecting hole and is flush with the surface of the driving circuit layer away from the backplane substrate.

[0024] A MicroLED connection structure is also disclosed, which is characterized by comprising:

[0025] an epitaxial layer, the epitaxial layer comprising a first epitaxial layer, a light-emitting layer, and a second epitaxial layer stacked in sequence from top to bottom;

[0026] an insulating layer, the insulating layer being disposed on a side of the second epitaxial layer away from the first epitaxial layer, the insulating layer having a connecting hole at a predetermined position corresponding to the second epitaxial layer; and

[0027] a third conductive layer, wherein the third conductive layer is filled in the connecting hole and is electrically connected to the second epitaxial layer.

[0028] Wherein, a first groove is provided on a side of the third conductive layer away from the second epitaxial layer.

[0029] Wherein, the depth of the first groove is 2nm-20nm.

[0030] Also disclosed is a driving backplane, characterized by comprising:

[0031] a backplane substrate;

[0032] a driving circuit layer, the driving circuit layer being disposed on one side of the backplane substrate, and having a fourth connecting hole on a side of the driving circuit layer away from the backplane substrate; and

[0033] A fourth conductive layer is filled in the fourth connecting hole.

[0034] Wherein, a second groove is provided on a side of the fourth conductive layer away from the backplane substrate.

[0035] Wherein, the depth of the second groove is 2nm-20nm.

[0036] Wherein, it further includes a contact point, which is arranged on the driving circuit layer, and the fourth conductive layer is electrically connected to at least two of the contact points.

[0037] A display panel is also disclosed, characterized by comprising:

[0038] a driving backplane, the driving backplane comprising a backplane substrate and a driving circuit layer, the driving circuit layer being disposed on one side of the backplane substrate;

[0039] A micro LED array structure, comprising a plurality of light-emitting mesa structures, each of which comprises a first epitaxial layer, a light-emitting layer, and a second epitaxial layer stacked in sequence from top to bottom; and

[0040] an insulating layer, the insulating layer being disposed on the second epitaxial layer and having a communication hole at a predetermined position corresponding to the second epitaxial layer, the communication hole being filled with a third conductive layer;

[0041] Among them, the driving circuit layer has a fourth connecting hole at a position corresponding to the connecting hole on the side away from the backplane substrate, and the fourth connecting hole is filled with a fourth conductive layer; the insulating layer is fixed on the driving circuit board, and the third conductive layer is electrically connected to the fourth conductive layer.

[0042] The third conductive layer and the fourth conductive layer adopt one of a single-layer structure and a multi-layer structure.

[0043] Among them, the third conductive layer and the fourth conductive layer adopt one of a metal conductive material and a non-metallic conductive material, the metal conductive material is at least one of Cu, Al, Sn, Pb, Ni, Ti, Ag, Au, Pt and ITO, and the non-metallic conductive material is at least one of carbon fiber, carbon nanotube and graphene.

[0044] The opening width of the connecting hole at a side close to the driving back plate is smaller than or larger than the opening width of the fourth connecting hole at a side away from the back plate substrate.

[0045] The opening width of the communication hole at a side close to the driving back plate and the opening width of the fourth communication hole at a side away from the back plate substrate are 0.6 μm-2.0 μm.

[0046] Wherein, it further includes a second conductive layer, which is arranged on a side of the second epitaxial layer away from the first epitaxial layer and is electrically connected to the second epitaxial layer and the third conductive layer.

[0047] Through the above content, the present invention can achieve the following beneficial effects:

[0048] (1) The insulating layer of the micro-LED array structure of the present invention has a connecting hole, and a third conductive layer is provided in the connecting hole; the driving circuit layer of the driving backplane has a fourth connecting hole corresponding to the connecting hole, and a fourth conductive layer is provided in the fourth connecting hole; the micro-LED array structure is bonded to the driving backplane, the connecting hole is connected to the fourth connecting hole, and the third conductive layer is electrically connected to the fourth conductive layer to form a conductive channel, which can effectively solve the problems of poor contact or contact dislocation between the micro-LED array structure and the driving backplane caused by uneven bonding due to metal thermal expansion during the bonding process of the existing eutectic bonding technology.

[0049] (2) The opening width of the connecting hole on the side close to the driving backplane is different from the opening width of the fourth connecting hole on the side away from the backplane substrate. During the bonding process between the micro LED array structure and the driving backplane, the alignment area can be increased and the alignment rate can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The above and other objects, features and advantages of the present disclosure will become more apparent through a more detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings, wherein like reference numerals generally represent like components in the exemplary embodiments of the present disclosure.

[0051] FIG. 1 a is a schematic structural diagram of a micro LED display panel according to a first embodiment of the present invention.

[0052] FIG. 1 b is a schematic structural diagram of the first barrier layer in FIG. 1 a with its length extended.

[0053] FIG. 1 c is a schematic structural diagram of FIG. 1 a in which the length of the first barrier layer is shortened.

[0054] FIG. 2 is a schematic structural diagram of a micro LED display panel according to a second embodiment of the present invention.

[0055] FIG3 is a schematic structural diagram of a micro LED display panel according to a third embodiment of the present invention.

[0056] FIG. 4 is a schematic structural diagram of a micro LED display panel according to a fourth embodiment of the present invention.

[0057] FIG. 5 a is a schematic structural diagram of a micro LED display panel according to a fifth embodiment of the present invention.

[0058] FIG5 b is a schematic structural diagram of a micro LED display panel according to a sixth embodiment of the present invention.

[0059] FIG6 a is a schematic structural diagram of a micro LED display panel according to a seventh embodiment of the present invention.

[0060] FIG6 b is a schematic structural diagram of a micro LED display panel according to an eighth embodiment of the present invention.

[0061] FIG. 7 is a schematic structural diagram of a micro LED display panel according to a ninth embodiment of the present invention.

[0062] FIG8 a is a schematic structural diagram of a micro LED array structure before bonding to a driving backplane according to an embodiment of the present invention.

[0063] FIG8 b is a schematic structural diagram of a micro LED array structure before bonding to a driving backplane according to another embodiment of the present invention.

[0064] FIG9 is a flowchart of a method for manufacturing a micro LED display panel according to an embodiment of the present invention.

[0065] FIG10 a is a diagram showing the light emitting display and positioning analysis of optical crosstalk in the prior art.

[0066] FIG10 b is a diagram showing the light crosstalk luminescence display and positioning analysis of the present invention. DETAILED DESCRIPTION

[0067] The preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although preferred embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. Rather, these embodiments are provided to make the present disclosure more thorough and complete, and to fully convey the scope of the present disclosure to those skilled in the art.

[0068] Some embodiments of the present invention provide a micro LED display panel.

[0069] Referring to Figure 1a, the micro LED display panel provided by the present invention includes a micro LED array structure 100 and a driving backplane 200. The micro LED array structure 100 is arranged on one side of the driving backplane 200, and the driving backplane 200 is used to drive the micro LED array structure 100 to emit light. In some embodiments, the driving backplane 200 is an IC backplane. In some embodiments, the driving backplane 200 is a thin film transistor. The micro LED array structure 100 includes a plurality of light-emitting mesa structures 101 and a first barrier layer 102. In some embodiments, the light-emitting mesa structure 101 is a mesa structure. In some embodiments, the light-emitting mesa structure 101 is a cylindrical mesa structure, a hemispherical mesa structure, or an ellipsoidal mesa structure.

[0070] The light-emitting mesa structure 101 includes a first epitaxial layer 1011, a light-emitting layer 1012, and a second epitaxial layer 1013, stacked sequentially from top to bottom. The first epitaxial layer 1011 is an n-type doped semiconductor, for example, doped with Si, V, C, or Mg; the second epitaxial layer 1013 is a p-type doped semiconductor, for example, doped with Be, Zn, Mg, or C; and the light-emitting layer 1012 is a quantum well. A first barrier layer 102 is located on the sidewalls of the light-emitting mesa structure 101, with at least a portion of the first barrier layer 102 positioned in the propagation path of horizontal light emitted by the light-emitting layer 1012. The first barrier layer 102 surrounds the light-emitting mesa structure 101. The first barrier layer 102 provided in the present invention effectively blocks light from the light-emitting layer 1012 of the light-emitting mesa structure 101 from lateral transmission to adjacent light-emitting mesa structures 101, preventing the light-emitting layer 1012 of adjacent light-emitting mesa structures 101 from being illuminated and causing optical crosstalk. Refer to Figure 10a, which shows a prior art optical crosstalk luminescence display and positioning analysis diagram. As shown in Figure 10a, without the first barrier layer 102, the number of optical crosstalk pixels between the light-emitting mesas 101 of the micro-LED array structure is three. Refer to Figure 10b, which shows a prior art optical crosstalk luminescence display and positioning analysis diagram of the present invention. As shown in Figure 10b, with the first barrier layer 102, the number of optical crosstalk pixels between the light-emitting mesas 101 of the micro-LED array structure is reduced to less than one.

[0071] Referring to Figure 1a, the micro-LED array structure 100 further includes a dielectric layer 103, at least a portion of which is disposed on the sidewalls of the light-emitting mesa structure 101. Specifically, the dielectric layer 103 is disposed on the sidewalls of the light-emitting mesa structure 101 and on the surface of the light-emitting mesa structure 101 where the light-emitting end 1014 is distal from the light-emitting mesa structure 101. The dielectric layer 103 is disposed continuously between adjacent light-emitting mesa structures 101. Furthermore, the dielectric layer 103 is disposed between the light-emitting mesa structure 101 and the first barrier layer 102. The dielectric layer 103 is made of an insulating material, such as Si or SiO2.

[0072] Referring to Figure 1a, the light-emitting mesa structure 101 further includes a light-emitting end 1014 and a light-reflecting end 1015. The light-emitting end 1014 is located at the end of the first epitaxial layer 1011 away from the second epitaxial layer 1013; the light-reflecting end 1015 is located at the end of the second epitaxial layer 1013 away from the first epitaxial layer 1011. The first barrier layer 102 includes a high end 1021 and a low end 1022, with the high end 1021 being closer to the light-emitting end 1014 and the low end 1022 being closer to the light-reflecting end 1015. The distance between the high end 1021 of two adjacent first barrier layers 102 corresponding to two adjacent light-emitting mesa structures 101 is within a range of 0.4 μm to 1.0 μm. The low end 1022 of two adjacent first barrier layers 102 corresponding to two adjacent light-emitting mesa structures 101 are connected by a barrier connection layer 1023. Along the central axis of the light-emitting mesa structure 101 , the projected area of ​​the light-emitting end 1014 is smaller than the projected area of ​​the light-reflecting end 1015 .

[0073] Referring to Figure 1a, the micro-LED array structure 100 further includes a first conductive layer 104. At least a portion of the first conductive layer 104 is located on a side of the light-emitting end 1014 away from the light-emitting mesa structure 101 and is electrically connected to the first epitaxial layer 1011. Specifically, the dielectric layer 103 located on the side of the light-emitting end 1014 away from the light-emitting mesa structure 101 has an opening, and the first conductive layer 104 completely fills the opening. Furthermore, the first conductive layer 104 is formed on the surface of the dielectric layer 103 away from the light-emitting mesa structure 101. Specifically, the first conductive layer 104 is located on the upper surface of the dielectric layer 103 away from the light-emitting end 1014 and on the side surface of the dielectric layer 103 away from the light-emitting mesa structure 101. The first conductive layer 104 is continuously disposed between adjacent light-emitting mesa structures 101. The first conductive layer 104 filling the opening in the dielectric layer 103 is electrically connected to the first epitaxial layer 1011. In some embodiments, the first conductive layer 104 is made of indium tin oxide (ITO). In some embodiments, the first conductive layer 104 is made of a transparent conductive oxide (TCO) such as aluminum-doped zinc oxide (AZO) or gallium zinc oxide (GZO), or other transparent conductive materials with higher conductivity than the first epitaxial layer 1011.

[0074] Referring to Figure 1a , the sum of the thicknesses of the second epitaxial layer 1013 and the light-emitting layer 1012 is H. The length of the first barrier layer 102 extends away from the light-emitting layer 1012 or decreases toward the light-emitting layer 1012; the length of the first barrier layer 102 is within ±50% of the sum of the thicknesses of the second epitaxial layer 1013 and the light-emitting layer 1012. The first barrier layer 102 is located on the sidewalls of the second epitaxial layer 1013 corresponding to the light-emitting layer 1012, and the length of the first barrier layer 102 is H. Referring to Figure 1b , FIG1b illustrates the structure of FIG1a in which the length of the first barrier layer is extended. As shown in FIG1b , the upper end 1021 of the first barrier layer 102 extends away from the light-emitting layer 1012. Therefore, the length of the first barrier layer 102 varies within the range of H and 1.5H. Referring to FIG1c , FIG1c illustrates the structure of FIG1a in which the length of the first barrier layer is shortened. As shown in Figure 1c, the lower end 1022 of the first barrier layer 102 shortens toward the light-emitting layer 1012. Therefore, the length of the first barrier layer 102 varies within a range of 0.5H and H. In practical applications, the length of the first barrier layer 102 is 20 nm to 2000 nm. The first barrier layer 102 and the barrier connection layer 1023 are made of the same material, including one or more of Cr, Ni, Ti, Au, and Pt.

[0075] Referring to FIG. 1 a , the micro-LED array structure 100 further includes a second conductive layer 105 , a second barrier layer 106 , and a reflective layer 107 . The second conductive layer 105 is disposed on the surface of the reflective end 1015 away from the second epitaxial layer 1013 and is electrically connected to the second epitaxial layer 1013 . In some embodiments, the second conductive layer 105 is made of a transparent conductive layer such as ITO. In some embodiments, the second conductive layer 105 is made of a transparent conductive oxide such as AZO or GZO. In some embodiments, the second conductive layer 105 is made of a metal conductive layer, and the metal includes Cr, Al, Ti, Pt, Au, Ag, Ni, Ge, Sn, etc. In some embodiments, the second conductive layer 105 is made of other conductive materials with higher conductivity efficiency than the first epitaxial layer 1011.

[0076] The second conductive layers 105 of adjacent light-emitting mesas 101 are spaced apart, and the second barrier layer 106 fills the gaps between adjacent second conductive layers 105. The second barrier layer 106 is located on the side of the second conductive layer 105 facing away from the second epitaxial layer 1013. The second barrier layer 106 has first communication holes at predetermined locations corresponding to the second conductive layer 105. These predetermined locations correspond to the first conductive layer 104 on the surface of the light-emitting end 1014. In practical applications, the second barrier layer 106 has a thickness of 20 nm to 500 nm and a width of 0.4 μm to 2.0 μm. The thickness is the vertical distance between the surface of the second barrier layer 106 closest to the second conductive layer 105 and the surface farther from the second conductive layer 105, while the width is the horizontal distance between two adjacent first communication holes in the second barrier layer 106. The second barrier layer 106 is made of an insulating material, such as SiO2, Al2O3, or silicon nitride. In some embodiments, the second barrier layer 106 is a single-layer structure. In some embodiments, the second barrier layer 106 is a multi-layer structure. At least a portion of the reflective layer 107 is located in the first via hole of the second barrier layer 106 and is electrically connected to the second conductive layer 105. The second barrier layer 105 is used to prevent metal from being deposited in the reflective layer 107.

[0077] Referring to Figure 1a, the reflective layer 107 includes a first reflective structure 1071 and a second reflective structure 1072. The first reflective structure 1071 is located within the first connecting hole and matches the first connecting hole. The second reflective structure 1072 is located on the side of the second barrier layer 106 away from the second conductive layer 105. In practical applications, the second reflective structure 1072 has a thickness of 0.1 μm to 1.0 μm and a width of 1.2 μm to 2.3 μm, where the thickness is the vertical distance between the surface of the second reflective structure 1072 near the second barrier layer 106 and the surface away from the second barrier layer 106. Along the central axis of the light-emitting mesa structure 101, the projected area of ​​the side of the first reflective structure 1071 of the reflective layer 107 near the second epitaxial layer 1013 is smaller than the projected area of ​​the side of the second conductive layer 105 away from the second epitaxial layer 1013. Adjacent emitting layers 107 are spaced apart.

[0078] Referring to Figure 1a, the micro-LED array structure 100 also includes an insulating layer having communication holes at predetermined locations corresponding to the reflective layer 107. The insulating layer includes a first insulating layer 108 and a second insulating layer 109. The communication holes include a second communication hole 1081 and a third communication hole 1091. The first insulating layer 108 is disposed on the side of the second barrier layer 106 away from the second conductive layer 105; the second insulating layer 109 is disposed on the side of the first insulating layer 108 away from the second barrier layer 106. The first insulating layer 108 has a second communication hole 1081 at predetermined locations corresponding to the reflective layer 107, and the second insulating layer 109 has a third communication hole 1091 that communicates with the second communication hole 1081. The predetermined locations of the reflective layer 107 are disposed corresponding to the first communication holes. In practical applications, the first insulating layer 108 is made of an insulating material such as SiO2, Al2O3, or silicon nitride. The first insulating layer 108 is disposed around the second reflective structure 1072 of the reflective layer 107 to prevent metal precipitation in the reflective layer 107. The second insulating layer 109 is made of an insulating material, such as SiO2, Al2O3, or silicon nitride. In some embodiments, the second insulating layer 109 is a single-layer structure. In some embodiments, the second insulating layer 109 is a composite oxide insulating layer structure, and the composite oxide insulating layer structure is made of a SiO2-silicon nitride composite material or a SiO2-Al2O3 composite material. The micro-LED array structure 100 also includes a third conductive layer 110 filled in the second connecting hole 1081 and the third connecting hole 1091. The third conductive layer 110 is electrically connected to the reflective layer 107. The width of the opening of the second connecting hole 1081 on the side close to the reflective layer 107 is less than the width of the reflective layer 107. The third conductive layer 110 is a single-layer structure or a multi-layer structure.

[0079] Referring to Figure 1a, the driving backplane 200 includes a backplane substrate 201 and a driving circuit layer 202, with the driving circuit layer 202 formed on the backplane substrate 201. The backplane substrate 201 is made of an insulating material, such as SiO2, Al2O3, or silicon nitride. In some embodiments, the backplane substrate 201 is a single-layer structure. In some embodiments, the backplane substrate 201 is a composite oxide insulating layer structure, and the composite oxide insulating layer structure is made of a SiO2-silicon nitride composite material or a SiO2-Al2O3 composite material. A fourth connecting hole 2021 is formed on the surface of the driving circuit layer 202 away from the backplane substrate 201. The fourth connecting hole 2021 is filled with a fourth conductive layer 2022, and the fourth conductive layer 2022 is electrically connected to a contact 2023. The fourth conductive layer 2022 is a single-layer structure or a multi-layer structure. The contact 2023 is located on the driving circuit layer 202 and is connected to the driving circuit for driving the micro LED array structure 100 to emit light. The fourth connecting hole 2021 electrically connects at least two contacts 2023, meaning each fourth connecting hole 2021 connects at least two contacts 2023. Connecting multiple contacts 2023, compared to connecting only one contact 2023, can prevent the micro-LED array structure 100 from igniting due to a single contact 2023 failing to conduct electricity. The fourth connecting hole 2021 is positioned corresponding to the third connecting hole 1091. The third conductive layer 110 of the third connecting hole 1091 electrically connects to the fourth conductive layer 2022 of the fourth connecting hole 2021, forming a conductive channel between the third conductive layer 110 and the fourth connecting hole 2021. In practical applications, the opening width of the third connecting hole 1091 on the side closest to the driver backplane 200 is 0.6 μm to 2.0 μm; the opening width of the fourth connecting hole 2021 on the side away from the backplane substrate 201 is 0.6 μm to 2.0 μm. In some embodiments, the opening width of the third connecting hole 1091 on the side close to the driver backplate 200 is greater than the opening width of the fourth connecting hole 2021 on the side away from the backplate substrate 201. In some embodiments, the opening width of the third connecting hole 1091 on the side close to the driver backplate 200 is less than the opening width of the fourth connecting hole 2021 on the side away from the driver backplate 200. In some embodiments, the opening width of the third connecting hole 1091 on the side close to the driver backplate 200 is equal to the opening width of the fourth connecting hole 2021 on the side away from the backplate substrate 201. The difference between the opening width of the third connecting hole 1091 on the side close to the driver backplate 200 and the opening width of the fourth connecting hole 2021 on the side away from the backplate substrate 201 can increase the alignment area and improve the alignment rate during the bonding process between the micro LED array structure 100 and the driver backplate 200.

[0080] Before the micro LED array structure 100 is bonded to the driving backplane 200, at least one of the third conductive layer 110 and the fourth conductive layer 2022 is provided with a groove; alternatively, the side of the third conductive layer 110 away from the second epitaxial layer 1013 is flush with the surface of the second insulating layer 109 away from the second epitaxial layer 1013, and the side of the fourth conductive layer 2022 away from the backplane substrate 201 is flush with the surface of the driving circuit layer 202 away from the backplane substrate 201.

[0081] In some embodiments, the third conductive layer 110 and the fourth conductive layer 2022 are made of metal conductive materials, such as Cu, Al, Sn, Pb, Ni, Ti, Ag, Au, Pt, ITO, etc. The third conductive layer 110 and the fourth conductive layer 2022 are metal layers composed of a single metal, or metal stacks composed of multiple metals. Referring to Figure 8a, Figure 8a is a schematic structural diagram of a micro-LED array structure before bonding to a driving backplane according to an embodiment of the present invention. As shown in Figure 8a, before the micro-LED array structure 100 is bonded to the driving backplane 200, a first groove 1101 is provided on the surface of the third conductive layer 110 away from the light-emitting mesa structure 101, and a second groove 2024 is provided on the surface of the fourth conductive layer 2022 away from the backplane substrate 201. In actual applications, the depths of the first groove 1101 and the second groove 2024 are both 2nm to 20nm. The micro-LED array structure 100 and the driver backplane 200 are bonded together using hybrid bonding technology. During the bonding process, the third conductive layer 110 and the fourth conductive layer 2022 expand. The expansion coefficient of the material used for bonding between the second insulating layer 109 and the driver circuit layer 202 is much smaller than that of the third conductive layer 110 and the fourth conductive layer 2022. During the expansion process, the third conductive layer 110 expands toward the driver backplane 200, while the fourth conductive layer 2022 expands away from the backplane substrate 201. The expanded third conductive layer 110 and the fourth conductive layer 2022 fill the first groove 1101 and the second groove 2024, forming a contact and connection to form a conductive path.

[0082] In some embodiments, the third conductive layer 110 and the fourth conductive layer 2022 are made of non-metallic conductive materials, such as carbon fiber, carbon nanotubes, graphene, etc. Referring to Figure 8b, Figure 8b is a schematic diagram of the structure of a micro-LED array structure before bonding to a driver backplane according to another embodiment of the present invention. As shown in Figure 8b, before the micro-LED array structure 100 is bonded to the driver backplane 200, the surface of the third conductive layer 110 proximal to the driver backplane 200 is flush with the surface of the second insulating layer 109; and the surface of the fourth conductive layer 2022 distal from the backplane substrate 201 is flush with the surface of the driver circuit layer 202. The expansion coefficient of the material used for bonding between the second insulating layer 109 and the driver circuit layer 202 is similar to that of the third conductive layer 110 and the fourth conductive layer 2022. This results in uniform bonding between the micro-LED array structure 100 and the driver backplane 200, and good contact between the conductive pathway formed by the contact between the third conductive layer 110 and the fourth conductive layer 2022.

[0083] In some embodiments, one of the third conductive layer 110 and the fourth conductive layer 2022 is made of a metallic conductive material, such as Cu, Al, Sn, Pb, Ni, Ti, Ag, Au, Pt, or ITO, while the other is made of a non-metallic conductive material, such as carbon fiber, carbon nanotubes, or graphene. The metallic conductive layer has grooves, while the non-metallic conductive layer is flat. During the bonding process between the micro LED array structure 100 and the driver backplane 200, the grooved conductive layer expands and contacts the flat conductive layer, forming a conductive path.

[0084] In some embodiments, at least one of the third conductive layer 110 and the fourth conductive layer 2022 has a protruding structure. The third conductive layer 110 has a protruding structure, and the thermal expansion coefficient of the conductive material of the third conductive layer 110 is much smaller than the thermal expansion coefficient of the second insulating layer 109; alternatively, the thermal expansion coefficient of the third conductive layer 110 is negative. The fourth conductive layer 2022 has a protruding structure, and the thermal expansion coefficient of the conductive material of the fourth conductive layer 2022 is much smaller than the thermal expansion coefficient of the driving circuit layer 202; alternatively, the thermal expansion coefficient of the fourth conductive layer 2022 is negative.

[0085] In the present invention, the micro LED array structure 100 is provided with a third connecting hole 1091, and the driving backplane 200 is provided with a corresponding fourth connecting hole 2021; the third connecting hole 1091 is filled with a third conductive layer 110, and the fourth connecting hole 2021 is filled with a fourth conductive layer 2022; the micro LED array structure 100 is bonded to the driving backplane 200, and the third conductive layer 110 and the fourth conductive layer 2022 are in contact and connected to form a conductive channel, which can effectively solve the problems of poor contact or contact dislocation between the micro LED array structure 100 and the driving backplane 200 caused by uneven bonding due to metal thermal expansion during the bonding process of the existing eutectic bonding technology.

[0086] Referring to Figure 1a, the micro-LED display panel also includes a micro-lens 300. The micro-lens 300 is located on the side of the micro-LED array structure 100 away from the driver backplane 200 and is located in the light path of the micro-LED array structure 100. Specifically, the micro-lens 300 is provided on the side of the light-emitting mesa structure 101 away from the driver backplane 200 and is located in the light path of the light-emitting mesa structure 101. The micro-lens 300 corresponds one-to-one with each light-emitting mesa structure 101, that is, each light-emitting mesa structure 101 is provided with a corresponding micro-lens 300.

[0087] Referring to Figure 2 , which is a schematic structural diagram of a micro-LED display panel according to a second embodiment of the present invention, as shown in Figure 2 , unlike the first embodiment, in the second embodiment, a first barrier layer 102 is disposed between the light-emitting mesa structure 101 and the dielectric layer 103 .

[0088] Referring to Figure 3, a schematic diagram of the structure of a micro-LED display panel according to a third embodiment of the present invention is shown. Unlike the first embodiment, in the third embodiment, the micro-LED array structure 100 lacks a second barrier layer 106. A reflective layer 107 is provided on the surface of the second conductive layer 105 facing away from the second epitaxial layer 1013. Along the central axis of the light-emitting mesa structure 101, the projected area of ​​the reflective layer 107 on the side closest to the second epitaxial layer 1013 is the same as the projected area of ​​the second conductive layer 105 on the side facing away from the second epitaxial layer 1013. During the fabrication process of the micro-LED array structure 100, this structure can be obtained through a single etching process, making it easy to manufacture. Adjacent second conductive layers 105 and adjacent reflective layers 107 are spaced apart. The space between two adjacent second conductive layers 105 and two adjacent reflective layers 107 of adjacent light-emitting mesa structures 101 is completely filled with a first insulating layer 108, and the surface of the reflective layer 107 facing away from the second conductive layer 105 is completely covered with the first insulating layer 108.

[0089] The reflective layer 107 is a metal reflective layer or a distributed Bragg reflector (DBR). Metal materials include Ni, Ag, Ti, Pt, Au, Al, etc. In some embodiments, the reflective layer 107 has a single-layer structure, and the single-layer structure uses a metal or a metal alloy. In some embodiments, the reflective layer 107 has a multi-layer structure; in the direction away from the light-emitting mesa structure 101, the reflective layer 107 is sequentially composed of a Ni layer, an Ag layer, a Ti layer, a Pt layer, and a Ti layer. The thickness of the reflective layer 107 is 0.1 μm to 1.0 μm, and the thickness is the vertical distance between the surface of the reflective layer 107 close to the second conductive layer 105 and the surface away from the second conductive layer 105. The reflective layer 107 provided in the present invention reflects the light received from the light-emitting mesa structure 101 to the light-emitting end 1014, thereby improving the brightness and light efficiency of the micro-LED display panel. As shown in Table 1, the brightness of the micro-LED display panel increased from 131 to 171, an increase of 30.5%; the light efficiency increased from 8% to 12%, an increase of 50.0%; and the forward voltage during operation was stabilized at approximately 2.8V.

[0090] Table 1 Brightness and light effect data

[0091] Referring to Figure 4, which is a schematic structural diagram of a micro-LED display panel according to a fourth embodiment of the present invention, as shown in Figure 4, unlike the first embodiment, in the fourth embodiment, the reflective layer 107 completely fills the first via hole in the second barrier layer 106, and the surface of the reflective layer 107 away from the second conductive layer 105 is flush with the surface of the second barrier layer 106 away from the second conductive layer 105. The width of the opening of the second via 1801 near the second conductive layer 105 is greater than the width of the opening of the first via away from the second conductive layer 105.

[0092] Referring to Figure 5a, which is a schematic structural diagram of a micro-LED display panel according to a fifth embodiment of the present invention, as shown in Figure 5a, unlike the first embodiment, in the fifth embodiment, the first conductive layer 104 is formed on the surface of the dielectric layer 103 away from the light-emitting end 1014 and on the sidewalls of the dielectric layer 103 near the light-emitting end 1014. The first conductive layer 104 is absent from the sidewalls of the dielectric layer 103 away from the light-emitting end 1014, and the first conductive layer 104 is discontinuous between adjacent light-emitting mesa structures 101. When projected onto the sidewalls of the dielectric layer 103, the projections of the first barrier layer 102 and the first conductive layer 104 do not overlap at all.

[0093] Referring to Figure 5b, which is a schematic structural diagram of a micro-LED display panel according to a sixth embodiment of the present invention, as shown in Figure 5b, unlike the first embodiment, in the sixth embodiment, the first conductive layer 104 is formed on the surface of the dielectric layer 103 away from the light-emitting end 1014, and the first conductive layer 104 is not formed on the sidewalls of the dielectric layer 103.

[0094] Refer to Figure 6a, which is a schematic structural diagram of a micro-LED display panel according to the seventh embodiment of the present invention. As shown in Figure 6a, unlike the first embodiment, in the seventh embodiment, the dielectric layer 103 is formed only on the sidewalls of the light-emitting mesa structure 101, and the dielectric layer 103 completely covers the sidewalls of the light-emitting mesa structure 101. No dielectric layer 103 is formed on the surface of the light-emitting end 1014 away from the light-emitting mesa structure 101. When projected onto the sidewalls of the light-emitting mesa structure 101, the first barrier layer 102 is entirely projected onto the dielectric layer 103.

[0095] Referring to Figure 6b, which is a schematic structural diagram of a micro-LED display panel according to an eighth embodiment of the present invention, as shown in Figure 6b, unlike the first embodiment, in the eighth embodiment, the dielectric layer 103 is formed only on the sidewalls of the light-emitting mesa structure 101 away from the light-emitting end 1014. In some embodiments, when projected onto the sidewalls of the light-emitting mesa structure 101, the first barrier layer 102 is entirely projected onto the dielectric layer 103. In some embodiments, when projected onto the sidewalls of the light-emitting mesa structure 101, the first barrier layer 102 is partially projected onto the dielectric layer 103 and partially onto the sidewalls of the light-emitting mesa structure 101.

[0096] Referring to Figure 7, Figure 7 is a schematic structural diagram of a micro-LED display panel according to a ninth embodiment of the present invention. As shown in Figure 7, unlike the first embodiment, in the ninth embodiment, along the central axis of the light-emitting mesa structure 101, the projected area of ​​the light-emitting end 1014 is larger than the projected area of ​​the light-reflecting end 1015. In some embodiments, the dielectric layer 103 is located between the light-emitting mesa structure 101 and the first barrier layer 102, and the first barrier layer 102 is located on the sidewall of the dielectric layer 103 near the light-emitting end 1014. In some embodiments, the first barrier layer 102 is located between the dielectric layer 103 and the light-emitting mesa structure 101, and the first barrier layer 102 is located on the sidewall of the light-emitting mesa structure 101 near the light-emitting end 1014.

[0097] Some embodiments of the present invention also provide a method for preparing a micro LED display panel.

[0098] Referring to Figure 9, which is a flowchart of the steps of a method for manufacturing a micro-LED display panel according to an embodiment of the present invention, the method for manufacturing a micro-LED display panel provided by the present invention includes steps S1 to S6.

[0099] In step S1 , a growth substrate is provided. An epitaxial layer is formed on the growth substrate. The epitaxial layer includes a first epitaxial layer 1011 , a light emitting layer 1012 , and a second epitaxial layer 1013 stacked in sequence from bottom to top.

[0100] In step S2, a second conductive layer 105, a reflective layer 107, and an insulating layer are sequentially formed on the side of the second epitaxial layer 1013 facing away from the growth substrate. The second conductive layer 105 is electrically connected to the second epitaxial layer 1013, and the reflective layer 107 is electrically connected to the second conductive layer 105. Predetermined locations of the insulating layer corresponding to the reflective layer 107 are exposed and etched to form a via. The via is then filled with a third conductive layer 110, electrically connecting the third conductive layer 110 to the reflective layer 107. In some embodiments, the side of the third conductive layer 110 facing away from the second epitaxial layer 1013 is flush with the surface of the insulating layer facing away from the second epitaxial layer 1013. In some embodiments, the side of the third conductive layer 110 facing away from the second epitaxial layer 1013 is exposed and etched to form a first recess 1101.

[0101] In step S3, a backplane substrate 201 is provided, on which a driving circuit layer 202 is formed. A portion of the driving circuit layer 202 facing away from the backplane substrate 201 corresponding to the third connecting hole 1091 is exposed and etched to form a fourth connecting hole 2021, which is then filled with a fourth conductive layer 2022. The surface of the driving circuit layer 202 facing away from the backplane substrate 201 is bonded to the surface of the insulating layer facing away from the growth substrate, electrically connecting the third conductive layer 110 to the fourth conductive layer 2022. In some embodiments, the side of the fourth conductive layer 2022 facing away from the backplane substrate 201 is flush with the surface of the driving circuit layer 202 facing away from the backplane substrate 201. In some embodiments, the side of the fourth conductive layer 2022 facing away from the backplane substrate 201 is exposed and etched to form a second groove 2024.

[0102] In step S4 , the growth substrate is peeled off.

[0103] In step S5, the epitaxial layer is exposed and etched to form the light-emitting mesa structure 101. In some embodiments, based on the contact area between the reflective layer 107 and the second conductive layer 105, a light-emitting window (i.e., the light-emitting end 1014 of the light-emitting mesa structure 101) is marked on the side of the epitaxial layer away from the driving backplane 200, and a corresponding light-reflecting window (i.e., the light-reflecting end 1015 of the light-emitting mesa structure 101) is marked on the side of the epitaxial layer close to the driving backplane 200. The area of ​​the light-reflecting window is larger than the contact area between the reflective layer 107 and the second conductive layer 105; the epitaxial layer is exposed, and based on the marked light-emitting window and light-reflecting window, the epitaxial layer is etched to obtain the light-emitting mesa structure 101.

[0104] In step S6 , a first barrier layer 102 is formed on the sidewall of the light-emitting mesa structure 101 . At least a portion of the first barrier layer 102 is located on a propagation path of the horizontal light emitted by the light-emitting layer 1012 .

[0105] In some embodiments, the above step S2 includes sub-steps S21 to S25.

[0106] In sub-step S21, a second conductive layer 105 is formed on a side of the second epitaxial layer 1013 away from the growth substrate. The second conductive layer 105 is exposed and etched at a predetermined position corresponding to the second epitaxial layer 1013 to form a first through hole.

[0107] In sub-step S22, a second barrier layer 106 is filled in the first through hole, and a second barrier layer 106 is formed on the side of the second conductive layer 105 away from the second epitaxial layer 1013; the preset position of the second barrier layer 106 corresponding to the second conductive layer 105 is exposed and etched to form a first connecting hole.

[0108] In sub-step S23 , a reflective layer 107 is formed on a side of the second conductive layer 105 away from the second epitaxial layer 1013 , and at least a portion of the reflective layer 107 fills the first connecting hole; the reflective layer 107 is electrically connected to the second conductive layer 105 .

[0109] In sub-step S24 , a first insulating layer 108 is formed on a side of the second barrier layer 106 away from the second conductive layer 105 ; a predetermined position of the first insulating layer 108 corresponding to the reflective layer 107 is exposed and etched to form a second connecting hole 1081 .

[0110] In sub-step S25, a second insulating layer 109 is formed on the side of the first insulating layer 108 away from the second blocking layer 106; the position of the second insulating layer 109 corresponding to the second connecting hole 1081 is exposed and etched to form a third connecting hole 1091, the second connecting hole 1081 is connected to the third connecting hole 1091, and the third conductive layer 110 is filled in the second connecting hole 1081 and the third connecting hole 1091.

[0111] In some embodiments, the above step S2 includes sub-steps S26 to S29.

[0112] In sub-step S26 , a second conductive layer 105 is formed on a side of the second epitaxial layer 1013 away from the growth substrate; and the second conductive layer 105 is exposed and etched at a predetermined position corresponding to the second epitaxial layer 1013 to form a first through hole.

[0113] In sub-step S27 , a reflective layer 107 is formed on a side of the second conductive layer 105 away from the second epitaxial layer 1013 .

[0114] In sub-step S28 , a first insulating layer 108 is formed on a side of the second epitaxial layer 1013 away from the first epitaxial layer 1011 , and a predetermined position of the first insulating layer 108 corresponding to the reflective layer 107 is exposed and etched to form a second connecting hole 1081 .

[0115] In sub-step S29, a second insulating layer 109 is formed on the side of the first insulating layer 108 away from the second epitaxial layer 1013; the position of the second insulating layer 109 corresponding to the second connecting hole 1081 is exposed and etched to form a third connecting hole 1091, the second connecting hole 1081 is connected to the third connecting hole 1091, and the third conductive layer 110 is filled in the second connecting hole 1081 and the third connecting hole 1091.

[0116] In some embodiments, the above step S6 includes sub-steps S61 to S63.

[0117] In sub-step S61 , a dielectric layer 103 is formed on the light-emitting mesa structure 101 in a direction away from the driving backplane 200 ; a predetermined position of the dielectric layer 103 corresponding to the light-emitting end 1014 is exposed and etched to form a second through hole.

[0118] In sub-step S62 , a first barrier layer 102 is formed on the sidewalls of the dielectric layer 103 .

[0119] In sub-step S63 , a first conductive layer 104 is formed at least on the surface of the light-emitting end 1014 of the light-emitting mesa structure 101 . The first conductive layer 104 is electrically connected to the first epitaxial layer 1011 .

[0120] In some embodiments, the above step S6 includes sub-steps S64 to S66.

[0121] In sub-step S64 , a first barrier layer 102 is formed on the sidewalls of the light-emitting mesa structure 101 .

[0122] In sub-step S65 , a dielectric layer 103 is formed on the light-emitting mesa structure 101 in a direction away from the driving backplane 200 ; a preset position of the dielectric layer 103 corresponding to the light-emitting end 1014 is exposed and etched to form a through hole, and a first barrier layer 102 is disposed between the light-emitting mesa structure 101 and the dielectric layer 103 .

[0123] In sub-step S66 , a first conductive layer 104 is formed at least on the surface of the light-emitting end 1014 of the light-emitting mesa structure 101 , and the first conductive layer 104 is electrically connected to the first epitaxial layer 1014 .

[0124] In some embodiments, the above step S23 includes sub-step S231.

[0125] In sub-step S231 , a reflective layer 107 is formed on a side of the second conductive layer 105 away from the second epitaxial layer 1013 , and the reflective layer 107 is completely filled in the first connecting hole; the reflective layer 107 is electrically connected to the second conductive layer 105 .

[0126] In some embodiments, the above step S23 includes sub-step S232 and step S233.

[0127] In sub-step S232 , a first reflective structure 1071 is formed on a side of the second conductive layer 105 away from the second epitaxial layer 1013 . The first reflective structure 1071 is formed in the first connecting hole. The first reflective structure 1071 is electrically connected to the second conductive layer 105 .

[0128] In sub-step S233 , a second reflective structure 1072 is formed on a side of the second barrier layer 106 away from the second conductive layer 105 .

[0129] Referring to the first embodiment of FIG1a , the first connecting hole of the second barrier layer 106 is filled with the first reflective structure 1071 of the reflective layer 107. The second conductive layer 105 contacts the reflective layer 107 only through the first reflective structure 1071. Referring to the third embodiment of FIG3 , no second barrier layer is provided between the second conductive layer 105 and the reflective layer 107, and the surface of the second conductive layer 105 away from the second epitaxial layer 1013 is completely covered with the reflective layer 107. In the micro-LED array structure 100 of the first embodiment of FIG1a , a second barrier layer 106 is provided, and the contact area between the reflective layer 107 and the second conductive layer 105 is relatively small. FIG9 includes the preparation method of FIG1a and FIG3 , wherein the epitaxial layer is etched, and the area of ​​the reflective window is larger than the contact area between the reflective layer 107 and the second conductive layer 105. Compared to the contact area between the reflective layer 107 and the second conductive layer 105 in the third embodiment of FIG3 , the second barrier layer 106 in the micro-LED array structure 100 of the first embodiment of FIG1a provides a larger reflective window area. Therefore, during the etching process, the alignment area of ​​the reflective window is also relatively large. As shown in Table 2, which shows the alignment area and IR yield data for the window, the alignment area increased from 13% to 66%, a five-fold improvement; the IR yield increased from 27% to 67%, a 2.5-fold improvement.

[0130] Table 2 Window alignment area and IR yield data

[0131] It should be noted that relational terms in this document, such as "first" and "second", are used only to distinguish an entity or operation from another entity or operation, and do not require or imply any actual relationship or order between these entities or operations. In addition, the words "include", "have" and "include" and other similar forms are intended to be equivalent in meaning and are open-ended, and one or more items following any of these words are not intended to be an exhaustive list of such one or more items, or to be limited to the listed one or more items.

[0132] As used herein, unless expressly stated otherwise, the term "or" encompasses all possible combinations unless not feasible. For example, if a component is stated to include either A or B, then unless expressly stated otherwise or not feasible, the component may include A, or B, or A and B. As a second example, if a component is stated to include either A, B, or C, then unless expressly stated otherwise or not feasible, the component may include A, or B, or C, or A and B, or A and C, or B and C, or A, B, and C.

[0133] In the foregoing description, embodiments have been described with reference to many specific details, which may vary depending on the implementation. Certain changes and modifications may be made to the described embodiments. Other embodiments will be clear to those skilled in the art in view of the description and practice of the invention disclosed herein. The description and examples are intended to be regarded as merely exemplary, with the true scope and spirit of the invention being indicated by the following claims. The order of steps shown in the accompanying drawings is also intended to be for illustrative purposes only and is not intended to be limited to any particular order of steps. Therefore, it will be understood by those skilled in the art that these steps may be performed in different orders while implementing the same method.

[0134] In the drawings and the specification, exemplary embodiments have been disclosed. However, many variations and modifications may be made to these embodiments. Therefore, although specific terms are employed, they are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A method for preparing a display panel, characterized in that The following steps are involved: Providing a growth substrate, on which an epitaxial layer is formed, and the epitaxial layer includes a first epitaxial layer, a light-emitting layer and a second epitaxial layer stacked in sequence from bottom to top; forming an insulating layer on a side of the second epitaxial layer away from the growth substrate; Exposing and etching a preset position of the insulating layer corresponding to the second epitaxial layer to form a connecting hole, and filling a third conductive layer in the connecting hole so that the third conductive layer is electrically connected to the second epitaxial layer; Providing a backplane substrate, on which a driving circuit layer is formed; Exposing and etching a position of the driving circuit layer on a side away from the backplane substrate and corresponding to the connecting hole to form a fourth connecting hole, and filling the fourth connecting hole with a fourth conductive layer; Bonding the driving circuit layer to the insulating layer so that the third conductive layer is electrically connected to the fourth conductive layer; peeling off the growth substrate; and The epitaxial layer is exposed and etched to form a light-emitting mesa structure.

2. The method for preparing a display panel according to claim 1, characterized in that: Before the step of bonding the driving circuit layer to the insulating layer, the method further comprises the following steps: At least one of the third conductive layer and the fourth conductive layer is exposed and etched to form at least one groove.

3. The method for preparing a display panel according to claim 2, characterized in that: Before the step of bonding the driving circuit layer to the insulating layer, the method further comprises the following steps: exposing and etching a side of the third conductive layer away from the second epitaxial layer to form a first groove; and The side of the fourth conductive layer away from the backplane substrate is exposed and etched to form a second groove.

4. The method for preparing a micro display panel according to claim 1, characterized in that , including the following steps: The third conductive layer is filled in the connecting hole and is flush with the surface of the insulating layer away from the second epitaxial layer; and The fourth conductive layer is filled in the fourth connecting hole and is flush with a surface of the driving circuit layer away from the backplane substrate.

5. A MicroLED connection structure, characterized in that include: An epitaxial layer, the epitaxial layer comprising a first epitaxial layer, a light emitting layer and a second epitaxial layer; an insulating layer, the insulating layer being disposed on a side of the second epitaxial layer away from the first epitaxial layer, the insulating layer having a connecting hole at a preset position corresponding to the second epitaxial layer; and A third conductive layer is filled in the connecting hole and is electrically connected to the second epitaxial layer.

6. The MicroLED connection structure according to claim 5, characterized in that: A first groove is disposed on a side of the third conductive layer away from the second epitaxial layer.

7. The MicroLED connection structure according to claim 6, characterized in that: The depth of the first groove is 2nm-20nm.

8. A driving backplane, characterized in that include: a backplane substrate; a driving circuit layer, the driving circuit layer being arranged on one side of the backplane substrate, and the side of the driving circuit layer away from the backplane substrate having a fourth connecting hole; as well as A fourth conductive layer is filled in the fourth connecting hole.

9. The driving backplane according to claim 8, characterized in that: A second groove is disposed on a side of the fourth conductive layer away from the backplane substrate.

10. The driving backplane according to claim 9, characterized in that: The depth of the second groove is 2nm-20nm.

11. The driving backplane according to claim 8, characterized in that: It further includes a contact point, which is arranged on the driving circuit layer, and the fourth conductive layer is electrically connected to at least two of the contact points.

12. A display panel, characterized in that include: A driving backplane, the driving backplane comprising a backplane substrate and a driving circuit layer, the driving circuit layer being arranged on one side of the backplane substrate; A micro LED array structure, the micro LED array structure comprising a plurality of light-emitting mesa structures, the light-emitting mesa structure comprising a first epitaxial layer, a light-emitting layer and a second epitaxial layer stacked in sequence from top to bottom; and an insulating layer, the insulating layer being disposed on the second epitaxial layer and having a connecting hole at a preset position corresponding to the second epitaxial layer, wherein the connecting hole is filled with a third conductive layer; Among them, the driving circuit layer has a fourth connecting hole at a position corresponding to the connecting hole on the side away from the backplane substrate, and the fourth connecting hole is filled with a fourth conductive layer; the insulating layer is fixed on the driving circuit board, and the third conductive layer is electrically connected to the fourth conductive layer.

13. The display panel according to claim 12, characterized in that: The third conductive layer and the fourth conductive layer adopt one of a single-layer structure and a multi-layer structure.

14. The display panel according to claim 13, characterized in that: The third conductive layer and the fourth conductive layer are made of a metal conductive material and a non-metal conductive material, the metal conductive material is at least one of Cu, Al, Sn, Pb, Ni, Ti, Ag, Au, Pt and ITO, and the non-metal conductive material is at least one of carbon fiber, carbon nanotube and graphene.

15. The display panel according to claim 12, characterized in that: The opening width of the connecting hole at a side close to the driving back plate is smaller than or larger than the opening width of the fourth connecting hole at a side away from the back plate substrate.

16. The display panel according to claim 15, characterized in that: The opening width of the connecting hole at a side close to the driving back plate and the opening width of the fourth connecting hole at a side away from the back plate substrate are 0.6 μm-2.0 μm.

17. The display panel according to claim 12, characterized in that: The invention further comprises a second conductive layer, which is arranged on a side of the second epitaxial layer away from the first epitaxial layer and is electrically connected to the second epitaxial layer and the third conductive layer.

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