Power supply automatic detection circuit for radio frequency switch

Abstract

The invention discloses a power supply automatic detection circuit for a radio frequency switch, and relates to the technical field of power supply automatic detection circuits. The detection circuit is directly powered by power supply voltage and comprises a two-stage inverter, a PMOS (P-channel Metal Oxide Semiconductor) tube, a resistor, a first NMOS (N-channel Metal Oxide Semiconductor) tube and a second NMOS tube, the source end of the PMOS tube is connected with the power supply voltage, the grid end and the drain end of the PMOS tube are connected together, the drain end of the PMOS tube is synchronously connected with one end of the resistor, the other end of the resistor is connected with the drain end of the first NMOS tube, and the other end of the resistor is connected with the drain end of the second NMOS tube. And the grid end and the drain end of the first NMOS tube are synchronously connected together. The invention provides an efficient solution for automatically detecting the power supply voltage to be compatible with the working application voltage of a 1.2 V / 1.8 V system, and has very high practical value in the aspects of improving the system compatibility of a product and enhancing the chip performance; the layout area is greatly reduced compared with traditional power supply circuit detection.

Description

Technical Field

[0001] The invention belongs to the technical field of automatic power detection circuits, and in particular relates to an automatic power detection circuit for a radio frequency switch. Background Art

[0002] In the field of RF front-end, RF switch is an important device with wide applications. With the increasing integration of chips and stronger performance, the demand for reducing power consumption is becoming more urgent.

[0003] Taking into account the specific application environment of the chip, different system applications have different system power supply voltages. On the one hand, some systems should use chips with smaller wafer manufacturing process line widths, such as 28nm or smaller process line widths to improve performance, and the system will be powered by a lower voltage such as 1.2V. Some other system applications may be applied to a higher power supply voltage such as 1.8V. Therefore, in order to improve the system compatibility of the chip without sacrificing performance, the chip needs to work with both high and low power supply voltages. In response to this technical problem, the automatic voltage detection circuit of the RF switch of this technical solution provides a new technical solution. Summary of the invention

[0004] The present invention provides an automatic power detection circuit for a radio frequency switch. The present invention aims at being compatible with 1.2V / 1.8V system working application voltages, and proposes an efficient solution for automatically detecting power supply voltages. The present invention has high practical value in terms of improving product system compatibility and enhancing chip performance, thereby solving the problems in the background technology.

[0005] In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

[0006] The present invention discloses an automatic power detection circuit for a radio frequency switch, which is directly powered by a power supply voltage and includes a two-stage inverter, a PMOS tube, a resistor, a first NMOS tube, and a second NMOS tube:

[0007] The source end of the PMOS tube is connected to the power supply voltage, the gate end and the drain end of the PMOS tube are connected together, and the drain end of the PMOS tube is synchronously connected to one end of the resistor, the other end of the resistor is connected to the drain end of the first NMOS tube, the gate end and the drain end of the first NMOS tube are synchronously connected together, the source end of the first NMOS tube is connected to the drain end of the second NMOS tube, the gate end of the second NMOS tube is used as the input end of the enable signal, and the source end of the second NMOS tube is grounded;

[0008] The two-stage inverter comprises a first inverter and a second inverter connected in series, wherein the first inverter is connected to the drain terminal of the PMOS tube.

[0009] Furthermore, the power supply voltage is 1.2V or 1.8V.

[0010] Furthermore, when the power supply voltage is 1.8V, a logic high level is output; and when the power supply voltage is 1.2V, a logic low level is output.

[0011] Furthermore, after the voltage is sampled by the sampling circuit composed of the PMOS tube, the resistor, the first NMOS tube and the second NMOS tube, the drain end of the PMOS tube is taken as the adopted voltage, and the adopted voltage is used as the sampling voltage. The sampling voltage is buffered by a two-stage inverter and then shaped and output.

[0012] Furthermore, the voltage is divided by connecting a PMOS tube connected by a diode, a resistor, and a first NMOS tube and a second NMOS tube connected by a diode in series to achieve voltage division of the power supply voltage.

[0013] Compared with the prior art, the present invention has the following beneficial effects:

[0014] (1) This solution proposes an efficient solution for automatically detecting power supply voltage to be compatible with 1.2V / 1.8V system operating application voltages. It has high practical value in terms of improving product system compatibility and enhancing chip performance.

[0015] (2) The layout area of ​​this solution is greatly reduced compared to traditional power circuit detection, and the power of the power detection circuit is smaller, usually less than 1uA, and the size is 1 / 15-1 / 20 of the traditional power detection circuit;

[0016] (2) This solution uses the power supply VDD to directly supply power, uses PMOS and NMOS and resistors to form a voltage sampling circuit, and the sampling circuit has a switch enable function; the detection output signal changes with the power supply voltage VDD, and has a dynamic detection feature;

[0017] (3) This scheme uses the drain end of the PMOS switch as the adopted voltage and the preliminary sampling voltage to achieve voltage sampling. The adopted voltage is achieved by connecting the diode-connected PMOS and the resistor and diode-connected NMOS in series to divide the power supply voltage;

[0018] (4) The power detection circuit of this solution determines the two power supply voltages of 1.2V and 1.8V through the logic output signal; when the power supply voltage is 1.8V, the logic output signal is high, and when the power supply voltage is 1.2V, the logic output signal is low, thereby realizing the function of the power supply detection circuit; through circuit simulation, the detection circuit of this technical solution can effectively detect the power supply voltage and output the logic signal, thereby completing the power supply detection output function.

[0019] Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0021] Figure 1 This is the schematic diagram of the traditional power supply detection working circuit;

[0022] Figure 2 This is a schematic diagram of a power automatic detection circuit for a radio frequency switch of the present invention;

[0023] Figure 3 A power supply detection simulation curve diagram of a specific embodiment of the present invention;

[0024] In the accompanying drawings, the components represented by the reference numerals are listed as follows:

[0025] VDD-power supply voltage, P-PMOS tube, R-resistance, N1-first NMOS tube, N2-second NMOS tube, EN-enable signal, Vs-sampling voltage, INV1-first inverter, INV2-second inverter, Vout-output voltage, VCP-first inverter output voltage, VCN-secondary inverter output voltage, R1-first resistor, R2-second resistor, C-capacitor. DETAILED DESCRIPTION

[0026] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0027] In the description of the present invention, it is necessary to understand that the terms "source end", "drain end", "gate end", "series" and the like indicate orientation or positional relationship and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the components or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention.

[0028] like Figure 1As shown, it is a schematic diagram of a conventional power supply detection working circuit, including resistor voltage division and voltage sampling, using resistor voltage division to realize that the sampling signal changes with the power supply voltage, and also includes a logic output part of the sampling voltage, the sampling voltage passes through a two-stage inverter logic output voltage, a first-stage inverter output voltage VCP and a second-stage inverter output voltage VCN; the specific circuit includes two first resistors R1 and a second resistor R2 connected in series, and a capacitor C connected in parallel on both sides of the second resistor R2;

[0029] Most traditional power detection circuits use resistor series voltage division to perform voltage sampling. In the traditional method, on the one hand, in order to achieve low module static power consumption, a larger resistor is required. On the other hand, the resistor with a large resistance value requires a large size, which consumes precious chip area. For example, in order to meet the static power consumption requirements, the resistor voltage division method of the traditional power detection circuit is usually used to achieve voltage sampling. A relatively large resistor, specifically MΩ level, is usually used. The other layout area is 1500%-2000% of the power detection circuit of this technical solution.

[0030] The reliability of traditional power supply inspection solutions is not high; the sampling resistor is connected in series to divide the voltage for voltage sampling, and the relationship between the sampling voltage and the power supply voltage is the resistor voltage division relationship. Therefore, the sampling voltage changes linearly with the power supply voltage fluctuation. The power supply fluctuation can easily lead to sampling errors, resulting in power supply inspection failure.

[0031] The power detection circuit mentioned in this article has a dynamic detection feature that the detection output signal changes with the power supply voltage VDD; the power detection circuit in this article has the characteristics of low power consumption and small size, and has low cost and low power consumption. The power consumption of the power detection circuit described in this article is usually less than 1uA, and the size is 1 / 15-1 / 20 of the traditional power detection circuit; through circuit simulation, the power detection circuit mentioned in this article can effectively detect the power supply voltage and output logic signals under different power supply voltages (1.2V and 1.8V), completing the power detection output function.

[0032] Specifically, the technical solution is as follows:

[0033] See also Figure 2 As shown, a power automatic detection circuit for a radio frequency switch of the present invention includes two parts, including a power supply voltage division and a voltage sampling part. The sampling voltage Vs after the voltage division of different working voltages VDD changes with the power supply voltage; and also includes a shaping output part of the sampling voltage. The sampling voltage Vs is shaped and logically output by INV1 and INV2 to convert the sampling voltage into a logic output voltage Vout; when the power supply voltage is 1.8V, the logic output signal Vout is high, and when the power supply voltage is 1.2V, the logic output signal Vout is low;

[0034] The detection circuit is specifically powered directly by the power supply voltage VDD, and includes a two-stage inverter, a PMOS tube P, a resistor R, a first NMOS tube N1 and a second NMOS tube N2:

[0035] The source end of the PMOS tube P is connected to the power supply voltage VDD, the gate end and the drain end of the PMOS tube P are connected together, and the drain end of the PMOS tube P is synchronously connected to one end of the resistor R, the other end of the resistor R is connected to the drain end of the first NMOS tube N1, the gate end and the drain end of the first NMOS tube N1 are synchronously connected together, the source end of the first NMOS tube N1 is connected to the drain end of the second NMOS tube N2, the gate end of the second NMOS tube N2 is used as the input end of the enable signal EN, and the source end of the second NMOS tube N2 is grounded;

[0036] The two-stage inverter includes a first inverter INV1 and a second inverter INV2 connected in series. The first inverter INV1 is connected to the drain terminal of the PMOS tube P, and the terminal of the second inverter INV2 is the output voltage Vout.

[0037] The power supply voltage VDD is 1.2V or 1.8V.

[0038] When the power supply voltage VDD is 1.8V, a logic high level is output; when the power supply voltage VDD is 1.2V, a logic low level is output.

[0039] Among them, after the voltage is sampled by the sampling circuit composed of the PMOS tube P, the resistor R, the first NMOS tube N1 and the second NMOS tube N2, the drain end of the PMOS tube P is taken as the adopted voltage, and the adopted voltage is used as the sampling voltage Vs. The sampling voltage Vs is buffered by two stages of inverters and then shaped and output.

[0040] The voltage is divided by connecting a PMOS transistor P connected by a diode, a resistor R, and a first NMOS transistor N1 and a second NMOS transistor N2 connected by a diode in series to realize voltage division of the power supply voltage VDD.

[0041] In order to realize automatic power supply detection, this paper adopts the following technical steps to realize the entire circuit device: (1) The power supply voltage is sampled by voltage division using a diode in series with a resistor, and the sampled voltage changes with the power supply; (2) After obtaining the preliminary sampled voltage, it is shaped and output through an inverter buffer; (3) The sampled and shaped output voltage is subjected to logical operation. When the power supply voltage is 1.8V, the output logic is high, and when the power supply voltage is 1.2V, the output logic is low.

[0042] Logic judgment: The power detection circuit in this article judges the two power supply voltages of 1.2V and 1.8V through the logic output signal. When the power supply voltage is 1.8V, the logic output signal is high, and when the power supply voltage is 1.2V, the logic output signal is low, realizing the function of the power supply detection circuit.

[0043] like Figure 3 The figure shows the power detection simulation curve. The figure compares the output signal waveform of the power detection circuit when the power supply voltage VDD is 1.8V and 1.2V respectively; Figure 3 When the power supply voltage VDD is 1.8V, the logic output signal Vout is 1.8V, a high level; when the power supply voltage VDD is 1.2V, the logic output signal Vout is 0V, a low level.

[0044] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A power automatic detection circuit for a radio frequency switch, characterized in that: The detection circuit is directly powered by the power supply voltage (VDD), and includes a two-stage inverter, a PMOS tube (P), a resistor (R), a first NMOS tube (N1) and a second NMOS tube (N2): The source end of the PMOS tube (P) is connected to the power supply voltage (VDD), the gate end and the drain end of the PMOS tube (P) are connected together, and the drain end of the PMOS tube (P) is synchronously connected to one end of the resistor (R), the other end of the resistor (R) is connected to the drain end of the first NMOS tube (N1), the gate end and the drain end of the first NMOS tube (N1) are synchronously connected together, the source end of the first NMOS tube (N1) is connected to the drain end of the second NMOS tube (N2), the gate end of the second NMOS tube (N2) is used as the input end of the enable signal (EN), and the source end of the second NMOS tube (N2) is grounded; The two-stage inverter comprises a first inverter (INV1) and a second inverter (INV2) connected in series, wherein the first inverter (INV1) is connected to the drain lead-out position of the PMOS tube (P).

2. The automatic power detection circuit for a radio frequency switch according to claim 1, characterized in that: The power supply voltage (VDD) is 1.2V or 1.8V.

3. The automatic power detection circuit for a radio frequency switch according to claim 2, characterized in that: When the power supply voltage (VDD) is 1.8V, the output is a logic high level; when the power supply voltage (VDD) is 1.2V, the output is a logic low level.

4. The automatic power detection circuit for a radio frequency switch according to claim 1, characterized in that: After voltage sampling is performed by a sampling circuit composed of a PMOS tube (P), a resistor (R), a first NMOS tube (N1) and a second NMOS tube (N2), a voltage is drawn out from the drain end of the PMOS tube (P) as an adopted voltage, and the adopted voltage is used as a sampling voltage (Vs). The sampling voltage (Vs) is buffered by a two-stage inverter and then shaped and output.

5. The automatic power detection circuit for a radio frequency switch according to claim 4, characterized in that: The voltage is divided by connecting a PMOS tube (P) connected by a diode, a resistor (R), and a first NMOS tube (N1) and a second NMOS tube (N2) connected by a diode in series to achieve voltage division of a power supply voltage (VDD).

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