Adaptive calibration power consumption measuring circuit based on FPGA and calibration method

Abstract

The invention discloses a self-adaptive calibration power consumption measuring circuit based on an FPGA and a calibration method. The circuit comprises a calibration module, a power consumption acquisition module and a control module. The method comprises the following steps: based on the number of coarse calibration maximum lookup table units and the length of an observable delay line, performing coarse calibration on a sensor input clock to obtain a sensor input clock after preliminary calibration; based on the maximum number of fine calibration CARRY4 primitives and the length of an observable delay line, performing fine calibration on the sensor input clock after preliminary calibration by adopting a dichotomy until a calibration threshold range is met, and obtaining a phase difference; and calibrating the power consumption measurement value according to the phase difference to obtain a calibrated power consumption measurement value. According to the embodiment of the invention, the delay chain length required by the TDC can be greatly reduced, so that the resource utilization rate is optimized, and the TDC can realize efficient measurement in a shorter delay chain. The method can be widely applied to the technical field of on-chip power consumption data analysis.

Description

Technical Field

[0001] The present application relates to the technical field of on-chip power consumption data analysis, and in particular to an FPGA-based adaptive calibration power consumption measurement circuit and calibration method. Background Art

[0002] The advanced sensor used to measure FPGA voltage fluctuations is the time-to-digital converter (TDC). TDC uses a delay chain structure composed of a fast carry unit (CARRY4) to reflect voltage fluctuations through the propagation position of the clock signal edge in the carry chain. The delay chain-based TDC is currently used as a voltage sensor to detect nanosecond voltage fluctuations, with a sampling rate 500 times that of the Xilinx on-chip analog-to-digital converter. Later, the TDC sensor was designed and calibrated, and the impact of transient voltage fluctuations caused by different switching activities on delay was analyzed. Subsequent research basically uses this structure.

[0003] Due to the large differences in manufacturing processes within and between chips, the exact length of the signal propagation path is usually unpredictable when designing a TDC sensor. Therefore, the length and layout of the TDC need to be manually adjusted according to different processes and frequency changes. After each adjustment, the bitstream must be recompiled and generated. This process is called calibration. The purpose of calibration is to ensure that the output register can make one edge of the signal fall within the observable delay chain when capturing the state of the clock signal. Since calibration is a long and trial-and-error process that consumes a lot of time and human resources, there is an urgent need to automate this process. Related technologies propose a TDC design with adjustable initial delay. The attacker can manually modify the number of components enabled in the initial delay segment through a multiplexer (MUX). However, this method still needs to be recompiled after modification, and has poor flexibility. In addition, a software-based calibration algorithm is proposed. The algorithm uses an exhaustive method. Although it can complete the calibration, the process is cumbersome and takes a long time.

[0004] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the invention

[0005] The main purpose of the embodiments of the present application is to propose an FPGA-based adaptive calibration power consumption measurement circuit and calibration method, which can significantly reduce the delay chain length required by the TDC, thereby optimizing resource utilization and enabling the TDC to achieve efficient measurement within a shorter delay chain.

[0006] To achieve the above-mentioned purpose, an embodiment of the present application proposes an FPGA-based adaptive calibration power consumption measurement circuit, the circuit comprising a calibration module, a power consumption acquisition module and a control module, the first output end of the control module is connected to the first input end of the calibration module, the second output end of the control module is connected to the first input end of the power consumption acquisition module, the second input end of the power consumption acquisition module is connected to the second input end of the calibration module, and the output end of the power consumption acquisition module is connected to the input end of the control module, wherein:

[0007] The control module is used to control the operation of the power consumption acquisition module through a start signal and an end signal, and to control the operation of the calibration module through a fine calibration control signal and a coarse calibration control signal;

[0008] The calibration module is used to delay and offset the sensor input clock according to the sampling clock to obtain the phase difference between the sensor input clock and the sampling clock;

[0009] The power consumption acquisition module is used to capture the propagation depth of the sensor input clock edge according to the phase difference and output calibrated power consumption data.

[0010] In some embodiments, the calibration module includes a fine calibration submodule and a coarse calibration submodule, and the fine calibration submodule is connected to the coarse calibration submodule via a wire, wherein:

[0011] The coarse calibration submodule is used to coarsely adjust the delay of the sensor input clock to ensure that the clock edge is within the range of the observable delay chain;

[0012] The fine calibration submodule is used to fine-tune the delay of the sensor input clock and accurately adjust the clock edge to the middle position of the observable delay chain.

[0013] In some embodiments, the fine calibration submodule includes a CARRY4 delay chain and a first thermometer code encoder, the CARRY4 delay chain includes a plurality of CARRY4 primitives, an output end of the first thermometer code encoder is connected to an input end of the CARRY4 delay chain, and the plurality of CARRY4 primitives are connected in cascade, wherein:

[0014] The first thermometer code encoder is used to convert the fine calibration control signal into a binary sequence control signal and use it as a selection signal for the CARRY4 delay chain;

[0015] The CARRY4 delay chain is used to generate a fine calibration delay offset based on the selection signal of the first thermometer code encoder to fine-tune the delay of the sensor input clock.

[0016] In some embodiments, the CARRY4 primitive includes a first multiplexer, a second multiplexer, a third multiplexer and a fourth multiplexer, the first input end of the first multiplexer, the first input end of the second multiplexer, the first input end of the third multiplexer and the first input end of the fourth multiplexer are all connected to the output end of the first thermometer code encoder, the output end of the first multiplexer is connected to the second input end of the second multiplexer, the output end of the second multiplexer is connected to the second input end of the third multiplexer, the output end of the third multiplexer is connected to the second input end of the fourth multiplexer, and the third input end of the first multiplexer, the third input end of the second multiplexer and the third input end of the third multiplexer are connected to the third input end of the fourth multiplexer.

[0017] In some embodiments, the coarse calibration submodule includes a lookup table delay chain module and a second thermometer code encoder, the lookup table delay chain module includes a plurality of lookup table units, the 10th pins of the plurality of lookup table units are connected to each other, the first output end of the second thermometer code encoder is connected to the 11th pins of the plurality of lookup table units, the second output end of the second thermometer code encoder is connected to the 13th pins of the plurality of lookup table units, and the plurality of lookup table units are cascaded to each other, wherein:

[0018] The second thermometer code encoder is used to convert the coarse calibration control signal into a binary sequence control signal and use it as a selection signal for the lookup table delay chain module;

[0019] The lookup table delay chain module is used to generate a coarse calibration delay offset based on the selection signal of the second thermometer code encoder, coarsely adjust the delay of the sensor input clock, and generate a phase difference between the sensor input clock and the sampling clock.

[0020] In some embodiments, the power consumption acquisition module includes a plurality of on-chip voltage sensors, and the on-chip voltage sensor includes an observable delay chain module, an output register, and a Hamming weight encoder, the output end of the observable delay chain module is connected to the D input end of the output register, and the Q output end of the output register is connected to the input end of the Hamming weight encoder, wherein:

[0021] The observable delay chain module is used to obtain a time interval of a phase difference between the sensor input clock and the sampling clock;

[0022] The output register is used to obtain the propagation depth of the sensor input clock edge according to the time interval and determine the propagation position of the sensor input clock edge;

[0023] The Hamming weight encoder is used to convert the propagation position of the sensor input clock edge into a Hamming weight value and output the calibrated power consumption data.

[0024] To achieve the above object, another aspect of the embodiment of the present application provides a calibration method for an adaptive calibration power consumption measurement circuit based on FPGA, the method comprising the following steps:

[0025] Set the maximum number of lookup table cells for coarse calibration, the maximum number of CARRY4 primitives for fine calibration, the length of the observable delay line and the calibration threshold range;

[0026] Based on the number of the coarse calibration maximum lookup table units and the length of the observable delay line, the sensor input clock is coarsely calibrated to obtain a preliminarily calibrated sensor input clock;

[0027] Based on the maximum number of the fine calibration CARRY4 primitives and the length of the observable delay line, a binary method is used to finely calibrate the sensor input clock after the preliminary calibration until a calibration threshold range is met to obtain a phase difference;

[0028] The power consumption measurement value is calibrated according to the phase difference to obtain a calibrated power consumption measurement value.

[0029] In some embodiments, the performing coarse calibration on the sensor input clock based on the number of the coarse calibration maximum lookup table units and the length of the observable delay line to obtain the sensor input clock after preliminary calibration includes:

[0030] adjusting the output of the observable delay chain from an initial state to a saturated state;

[0031] Based on the number of the rough-calibrated maximum lookup table units, the initial delay is increased by gradually increasing the number of lookup table units until the edge of the sensor input clock enters the length range of the observable delay line, and the preliminarily calibrated sensor input clock is output.

[0032] In some embodiments, the fine calibration of the sensor input clock after the preliminary calibration is performed by using a dichotomy method based on the maximum number of the fine calibration CARRY4 primitives and the length of the observable delay line until the calibration threshold range is satisfied to obtain the phase difference, including:

[0033] Based on the maximum number of fine-calibrated CARRY4 primitives, increasing the number of CARRY4 primitives one by one;

[0034] The sensor input clock after the preliminary calibration is finely calibrated by binary division, and the edge of the sensor input clock after the preliminary calibration is adjusted to the middle range of the length of the observable delay line to meet the calibration threshold range, thereby obtaining the phase difference.

[0035] In some embodiments, the combining the phase difference and the length of the observable delay line to calibrate the power consumption measurement value to obtain the calibrated power consumption measurement value includes:

[0036] determining a time interval according to the phase difference;

[0037] Acquire the propagation depth of the sensor input clock edge according to the time interval, and determine the propagation position of the sensor input clock edge;

[0038] The propagation position of the sensor input clock edge is converted into a Hamming weight value, and the calibrated power consumption measurement value is output.

[0039] The embodiments of the present application include at least the following beneficial effects: The present application provides an FPGA-based adaptive calibration power consumption measurement circuit and calibration method. The scheme ensures that the calibration process is faster and more accurate through a two-stage calibration mechanism of coarse calibration and fine calibration, thereby improving the stability and adaptability of the system. The coarse calibration stage can significantly reduce the delay chain length required by the TDC, thereby optimizing resource utilization and enabling the TDC to achieve efficient measurement within a shorter delay chain. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is a structural schematic diagram of an FPGA-based adaptive calibration power consumption measurement circuit provided in an embodiment of the present application;

[0041] Figure 2 It is a schematic flow chart of the steps of a calibration method of an FPGA-based adaptive calibration power consumption measurement circuit provided in an embodiment of the present application;

[0042] Figure 3 is a schematic diagram of the structure of the fine calibration submodule provided in an embodiment of the present application;

[0043] Figure 4 is a schematic diagram of the structure of the coarse calibration submodule provided in an embodiment of the present application;

[0044] Figure 5 It is a structural diagram of the power consumption collection module provided in an embodiment of the present application;

[0045] Figure 6 It is a pseudo code diagram of an FPGA-based optimization calibration algorithm provided in an embodiment of the present application;

[0046] Figure 7is a schematic diagram of the calibration steps provided in the embodiment of the present application;

[0047] Figure 8 It is a structural schematic diagram of an adaptive calibration power consumption measurement system for an on-chip encryption circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is further described in detail below in conjunction with the accompanying drawings and examples. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the embodiments of the present application. They are only examples of systems and methods consistent with some aspects of the embodiments of the present application as detailed in the attached claims.

[0049] It is understood that the terms "first", "second", etc. used in this application can be used to describe various concepts in this article, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another concept. For example, without departing from the scope of the embodiment of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if" and "if" as used herein can be interpreted as "at the time of" or "when" or "in response to determination".

[0050] The terms "at least one", "multiple", "each", "any", etc. used in this application, at least one includes one, two or more, multiple includes two or more, each refers to each of the corresponding multiple, and any refers to any one of the multiple.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0052] With the rapid expansion of cloud computing services, the demand for high-performance computing has increased significantly. Field Programmable Gate Arrays (FPGAs) have become a key choice to meet this demand due to their highly parallel architecture, flexible programmability, and excellent energy efficiency. Currently, cloud service providers are actively exploring the possibility of multi-tenant sharing of FPGAs, that is, allowing multiple tenants to share the physical resources of the same FPGA while being logically isolated from each other. However, these emerging cloud FPGA architectures have introduced new security risks while improving computing power and efficiency.

[0053] Side channel attacks are an attack method that uses unexpected physical information such as power consumption, time delay, and electromagnetic radiation generated during the operation of hardware devices to steal sensitive information. Unlike traditional cryptanalysis, side channel attacks do not rely on the mathematical principles of cryptographic algorithms, but obtain key data by monitoring and measuring the physical characteristics of hardware devices when executing algorithms. In side channel attacks, power consumption analysis is an effective attack method. Since power consumption data is associated with information being processed, traditional power consumption analysis usually relies on measurement equipment such as oscilloscopes to monitor power consumption fluctuations and then analyze power consumption traces. However, on the cloud FPGA platform, attackers cannot physically access the target device and cannot directly measure power consumption leakage, which makes traditional attack methods difficult to work. However, since tenants on a multi-tenant shared FPGA platform share a power distribution network, during the operation of the encryption algorithm, attackers can use specific power consumption measurement circuits to capture voltage fluctuations and recover encryption keys through remote power consumption analysis attacks, revealing potential security risks of multi-tenant shared FPGAs.

[0054] In view of this, an embodiment of the present application provides an FPGA-based adaptive calibration power consumption measurement circuit. By introducing a calibration module, the problem of a too long TDC delay chain is effectively avoided. Considering the importance of the concealment of the power consumption measurement circuit in applications such as side channel attacks, the observability of the TDC is effectively reduced, thereby enhancing the security of the measurement process.

[0055] Reference Figure 1 , Figure 1 A flowchart of an FPGA-based adaptive calibration power consumption measurement circuit provided by an embodiment of the present invention, referring to Figure 1 The circuit includes a calibration module, a power consumption acquisition module and a control module, wherein the first output end of the control module is connected to the first input end of the calibration module, the second output end of the control module is connected to the first input end of the power consumption acquisition module, the second input end of the power consumption acquisition module is connected to the second input end of the calibration module, and the output end of the power consumption acquisition module is connected to the input end of the control module, wherein:

[0056] The control module is used to control the operation of the power consumption acquisition module through a start signal and an end signal, and to control the operation of the calibration module through a fine calibration control signal and a coarse calibration control signal;

[0057] The calibration module is used to delay and offset the sensor input clock according to the sampling clock to obtain the phase difference between the sensor input clock and the sampling clock;

[0058] Specifically, the calibration module includes a fine calibration submodule and a coarse calibration submodule, and the fine calibration submodule and the coarse calibration submodule are connected by lines, wherein the coarse calibration submodule is used to coarsely adjust the delay of the sensor input clock to ensure that the clock edge is within the range of the observable delay chain; the fine calibration submodule is used to fine-tune the delay of the sensor input clock to accurately adjust the clock edge to the middle position of the observable delay chain.

[0059] In this embodiment, the calibration module is composed of two submodules: fine calibration and coarse calibration. The function of the coarse calibration submodule is to roughly adjust the delay of the calibration module to ensure that the clock edge is within the range of the observable delay chain. The function of the fine calibration submodule is to further fine-tune the coarse calibration to accurately adjust the clock edge to the middle position of the observable delay chain.

[0060] More specifically, the fine calibration submodule includes a CARRY4 delay chain and a first thermometer code encoder, the CARRY4 delay chain includes a plurality of CARRY4 primitives, the output end of the first thermometer code encoder is connected to the input end of the CARRY4 delay chain, and the plurality of CARRY4 primitives are cascaded, wherein the first thermometer code encoder is used to convert a fine calibration control signal into a binary sequence control signal and use it as a selection signal for the CARRY4 delay chain; the CARRY4 delay chain is used to generate a fine calibration delay offset based on the selection signal of the first thermometer code encoder, and to fine-tune the delay of the sensor input clock.

[0061] In this embodiment, the fine calibration submodule is composed of a CARRY4 delay chain and a thermometer code encoder, such as Figure 3 As shown in Figure 1. The function of the CARRY4 delay chain is to provide a small delay offset so that the input clock signal can be cut into the delay chain at different depths. The function of the thermometer code encoder is to convert the control signal into a binary sequence and use it as the selection signal of the carry multiplexer on the CARRY4 delay chain.

[0062] The input clock is connected to all inputs in the delay chain that can be selected by the carry multiplexer, allowing the clock to enter the CARRY4 primitive at different depths of the delay chain, thereby providing small delay offsets on the time scale of a single MUX element within the CARRY4. Since the fine calibration submodule is more sensitive to small delay variations, it is placed before the coarse calibration submodule to take advantage of the balanced clock tree provided by the mixed-mode clock manager, ensuring a more linear step during the fine calibration process.

[0063] The CARRY4 primitive includes a first multiplexer, a second multiplexer, a third multiplexer and a fourth multiplexer. The first input terminal of the first multiplexer, the first input terminal of the second multiplexer, the first input terminal of the third multiplexer and the first input terminal of the fourth multiplexer are all connected to the output terminal of the first thermometer code encoder, the output terminal of the first multiplexer is connected to the second input terminal of the second multiplexer, the output terminal of the second multiplexer is connected to the second input terminal of the third multiplexer, the output terminal of the third multiplexer is connected to the second input terminal of the fourth multiplexer, and the third input terminal of the first multiplexer, the third input terminal of the second multiplexer, the third input terminal of the third multiplexer are connected to the third input terminal of the fourth multiplexer.

[0064] The coarse calibration submodule includes a lookup table delay chain module and a second thermometer code encoder, the lookup table delay chain module includes a plurality of lookup table units, the I 0th pins of the plurality of lookup table units are connected to each other, the first output end of the second thermometer code encoder is connected to the I 1th pin of the plurality of lookup table units, the second output end of the second thermometer code encoder is connected to the I 3rd pin of the plurality of lookup table units, and the plurality of lookup table units are cascaded to each other, wherein the second thermometer code encoder is used to convert a coarse calibration control signal into a binary sequence control signal and use it as a selection signal of the lookup table delay chain module; the lookup table delay chain module is used to generate a coarse calibration delay offset based on the selection signal of the second thermometer code encoder, coarsely adjust the delay of the sensor input clock, and generate a phase difference between the sensor input clock and the sampling clock.

[0065] In this embodiment, the coarse calibration submodule consists of a lookup table (LUT) delay chain and a thermometer code encoder, such as Figure 4 As shown in the figure, the function of the LUT delay chain is to provide a larger delay offset than CARRY4 and to make a coarse adjustment to the delay. The function of the thermometer code encoder is to convert the control signal into a binary sequence and use it as the selection signal for the clock input and transmission on the LUT delay chain.

[0066] The truth table of the LUT is configured as 64'h00000000000088c0. Similar to the cascade mode of the CARRY4 element, the output of the fine calibration submodule is used as the input of the I 0 port of all LUTs in the coarse calibration submodule. For example, in the shortest calibration path, the clock passes through the last MUX of the fine calibration CARRY4 element and a LUT of the coarse calibration to reach the input of the power acquisition module.

[0067] The power consumption acquisition module is used to capture the propagation depth of the sensor input clock edge according to the phase difference and output the calibrated power consumption data.

[0068] Specifically, the power consumption acquisition module includes several on-chip voltage sensors, which include an observable delay chain module, an output register and a Hamming weight encoder. The output end of the observable delay chain module is connected to the D input end of the output register, and the Q output end of the output register is connected to the input end of the Hamming weight encoder. The observable delay chain module is used to obtain the time interval of the phase difference between the sensor input clock and the sampling clock; the output register is used to obtain the propagation depth of the sensor input clock edge according to the time interval and determine the propagation position of the sensor input clock edge; the Hamming weight encoder is used to convert the propagation position of the sensor input clock edge into a Hamming weight value and output calibrated power consumption data.

[0069] In this embodiment, the power consumption acquisition module integrates multiple on-chip voltage sensors with TDC as the core. The number of TDCs can be specified at compile time, ranging from 1 to 4. Each voltage sensor consists of an observable delay chain, an output register, and a Hamming weight encoder, such as Figure 5 As shown in the figure, the observable delay chain reflects the fluctuation of the on-chip voltage through the delay change of the cascaded CARRY4, the output register captures the state of the observable delay chain, and the Hamming weight encoder converts the binary sequence captured by the register into a low-bit-width Hamming weight value.

[0070] The observable delay chain consists of CARRY4, and the output of the calibration module serves as the carry input of the delay chain. The output register is connected to each carry output of the delay chain, and the phase difference between the sampling clock provided by the calibration module and the input clock of the delay chain enables the register to capture the propagation depth of the input clock edge. The series of 0s and 1s stored in the register is the original output of the TDC, reflecting the propagation position of the clock edge. In order to reduce the storage and transmission pressure caused by the direct transmission of the TDC register value, Hamming weight encoding is used to represent the propagation depth of the clock edge. The encoder is based on the adder chain design, which converts the binary sequence in the TDC register into a Hamming weight value. Finally, the output of the power consumption acquisition module is a plurality of Hamming weight values.

[0071] In addition, it should be noted that the multiple output values ​​of the power consumption acquisition module are then fed back to the control module, which adjusts the number of delay elements enabled in the coarse calibration and fine calibration stages according to the calibration algorithm, and determines whether the calibration is successful at the end of the calibration, and finally outputs a success or failure signal. In addition, through the multiplexer, the output values ​​of different voltage sensors can be selected to input into the calibration module, thereby realizing independent calibration of multiple voltage sensors.

[0072] In summary, the adaptive calibration power consumption measurement circuit proposed in the embodiment of the present invention is composed of three parts: a calibration module, a power consumption acquisition module and a control module. The function of the calibration module is to provide a phase difference between the input clock and the sampling clock to ensure that the edge of the input clock signal is always within the range of the observable delay chain. The function of the power consumption acquisition module is to capture the propagation depth of the clock edge through the on-chip voltage sensor, and use the delay change to reflect the fluctuation of the on-chip voltage. The function of the control module is to determine the adjustment direction of the calibration based on the calibration algorithm and the output of the power consumption acquisition module, and provide the corresponding configuration signal to the calibration module.

[0073] See also Figure 2 The embodiment of the present application also provides a calibration method of an FPGA-based adaptive calibration power consumption measurement circuit, which can implement the above-mentioned FPGA-based adaptive calibration power consumption measurement circuit, and the method includes the following steps:

[0074] S100, setting the maximum number of lookup table units for coarse calibration, the maximum number of CARRY4 primitives for fine calibration, the length of the observable delay line and the calibration threshold range;

[0075] S200, based on the number of coarsely calibrated maximum lookup table units and the length of the observable delay line, coarsely calibrate the sensor input clock to obtain a preliminarily calibrated sensor input clock;

[0076] It should be noted that, in some embodiments, step S200 may include: S210, adjusting the output of the observable delay chain from an initial state to a saturation state; S220, based on the coarse calibration of the maximum number of lookup table units, increasing the initial delay by increasing the number of lookup table units one by one until the edge of the sensor input clock enters the length range of the observable delay line, and outputting the sensor input clock after preliminary calibration.

[0077] S300, based on the maximum number of fine-calibrated CARRY4 primitives and the length of the observable delay line, fine-calibrate the sensor input clock after the preliminary calibration by using a binary search method until the calibration threshold range is met to obtain a phase difference;

[0078] It should be noted that, in some embodiments, step S300 may include: S310, based on the maximum number of fine-calibrated CARRY4 primitives, increasing the number of CARRY4 primitives one by one; S320, performing fine calibration on the sensor input clock after the preliminary calibration by bisection, adjusting the edge of the sensor input clock after the preliminary calibration to the middle range of the length of the observable delay line to meet the calibration threshold range, and obtaining the phase difference.

[0079] S400, calibrating the power consumption measurement value according to the phase difference to obtain a calibrated power consumption measurement value;

[0080] It should be noted that, in some embodiments, step S400 may include: S410, determining the time interval based on the phase difference; S420, obtaining the propagation depth of the sensor input clock edge based on the time interval, and determining the propagation position of the sensor input clock edge; S430, converting the propagation position of the sensor input clock edge into a Hamming weight value, and outputting the calibrated power consumption measurement value.

[0081] In some specific embodiments, the present invention improves the calibration algorithm based on software and proposes an optimized calibration algorithm based on FPGA. The pseudo code of the calibration process algorithm is as follows: Figure 6 In this algorithm, δ min and δ max Represents the upper and lower limits of the final calibration output, which can be adjusted by modifying the macro definition to meet different calibration accuracy requirements. Usually, these two parameters are set around N / 2.

[0082] The purpose of calibration is to ensure that when the output register captures the clock signal state, a certain edge of the clock signal falls within the range of the observable delay chain. You can choose the rising edge or the falling edge for calibration. Here, the rising edge is taken as an example. The calibration steps are as follows: Figure 7 shown.

[0083] The whole calibration process can be divided into two stages: coarse calibration and fine calibration. Figure 7 Steps 1 to 3 in : First, adjust the output of the observable delay chain from its initial state to the saturation state ( Figure 7 Then, by gradually increasing the number of LUTs, the initial delay is increased until the rising edge of the clock signal enters the range of the observable delay chain ( Figure 7 3 in ), thus completing the coarse calibration stage.

[0084] After entering the fine calibration stage, due to the small delay step, in order to avoid the long calibration time caused by adding and subtracting delay units one by one, the binary method is used to improve the adjustment efficiency, and finally the rising edge is accurately adjusted to the middle range of the observable delay chain ( Figure 7 4 in the .

[0085] Finally, the application of the circuit constructed by the embodiment of the present invention is described. The proposed adaptive calibration power consumption measurement circuit and the corresponding calibration algorithm are implemented on the Zedboard development board equipped with the Xilinx ZYNQ chip. Vivado2022.2 is used to synthesize the power consumption measurement circuit, and the maximum sampling rate can reach 265MHz. The key resources required for the adaptive calibration process of the power consumption measurement circuit are shown in Table 1.

[0086] Table 1 Data table of resource usage of adaptive calibration part

[0087] \ LUT FF CARRY4 Coarse calibration 16 0 0 Fine calibration 0 0 16 Observable Delay Chain 0 96 24

[0088] This embodiment further proposes a system for collecting and analyzing power consumption of an on-chip encryption circuit based on an adaptive calibration power consumption measurement circuit, such as Figure 8 The system includes the programmable logic of the ZYNQ chip and the processing system of the ZYNQ chip, specifically:

[0089] For the programmable logic (PL) of the ZYNQ chip: it is used to implement encryption and power consumption measurement, and to temporarily store and transmit power consumption data.

[0090] Among them, the specific modules required to implement encryption include:

[0091] 1) Encryption circuit: The encryption circuit running on the FPGA chip provides a signal indicating the end of encryption to the control module and reads the plaintext data to be encrypted from the encrypted data storage module.

[0092] 2) Encryption circuit control module: sends an encryption start signal to the encryption circuit to control the encryption circuit to read plaintext data.

[0093] 3) Encrypted data storage module: It consists of a true dual-port random access memory (RAM) and a corresponding AXI BRAM controller, used to store plaintext and ciphertext, with a read and write bit width of 32 bits.

[0094] The specific modules required to implement power consumption measurement include:

[0095] 1) Calibration module: Through two stages of coarse calibration and fine calibration, the on-chip voltage sensor is calibrated quickly and accurately to adjust one edge of the clock signal to the middle of the observable delay chain.

[0096] 2) Power consumption acquisition module: It contains multiple independent on-chip voltage sensors, each of which consists of an observable delay chain, an output register, and a Hamming weight encoder. The original output of the register is 96 bits, which is compressed to 1 byte by the encoder, and finally generates multiple Hamming weight values ​​as the output of power consumption data.

[0097] 3) FIFO buffer: used to temporarily store the collected power consumption data. The data width is 1 byte and the depth can be configured according to the collection time length during compilation.

[0098] 4) AXIDatamover IP: used to implement direct memory access and complete the transmission of large amounts of power consumption data. After a power consumption acquisition is completed, AXIDatamover IP writes the data in the FIFO buffer to DDR.

[0099] 5) Control module: responsible for controlling the start and end of the power consumption acquisition module, the data read and write operations of the FIFO cache, and configuring the start address, data length and data block content written to the DDR by the AXIDatamover IP.

[0100] For the Zynq chip's processing system (PS): used for storage, access, and advanced analysis of power consumption data, and executing specific algorithms to extract key information from the collected data and obtain the required results, including:

[0101] 1) DDR controller: provides efficient data storage and access capabilities, and supports large-scale power-saving data transmission between PL and PS.

[0102] 2) ARM processor: used for analyzing and processing power consumption data, and also responsible for configuring the PL-side encryption circuit and power consumption measurement circuit.

[0103] In the specific implementation process, the host computer is required to cooperate with the power consumption measurement system to complete power consumption collection and analysis. The host computer can generally run on a local computer.

[0104] In addition, it should be noted that in addition to the methods mentioned in this embodiment, the following changes can also be made: the encryption circuit can be replaced with a soft-core processor or a neural network accelerator, and the control module and the storage module can be adjusted accordingly to build an adaptive calibration power consumption measurement system for soft-core processors and neural network accelerators. The system can be used to identify the instructions currently executed by the soft-core processor, and to parse the parameter configuration and network structure of the neural network accelerator, thereby realizing accurate power consumption collection and in-depth analysis for different computing architectures.

[0105] In summary, the embodiments of the present invention have the following improvements compared to the prior art:

[0106] 1) An FPGA-based optimization calibration algorithm is proposed to achieve efficient automatic calibration without relying on complex software processing, thereby significantly improving the deployment convenience of the power consumption measurement circuit. Through the dual-stage calibration mechanism of coarse calibration and fine calibration, combined with the adjustment strategy of binary optimization, the calibration process is ensured to be faster and more accurate, and the stability and adaptability of the system are improved.

[0107] 2) By introducing the calibration module, the problem of too long TDC delay chain is effectively avoided. In the rough calibration stage, a LUT with a delay much greater than CARRY4 is used as a delay unit, which greatly reduces the delay chain length required by TDC, thereby optimizing resource utilization and enabling TDC to achieve efficient measurement in a shorter delay chain. In addition, considering the importance of the concealment of power consumption measurement circuits in applications such as side channel attacks, the optimization scheme of the present invention effectively reduces the observability of TDC and enhances the security of the measurement process.

[0108] 3) The designed calibration module can select the output values ​​of different voltage sensors through a multiplexer to achieve independent calibration of multiple sensors. This architecture allows a single calibration module to efficiently manage multiple sensors, reducing the reuse of hardware resources and improving overall resource utilization. In addition, the calibration module has flexible configuration capabilities and can adapt to different numbers of TDCs and multiple application requirements, thereby enhancing the scalability of the system and being suitable for power consumption monitoring and analysis in different scenarios.

[0109] It can be understood that the contents of the above method embodiments are all applicable to the present circuit embodiment, the functions specifically implemented by the present circuit embodiment are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0110] The preferred embodiments of the present invention are described above with reference to the accompanying drawings, but the scope of the rights of the present invention is not limited thereto. Any modification, equivalent substitution and improvement made by a person skilled in the art without departing from the scope and essence of the present invention should be within the scope of the rights of the present invention.

Claims

1. An adaptive calibration power consumption measurement circuit based on FPGA, characterized in that: The circuit includes a calibration module, a power consumption acquisition module and a control module, wherein a first output end of the control module is connected to a first input end of the calibration module, a second output end of the control module is connected to a first input end of the power consumption acquisition module, a second input end of the power consumption acquisition module is connected to a second input end of the calibration module, and an output end of the power consumption acquisition module is connected to an input end of the control module, wherein: The control module is used to control the operation of the power consumption acquisition module through a start signal and an end signal, and to control the operation of the calibration module through a fine calibration control signal and a coarse calibration control signal; The calibration module is used to delay and offset the sensor input clock according to the sampling clock to obtain the phase difference between the sensor input clock and the sampling clock; The power consumption acquisition module is used to capture the propagation depth of the sensor input clock edge according to the phase difference and output calibrated power consumption data.

2. The circuit according to claim 1, characterized in that The calibration module includes a fine calibration submodule and a coarse calibration submodule, and the fine calibration submodule is connected to the coarse calibration submodule via a wire, wherein: The coarse calibration submodule is used to coarsely adjust the delay of the sensor input clock to ensure that the clock edge is within the range of the observable delay chain; The fine calibration submodule is used to fine-tune the delay of the sensor input clock and accurately adjust the clock edge to the middle position of the observable delay chain.

3. The circuit according to claim 2, characterized in that The fine calibration submodule includes a CARRY4 delay chain and a first thermometer code encoder, the CARRY4 delay chain includes a plurality of CARRY4 primitives, an output end of the first thermometer code encoder is connected to an input end of the CARRY4 delay chain, and the plurality of CARRY4 primitives are connected in cascade connection, wherein: The first thermometer code encoder is used to convert the fine calibration control signal into a binary sequence control signal and use it as a selection signal for the CARRY4 delay chain; The CARRY4 delay chain is used to generate a fine calibration delay offset based on the selection signal of the first thermometer code encoder to fine-tune the delay of the sensor input clock.

4. The circuit according to claim 3, characterized in that The CARRY4 primitive includes a first multiplexer, a second multiplexer, a third multiplexer and a fourth multiplexer, the first input end of the first multiplexer, the first input end of the second multiplexer, the first input end of the third multiplexer and the first input end of the fourth multiplexer are all connected to the output end of the first thermometer code encoder, the output end of the first multiplexer is connected to the second input end of the second multiplexer, the output end of the second multiplexer is connected to the second input end of the third multiplexer, the output end of the third multiplexer is connected to the second input end of the fourth multiplexer, and the third input end of the first multiplexer, the third input end of the second multiplexer and the third input end of the third multiplexer are connected to the third input end of the fourth multiplexer.

5. The circuit according to claim 2, characterized in that The coarse calibration submodule includes a lookup table delay chain module and a second thermometer code encoder, the lookup table delay chain module includes a plurality of lookup table units, the I0th pins of the plurality of the lookup table units are connected to each other, the first output end of the second thermometer code encoder is connected to the I1th pins of the plurality of the lookup table units, the second output end of the second thermometer code encoder is connected to the I3rd pins of the plurality of the lookup table units, and the plurality of the lookup table units are cascaded to each other, wherein: The second thermometer code encoder is used to convert the coarse calibration control signal into a binary sequence control signal and use it as a selection signal for the lookup table delay chain module; The lookup table delay chain module is used to generate a coarse calibration delay offset based on the selection signal of the second thermometer code encoder, coarsely adjust the delay of the sensor input clock, and generate a phase difference between the sensor input clock and the sampling clock.

6. The circuit according to claim 1, characterized in that The power consumption acquisition module includes a plurality of on-chip voltage sensors, and the on-chip voltage sensor includes an observable delay chain module, an output register and a Hamming weight encoder, the output end of the observable delay chain module is connected to the D input end of the output register, and the Q output end of the output register is connected to the input end of the Hamming weight encoder, wherein: The observable delay chain module is used to obtain a time interval of a phase difference between the sensor input clock and the sampling clock; The output register is used to obtain the propagation depth of the sensor input clock edge according to the time interval and determine the propagation position of the sensor input clock edge; The Hamming weight encoder is used to convert the propagation position of the sensor input clock edge into a Hamming weight value and output the calibrated power consumption data.

7. A calibration method for an adaptive calibration power consumption measurement circuit based on FPGA, characterized in that: The method comprises the following steps: Set the maximum number of lookup table cells for coarse calibration, the maximum number of CARRY4 primitives for fine calibration, the length of the observable delay line and the calibration threshold range; Based on the number of the coarse calibration maximum lookup table units and the length of the observable delay line, the sensor input clock is coarsely calibrated to obtain a preliminarily calibrated sensor input clock; Based on the maximum number of the fine calibration CARRY4 primitives and the length of the observable delay line, a binary method is used to finely calibrate the sensor input clock after the preliminary calibration until a calibration threshold range is met to obtain a phase difference; The power consumption measurement value is calibrated according to the phase difference to obtain a calibrated power consumption measurement value.

8. The method according to claim 7, characterized in that The step of roughly calibrating the sensor input clock based on the number of the roughly calibrated maximum lookup table units and the length of the observable delay line to obtain a preliminarily calibrated sensor input clock includes: adjusting the output of the observable delay chain from an initial state to a saturated state; Based on the number of the rough-calibrated maximum lookup table units, the initial delay is increased by gradually increasing the number of lookup table units until the edge of the sensor input clock enters the length range of the observable delay line, and the preliminarily calibrated sensor input clock is output.

9. The method according to claim 7, characterized in that: The fine calibration of the sensor input clock after the preliminary calibration is performed by using a dichotomy method based on the maximum number of the fine calibration CARRY4 primitives and the length of the observable delay line until the calibration threshold range is satisfied to obtain a phase difference, including: Based on the maximum number of fine-calibrated CARRY4 primitives, increasing the number of CARRY4 primitives one by one; The sensor input clock after the preliminary calibration is finely calibrated by binary division, and the edge of the sensor input clock after the preliminary calibration is adjusted to the middle range of the length of the observable delay line to meet the calibration threshold range, thereby obtaining the phase difference.

10. The method according to claim 7, characterized in that The step of calibrating the power consumption measurement value by combining the phase difference with the length of the observable delay line to obtain the calibrated power consumption measurement value includes: determining a time interval according to the phase difference; Acquire the propagation depth of the sensor input clock edge according to the time interval, and determine the propagation position of the sensor input clock edge; The propagation position of the sensor input clock edge is converted into a Hamming weight value, and the calibrated power consumption measurement value is output.

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