Multi-layer stacked motherboard testing method and device

Abstract

The present application discloses a method and device for testing a multi-layer stacked main board, relating to the technical field of main board testing. The disclosed method for testing a multi-layer stacked main board performs testing by using an electromagnetic detection signal that matches the specific structural parameters of the multi-layer stacked main board to obtain an electromagnetic anomaly area, and performs a hierarchical current injection test on the electromagnetic anomaly area through a probe to obtain an electrical anomaly area. Then, by spatially matching the obtained electromagnetic anomaly area and the electrical anomaly area to jointly determine defects, the accuracy of detecting the multi-layer stacked main board is improved. The above detection method does not require detecting each layer of the multi-layer stacked main board one by one, thus improving the testing efficiency of the multi-layer stacked main board.

Description

Technical Field

[0001] This application relates to the technical field of motherboard testing, and particularly to a method and device for testing multi-layer stacked motherboards. Background Art

[0002] Motherboard testing is used to ensure that the performance and quality of the motherboard meet the design requirements, and it is a crucial link in the manufacturing process of electronic products. With the continuous development of electronic technology, multi-layer stacked motherboards are widely used in various electronic devices due to their high density and high performance characteristics.

[0003] Traditional testing of multi-layer stacked motherboards generally involves testing each layer of the multi-layer stacked motherboard one by one, which is not only time-consuming and laborious with low efficiency, but also difficult to accurately detect some minor defects inside due to the complex interlayer structure of the multi-layer stacked motherboard.

[0004] The above content is only used to assist in understanding the technical solution of this application, and does not represent an admission that the above content is prior art. Summary of the Invention

[0005] The main purpose of this application is to provide a method and device for testing multi-layer stacked motherboards, aiming to improve the accuracy and testing efficiency of multi-layer stacked motherboard testing.

[0006] To achieve the above purpose, this application proposes a method for testing multi-layer stacked motherboards, and the method includes:

[0007] Determine the electromagnetic detection frequency band based on the number of layers and dielectric constant of the multi-layer stacked motherboard, and emit corresponding electromagnetic detection signals to the multi-layer stacked motherboard at the electromagnetic detection frequency band to obtain original electromagnetic field data;

[0008] Calculate the interlayer magnetic field gradient change rate based on the original electromagnetic field data;

[0009] When the interlayer magnetic field gradient change rate is greater than the preset magnetic field gradient change rate threshold, determine the corresponding electromagnetic anomaly area;

[0010] Perform hierarchical current injection testing in the electromagnetic anomaly area through a probe to obtain an electrical anomaly area;

[0011] Perform spatial matching between the electromagnetic anomaly area and the electrical anomaly area, and determine that there is an effective defect when the overlap degree between the two is higher than the preset threshold, and output the corresponding defect coordinates.

[0012] In an embodiment, the step of determining the electromagnetic detection frequency band based on the number of layers and dielectric constant of the multi-layer stacked motherboard, and emitting corresponding electromagnetic detection signals to the multi-layer stacked motherboard at the electromagnetic detection frequency band to obtain original electromagnetic field data includes:

[0013] Determine the reference electromagnetic frequency according to the following formula:

[0014] ;

[0015] wherein, represents the reference electromagnetic frequency, represents the number of layers of the multi-layer stacked main board; represents the dielectric constant of the multi-layer stacked main board;

[0016] Determine the electromagnetic detection frequency band based on the reference electromagnetic frequency and the dielectric constant of the multi-layer stacked main board, wherein:

[0017] When the dielectric constant of the multi-layer stacked main board is less than 3.5, determine the electromagnetic detection frequency band as: ;

[0018] When the dielectric constant of the multi-layer stacked main board is greater than 3.5, determine the electromagnetic detection frequency band as: .

[0019] In one embodiment, before the step of calculating the interlayer magnetic field gradient change rate of the multi-layer stacked main board based on the original electromagnetic field data, the method further includes:

[0020] Identify the blind hole ratio of the multi-layer stacked main board, and when the blind hole ratio is greater than a preset threshold, emit an electromagnetic detection signal of a preset frequency band to the multi-layer stacked main board.

[0021] In one embodiment, before the step of calculating the interlayer magnetic field gradient change rate of the multi-layer stacked main board based on the original electromagnetic field data, the method further includes:

[0022] Determine the polarization direction of the electromagnetic detection signal based on the number of layers of the electromagnetic multi-layer stacked main board, specifically including:

[0023] When the number of layers of the multi-layer stacked main board is even, determine the polarization direction of the electromagnetic detection signal as left-handed circular polarization;

[0024] When the number of layers of the multi-layer stacked main board is odd, determine the polarization direction of the electromagnetic detection signal as right-handed circular polarization.

[0025] In one embodiment, the step of calculating the interlayer magnetic field gradient change rate of the multi-layer stacked main board based on the original electromagnetic field data includes:

[0026] Perform eddy current compensation on the original electromagnetic field data to obtain the electromagnetic field data after eddy current compensation;

[0027] Calculate the interlayer magnetic field gradient of the multi-layer stacked main board based on the compensated electromagnetic field data;

[0028] Calculate the interlayer magnetic field gradient change rate of the multi-layer stacked main board based on the interlayer magnetic field gradient.

[0029] In one embodiment, the interlayer magnetic field gradient is calculated according to the following formula:

[0030] ;

[0031] wherein, represents the interlayer magnetic field gradient, represents the electromagnetic field data of the th layer after eddy current compensation, represents the dielectric thickness of the main board of the th layer;

[0032] The rate of change of the interlayer magnetic field gradient is calculated according to the following formula:

[0033] ;

[0034] wherein, represents the rate of change of the interlayer magnetic field gradient of the multi-layer stacked main board, represents the interlayer magnetic field gradient of the th layer, represents the dielectric thickness of the main board of the th layer.

[0035] In one embodiment, the steps of determining the corresponding electromagnetic anomaly region when the rate of change of the interlayer magnetic field gradient is greater than the preset magnetic field gradient change rate threshold include:

[0036] When the rate of change of the interlayer magnetic field gradient is greater than the preset magnetic field gradient change rate threshold, determine the corresponding abnormal plane coordinates and determine the corresponding abnormal interlayer coordinates by the time difference positioning method;

[0037] Determine the corresponding abnormal three-dimensional coordinates based on the abnormal plane coordinates and the abnormal interlayer coordinates;

[0038] Mark the region within the first preset radius centered on the abnormal three-dimensional coordinates as the electromagnetic anomaly region.

[0039] In one embodiment, the steps of performing a layered current injection test in the electromagnetic anomaly region through a probe to obtain the electrical anomaly region include:

[0040] Inject multiple levels of preset DC currents in sequence at the abnormal three-dimensional coordinates at preset time intervals through the probe, and mark the region within the second preset radius centered on the abnormal three-dimensional coordinates as the initial electrical anomaly region; wherein, the second preset radius is greater than the first preset radius;

[0041] Obtain the potential distribution within the initial electrical anomaly region. When there is a sub-region within the initial electrical anomaly region where the potential gradient in two consecutive preset DC current steps is greater than the preset potential gradient threshold, use the sub-region as the electrical anomaly correction region;

[0042] Inject an alternating current with a corresponding frequency into the electrical anomaly correction region based on the potential distribution of the electrical anomaly correction region, and obtain the corresponding phase angle and impedance;

[0043] Inject a corresponding pulsed current into the electrical anomaly correction region according to the phase angle and impedance, and obtain the corresponding waveform characteristics through time-domain reflectometry testing;

[0044] Correct the electrical anomaly correction region according to the waveform characteristics to generate a corresponding electrical anomaly region.

[0045] In one embodiment, the method further includes:

[0046] Determine the corresponding defect type according to the waveform characteristics;

[0047] After the step of spatially matching the electromagnetic anomaly region with the electrical anomaly region and determining the existence of an effective defect and outputting the corresponding defect coordinates when the overlap degree between the two is higher than the preset threshold, the method further includes:

[0048] Output the corresponding defect type.

[0049] In addition, to achieve the above object, the present application also proposes a multi-layer stacked main board testing device. The multi-layer stacked main board testing device includes a memory, a processor, and a computer program stored on the memory and executable on the processor. The computer program is configured to implement the steps of the multi-layer stacked main board testing method.

[0050] The multi-layer stacked main board testing method proposed in this application determines the electromagnetic detection frequency band based on the number of layers and dielectric constant of the multi-layer stacked main board, and emits corresponding electromagnetic detection signals to the multi-layer stacked main board in the electromagnetic detection frequency band to obtain the original electromagnetic field data; then calculates the inter-layer magnetic field gradient change rate based on the original electromagnetic field data; and when the inter-layer magnetic field gradient change rate is greater than the preset magnetic field gradient change rate threshold, determines the corresponding electromagnetic anomaly area; then performs hierarchical current injection testing in the electromagnetic anomaly area through a probe to obtain the electrical anomaly area; finally, spatially matches the electromagnetic anomaly area with the electrical anomaly area, and determines the existence of an effective defect when the overlap degree between the two is higher than the preset threshold, and outputs the corresponding defect coordinates. In this way, this application uses an electromagnetic detection signal matching the specific structural parameters of the multi-layer stacked main board for testing to obtain the electromagnetic anomaly area, and performs hierarchical current injection testing in the electromagnetic anomaly area through a probe to obtain the electrical anomaly area, and then jointly determines the defect by spatially matching the obtained electromagnetic anomaly area and the electrical anomaly area, improving the accuracy of the multi-layer stacked main board detection. The above detection method does not require detecting each layer of the multi-layer stacked main board one by one, improving the testing efficiency of the multi-layer stacked main board. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings here are incorporated into the specification and form a part of this specification, showing the embodiments consistent with this application, and are used together with the specification to explain the principles of this application.

[0052] In order to more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0053] Figure 1 It is a schematic flowchart provided for an embodiment of the multi-layer stacked main board testing method of this application;

[0054] Figure 2 It is a schematic flowchart provided for another embodiment of the multi-layer stacked main board testing method of this application;

[0055] Figure 3 It is a schematic flowchart provided for yet another embodiment of the multi-layer stacked main board testing method of this application;

[0056] Figure 4 For this application Figure 1 It is a detailed flowchart of step S200 in

[0057] Figure 5 For this application Figure 1 It is a detailed flowchart of step S300 in

[0058] Figure 6 For this application Figure 1 is a detailed flowchart of step S400 in the application;

[0059] Figure 7 is a schematic structural diagram provided by an embodiment of a multi-layer stacked main board testing device of this application.

[0060] Explanation of the reference numerals in the drawings:

[0061] 10. Memory; 20. Processor.

[0062] The realization of the purpose, functional characteristics and advantages of this application will be further described with reference to the embodiments and the accompanying drawings. Specific embodiments

[0063] It should be understood that the specific embodiments described herein are only used to explain the technical solutions of this application and are not used to limit this application.

[0064] In order to better understand the technical solutions of this application, the following will be described in detail with reference to the drawings in the specification and specific embodiments.

[0065] The main solution of the embodiment of this application is: determining the electromagnetic detection frequency band based on the number of layers and dielectric constant of the multi-layer stacked main board, and transmitting corresponding electromagnetic detection signals to the multi-layer stacked main board at the electromagnetic detection frequency band to obtain original electromagnetic field data; then calculating the inter-layer magnetic field gradient change rate of the multi-layer stacked main board based on the original electromagnetic field data; and when the inter-layer magnetic field gradient change rate is greater than a preset magnetic field gradient change rate threshold, determining the corresponding electromagnetic anomaly region; then performing a hierarchical current injection test in the electromagnetic anomaly region through a probe to obtain an electrical anomaly region; and finally, performing spatial matching between the electromagnetic anomaly region and the electrical anomaly region, and determining that there is an effective defect when the overlap degree between the two is higher than a preset threshold, and outputting the corresponding defect coordinates.

[0066] In this embodiment, for the convenience of description, the following will be described with the multi-layer stacked main board testing device as the execution subject.

[0067] In the prior art, the main board test is used to ensure that the performance and quality of the main board meet the design requirements, and it is a crucial link in the manufacturing process of electronic products. With the continuous development of electronic technology, multi-layer stacked main boards are widely used in various electronic devices due to their high density and high performance characteristics.

[0068] Since the traditional multi-layer stacked main board test generally tests each layer of the multi-layer stacked main board one by one, it is not only time-consuming and laborious, with low efficiency, but also due to the complex inter-layer structure of the multi-layer stacked main board, it is difficult to accurately detect some minor defects inside by the existing test methods.

[0069] The solution provided by this application tests by using electromagnetic detection signals that match the specific structural parameters of a multi-layer stacked main board to obtain electromagnetic anomaly regions, and performs hierarchical current injection testing in the electromagnetic anomaly regions through probes to obtain electrical anomaly regions. Then, by spatially matching the obtained electromagnetic anomaly regions and the electrical anomaly regions to jointly determine defects, the accuracy of multi-layer stacked main board detection is improved. The above detection method does not require detecting each layer of the multi-layer stacked main board one by one, which improves the testing efficiency of the multi-layer stacked main board.

[0070] It should be noted that the execution subject of this embodiment can be a computing service device with data processing, network communication, and program running functions, such as a tablet computer, a personal computer, etc., or an electronic device, a multi-layer stacked main board testing device, etc. that can implement the above functions. Hereinafter, taking the multi-layer stacked main board testing device as an example, this embodiment and the following embodiments will be described.

[0071] Based on this, the embodiment of this application provides a multi-layer stacked main board testing method. Referring to Figure 1 , in this embodiment, the multi-layer stacked main board testing method includes steps S100 to S500, where:

[0072] Step S100: Determine the electromagnetic detection frequency band based on the number of layers and dielectric constant of the multi-layer stacked main board, and emit corresponding electromagnetic detection signals to the multi-layer stacked main board at the electromagnetic detection frequency band to obtain the original electromagnetic field data.

[0073] It can be understood that due to the complex structure of the multi-layer stacked main board, the responses of different numbers of layers and dielectric constants to electromagnetic detection signals are also different. When the number of layers of the multi-layer stacked main board is more, the medium superposition effect experienced by the electromagnetic signal during penetration is more significant. The high-frequency components are easily absorbed by the surface layer due to the skin effect, while the low-frequency components, although able to penetrate deep into the inner layer, may cause signal blurring due to multi-path reflection. At the same time, material layers with different dielectric constants will cause non-uniform changes in the electromagnetic wave velocity, exacerbating signal phase distortion, making it difficult for traditional single-frequency band scanning to accurately capture deep and tiny defects. Therefore, it is necessary to adapt the electromagnetic detection frequency band according to the actual number of layers and dielectric characteristics of the multi-layer stacked main board, balance signal attenuation and defect sensitivity, so as to penetrate the complex stacked structure and lock in hidden physical anomalies.

[0074] In a feasible implementation manner, step S100 includes determining the reference electromagnetic frequency according to the following formula:

[0075] ;

[0076] Where, represents the reference electromagnetic frequency, represents the number of layers of the multi-layer stacked main board; Represents the dielectric constant of a multi-layer stacked main board.

[0077] In this embodiment, the dielectric constant of the above formula for the multi-layer stacked main board is specifically the average effective dielectric constant of the multi-layer stacked main board, which can be calculated by weighting according to the dielectric constant of each layer of the main board. The constant "15 GHz" in the above formula is an empirical constant, which is obtained through multiple experiments and is used to balance the signal penetration ability and the defect detection sensitivity. For example, when detecting a 10-layer FR-4 main board ( ), . When detecting a 6-layer Rogers board ( ), . The reference electromagnetic frequency calculated by this formula can be used as the starting point of the actual frequency scan, and a certain frequency range can be set around this reference frequency as the electromagnetic detection frequency band.

[0078] In a feasible embodiment, after obtaining the reference electromagnetic frequency, step S100 further includes determining the electromagnetic detection frequency band based on the reference electromagnetic frequency and the dielectric constant of the multi-layer stacked main board, where:

[0079] When the dielectric constant of the multi-layer stacked main board is less than 3.5, determine the electromagnetic detection frequency band as: ;

[0080] When the dielectric constant of the multi-layer stacked main board is greater than 3.5, determine the electromagnetic detection frequency band as: .

[0081] In this embodiment, the setting of the dielectric constant threshold of 3.5 is determined based on the typical characteristics of high-frequency and conventional PCB materials, the law of electromagnetic wave propagation, and engineering experience. In specific implementation, similar dielectric constant thresholds (such as 3.4, 3.6, etc.) can also be used for frequency band division. When the dielectric constant of the multi-layer stacked main board is small, the propagation speed of electromagnetic waves in it is fast and the attenuation is small. Therefore, the frequency range of the electromagnetic detection frequency band can be appropriately increased to improve the detection accuracy. When the dielectric constant of the multi-layer stacked main board is large, the propagation speed of electromagnetic waves in it is slow and the attenuation is large. Therefore, the frequency range of the electromagnetic detection frequency band needs to be appropriately reduced to ensure that the signal can penetrate the multi-layer stacked main board to achieve the detection purpose. For example, when detecting a 10-layer FR-4 main board ( ), , then its actual frequency band is 0.57 GHz~1.37 GHz, and when detecting a 6-layer Rogers board ( ), , its actual frequency band is then 1.15 GHz to 1.73 GHz. In this way, by adapting the electromagnetic detection frequency band according to the actual number of layers and dielectric properties of the multi-layer stacked main board, the signal attenuation and defect sensitivity are balanced, so that the electromagnetic detection signal can penetrate the complex stacked structure and lock the hidden physical anomalies.

[0082] In a feasible implementation, referring to Figure 1-2 , before the step S200, the method further includes a step S1001 of identifying the blind via ratio of the multi-layer stacked main board, and when the blind via ratio is greater than a preset threshold, emitting an electromagnetic detection signal of a preset frequency band to the multi-layer stacked main board.

[0083] In this embodiment, the blind via ratio of the multi-layer stacked main board can be identified by the image recognition module of the multi-layer stacked main board test device. This image recognition module can analyze the scanned image of the multi-layer stacked main board, calculate the number and total area of the blind vias, and then obtain the blind via ratio. The setting of the preset threshold can be determined according to the conventional design parameters of the multi-layer stacked main board and the actual test requirements, and is not specifically limited here. When the blind via ratio exceeds this preset threshold, it means that there may be more blind via structures inside the multi-layer stacked main board, and these blind vias may interfere with the electromagnetic detection signal and affect the accuracy of defect detection. Therefore, it is necessary to emit an electromagnetic detection signal of a preset frequency band to the multi-layer stacked main board, and this preset frequency band can be determined according to the characteristics of the blind via structure and the actual test requirements to ensure that the signal can penetrate the blind via structure and achieve the detection purpose. In this way, the accuracy of the multi-layer stacked main board test can be further improved.

[0084] In a feasible implementation, referring to Figure 1 , Figure 3 , before the step S200, the method further includes a step S1002 of determining the polarization direction of the electromagnetic detection signal based on the number of layers of the electromagnetic multi-layer stacked main board, specifically including: when the number of layers of the multi-layer stacked main board is even, determining the polarization direction of the electromagnetic detection signal as left-handed circular polarization; when the number of layers of the multi-layer stacked main board is odd, determining the polarization direction of the electromagnetic detection signal as right-handed circular polarization.

[0085] In this embodiment, since in the multi-layer stacked main board detection, the stacked structures with even and odd numbers of layers have different effects on the reflection and propagation path of electromagnetic waves. Even layers are prone to form multiple reflection interferences due to symmetry. Therefore, left-handed circular polarization is adopted in this embodiment to suppress the crosstalk of co-directional reflection signals; while odd layers have skewed electromagnetic coupling paths due to asymmetry. Therefore, right-handed circular polarization is adopted in this embodiment to adapt to the waveguide phase shift characteristics and enhance the electromagnetic field distortion characteristics at the defect. By matching the rotation direction with the number of layers, the background noise interference can be minimized to the greatest extent, and the electromagnetic response contrast of interlayer micro-shorts or dielectric anomalies can be improved, thereby improving the sensitivity and accuracy of defect detection.

[0086] In this embodiment, the electromagnetic detection signal can be transmitted to the multi-layer stacked main board through a programmable antenna array. The programmable antenna array can dynamically adjust its radiation characteristics, such as directivity and polarization mode, according to the preset electromagnetic detection frequency band to ensure that the electromagnetic detection signal can evenly and effectively cover the entire test area of the multi-layer stacked main board. In addition, the multi-input multi-output function can also be realized through the programmable antenna array to simultaneously transmit and receive multiple electromagnetic detection signals, further improving the test efficiency. The original electromagnetic field data can be collected by the electromagnetic field data acquisition module in the multi-layer stacked main board test device. The electromagnetic field data acquisition module can monitor and record the electromagnetic field generated after the interaction between the transmitted electromagnetic detection signal and the multi-layer stacked main board in real time, so as to obtain the original electromagnetic field data containing the internal defect information of the multi-layer stacked main board. By obtaining this original electromagnetic field data, a data basis can be provided for subsequent identification of defects in the multi-layer stacked main board.

[0087] Step S200: Calculate the inter-layer magnetic field gradient change rate of the multi-layer stacked main board based on the original electromagnetic field data.

[0088] In this embodiment, the inter-layer magnetic field gradient change rate refers to the change rate of the magnetic field strength between the layers of the multi-layer stacked main board, which reflects the non-uniformity of the internal electromagnetic field distribution of the multi-layer stacked main board. By calculating the inter-layer magnetic field gradient change rate, the areas where the electromagnetic field changes abnormally can be identified, and these areas are often the positions where there are defects inside the multi-layer stacked main board. When calculating the inter-layer magnetic field gradient change rate, a preset formula or the method of numerical differentiation can be used to process the original electromagnetic field data to obtain the gradient value of the magnetic field strength of each layer, and then the inter-layer magnetic field gradient change rate can be obtained. When the inter-layer magnetic field gradient change rate exceeds the preset threshold, it can be considered that there is an electromagnetic anomaly in this area and further detection is required.

[0089] In a feasible implementation manner, refer to Figure 4 , step S200 includes steps S210 to S230, where:

[0090] Step S210: Perform eddy current compensation on the original electromagnetic field data to obtain the electromagnetic field data after eddy current compensation.

[0091] In this embodiment, since the propagation of electromagnetic detection signals in the multi-layer stacked main board is affected by the eddy current effect, the measurement of electromagnetic field data is deviated. Therefore, before calculating the change rate of the inter-layer magnetic field gradient, it is necessary to perform eddy current compensation on the original electromagnetic field data to eliminate the influence of the eddy current effect on the measurement results. The specific method of eddy current compensation can be determined according to parameters such as the material, structure of the multi-layer stacked main board, and the frequency of the electromagnetic detection signal, and no specific limitation is made here. Through eddy current compensation, more accurate electromagnetic field data can be obtained, providing a reliable basis for subsequent calculations.

[0092] Step S220, calculate the inter-layer magnetic field gradient of the multi-layer stacked main board based on the compensated electromagnetic field data.

[0093] In this embodiment, after obtaining the electromagnetic field data after eddy current compensation, the inter-layer magnetic field gradient can be calculated based on this data. The inter-layer magnetic field gradient refers to the change amount of the magnetic field strength between adjacent two layers of the multi-layer stacked main board, which reflects the subtle differences in the internal electromagnetic field distribution of the multi-layer stacked main board. By calculating the inter-layer magnetic field gradient, the regions where the electromagnetic field changes slightly can be further identified, and these regions may be the positions of potential defects inside the multi-layer stacked main board. When calculating the inter-layer magnetic field gradient, a preset formula can be used to process the compensated electromagnetic field data to obtain the gradient value of the magnetic field strength of each layer.

[0094] In a feasible implementation manner, the inter-layer magnetic field gradient is calculated according to the following formula:

[0095] ;

[0096] Wherein, represents the inter-layer magnetic field gradient, represents the electromagnetic field data of the th layer after eddy current compensation, represents the th layer of the main board's dielectric thickness.

[0097] In this embodiment, the dielectric thickness can be obtained through the design parameters of the multi-layer stacked main board or actual measurement. By calculating the inter-layer magnetic field gradient of each layer, the subtle differences in the internal electromagnetic field distribution of the multi-layer stacked main board can be obtained, providing an important basis for subsequent defect determination.

[0098] Step S230, calculate the change rate of the inter-layer magnetic field gradient of the multi-layer stacked main board based on the inter-layer magnetic field gradient.

[0099] In this embodiment, based on the calculated interlayer magnetic field gradient, the change rate of the interlayer magnetic field gradient can be further obtained. The change rate of the interlayer magnetic field gradient refers to the change rate of the magnetic field gradient values between the layers of the multi-layer stacked main board, which reflects the degree of non-uniformity of the electromagnetic field distribution inside the multi-layer stacked main board. By comparing the change rate of the interlayer magnetic field gradient with a preset threshold value, it is possible to determine whether there is an electromagnetic anomaly area inside the multi-layer stacked main board. When the change rate of the interlayer magnetic field gradient is greater than the preset threshold value, it can be considered that there is an electromagnetic anomaly in this area.

[0100] In a feasible implementation manner, the change rate of the interlayer magnetic field gradient is calculated according to the following formula:

[0101] ;

[0102] Wherein, represents the change rate of the interlayer magnetic field gradient of the multi-layer stacked main board, represents the interlayer magnetic field gradient of the th layer, represents the dielectric thickness of the main board of the th layer. In this embodiment, the dielectric thickness can be obtained through the design parameters of the multi-layer stacked main board or actual measurement.

[0103] Step S300, when the change rate of the interlayer magnetic field gradient is greater than the preset magnetic field gradient change rate threshold, determine the corresponding electromagnetic anomaly area.

[0104] In this embodiment, the setting of the preset magnetic field gradient change rate threshold can be comprehensively determined based on factors such as the conventional design parameters of the multi-layer stacked main board, actual test requirements, and historical test data. When the change rate of the interlayer magnetic field gradient exceeds this preset threshold, it means that there is an electromagnetic anomaly in the corresponding area inside the multi-layer stacked main board, which may be the location of the defect. At this time, the system can automatically mark these electromagnetic anomaly areas and generate corresponding detection reports for testers to further analyze and process. In this way, rapid and accurate detection of internal defects of the multi-layer stacked main board can be achieved, improving the test efficiency and accuracy.

[0105] In a feasible implementation manner, referring to Figure 5 , step S300 includes steps S310 to S330, where:

[0106] Step S310, when the change rate of the interlayer magnetic field gradient is greater than the preset magnetic field gradient change rate threshold, determine its corresponding abnormal plane coordinates, and determine its corresponding abnormal interlayer coordinates by the time difference positioning method.

[0107] In this embodiment, the abnormal planar coordinates can be specifically determined according to the coordinate system established by the multi-layer stacked main board testing device based on a preset origin (such as the lower left corner of the multi-layer stacked main board). This coordinate system can accurately record the position of the electromagnetic abnormal area on the plane of the multi-layer stacked main board. The time difference positioning method is to use the time difference of the electromagnetic detection signal propagating in the multi-layer stacked main board to determine the interlayer position where the abnormality is located. Since the propagation speed and path of the electromagnetic detection signal may vary among different layers, by measuring the time difference of the electromagnetic detection signal reaching the abnormal area and combining the interlayer structure and medium characteristics of the multi-layer stacked main board, the interlayer coordinates where the abnormality is located can be deduced.

[0108] Step S320, determine the corresponding abnormal three-dimensional coordinates based on the abnormal planar coordinates and the abnormal interlayer coordinates.

[0109] In this embodiment, the abnormal three-dimensional coordinates can be specifically obtained by combining the abnormal planar coordinates and the abnormal interlayer coordinates. This three-dimensional coordinate can accurately describe the specific position of the electromagnetic abnormal area in the multi-layer stacked main board. By determining the abnormal three-dimensional coordinates, precise positioning of the internal defects of the multi-layer stacked main board can be achieved, providing an important basis for subsequent defect analysis and processing.

[0110] Step S330, mark the area within the first preset radius centered on the abnormal three-dimensional coordinates as the electromagnetic abnormal area.

[0111] In this embodiment, the specific value of the first preset radius can be comprehensively determined according to factors such as the size of the multi-layer stacked main board, the requirements for testing accuracy, and actual testing experience. By setting the first preset radius, it can be ensured that the electromagnetic abnormal area and the surrounding areas that may be affected are included in the detection range, thereby improving the comprehensiveness and accuracy of defect detection.

[0112] Step S400, perform a layered current injection test in the electromagnetic abnormal area through a probe to obtain the electrical abnormal area.

[0113] In this embodiment, the multi-layer stacked main board testing device can position the probe to the precise position of the electromagnetic abnormal area, and then inject a current with a preset frequency and amplitude into this area. During the current injection process, the multi-layer stacked main board testing device will monitor and record the current distribution and voltage change between each layer in real time. By comparing the current and voltage data of the normal area and the electromagnetic abnormal area, the areas where the electrical properties change abnormally can be identified, that is, the electrical abnormal areas. These areas often correspond to the defect positions inside the multi-layer stacked main board. By obtaining the electrical abnormal area, it can provide support for subsequent spatial matching of the electromagnetic abnormal area and the electrical abnormal area to confirm the defects.

[0114] In a feasible implementation manner, before the step S400, the method further includes starting an impedance matching network at a corresponding position in the electromagnetic anomaly region. In this embodiment, the main function of the impedance matching network is to adjust the impedance relationship between the electromagnetic detection signal and the multi-layer stacked main board, so as to reduce signal reflection and energy loss, thereby improving the penetration ability and detection sensitivity of the electromagnetic detection signal. By starting the impedance matching network, it can be ensured that the electromagnetic detection signal can interact more effectively with the multi-layer stacked main board, so as to obtain more accurate electromagnetic field data. In specific implementation, the parameters and specific structure of the impedance matching network can be dynamically adjusted according to the characteristics of the material, structure of the multi-layer stacked main board, and the frequency of the electromagnetic detection signal, etc., so as to achieve the best matching effect.

[0115] In a feasible implementation manner, referring to Figure 6 , the step S400 includes steps S410 to S450, where:

[0116] Step S410, injecting multiple levels of preset DC currents at preset time intervals in sequence through a probe at the abnormal three-dimensional coordinates, and recording the area within the second preset radius centered on the abnormal three-dimensional coordinates as the initial electrical anomaly area; wherein, the second preset radius is greater than the first preset radius.

[0117] In this embodiment, the specific values of the preset time interval and the multiple levels of preset DC currents can be flexibly set according to the material, structural characteristics of the multi-layer stacked main board, and actual test requirements, and are not limited here. By injecting multiple levels of preset DC currents in sequence, the change of the electrical properties at different depths inside the multi-layer stacked main board can be gradually revealed, so as to more accurately locate the electrical anomaly area. The setting of the initial electrical anomaly area can ensure that the possible electrical anomaly area and its surrounding potentially affected areas are included in the detection range. The design that the second preset radius is greater than the first preset radius can cover a wider area during the current injection test stage, improving the comprehensiveness and accuracy of defect detection.

[0118] Step S420, obtaining the potential distribution in the initial electrical anomaly area. When there is a sub-area in the initial electrical anomaly area where the potential gradient in two consecutive levels of preset DC current steps is greater than the preset potential gradient threshold, the sub-area is used as the electrical anomaly correction area.

[0119] In this embodiment, the electric potential gradient is the change in electric potential per unit length, which reflects the distribution of the electric field strength. During the current injection test, by monitoring and recording the electric potential values at each point within the initial electrically abnormal area, the electric potential distribution map of this area can be obtained. Among two consecutive preset DC current steps, if the electric potential gradients of a certain sub-area are all greater than the preset electric potential gradient threshold, it means that the electric field strength in this area has changed significantly, and it is very likely the location of the defect inside the multi-layer stacked main board. Therefore, taking these sub-areas as the electrically abnormal correction areas can narrow down the scope of defect location and improve the detection accuracy. During specific implementation, the setting of the preset electric potential gradient threshold can be comprehensively determined based on the material, structural characteristics of the multi-layer stacked main board, and actual test requirements.

[0120] Step S430: Inject an alternating current with a corresponding frequency into the electrically abnormal correction area based on the electric potential distribution of the electrically abnormal correction area, and obtain the corresponding phase angle and impedance.

[0121] In this embodiment, by injecting an alternating current with a corresponding frequency into the electrically abnormal correction area, the electromagnetic field in this area can be further excited, and its response characteristics can be monitored. The phase angle and impedance are important parameters for describing the electromagnetic field response, and they can reflect the subtle changes in the internal electrical properties of the multi-layer stacked main board. During the current injection process, the multi-layer stacked main board testing device will monitor and record the phase angle and impedance data of the electrically abnormal correction area in real time. By comparing the phase angle and impedance data of the normal area with those of the electrically abnormal correction area, the electrically abnormal area can be further confirmed, providing a basis for the precise determination of the defect.

[0122] Step S440: Inject a corresponding pulsed current into the electrically abnormal correction area according to the phase angle and impedance, and obtain the corresponding waveform characteristics through time-domain reflectometry testing.

[0123] In this embodiment, time-domain reflectometry testing is a method for detecting the change in the characteristic impedance of a transmission line by using the reflection principle of electromagnetic waves in the transmission line. When a pulsed current is injected into the electrically abnormal correction area, if there is a defect in this area, it will cause the reflection and scattering of electromagnetic waves. The corresponding waveform receiver of the multi-layer stacked main board testing device can capture the reflected electromagnetic wave signal and convert it into the corresponding waveform characteristics.

[0124] Step S450: Correct the electrically abnormal correction area according to the waveform characteristics to generate the corresponding electrically abnormal area.

[0125] In this embodiment, by comparing and analyzing the waveform characteristics under different pulsed current injections, the range of the electrical anomaly region can be further confirmed. The changes in waveform characteristics are often closely related to the types, sizes, and positions of defects inside the multi-layer stacked main board. For example, certain specific waveform distortions may indicate the presence of defects such as cracks, holes, or material inhomogeneities. During the correction process, based on the similarities and differences in waveform characteristics, the electrical anomaly correction region can be subdivided and adjusted to ensure that the finally generated electrical anomaly region can accurately reflect the defects inside the multi-layer stacked main board, so as to achieve in-depth analysis and precise positioning of the defects inside the multi-layer stacked main board.

[0126] In a feasible implementation manner, the method further includes determining the corresponding defect type according to the waveform characteristics.

[0127] In this embodiment, since the changes in waveform characteristics are often closely related to the types, sizes, and positions of defects inside the multi-layer stacked main board. Therefore, the corresponding relationship between waveform characteristics and defect types can be established in advance. This corresponding relationship can be established and optimized based on a large amount of experimental data and historical test experience to ensure the accuracy and reliability of defect type determination. After determining the defect type, the tester can take corresponding repair measures for different types of defects to improve the quality and reliability of the multi-layer stacked main board. By comparing the obtained waveform characteristics with the waveform characteristics corresponding to different defect types through the above corresponding relationship between waveform characteristics and defect types, the defect type can be accurately judged.

[0128] Step S500: Perform spatial matching between the electromagnetic anomaly region and the electrical anomaly region. When the overlap degree between the two is higher than a preset threshold, it is determined that there is an effective defect, and the corresponding defect coordinates are output.

[0129] In this embodiment, the spatial matching between the electromagnetic anomaly region and the electrical anomaly region can be achieved by comparing their position information. Specifically, the coordinate system established by the multi-layer stacked main board test device can be used to compare the three-dimensional coordinates of the electromagnetic anomaly region and the electrical anomaly region to determine their spatial relationship. The preset threshold can be determined comprehensively based on factors such as the test accuracy requirements of the multi-layer stacked main board, defect detection standards, and actual test experience. When the overlap degree between the electromagnetic anomaly region and the electrical anomaly region is higher than the preset threshold, it means that the two regions are highly consistent in spatial position, which usually indicates that there are indeed defects inside the multi-layer stacked main board. At this time, the system can determine it as an effective defect and output the corresponding defect coordinates.

[0130] In this embodiment, the defect coordinates can be specifically obtained by comprehensively analyzing the three-dimensional coordinates of the electromagnetic anomaly region and the electrical anomaly region. Specifically, the central coordinates or geometric centroids of the electromagnetic anomaly region and the electrical anomaly region can be used as the preliminary estimated values of the defect coordinates, and then fine-tuning can be performed in combination with factors such as their shapes, sizes, and overlapping degrees to obtain accurate defect coordinates. The output of the defect coordinates can be in various ways, such as directly displaying on the display screen of the multi-layer stacked main board testing device, generating a detection report containing defect coordinate information, or exporting it in the form of a data file, etc., so that the tester can intuitively understand the specific positions and distributions of the internal defects of the multi-layer stacked main board, facilitating subsequent defect repair.

[0131] In a feasible implementation manner, the method further includes outputting the corresponding defect type.

[0132] In this embodiment, after determining the existence of an effective defect and outputting the corresponding defect coordinates, the system can further output the corresponding defect type to provide key reference information for subsequent defect repair work. Specifically, the tester can select the corresponding repair methods and tools according to the output defect type to efficiently solve the problems existing inside the multi-layer stacked main board. In addition, the output of the defect type also helps the tester to trace and analyze the production process and quality control process of the multi-layer stacked main board, so as to find out the possible causes of the defects and take effective measures for improvement to improve the overall quality and reliability of the multi-layer stacked main board.

[0133] In this embodiment, the multi-layer stacked main board testing method determines the electromagnetic detection frequency band based on the number of layers and dielectric constant of the multi-layer stacked main board, and emits the corresponding electromagnetic detection signal to the multi-layer stacked main board at the electromagnetic detection frequency band to obtain the original electromagnetic field data; then calculates the inter-layer magnetic field gradient change rate based on the original electromagnetic field data; and when the inter-layer magnetic field gradient change rate is greater than the preset magnetic field gradient change rate threshold, determines the corresponding electromagnetic anomaly region; then performs a hierarchical current injection test in the electromagnetic anomaly region through a probe to obtain the electrical anomaly region; finally, spatially matches the electromagnetic anomaly region with the electrical anomaly region, and determines the existence of an effective defect when the overlap degree between the two is higher than the preset threshold, and outputs the corresponding defect coordinates. In this way, this application tests by using an electromagnetic detection signal matching the specific structural parameters of the multi-layer stacked main board to obtain the electromagnetic anomaly region, and performs a hierarchical current injection test in the electromagnetic anomaly region through a probe to obtain the electrical anomaly region, and then jointly determines the defect by spatially matching the obtained electromagnetic anomaly region and the electrical anomaly region, improving the accuracy of the multi-layer stacked main board detection. The above detection method does not require detecting each layer of the multi-layer stacked main board one by one, improving the testing efficiency of the multi-layer stacked main board.

[0134] The present application also provides a multi-layer stacked main board testing device. Refer to Figure 7 , the multi-layer stacked main board testing device includes a memory 10, a processor 20, and a computer program stored on the memory 10 and executable on the processor 20. The computer program is configured to implement the steps of the multi-layer stacked main board testing method described above.

[0135] The multi-layer stacked main board testing device provided by the present application adopts the multi-layer stacked main board testing method in the above embodiment, which can improve the accuracy and testing efficiency of the multi-layer stacked main board testing. Compared with the prior art, the beneficial effects of the multi-layer stacked main board testing device provided by the present application are the same as those of the multi-layer stacked main board testing method provided by the above embodiment, and other technical features in the multi-layer stacked main board testing device are the same as the features disclosed in the above embodiment method, which will not be elaborated here.

[0136] The above are only partial embodiments of the present application, and thus do not limit the patent scope of the present application. All equivalent structural transformations made under the technical concept of the present application by using the content of the specification and drawings of the present application, or direct / indirect applications in other related technical fields are included in the patent protection scope of the present application.

Claims

1. A multi-layer stacked motherboard testing method, characterized in that: The method includes: Determine an electromagnetic detection frequency band based on the number of layers and the dielectric constant of the multi-layer stacked mainboard, and transmit a corresponding electromagnetic detection signal to the multi-layer stacked mainboard at the electromagnetic detection frequency band to obtain original electromagnetic field data; Calculate the interlayer magnetic field gradient change rate of the multi-layer stacked motherboard based on the original electromagnetic field data; When the interlayer magnetic field gradient change rate is greater than a preset magnetic field gradient change rate threshold, determining a corresponding electromagnetic anomaly area; Performing a layered current injection test in the electromagnetic abnormal area by using a probe to obtain the electrical abnormal area; Spatially matching the electromagnetic abnormal area with the electrical abnormal area, determining that a valid defect exists when the overlap between the two is higher than a preset threshold, and outputting the corresponding defect coordinates; The step of determining the electromagnetic detection frequency band based on the number of layers and the dielectric constant of the multi-layer laminated mainboard, and transmitting a corresponding electromagnetic detection signal to the multi-layer laminated mainboard at the electromagnetic detection frequency band to obtain the original electromagnetic field data includes: Determine the reference electromagnetic frequency according to the following formula: ； in, represents the reference electromagnetic frequency, Indicates the number of layers of a multi-stacked motherboard; Indicates the dielectric constant of the multi-layer stacked motherboard; The electromagnetic detection frequency band is determined based on the reference electromagnetic frequency and the dielectric constant of the multi-layer stacked motherboard, wherein: When the dielectric constant of the multi-layer laminated motherboard is less than 3.5, the electromagnetic detection frequency band is determined to be: ; When the dielectric constant of the multi-layer laminated motherboard is greater than 3.5, the electromagnetic detection frequency band is determined to be: ; The step of calculating the interlayer magnetic field gradient change rate of the multi-layer stacked motherboard based on the original electromagnetic field data includes: Performing eddy current compensation on the original electromagnetic field data to obtain electromagnetic field data after eddy current compensation; Calculating the interlayer magnetic field gradient of the multi-layer stacked motherboard based on the compensated electromagnetic field data; The interlayer magnetic field gradient is calculated according to the following formula: ； in, represents the interlayer magnetic field gradient, Indicates the first The electromagnetic field data of the layer, Indicates The dielectric thickness of the layer motherboard; Calculating the interlayer magnetic field gradient change rate of the multi-layer stacked mainboard based on the interlayer magnetic field gradient; The interlayer magnetic field gradient change rate is calculated according to the following formula: ； in, Indicates the rate of change of the interlayer magnetic field gradient of the multi-layer stacked motherboard, Indicates The interlayer magnetic field gradient of the layer, Indicates The dielectric thickness of the main board.

2. The multi-layer motherboard testing method according to claim 1, characterized in that: Before the step of calculating the interlayer magnetic field gradient change rate of the multi-layer laminated mainboard based on the original electromagnetic field data, the method further includes: The blind hole ratio of the multi-layer stacked mainboard is identified, and when the blind hole ratio is greater than a preset threshold, an electromagnetic detection signal of a preset frequency band is additionally emitted to the multi-layer stacked mainboard.

3. The multi-layered motherboard testing method according to claim 1, wherein: Before the step of calculating the interlayer magnetic field gradient change rate of the multi-layer laminated mainboard based on the original electromagnetic field data, the method further includes: The polarization direction of the electromagnetic detection signal is determined based on the number of layers of the electromagnetic multi-layer stacked motherboard, specifically including: When the number of layers of the multi-layer stacked mainboard is an even number, determining that the polarization direction of the electromagnetic detection signal is left-hand circular polarization; When the number of layers of the multi-layer stacked mainboard is an odd number, the polarization direction of the electromagnetic detection signal is determined to be right-hand circular polarization.

4. The multi-layered motherboard testing method according to claim 1, wherein: When the interlayer magnetic field gradient change rate is greater than a preset magnetic field gradient change rate threshold, the step of determining the corresponding electromagnetic abnormal area comprises: When the interlayer magnetic field gradient change rate is greater than a preset magnetic field gradient change rate threshold, the corresponding abnormal plane coordinates are determined, and the corresponding abnormal interlayer coordinates are determined by the time difference positioning method; Determine corresponding abnormal three-dimensional coordinates based on the abnormal plane coordinates and the abnormal interlayer coordinates; The area within a first preset radius with the abnormal three-dimensional coordinates as the center is recorded as the electromagnetic abnormal area.

5. The multi-layered motherboard testing method according to claim 4, characterized in that: The step of performing a layered current injection test in the electromagnetic abnormal area by using a probe to obtain the electrical abnormal area includes: Inject multiple levels of preset direct current in sequence at preset time intervals at the abnormal three-dimensional coordinates through the probe, and record the area within a second preset radius centered on the abnormal three-dimensional coordinates as the initial electrical abnormal area; wherein the second preset radius is greater than the first preset radius; Acquire the potential distribution in the initial electrical anomaly region, and when there is a sub-region in the initial electrical anomaly region whose potential gradient in two consecutive preset direct current steps is greater than a preset potential gradient threshold, use the sub-region as an electrical anomaly correction region; Injecting an alternating current of a corresponding frequency into the electrical anomaly correction area based on the potential distribution of the electrical anomaly correction area, and obtaining a corresponding phase angle and impedance; Injecting a corresponding pulse current into the electrical anomaly correction area according to the phase angle and the impedance, and acquiring corresponding waveform characteristics through a time domain reflection test; The electrical abnormality correction region is corrected according to the waveform characteristics to generate a corresponding electrical abnormality region.

6. The multi-layered motherboard testing method according to claim 5, characterized in that: The method further comprises: Determine the corresponding defect type according to the waveform characteristics; After the step of spatially matching the electromagnetic abnormal area with the electrical abnormal area, determining that a valid defect exists when the overlap between the two is higher than a preset threshold, and outputting the corresponding defect coordinates, the method further includes: Output the corresponding defect type.

7. A multi-layer stacked motherboard testing device, characterized in that: The multi-layer stacked motherboard testing device includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program is configured to implement the steps of the multi-layer stacked motherboard testing method according to any one of claims 1 to 6.

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