Correction compensation system and method for anti-aging of analog chip

Abstract

The invention provides a correction compensation system and method for simulating chip aging resistance, the system comprises an aging simulation unit and an aging compensation unit, the aging simulation unit comprises a current source system and a metal resistor and is used for simulating a chip aging process; the aging compensation unit comprises a comparator, a correction control circuit and an analog circuit, and the comparator is used for detecting the output voltage difference between the two ends of the metal resistor and obtaining chip life information; the correction control circuit generates a correction code according to chip life information and superposes the correction code to the analog circuit to compensate for loss caused by aging of a device, so that the service life of the chip is effectively prolonged, and the reliability and stability of the chip are improved.

Description

Technical Field

[0001] The present invention relates to the field of information technology, and more particularly to a correction and compensation system and method for analog chip anti-aging. Background Art

[0002] With the development of information technology and the growing trend of domestic chip substitution, analog chips, especially high-performance analog chips, have become increasingly important in the market. Compared to digital chips, analog chips are more sensitive to process, voltage, and temperature. After production, analog chips are typically fine-tuned using calibration codes to compensate for the effects of process, voltage, and temperature, ensuring precise operation. However, this calibration can only be performed once before the chips leave the factory. Once in customer systems, devices gradually age over time, causing chip performance to degrade and, in severe cases, failure to occur, impacting system stability.

[0003] Currently, most analog circuits on the market are calibrated once before shipment. This method is cost-effective, but only works well in the early stages of a product's life. As devices age, the calibration code gradually shifts, causing chip performance to degrade.

[0004] A few systems can incorporate processors, enabling in-use corrections through system feedback and control. This significantly increases the complexity and cost of system design. Furthermore, some small analog circuits cannot be integrated with processors, requiring comprehensive consideration and innovative breakthroughs at the chip design and system integration levels. Summary of the Invention

[0005] The present invention addresses the issue of chip performance degradation caused by aging by proposing a correction and compensation system and method for simulating chip anti-aging. By integrating aging simulation, aging detection, and compensation circuitry, the system addresses the performance degradation caused by chip aging.

[0006] The technical solution of the present invention is: The present invention provides a correction and compensation system for analog chip anti-aging, the system comprising: An aging simulation unit, comprising a current source system and a metal resistor, for simulating the chip aging process. The current source system generates a current flowing through the metal resistor to produce an electromigration effect, causing the resistance of the metal resistor to gradually increase. The aging compensation unit includes a comparator, a correction control circuit and an analog circuit. The comparator is used to detect the output voltage difference across the metal resistor to obtain chip life information; the correction control circuit generates a correction code based on the chip life information and superimposes it on the analog circuit to compensate for the loss caused by device aging.

[0007] Furthermore, the current source system includes: An adjustable current source, used for generating an adjustable current; The external correction loop includes a standard current source and a current comparator, which is used to connect to the standard current source through a reserved external pin. The current comparator compares the reference current generated by the standard current source with the internal current generated by the adjustable current source, generates a correction code for the internal current source, and burns it into the non-volatile memory inside the chip.

[0008] Furthermore, the comparator is an analog-to-digital converter, which detects the voltage in years and divides the chip life into different stages according to the voltage difference.

[0009] Furthermore, the comparator includes a two-part comparator and a four-part comparator. The two-part comparator divides the chip life into early and late stages, and the four-part comparator divides the chip life into early, early middle, late middle and late stages.

[0010] Furthermore, the output results of the binary comparator are 0 and 1. When the output result is 0, it indicates an early stage chip, and when the output result is 1, it indicates a late stage chip.

[0011] Furthermore, the correction control circuit includes a plurality of correction code generation modules, the number of which is consistent with the number of correction code bits, and each correction code generation module includes a director, at least two AND gate circuits and an OR gate circuit; wherein, a director, for directing the output signal of the comparator to at least two AND gate circuits respectively according to the comparison result of the comparator; at least two AND gate circuits, wherein one input terminal of one AND gate circuit is connected to ground, and one input terminal of the other AND gate circuit is connected to a power supply; An OR gate circuit performs an OR operation on the outputs of the at least two AND gate circuits and outputs a correction code; wherein the output signal of the comparator represents the aging degree of the chip under test, and the correction code is used to compensate and correct the aging characteristics of the chip under test.

[0012] Furthermore, the AND gate circuit has the same number of branches as the comparator. When the comparator is a two-way comparator, two AND gate circuits are used. When the comparator is a four-way comparator, four AND gate circuits are used.

[0013] Furthermore, in the aging compensation unit, the analog circuit adopts a programmable resistor-capacitor network, generates corresponding correction codes for different analog circuits based on the acquired life information, and controls the resistance and capacitance of the analog circuit through the programmable resistor-capacitor network interface to compensate for the loss caused by aging.

[0014] A correction and compensation method adopted by the system comprises the following steps: S1. Obtain the standard current output by the reference current source, generate an internal current through an adjustable current source, use a current comparator to compare the reference current and the internal current, generate a calibration code for the internal current source, and burn it into the non-volatile memory inside the chip; S2, using metal resistors to simulate the aging process of the device, the resistance of the metal resistors gradually increases over time; S3. Detect the voltage difference between the two ends of the metal resistor through a comparator to obtain chip life information and divide the chip life into different stages; S4. Generate a correction code based on the life information, and apply the correction code to adjust the resistance and capacitance values ​​of the analog circuit through a programmable resistance-capacitance network interface to compensate for the loss caused by device aging.

[0015] Beneficial effects of the present invention: This invention simulates the chip aging process using a current source system and metal resistors. A comparator detects the voltage difference across the metal resistors to obtain chip life information. Based on the life stage, a correction control circuit generates a corresponding correction code and adjusts the resistance and capacitance values ​​of the simulated circuit through a programmable resistor-capacitor network to compensate for the loss caused by aging.

[0016] The present invention also includes an external correction circuit that calibrates the internal current source using a standard current source and current comparator, improving simulation accuracy. This method accurately simulates the chip aging process, monitors chip life status in real time, and provides targeted compensation based on different aging stages, effectively extending the chip's service life and improving its reliability and stability.

[0017] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention with reference to the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present invention.

[0019] Figure 1 The block diagram of the correction and compensation system for analog chip anti-aging of the present invention is shown.

[0020] Figure 2 FIG. 4 is a correction control circuit diagram of an embodiment of the present invention.

[0021] Figure 3 for Figure 2 Equivalent topology transformation circuit diagram of the correction control circuit.

[0022] Figure 4 FIG. 1 is a schematic diagram of a simulation circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] The preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0024] Example 1: like Figure 1 The present invention provides a correction and compensation system for analog chip anti-aging, specifically comprising: An aging simulation unit, comprising a current source system and a metal resistor, for simulating the chip aging process. The current source system generates a current flowing through the metal resistor to produce an electromigration effect, causing the resistance of the metal resistor to gradually increase. The aging compensation unit includes a comparator, a correction control circuit and an analog circuit. The comparator is used to detect the output voltage difference across the metal resistor to obtain chip life information; the correction control circuit generates a correction code based on the chip life information and superimposes it on the analog circuit to compensate for the loss caused by device aging.

[0025] In this embodiment, the current source system in the aging simulation unit simulates the electromigration effect during the chip aging process by generating a constant current flowing through the metal resistor. Electromigration is a metal migration phenomenon caused by the action of current and temperature on metal wires. The moving electrons and the main metal lattice exchange momentum with each other. When metal atoms migrate along the direction of the electron flow, cavities are formed at the original positions. These cavities will cause the metal resistance to increase or even open the circuit on a macro scale. In traditional chip design, electromigration is to be avoided as much as possible, so the current density will be reduced. In contrast, in our application here, the current density will be appropriately increased to promote the occurrence of electromigration, and the aging process of the device will be gradually simulated by integrating the power-on time. The enhancement of current density can be achieved by selecting a stronger current source.

[0026] For example, a current source system can generate a constant current flowing through a metal resistor. Over time, metal atoms in the resistor migrate under high current density, causing the resistance to increase. This change in resistance reflects the degradation of device performance as the chip ages.

[0027] The comparator in the aging compensation unit detects the output voltage difference across the metal resistor, thereby obtaining chip life information. The comparator compares the voltage across the metal resistor with a reference voltage. When the voltage difference exceeds a certain threshold, it indicates that the chip has aged to the point where correction is required. This allows real-time monitoring of chip aging, ensuring timely compensation when performance degrades.

[0028] The correction control circuit in the aging compensation unit generates a correction code based on the chip life information detected by the comparator and superimposes it on the analog circuit to compensate for the loss caused by device aging. This correction mechanism operates regularly during chip use to ensure the stability and reliability of chip performance.

[0029] The analog circuitry within the aging compensation unit is its core component. It receives the correction code generated by the calibration control circuit and adjusts the circuit's operating parameters accordingly. This adjustment process is implemented through a programmable resistor-capacitor network, ensuring that the correction code is applied to the analog circuitry, extending the chip's lifespan and improving system stability.

[0030] In one example, a current source system includes: An adjustable current source, used for generating an adjustable current; The external correction loop includes a standard current source and a current comparator, which is used to connect to the standard current source through a reserved external pin. The current comparator compares the reference current generated by the standard current source with the internal current generated by the adjustable current source, generates a correction code for the internal current source, and burns it into the non-volatile memory inside the chip.

[0031] In this embodiment, the current source system is the core component of the entire aging simulation. The current source system consists of an adjustable current source and an external correction loop. In order to prevent the aging mismatch of the current source itself, an external correction loop is added. The standard current source is connected through the reserved external pin, and the internal current comparator compares the reference current and the internal current. According to the difference between the two, the correction code of the internal current source is generated and burned into the non-volatile memory inside the chip. Since analog chips generally have non-volatile memory to store fine-tuned device parameters, this part of the function will not increase additional costs. The calibration of the current source is generally performed once a year and can be completed in the system, so the additional cost is not high. For extremely low-cost applications, a fixed current source can be used directly to eliminate the correction system. Since the aging degree of the current source is much smaller than that of the metal resistor R, the impact on the system accuracy is limited and can meet most daily applications.

[0032] This design ensures the current source maintains high accuracy even after extended use, eliminating the need for frequent recalibration. If the current source's accuracy degrades during use due to ambient temperature fluctuations or device aging, the user can recalibrate the current source by reconnecting a standard current source via the external pins. This design not only improves system reliability but also extends the product's lifespan.

[0033] In one example, the comparator is an analog-to-digital converter that detects voltage in years and divides the chip life into different stages based on the voltage difference; the comparator includes a two-part comparator and a four-part comparator, the two-part comparator divides the chip life into early and late stages, and the four-part comparator divides the chip life into early, early middle, late middle and late stages.

[0034] In this embodiment, the comparator is an analog-to-digital converter (ADC), which detects voltage in years and divides the chip lifespan into different stages based on voltage differences. By converting analog voltage signals into digital signals, the ADC accurately monitors chip voltage changes at different time points. This detection method provides real-time information on the chip's health status, providing data support for subsequent corrections and optimizations.

[0035] The design of the two-way comparator is relatively simple and is suitable for scenarios where the chip lifespan is roughly divided. This division method is suitable for application scenarios where the lifespan requirements are not high and can quickly determine whether the chip needs to be replaced or maintained.

[0036] The four-way comparator uses multiple voltage thresholds to more accurately classify chip lifecycle stages. For example, the initial stage, early intermediate stage, intermediate late stage, and final stage can more accurately reflect the chip's aging process, providing a more precise basis for system correction and optimization.

[0037] By using analog-to-digital converters and comparators with different partitioning methods, it is possible to accurately monitor and partition the chip lifespan. This technology not only improves chip reliability and service life, but also reduces system maintenance costs.

[0038] In one example, the correction control circuit includes a correction code generation module with the same number of correction code bits, that is, each bit of the correction code requires a correction code generation module, that is, one correction code generation module generates a 1-bit correction code, and each correction code generation module includes a director, at least two AND gate circuits and an OR gate circuit; wherein, a director, for directing the output signal of the comparator to at least two AND gate circuits respectively according to the comparison result of the comparator; at least two AND gate circuits, wherein one input terminal of one AND gate circuit is connected to ground, and one input terminal of another AND gate circuit is connected to a power supply; An OR gate circuit performs an OR operation on the outputs of the at least two AND gate circuits and outputs a correction code; wherein the output signal of the comparator represents the aging degree of the chip under test, and the correction code is used to compensate and correct the aging characteristics of the chip under test.

[0039] In this embodiment, taking a binary comparator as an example, the output results are 0 and 1. When the output result is 0, it indicates an early stage chip, and when the output result is 1, it indicates a late stage chip.

[0040] When the comparator output is A is 0, it indicates the initial chip; at this time, the AND gate A connected to the A guide input is selected, and since its other end is grounded, the output B is 0; the AND gate B connected to the A input is closed, and the output C is 0; after passing through the OR gate circuit, the output D is 0, indicating that the correction code 0 is 0; using 8 of the above circuits, an 8-bit 0 correction code can be generated; When the comparator output A is 1, it indicates the end of the chip; at this time, the AND gate A connected to the A guide input is closed, and the output B is 0; the AND gate B connected to the A input is selected, and since its other end is connected to the power supply, the output C is 1; after passing through the OR gate circuit, the output D is 1, indicating that the correction code 0 is 1; using 8 of the above circuits, an 8-bit 1 correction code can be generated; The above circuit generates an all-0 correction code for a new chip based on the comparator circuit, i.e. no correction; and generates an all-1 correction code for an old chip, i.e. maximum correction, to achieve the effect of compensating for the aging chip.

[0041] like Figure 2 As shown, the initial chip calibration code is all 0s, while the final chip calibration code is all 1s. For actual circuits, appropriate calibration codes for the initial and final stages can be selected based on the specific application and characteristics of each circuit. The positions of the guides within the eight cells can be adjusted to generate different calibration codes, allowing for design based on actual conditions.

[0042] The correction code generation module in the correction control circuit is designed to dynamically adjust the correction code based on the chip's aging. The number of AND gates can be flexibly adjusted based on the number of comparator branches, ensuring the correction control circuit can adapt to different comparator configurations and improving system compatibility and flexibility. This circuit design allows the correction control circuit to dynamically generate correction codes based on the comparator's output signal, compensating for chip aging characteristics.

[0043] In fact, because digital logic can be replaced by equivalent, the implementation does not necessarily follow this gate-level structure. The correction code generation system in the figure is only to describe the working principle of the entire system, and other digital logic equivalents can also be used, such as Figure 3 As shown, Figure 2 Equivalent topology transformation circuit diagram of the correction control circuit.

[0044] In one example, in the aging compensation unit, the analog circuit uses a programmable resistor-capacitor network to generate corresponding correction codes for different analog circuits based on the acquired lifetime information, and controls the resistance and capacitance of the analog circuit through a programmable resistor-capacitor network interface to compensate for the loss caused by aging.

[0045] In this embodiment, a programmable resistor-capacitor network (RCN) is a circuit structure whose resistance and capacitance values ​​can be adjusted by external signals. It typically consists of multiple programmable resistor and capacitor units, which are switched or adjusted by signals. This structure enables analog circuits to dynamically adjust their parameters based on aging information, thereby maintaining stable performance.

[0046] Compared to traditional processor calibration methods, programmable RC networks eliminate the need for complex calculations and control logic, enabling parameter adjustments directly at the analog circuit level, thereby reducing system complexity and cost. Furthermore, because programmable RC networks can adjust circuit parameters in real time based on aging information, they can effectively extend the life of analog circuits and improve product reliability and stability.

[0047] For example: In analog circuits, it is a very common circuit to generate a delayed pulse by forming an RC circuit with resistors and capacitors, such as Figure 4 As shown in the figure, resistor R is factory-set to 1 kΩ and capacitor to 10 pF, resulting in an RC delay of 10 ns. After five years of use without compensation, resistor R increases by 10% to 1.1 kΩ due to electromigration, and the RC delay now becomes 11 ns. Because the electromigration effect of the metal resistors in the detection circuit is much stronger than that of ordinary resistors, their output voltage changes significantly, and the comparator detects that they are in the late stage of their life cycle. The correction algorithm logic recognizes this as an RC delay circuit and adjusts the correction code to return resistor R to 1 kΩ. In a real circuit, C may also vary, requiring adjustment of the correction code based on the combined changes in R and C.

[0048] Example 2: The present invention provides a correction and compensation method for analog chip anti-aging, comprising the following steps: S1. Obtain the standard current output by the reference current source, generate an internal current through an adjustable current source, use a current comparator to compare the reference current and the internal current, generate a calibration code for the internal current source, and burn it into the non-volatile memory inside the chip; S2, using metal resistors to simulate the aging process of the device, the resistance of the metal resistors gradually increases over time; S3. Detect the voltage difference between the two ends of the metal resistor through a comparator to obtain chip life information and divide the chip life into different stages; S4. Generate a correction code based on the life information, and apply the correction code to adjust the resistance and capacitance values ​​of the analog circuit through a programmable resistance-capacitance network interface to compensate for the loss caused by device aging.

[0049] In this embodiment, a current comparator compares the reference current with the internal current. When the difference between the two exceeds a set threshold, a correction code is generated. The correction code is an 8-bit binary number. The non-volatile memory uses EFUSE to store the correction code over a long period of time, ensuring stable chip performance across various temperatures and operating conditions.

[0050] Metal resistors are used to simulate the device aging process. Under high temperature and high current density conditions, metal atoms will undergo electromigration, causing the resistance value to gradually increase, reflecting the performance degradation of other devices inside the chip and providing a basis for subsequent corrections.

[0051] A comparator detects the voltage difference across a metal resistor to obtain chip life information, which is then divided into different life stages. A correction code is generated based on this life information. This correction code is applied to the analog circuit's resistance and capacitance values ​​through a programmable resistance-capacitance network interface to compensate for device aging losses. This adjustment effectively compensates for performance degradation caused by device aging and extends the chip's lifespan.

[0052] While various embodiments of the present invention have been described above, the above description is intended to be illustrative, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A correction and compensation system for analog chip anti-aging, characterized in that: The system includes: An aging simulation unit, comprising a current source system and a metal resistor, for simulating the chip aging process, wherein the current source system generates a current flowing through the metal resistor to generate an electromigration effect, so that the resistance of the metal resistor gradually increases; The aging compensation unit includes a comparator, a correction control circuit and an analog circuit. The comparator is used to detect the output voltage difference between the two ends of the metal resistor to obtain chip life information; the correction control circuit generates a correction code according to the chip life information and superimposes it on the analog circuit to compensate for the loss caused by device aging.

2. The correction and compensation system for analog chip anti-aging as claimed in claim 1, characterized in that: The current source system comprises: An adjustable current source, used for generating an adjustable current; The external correction loop includes a standard current source and a current comparator, which is used to access the standard current source through a reserved external pin. The current comparator compares the reference current generated by the standard current source with the internal current generated by the adjustable current source, generates a correction code for the internal current source, and burns it into the non-volatile memory inside the chip.

3. The correction and compensation system for analog chip anti-aging as claimed in claim 1, characterized in that: The comparator is an analog-to-digital converter that detects voltage in years and divides the chip life into different stages according to voltage differences.

4. The correction and compensation system for analog chip anti-aging as claimed in claim 3, characterized in that: The comparator includes a two-part comparator and a four-part comparator. The two-part comparator divides the chip life into an early stage and a late stage, and the four-part comparator divides the chip life into an early stage, an early middle stage, a late middle stage and a late stage.

5. The correction and compensation system for analog chip anti-aging as claimed in claim 4, characterized in that: The output results of the binary comparator are 0 and 1. When the output result is 0, it indicates an early stage chip, and when the output result is 1, it indicates a late stage chip.

6. The correction and compensation system for analog chip anti-aging as claimed in claim 4, characterized in that: The correction control circuit includes a plurality of correction code generation modules, the number of which is consistent with the number of correction code bits, and each correction code generation module includes a director, at least two AND gate circuits and an OR gate circuit; wherein, A director, which directs the output signal of the comparator to at least two AND gate circuits respectively according to the comparison result of the comparator; at least two AND gate circuits, wherein one input terminal of one AND gate circuit is connected to ground, and one input terminal of another AND gate circuit is connected to a power supply; The OR gate circuit performs an OR operation on the outputs of the at least two AND gate circuits and outputs a correction code; wherein the output signal of the comparator represents the aging degree of the chip to be tested, and the correction code is used to compensate and correct the aging characteristics of the chip to be tested.

7. The correction and compensation system for analog chip anti-aging as claimed in claim 6, characterized in that: The AND gate circuit has the same number of branches as the comparator. When the comparator is a two-way comparator, two AND gate circuits are used. When the comparator is a four-way comparator, four AND gate circuits are used.

8. The correction and compensation system for analog chip anti-aging as claimed in claim 1, characterized in that: In the aging compensation unit, the analog circuit adopts a programmable resistor-capacitor network, generates corresponding correction codes for different analog circuits according to the acquired life information, and controls the resistor and capacitor fine-tuning of the analog circuit through the programmable resistor-capacitor network interface to compensate for the loss caused by aging.

9. A correction and compensation method used in the system according to any one of claims 1 to 8, characterized in that: S1. Obtain the standard current output by the reference current source, generate the internal current through the adjustable current source, use the current comparator to compare the reference current and the internal current, generate the correction code of the internal current source, and burn it into the non-volatile memory inside the chip; S2, using metal resistors to simulate the device aging process, the resistance of the metal resistors gradually increases over time; S3, detecting the voltage difference between the two ends of the metal resistor by a comparator, obtaining chip life information, and dividing the chip life into different stages; S4. Generate a correction code based on the life information, and apply the correction code to adjust the resistance and capacitance values ​​of the analog circuit through a programmable resistance and capacitance network interface to compensate for the loss caused by device aging.

Images