A calibration and compensation system and method for simulating the anti-aging of a chip

Abstract

The present invention provides a calibration compensation system and method for simulating the anti-aging of a chip. The system includes an aging simulation unit and an aging compensation unit. The aging simulation unit includes a current source system and a metal resistor, and is used to simulate the chip aging process. The aging compensation unit includes a comparator, a calibration control circuit, and an analog circuit. The comparator is used to detect the output voltage difference across the metal resistor to obtain chip life information. The calibration control circuit generates a calibration code according to the chip life information and superimposes it on the analog circuit to compensate for the loss caused by device aging, effectively extending the chip service life and improving the reliability and stability of the chip.

Description

Technical Field

[0001] The present invention relates to the field of information technology, and more particularly, to a calibration compensation system and method for simulating chip anti-aging. Background Art

[0002] With the development of information technology and the continuous rise of the wave of domestic substitution of chips, analog chips, especially high-performance analog chips, occupy an increasingly important position in the market. Compared with digital chips, analog chips are more sensitive to process, voltage, and temperature. Generally, after an analog chip is produced, calibration codes are used to fine-tune the chip to compensate for the effects of process, voltage, and temperature, so as to achieve the effect of accurate operation. However, this calibration can only be completed once before the chip leaves the factory. Once it reaches the customer system, as the service life increases, the device will gradually age, resulting in a decline in the performance of the chip. In severe cases, failures will occur, affecting the stable operation of the system.

[0003] Currently, most analog circuit calibrations on the market are completed once before leaving the factory, and this method is cost-effective. However, it only has a good effect in the early stage of product use. In the later stage, as the device ages, the previous calibration codes gradually shift, resulting in a decline in chip performance.

[0004] A few systems can be equipped with a processor to perform calibration during use through system feedback and control, which will greatly increase the complexity and cost of system design. In addition, for some small analog circuits, a processor cannot be integrated, and comprehensive consideration and innovative breakthroughs are required at the chip design and system integration levels. Summary of the Invention

[0005] The object of the present invention is to address the problem of performance degradation caused by chip aging, and to propose a calibration compensation system and method for simulating chip anti-aging. By the collaborative work of aging simulation, aging detection, and compensation calibration circuits, the problem of performance degradation caused by chip aging is solved.

[0006] The technical solution of the present invention is as follows:

[0007] The present invention provides a calibration compensation system for simulating chip anti-aging, which includes:

[0008] An aging simulation unit, including a current source system and a metal resistor, is used to simulate the chip aging process. The current source system generates a current that flows through the metal resistor to produce an electromigration effect, causing the resistance value of the metal resistor to gradually increase;

[0009] The aging compensation unit includes a comparator, a calibration control circuit, and an analog circuit. The comparator is used to detect the output voltage difference across the metal resistor and obtain chip life information. The calibration control circuit generates a calibration code based on the chip life information and superimposes it on the analog circuit to compensate for the losses caused by device aging.

[0010] Further, the current source system includes:

[0011] An adjustable current source for generating an adjustable current;

[0012] An external calibration loop, including a standard current source and a current comparator, is used to access the standard current source through a reserved external pin. The current comparator compares the reference current generated by the standard current source with the internal current generated by the adjustable current source, generates a calibration code for the internal current source, and burns it into the internal non-volatile memory of the chip.

[0013] Further, the comparator is an analog-to-digital converter that detects the voltage in years and divides the chip life into different stages according to the voltage difference.

[0014] Further, the comparator includes a two-point comparator and a four-point comparator. The two-point comparator divides the chip life into an initial stage and an end stage, and the four-point comparator divides the chip life into an initial stage, a mid-early stage, a mid-late stage, and an end stage.

[0015] Further, the output results of the two-point comparator are 0 and 1. When the output result is 0, it indicates an initial-stage chip, and when the output result is 1, it indicates an end-stage chip.

[0016] Further, the calibration control circuit includes a number of calibration code generation modules. The number of calibration code generation modules is the same as the number of bits of the calibration code. Each calibration code generation module includes a director, at least two AND gate circuits, and an OR gate circuit. Among them,

[0017] The director, according to the comparison result of the comparator, directs the output signal of the comparator to at least two AND gate circuits respectively;

[0018] At least two AND gate circuits, one input terminal of one AND gate circuit is connected to the ground, and one input terminal of the other AND gate circuit is connected to the power supply;

[0019] The OR gate circuit performs an OR operation on the outputs of the at least two AND gate circuits and outputs a calibration code. Among them, the output signal of the comparator represents the aging degree of the chip to be tested, and the calibration code is used to compensate and correct the aging characteristics of the chip to be tested.

[0020] Further, the number of branches of the AND gate circuit is the same as that of the comparator. When the comparator is a two-branch comparator, two AND gate circuits are used. When the comparator is a four-branch comparator, four AND gate circuits are used.

[0021] Further, in the aging compensation unit, the analog circuit uses a programmable resistive-capacitive network. According to the obtained lifetime information, corresponding correction codes are generated for different analog circuits, and the resistance and capacitance of the analog circuit are finely adjusted through the programmable resistive-capacitive network interface to compensate for the loss caused by aging.

[0022] A correction compensation method adopted by the system includes the following steps:

[0023] S1. Obtain the standard current output by the reference current source, generate an internal current through the adjustable current source, compare the reference current and the internal current using a current comparator to generate a correction code for the internal current source, and burn it into the non-volatile memory inside the chip.

[0024] S2. Use a metal resistor to simulate the aging process of the device. The resistance value of the metal resistor gradually increases with time.

[0025] S3. Detect the voltage difference across the metal resistor through a comparator to obtain the chip lifetime information and divide the chip lifetime into different stages.

[0026] S4. Generate a correction code according to the lifetime information, and apply the correction code to adjust the resistance and capacitance values of the analog circuit through the programmable resistive-capacitive network interface to compensate for the loss caused by device aging.

[0027] Advantages of the present invention:

[0028] The present invention simulates the chip aging process through a current source system and a metal resistor, and uses a comparator to detect the voltage difference across the metal resistor to obtain the chip lifetime information. According to the lifetime stage, the correction control circuit generates corresponding correction codes, and adjusts the resistance and capacitance values of the analog circuit through a programmable resistive-capacitive network, thereby compensating for the loss caused by aging.

[0029] The present invention further includes an external correction loop to correct the internal current source through a standard current source and a current comparator, improving the analog accuracy. This method can accurately simulate the chip aging process, monitor the chip lifetime status in real time, and perform targeted compensation according to different aging stages, effectively extending the chip service life and improving the reliability and stability of the chip.

[0030] Other features and advantages of the present invention will be described in detail in the subsequent specific implementation section. Description of the Drawings

[0031] The above and other objects, features, and advantages of the present invention will become more apparent by describing the exemplary embodiments of the present invention in more detail with reference to the accompanying drawings, in which, in the exemplary embodiments of the present invention, the same reference numerals generally represent the same components.

[0032] Figure 1 It is a block diagram of a calibration compensation system for simulating chip anti-aging of the present invention.

[0033] Figure 2 It is a calibration control circuit diagram of an embodiment of the present invention.

[0034] Figure 3 is Figure 2 The equivalent topological transformation circuit diagram of the calibration control circuit.

[0035] Figure 4 It is a schematic diagram of an analog circuit of an embodiment of the present invention. Specific embodiments

[0036] The preferred embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the preferred embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein.

[0037] Embodiment 1:

[0038] As Figure 1 , the present invention provides a calibration compensation system for simulating chip anti-aging, specifically including:

[0039] An aging simulation unit, including a current source system and a metal resistor, for simulating the chip aging process, wherein the current source system generates a current flowing through the metal resistor to generate an electromigration effect, causing the resistance value of the metal resistor to gradually increase;

[0040] An aging compensation unit, including a comparator, a calibration control circuit, and an analog circuit, wherein the comparator is used to detect the output voltage difference across the metal resistor to obtain chip life information; the calibration control circuit generates a calibration code based on the chip life information and superimposes it on the analog circuit to compensate for the loss caused by device aging.

[0041] In this embodiment, the current source system in the aging simulation unit simulates the electromigration effect during the chip aging process by generating a constant current flowing through a metal resistor. Electromigration is a metal migration phenomenon that occurs in metal wires under the action of current and temperature. When electrons in motion exchange momentum with the host metal lattice, metal atoms migrate along the direction of the electron flow, and voids will be formed at their original positions. Macroscopically, these voids will cause the metal resistance to increase or even open circuit. In traditional chip design, electromigration is to be avoided at all costs, so the current density is reduced. On the contrary, in our application, the current density is appropriately increased to promote the occurrence of electromigration, and the aging process of the device is gradually simulated through the integration of the energization time. The enhancement of the current density can be achieved by selecting a stronger current source.

[0042] For example, the current source system can generate a constant current flowing through a metal resistor. As time goes by, metal atoms in the metal resistor migrate under high current density, resulting in an increase in the resistance value. This change in resistance value reflects the degradation trend of device performance during the chip aging process.

[0043] The comparator in the aging compensation unit is used to detect the output voltage difference across the metal resistor, so as to obtain the chip life information. The comparator compares the voltage across the metal resistor with a reference voltage. When the voltage difference exceeds a certain threshold, it indicates that the aging degree of the chip has reached the level that needs to be corrected. The chip aging state can be monitored in real time to ensure timely compensation when the performance deteriorates.

[0044] The correction control circuit in the aging compensation unit generates a correction code based on the chip life information detected by the comparator and superimposes it on the analog circuit to compensate for the losses caused by device aging. This correction mechanism can work regularly during the chip usage process to ensure the stability and reliability of the chip performance.

[0045] The analog circuit in the aging compensation unit is the core part of the aging compensation unit. It receives the correction code generated by the correction control circuit and adjusts the working parameters of the circuit according to the correction code. This adjustment process is achieved through a programmable resistor-capacitor network to ensure that the correction code can act on the analog circuit, extend the service life of the chip, and improve the system stability.

[0046] In one example, the current source system includes:

[0047] An adjustable current source for generating an adjustable current;

[0048] An external correction loop, including a standard current source and a current comparator, for accessing the standard current source through a reserved external pin. The current comparator compares the reference current generated by the standard current source with the internal current generated by the adjustable current source, generates a correction code for the internal current source, and burns it into the internal non-volatile memory of the chip.

[0049] In this embodiment, the current source system is the core device of the entire aging simulation. The current source system consists of an adjustable current source and an external correction loop. In order to prevent the aging mismatch of the current source itself, an external correction loop is added. The standard current source is connected through the reserved external pin, and the internal current comparator compares the reference current and the internal current. According to the difference between the two, the correction code of the internal current source is generated and burned into the non-volatile memory inside the chip. Since analog chips generally have non-volatile memory to store fine-tuned device parameters, this part of the function will not increase additional costs. The calibration of the current source is generally performed once a year and can be completed in the system, so the additional cost is not high. For extremely low-cost applications, a fixed current source can be used directly to eliminate the correction system. Since the aging degree of the current source is much smaller than that of the metal resistor R, the impact on the system accuracy is limited and can meet most daily applications.

[0050] This design allows the current source to maintain high accuracy after long-term use without frequent recalibration. During use, if the accuracy of the current source decreases due to changes in ambient temperature or device aging, the user can reconnect the standard current source through the external pin for calibration to restore the accuracy of the current source. This design not only improves the reliability of the system, but also extends the service life of the product.

[0051] In one example, the comparator is an analog-to-digital converter that detects voltage in years and divides the chip life into different stages based on the voltage difference; the comparator includes a two-part comparator and a four-part comparator, the two-part comparator divides the chip life into early and late stages, and the four-part comparator divides the chip life into early, early middle, late middle and late stages.

[0052] In this embodiment, the comparator is an analog-to-digital converter, which detects the voltage in years and divides the chip life into different stages according to the voltage difference. The analog-to-digital converter can accurately monitor the voltage changes of the chip at different time points by converting the analog voltage signal into a digital signal. This detection method can reflect the health status of the chip in real time and provide data support for subsequent correction and optimization.

[0053] The design of the two-point comparator is relatively simple and is suitable for scenarios where the chip life is roughly divided. This division method is suitable for application scenarios where the life requirement is not high and can quickly determine whether the chip needs to be replaced or maintained.

[0054] The four-point comparator can more accurately divide the life stages of the chip by setting multiple voltage thresholds. For example, the initial stage, early middle stage, late middle stage and final stage. This division method can more carefully reflect the aging process of the chip and provide a more accurate basis for correction and optimization of the system.

[0055] By using an analog-to-digital converter and comparators with different partitioning methods, accurate monitoring and partitioning of the chip lifespan can be achieved. This technology can not only improve the reliability and service life of the chip, but also reduce the maintenance cost of the system.

[0056] In one example, the calibration control circuit includes a calibration code generation module that is consistent with the number of calibration code bits. That is, each bit of the calibration code requires a calibration code generation module. In other words, one calibration code generation module generates 1-bit calibration code. Each calibration code generation module includes a director, at least two AND gate circuits, and an OR gate circuit; where

[0057] The director, according to the comparison result of the comparator, directs the output signal of the comparator to at least two AND gate circuits respectively;

[0058] At least two AND gate circuits, one input terminal of one AND gate circuit is connected to the ground, and one input terminal of the other AND gate circuit is connected to the power supply;

[0059] The OR gate circuit performs an OR operation on the outputs of the at least two AND gate circuits and outputs a calibration code; where, the output signal of the comparator represents the aging degree of the chip to be tested, and the calibration code is used to compensate and correct the aging characteristics of the chip to be tested.

[0060] In this embodiment, taking the two-part comparator as an example, the output results are 0 and 1. When the output result is 0, it represents the initial stage chip, and when the output result is 1, it represents the end-stage chip.

[0061] When the output of the comparator A is 0, it represents the initial stage chip; at this time, AND gate A connected to the input of the director is selected, and since its other end is grounded, the output B is 0; AND gate B connected to the input of A is closed, and the output C is 0; after passing through the OR gate circuit, the output D is 0; it means that calibration code 0 is 0; 8 such circuits can generate 8-bit 0 calibration code;

[0062] When the output of the comparator A is 1, it represents the end-stage chip; at this time, AND gate A connected to the input of the director is closed, the output B is 0; AND gate B connected to the input of A is selected, and since its other end is connected to the power supply, the output C is 1; after passing through the OR gate circuit, the output D is 1, indicating that calibration code 0 is 1; 8 such circuits can generate 8-bit 1 calibration code;

[0063] The above circuit generates all 0 calibration codes for a brand-new chip according to the comparator circuit, that is, no correction; it generates all 1 calibration codes for an old chip, that is, maximum correction, in order to achieve the effect of compensating the aging chip.

[0064] Such as Figure 2As shown, the calibration code of the initial chip is all 0, and the calibration code of the final chip is all 1. For the actual circuit, the appropriate calibration codes of the initial and final stages can be selected according to the specific uses and characteristics of each circuit. The positions of the directors in the eight units can be set to generate different calibration codes, and the design can be carried out according to the actual situation.

[0065] The design of the calibration code generation module in the calibration control circuit can dynamically adjust the calibration code according to the aging degree of the chip; according to the number of branches of the comparator, the number of AND gates can be flexibly adjusted to ensure that the calibration control circuit can adapt to different comparator configurations, improving the compatibility and flexibility of the system. Through the above circuit design, the calibration control circuit can dynamically generate calibration codes according to the output signal of the comparator, realizing the compensation and calibration of the chip aging characteristics.

[0066] In fact, because digital logic can be equivalently replaced, the implementation may not necessarily be in accordance with this gate-level structure. The calibration code generation system in the figure is only for describing the working principle of the whole system, and other digital logics can also be equivalently replaced, such as Figure 3 As shown, it is Figure 2 The equivalent topological transformation circuit diagram of the calibration control circuit.

[0067] In one example, in the aging compensation unit, the analog circuit uses a programmable resistor-capacitor network. According to the obtained lifetime information, corresponding calibration codes are generated for different analog circuits, and the resistance and capacitance of the analog circuit are finely adjusted through the programmable resistor-capacitor network interface to compensate for the loss caused by aging.

[0068] In this embodiment, the programmable resistor-capacitor network is a circuit structure that can adjust its resistance and capacitance values through external signals. It is usually composed of multiple programmable resistor and capacitor units, and is switched or adjusted through signals. This structure enables the analog circuit to dynamically adjust its parameters according to the aging information, thereby maintaining stable performance.

[0069] Compared with the traditional processor calibration method, the programmable resistor-capacitor network does not require complex calculation and control logic, and can directly implement parameter adjustment at the analog circuit level, thereby reducing the system complexity and cost. In addition, since the programmable resistor-capacitor network can adjust the circuit parameters in real time according to the aging information, it can effectively extend the service life of the analog circuit and improve the reliability and stability of the product.

[0070] For example: in an analog circuit, generating a delay pulse through an RC circuit composed of a resistor and a capacitor is a very common circuit, such as Figure 4As shown, the resistance R is set to 1 KΩ at the time of factory shipment, the capacitance is 10 PF, and the RC delay is 10 ns. After 5 years of use, without compensation, due to the electromigration effect, the resistance value of the resistor R increases by 10% and becomes 1.1 KΩ. At this time, the RC delay becomes 11 ns. Since the electromigration effect of the metal resistor in the detection circuit is much stronger than that of the ordinary resistor, its output voltage changes significantly, and it is detected as being in the late stage of life through a comparator. The correction algorithm logic knows that this is an RC delay circuit, so it adjusts the resistor R back to 1 KΩ by modifying the correction code. In an actual circuit, C may also change. At this time, the correction code needs to be adjusted according to the comprehensive changes of R and C.

[0071] Embodiment 2:

[0072] The present invention provides a correction compensation method for simulating the anti-aging of a chip, including the following steps:

[0073] S1. Obtain the standard current output by the reference current source, generate an internal current through an adjustable current source, compare the reference current and the internal current using a current comparator, generate a correction code for the internal current source, and burn it into the non-volatile memory inside the chip;

[0074] S2. Use a metal resistor to simulate the device aging process, and the resistance value of the metal resistor gradually increases with time;

[0075] S3. Detect the voltage difference across the metal resistor through a comparator, obtain the chip life information, and divide the chip life into different stages;

[0076] S4. Generate a correction code according to the life information, and apply the correction code to adjust the resistance and capacitance values of the analog circuit through a programmable resistor-capacitor network interface to compensate for the losses caused by device aging.

[0077] In this embodiment, the current comparator compares the reference current and the internal current. When the difference between the two exceeds the set threshold, a correction code is generated. The correction code is an 8-bit binary number. The non-volatile memory uses EFUSE, which can store the correction code for a long time to ensure the stable performance of the chip under different temperatures and working conditions.

[0078] Using a metal resistor to simulate the device aging process, under high temperature and high current density conditions, metal atoms will undergo electromigration, resulting in a gradual increase in the resistance value, reflecting the performance degradation of other devices inside the chip, providing a basis for subsequent correction.

[0079] Detect the voltage difference across the metal resistor through a comparator, obtain the chip life information, divide the chip life into different stages, generate a correction code according to the life information, and apply the correction code to adjust the resistance and capacitance values of the analog circuit through a programmable resistor-capacitor network interface to compensate for the losses caused by device aging. This adjustment can effectively compensate for the performance degradation caused by device aging and extend the service life of the chip.

[0080] The embodiments of the present invention have been described above. The above description is exemplary and not exhaustive, and is also not limited to the disclosed embodiments. Many modifications and variations are obvious to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A calibration compensation system for simulating the anti-aging of a chip, characterized in that The system includes: An aging simulation unit, including a current source system and a metal resistor, for simulating the chip aging process. The current source system generates a current that flows through the metal resistor to produce an electromigration effect, causing the resistance value of the metal resistor to gradually increase; An aging compensation unit, including a comparator, a correction control circuit, and an analog circuit. The comparator is used to detect the output voltage difference across the metal resistor to obtain chip life information; the correction control circuit generates a correction code based on the chip life information and superimposes it on the analog circuit to compensate for the loss caused by device aging; The correction control circuit includes a number of correction code generation modules. The number of correction code generation modules is the same as the number of correction code bits. Each correction code generation module includes a director, at least two AND gate circuits, and an OR gate circuit; wherein, The director, according to the comparison result of the comparator, directs the output signal of the comparator to at least two AND gate circuits respectively; At least two AND gate circuits, one input terminal of one AND gate circuit is connected to the ground, and one input terminal of the other AND gate circuit is connected to the power supply; The OR gate circuit performs an OR operation on the outputs of the at least two AND gate circuits and outputs a correction code; wherein, the output signal of the comparator represents the aging degree of the chip to be tested, and the correction code is used to compensate and correct the aging characteristics of the chip to be tested.

2. The calibration compensation system for simulating the anti-aging of a chip according to claim 1, wherein The current source system includes: An adjustable current source, for generating an adjustable current; An external correction loop, including a standard current source and a current comparator, for accessing the standard current source through a reserved external pin. The current comparator compares the reference current generated by the standard current source with the internal current generated by the adjustable current source, generates a correction code for the internal current source, and burns it into the internal non-volatile memory of the chip.

3. The calibration and compensation system for simulating the anti-aging of a chip according to claim 1, wherein The comparator is an analog-to-digital converter, which detects the voltage in years and divides the chip life into different stages according to the voltage difference.

4. The calibration and compensation system for simulating the anti-aging of a chip according to claim 3, wherein, The comparator includes a two-way comparator or a four-way comparator. The two-way comparator divides the chip life into the initial stage and the final stage, and the four-way comparator divides the chip life into the initial stage, the early middle stage, the late middle stage, and the final stage.

5. The calibration and compensation system for simulating the anti-aging of a chip according to claim 4, characterized in that, The output result of the two-way comparator is 0 or 1. When the output result is 0, it represents an initial-stage chip, and when the output result is 1, it represents a final-stage chip.

6. The calibration and compensation system for simulating chip anti-aging according to claim 1, characterized in that, The number of AND gate circuits is the same as the number of branches of the comparator. When the comparator is a two-way comparator, two AND gate circuits are used. When the comparator is a four-way comparator, four AND gate circuits are used.

7. The calibration and compensation system for simulating the anti-aging of a chip according to claim 1, wherein, In the aging compensation unit, the analog circuit uses a programmable resistor-capacitor network. According to the obtained life information, corresponding correction codes are generated for different analog circuits, and the resistance and capacitance of the analog circuit are finely adjusted through the programmable resistor-capacitor network interface to compensate for the loss caused by aging.

8. A correction and compensation method adopted by the system according to any one of claims 1-7, characterized in that S1. Obtain the standard current output by the reference current source, generate an internal current through the adjustable current source, use the current comparator to compare the reference current with the internal current, generate a correction code for the internal current source, and burn it into the internal non-volatile memory of the chip; S2. Use a metal resistor to simulate the device aging process, and the resistance value of the metal resistor gradually increases with time; S3. Detect the voltage difference across the metal resistor through a comparator to obtain chip life information and divide the chip life into different stages; S4. Generate a correction code based on the life information and apply the correction code to adjust the resistance and capacitance values of the analog circuit through a programmable resistor-capacitor network interface to compensate for the losses caused by device aging.

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