Photoetching method of super junction alignment structure and manufacturing method of super junction device

Abstract

The invention relates to a photoetching method of a super junction alignment structure and a manufacturing method of a super junction device. The photoetching method of the super junction alignment structure comprises the following steps: obtaining a wafer on which an epitaxial layer is formed on a substrate; coating photoresist on the epitaxial layer at the top of the wafer; after the position of an alignment structure photoetching plate is corrected according to the crystal orientation deviation angle of the substrate, the photoresist is exposed through the alignment structure photoetching plate; the crystal orientation deviation angle of the substrate is the angle that the crystal orientation of the substrate deviates from the target crystal orientation. According to the relation between the crystal orientation deviation angle of the substrate and the alignment structure overlay error, the alignment structure (alignment mark) is formed after the position of the alignment structure photolithography mask is corrected, the overlay error of the alignment mark can be reduced, and finally the manufacturing cost, the abnormal rate and the Cycle time of a product can be reduced.

Description

Technical Field

[0001] The present application relates to semiconductor manufacturing, and in particular to a photolithography method for a super junction alignment structure, and also to a method for manufacturing a super junction device. Background Art

[0002] The multi-layer epitaxial super junction process forms N-columns and P-columns with balanced electric fields in each epitaxial layer, and stacks the multiple layers of epitaxy to a certain thickness to achieve a high-voltage, low-impedance device structure.

[0003] In the exemplary multi-layer epitaxial super junction process, the process flow of multiple epitaxy requires the use of an alignment layer every two epitaxy layers to ensure that the subsequent graphics will not shift. However, due to the poor shape retention of the epitaxial process, the alignment layer (alignment mark) is often affected by various factors and shifts, resulting in a large overlay error (Overlay, hereinafter referred to as OL value). Since the large OL value requires the product to be reworked and compensated, the manufacturing cost of the product and the cycle time are greatly increased. Summary of the invention

[0004] Based on this, it is necessary to provide a photolithography method for super junction alignment structure.

[0005] A photolithography method for a super junction alignment structure comprises: obtaining a wafer with an epitaxial layer formed on a substrate; coating photoresist on the epitaxial layer on top of the wafer; exposing the photoresist through the alignment structure photoresist after correcting the position of the alignment structure photoresist according to the crystal orientation deviation angle of the substrate; the crystal orientation deviation angle of the substrate is the angle at which the crystal orientation of the substrate deviates from the target crystal orientation.

[0006] The above-mentioned super junction alignment structure lithography method corrects the position of the alignment structure photolithography plate according to the relationship between the crystal orientation deviation angle of the substrate and the alignment structure overlay error and then forms the alignment structure (alignment mark), which can reduce the overlay error of the alignment mark and ultimately reduce the manufacturing cost, abnormality rate and cycle time of the product.

[0007] In one of the embodiments, after the step of exposing the photoresist through the alignment structure photomask, the method further includes: developing the photoresist to obtain a photoresist layer; and etching the photoresist layer as an etching barrier to obtain an alignment mark.

[0008] In one embodiment, the step of correcting the position of the alignment structure photomask according to the crystal deviation angle of the substrate comprises: obtaining an overlay error prediction value L1 of the alignment mark in the first direction according to the crystal deviation angle α of the substrate in the first direction, and obtaining an overlay error prediction value L2 of the alignment mark in the second direction according to the crystal deviation angle β of the substrate in the second direction; correcting the position of the alignment structure photomask by -a×L1 in the first direction, and correcting the position of the alignment structure photomask by -b×L2 in the second direction, where a and b are correction coefficients, and 0 <a≤1,0<b≤1。

[0009] In one embodiment, the first direction is perpendicular to the second direction.

[0010] In one embodiment, L1=1.984α-0.038; L2=1.203β+0.01.

[0011] In one embodiment, a=b=1 / 2.

[0012] In one of the embodiments, an initial alignment mark located below the epitaxial layer is formed on the substrate.

[0013] It is also necessary to provide a method for manufacturing a super junction device.

[0014] A method for manufacturing a super junction device comprises: controlling the crystal orientation deviation angle of a substrate acquired according to the overlay error control requirement of a super junction alignment structure; and performing alignment structure lithography according to the lithography method of the super junction alignment structure described in any of the above embodiments.

[0015] The manufacturing method of the super junction device described above firstly controls the crystal deviation angle of the substrate to make the overlay error of the multi-layer epitaxial super junction alignment structure fluctuate within the required range. On this basis, the lithography of the super junction alignment structure is further pre-compensated, that is, according to the relationship between the crystal deviation angle of the substrate and the overlay error of the alignment structure, the position of the alignment structure photomask is corrected and then the alignment structure (alignment mark) is formed, which can reduce the overlay error of the alignment mark, and ultimately reduce the manufacturing cost, abnormality rate and cycle time of the product.

[0016] In one of the embodiments, the step of obtaining the crystal orientation deviation angle of the substrate by card control is that α is within ±0.1 degree and β is within ±0.1 degree.

[0017] In one embodiment, the epitaxial layer is a first conductive type epitaxial layer, and the method also includes the step of forming a second conductive type column, the step of forming the second conductive type column includes performing photolithography of the second conductive type region, and the photolithography alignment of the second conductive type region is aligned through the super junction alignment structure; the first conductive type and the second conductive type are opposite conductive types.

[0018] In one embodiment, the first conductivity type is N-type, and the second conductivity type is P-type. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to better describe and illustrate the embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more drawings. The additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the embodiments and / or examples currently described, and the best modes of these inventions currently understood.

[0020] Figure 1 is a schematic diagram of an exemplary overlay error of a multi-layer epitaxial super junction alignment structure;

[0021] Figure 2 is a flow chart of a photolithography method for super junction alignment structure in one embodiment of the present application;

[0022] Figure 3 is a flowchart of the sub-steps of step S230 in one embodiment of the present application;

[0023] Figure 4 is a flow chart of a method for manufacturing a super junction device in one embodiment of the present application;

[0024] Figure 5 It is a schematic diagram of the overlay error of the alignment structure of a super junction device manufactured by the method for manufacturing a super junction device in an embodiment of the present application. DETAILED DESCRIPTION

[0025] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present invention are shown in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0027] It should be understood that the purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present invention. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the terms "consisting of" and / or "comprising" when used in this specification determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0028] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of the invention. Thus, variations from the shapes shown due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, embodiments of the invention should not be limited to the specific shapes of the zones shown herein, but include shape deviations due to, for example, manufacturing. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the actual shape of the region of the device and are not intended to limit the scope of the invention.

[0029] The semiconductor field vocabulary used in this article is technical vocabulary commonly used by technical personnel in this field. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents P-type with heavy doping concentration, P-type represents P-type with medium doping concentration, P-type represents P-type with light doping concentration, N+ type represents N-type with heavy doping concentration, N-type represents N-type with medium doping concentration, and N-type represents N-type with light doping concentration.

[0030] For example, the overlay error of the alignment mark can be reduced by optimizing the conformality of the epitaxial process, optimizing the etching morphology, improving the recognition capability of the photolithography machine, etc. These methods are all based on the optimization of the Fab (semiconductor factory) machine end.

[0031] The inventors have found through research that the overlay error of the multi-layer epitaxial super junction alignment structure is strongly correlated with the crystal orientation deviation angle of the substrate (i.e., the angle at which the crystal orientation of the substrate deviates from the target crystal orientation). For example, a wafer with a crystal orientation deviation angle of 0° and 0.3° in the X-axis direction of the substrate is taken, and after etching the initial alignment mark (ZERO MARK, abbreviated as ZM), an epitaxial layer of a certain thickness is grown. The initial alignment mark is then aligned with the lithography machine for measurement again, and it is found that for a wafer with a crystal orientation deviation angle of 0°, the measured overlay error in the X-axis direction is 0, while for a wafer with a crystal orientation deviation angle of 0.3°, the measured overlay error in the X-axis direction can reach 0.6 microns (see Figure 1 ). Therefore, based on the relationship between the crystal orientation deviation angle of the substrate and the overlay error of the alignment mark, the present application proposes a photolithography method for a super junction alignment structure and a method for manufacturing a super junction device.

[0032] Figure 2 1 is a flow chart of a photolithography method for super junction alignment structure in one embodiment of the present application, comprising the following steps:

[0033] S210, obtaining a wafer having an epitaxial layer formed on a substrate.

[0034] In one embodiment of the present application, the multi-layer epitaxial super junction process includes re-forming (refreshing) an alignment structure after forming several layers (e.g., two layers) of epitaxial layers of the first conductivity type on the substrate. The function of the alignment structure is that when performing photolithography of the second conductivity type region in the super junction, the photomask is aligned through the alignment structure. Therefore, before performing photolithography of the super junction alignment structure, several layers of epitaxial layers of the first conductivity type must first be formed on the substrate. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type.

[0035] In one embodiment of the present application, before forming the epitaxial layer, an initial alignment mark (ZERO MARK) is first formed on the substrate.

[0036] S220 , coating photoresist on the epitaxial layer on the top of the wafer.

[0037] After forming a preset number of epitaxial layers, photoresist is coated on the epitaxial layers to perform super junction alignment structure lithography.

[0038] S230, after correcting the position of the alignment structure photomask according to the crystal orientation deviation angle of the substrate, the photoresist is exposed.

[0039] According to the above, the overlay error of the super junction alignment structure is strongly correlated with the crystal deviation angle of the substrate. Therefore, according to the crystal deviation angle of the substrate, the overlay error prediction value of the alignment structure can be obtained, and the position of the alignment structure photomask can be corrected according to the prediction value, and then the photoresist is exposed. After exposure, the photoresist can be developed to obtain a photoresist layer, and then the photoresist layer is used as an etching barrier layer to etch the alignment mark.

[0040] In one embodiment of the present application, before step S230, a step of obtaining a crystal orientation deviation angle of the substrate is further included. The crystal orientation deviation angle of the substrate can be measured using a measurement method known in the art.

[0041] In one embodiment of the present application, the corresponding relationship between the crystal orientation deviation angle of the substrate and the alignment structure overlay error can be obtained by fitting the relationship between the crystal orientation deviation angle of the substrate and the alignment structure overlay error by actually measuring the alignment structure overlay errors corresponding to multiple groups of substrates with different crystal orientation deviation angles. In one embodiment of the present application, the crystal orientation deviation angle of the substrate is measured in both the X-axis direction and the Y-axis direction.

[0042] The above-mentioned super junction alignment structure lithography method corrects the position of the alignment structure photolithography plate according to the relationship between the crystal orientation deviation angle of the substrate and the alignment structure overlay error and then forms the alignment structure (alignment mark), which can reduce the overlay error of the alignment mark and ultimately reduce the manufacturing cost, abnormality rate and cycle time of the product.

[0043] See also Figure 3 In one embodiment of the present application, step S230 includes the following steps:

[0044] S232, obtaining a predicted overlay error value L1 of the alignment mark in the first direction according to a crystal orientation deviation angle α of the substrate in the first direction.

[0045] If the corresponding relationship between the crystal orientation deviation angle of the substrate and the alignment structure overlay error is known, L1 can be calculated based on α.

[0046] S234, obtaining a predicted overlay error value L2 of the alignment mark in the second direction according to a crystal orientation deviation angle β of the substrate in the second direction.

[0047] In other embodiments, step S234 may be performed first, and then step S232, or both may be performed simultaneously. In one embodiment of the present application, the first direction is perpendicular to the second direction. For example, the first direction is the X-axis direction, and the second direction is the Y-axis direction.

[0048] S236, correcting the position of the alignment structure photomask by -a×L1 in the first direction.

[0049] The negative sign indicates that the reverse movement should be made in the direction of the Overlay offset of the photomask. a is a correction factor, and 0 < a ≤ 1. A correction factor less than 1 is used to avoid overcompensation.

[0050] S238, correct the position of the alignment structure photomask in the second direction by -b × L2.

[0051] In other embodiments, step S238 can also be executed first, then step S236, or they can be carried out simultaneously. b is a correction factor, and 0 < b ≤ 1. In an embodiment of the present application, a = b = 1 / 2.

[0052] The relationship between the crystal orientation deviation angle of the substrate actually measured and fitted by the inventor and the overlay error of the alignment structure satisfies the following relation:

[0053] L1 = 1.984α - 0.038 (standard deviation: 0.078); L2 = 1.203β + 0.01 (standard deviation: 0.089). The units of L1 and L2 in this relation are micrometers.

[0054] Figure 4 is a flowchart of a manufacturing method of a superjunction device in an embodiment of the present application, including the following steps:

[0055] S410, control the crystal orientation deviation angle of the obtained substrate according to the overlay error control requirements of the superjunction alignment structure.

[0056] According to the foregoing, after obtaining the corresponding relationship between the crystal orientation deviation angle of the substrate and the overlay error of the alignment structure, the control requirements for the crystal orientation deviation angle of the substrate can be deduced based on the overlay error control requirements of the superjunction alignment structure - for example, requiring the overlay error of the superjunction alignment structure to be controlled within the range of ±0.4 micrometers (±3std). After controlling the crystal orientation deviation angle of the substrate accordingly, the overlay error of the multi-layer epitaxial superjunction alignment structure can fluctuate within the required range. Here, std (Standard Deviation) represents the standard deviation σ. In actual production, the process capabilities of the substrate manufacturer and the cost increase caused by controlling the crystal orientation deviation angle of the substrate to be very small also need to be considered. In an embodiment of the present application, α is controlled within ±0.1 degrees, and β is controlled within ±0.1 degrees.

[0057] In actual production, for α ∈ [-0.1°, 0.1°] and β ∈ [-0.1°, 0.1°], there may still be cases where the overlay error of the superjunction alignment structure exceeds the SPEC (range index). In this regard, according to the corresponding relationship between the crystal orientation deviation angle of the substrate and the overlay error of the alignment structure, pre-compensation is further performed on the lithography of the superjunction alignment structure, that is, pre-compensation is performed using the foregoing lithography method of the superjunction alignment structure, including the following steps:

[0058] S420, obtaining a wafer having an epitaxial layer formed on a substrate.

[0059] In one embodiment of the present application, the multi-layer epitaxial super junction process includes re-forming an alignment structure after each formation of several layers of epitaxial layers of the first conductivity type on the substrate. The function of the alignment structure is: when performing photolithography of the second conductivity type region in the super junction, the photomask is aligned through the alignment structure. Therefore, before performing photolithography of the super junction alignment structure, several layers of epitaxial layers of the first conductivity type must first be formed on the substrate. In one embodiment of the present application, the first conductivity type is N-type and the second conductivity type is P-type.

[0060] In one embodiment of the present application, before forming the epitaxial layer, an initial alignment mark (ZERO MARK) is first formed on the substrate.

[0061] S430 , coating photoresist on the epitaxial layer on the top of the wafer.

[0062] After forming a preset number of epitaxial layers, photoresist is coated on the epitaxial layers to perform super junction alignment structure lithography.

[0063] S440, after correcting the position of the alignment structure photomask according to the crystal orientation deviation angle of the substrate, the photoresist is exposed.

[0064] According to the above, the overlay error of the super junction alignment structure is strongly correlated with the crystal orientation deviation angle of the substrate. Therefore, based on the crystal orientation deviation angle of the substrate, the overlay error prediction value of the alignment structure can be obtained, and the position of the alignment structure photomask can be corrected according to the predicted value before the photoresist is exposed.

[0065] In one embodiment of the present application, before step S440, a step of obtaining a crystal orientation deviation angle of the substrate is also included.

[0066] The manufacturing method of the super junction device described above firstly controls the crystal deviation angle of the substrate to make the overlay error of the multi-layer epitaxial super junction alignment structure fluctuate within the required range. On this basis, the lithography of the super junction alignment structure is further pre-compensated, that is, according to the relationship between the crystal deviation angle of the substrate and the overlay error of the alignment structure, the position of the alignment structure photomask is corrected and then the alignment structure (alignment mark) is formed, which can reduce the overlay error of the alignment mark, and ultimately reduce the manufacturing cost, abnormality rate and cycle time of the product.

[0067] See also Figure 3 In one embodiment of the present application, step S440 includes the following steps (same as step S230):

[0068] S232, obtaining a predicted overlay error value L1 of the alignment mark in the first direction according to a crystal orientation deviation angle α of the substrate in the first direction.

[0069] If the corresponding relationship between the crystal orientation deviation angle of the substrate and the alignment structure overlay error is known, L1 can be calculated according to α. In one embodiment of the present application, L1 = 1.984α - 0.038 (standard deviation: 0.078).

[0070] S234, obtaining a predicted overlay error value L2 of the alignment mark in the second direction according to a crystal orientation deviation angle β of the substrate in the second direction.

[0071] In one embodiment of the present application, the first direction is perpendicular to the second direction. For example, the first direction is the X-axis direction, and the second direction is the Y-axis direction. In one embodiment of the present application, L2 = 1.203β + 0.01 (standard deviation: 0.089). Under the conditions of α∈[-0.1°, 0.1°], β∈[-0.1°, 0.1°], the calculated absolute value fluctuation range of L1 and L2 (+3std) ≤ 0.43 (micrometers).

[0072] S236, correcting the position of the alignment structure photomask by -a×L1 in the first direction.

[0073] The negative sign indicates that the Overlay offset direction of the photomask needs to be moved in the opposite direction. a is the correction coefficient, and 0 <a≤1。

[0074] S238, correcting the position of the alignment structure photomask by -b×L2 in the second direction.

[0075] b is the correction coefficient, and 0 <b≤1。

[0076] In order to avoid overcompensation, in one embodiment of the present application, a=b=1 / 2 is taken. Then the final super junction alignment structure overlay error fluctuation range (±3std) is: X coordinate ±0.31 micron, Y coordinate ±0.33 micron. It can meet the Fab's control requirements for the overlay error of the super junction device alignment structure, and greatly reduce the rework ratio of the multi-layer epitaxial super junction process in the Fab.

[0077] Figure 5 1 is a schematic diagram of the overlay error of the alignment structure of a super junction device manufactured by the manufacturing method of the super junction device in one embodiment of the present application. The overlay error of the alignment structure of the super junction device obtained by the manufacturing method of the super junction device of the present application can approach 0.

[0078] exist Figure 4 In the illustrated embodiment, after step S440, the following steps are further included:

[0079] S450, developing the photoresist to obtain a photoresist layer.

[0080] The photoresist exposed in step S440 is developed using a developer to obtain a photoresist layer having an alignment mark pattern on the alignment structure photomask.

[0081] S460, using the photoresist layer as an etching barrier layer, etching to obtain an alignment mark.

[0082] The photoresist layer obtained in step S450 is used as an etching barrier layer, and the epitaxial layer is etched to obtain an alignment mark.

[0083] S470 , forming a second conductive type column.

[0084] Before step S470, the photoresist layer obtained in step S450 must be removed. Step S470 includes performing photolithography in the second conductive type area, and the alignment of the photolithography is performed by aligning through a super junction alignment structure (i.e., the alignment mark obtained in step S460). In one embodiment of the present application, after photolithography, the second conductive type ions can be implanted with the photoresist as an injection barrier layer, thereby forming a second conductive type area in the epitaxial layer. Then, a push well is performed so that the second conductive type is connected to the second conductive type area in the epitaxial layer below, i.e., connected to form a second conductive type column. The second conductive type column and the epitaxial layer of the first conductive type form a super junction. In another embodiment of the present application, after performing photolithography in the second conductive type area, a groove can also be etched in the epitaxial layer with the photoresist as an etching barrier layer, and then the second conductive type area is filled in the groove (forming a second conductive type epitaxial layer), and the second conductive type area in the groove is connected to the second conductive type area in the epitaxial layer below, i.e., connected to form a second conductive type column.

[0085] The present application accordingly provides a super junction device, which is manufactured according to the manufacturing method of the super junction device described in any of the aforementioned embodiments.

[0086] It should be understood that, although the various steps in the flowchart of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence in the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowchart of the present application may include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0087] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0088] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0089] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A photolithography method for super junction alignment structure, comprising: obtaining a wafer having an epitaxial layer formed on a substrate; coating a photoresist on the epitaxial layer on top of the wafer; After correcting the position of the alignment structure photomask according to the crystal orientation deviation angle of the substrate, exposing the photoresist through the alignment structure photomask; The crystal orientation deviation angle of the substrate is an angle at which the crystal orientation of the substrate deviates from the target crystal orientation.

2. The photolithography method for super junction alignment structure according to claim 1, characterized in that: After the step of exposing the photoresist through the alignment structure photomask, the method further comprises: developing the photoresist to obtain a photoresist layer; The photoresist layer is used as an etching barrier layer to obtain an alignment mark by etching.

3. The photolithography method for super junction alignment structure according to claim 1, characterized in that: The step of correcting the position of the alignment structure photomask according to the crystal orientation deviation angle of the substrate comprises: Obtaining a predicted overlay error value L1 of the alignment mark in the first direction according to a crystal orientation deviation angle α of the substrate in the first direction, and obtaining a predicted overlay error value L2 of the alignment mark in the second direction according to a crystal orientation deviation angle β of the substrate in the second direction; The position of the alignment structure photomask is corrected by -a×L1 in the first direction, and the position of the alignment structure photomask is corrected by -b×L2 in the second direction, where a and b are correction coefficients, and 0 <a≤1,0<b≤1。 4. The photolithography method for super junction alignment structure according to claim 3, characterized in that: The first direction is perpendicular to the second direction.

5. The photolithography method for super junction alignment structure according to claim 3, characterized in that: L1=1.984α-0.038; L2=1.203β+0.

01.

6. The photolithography method for super junction alignment structure according to claim 1, characterized in that: An initial alignment mark is formed on the substrate and is located below the epitaxial layer.

7. A method for manufacturing a super junction device, comprising: According to the overlay error control requirements of the super junction alignment structure, the crystal orientation deviation angle of the substrate obtained by the card control; Perform alignment structure lithography according to the super junction alignment structure lithography method according to any one of claims 1 to 6.

8. The method for manufacturing a super junction device according to claim 7, characterized in that: The step of obtaining the crystal orientation deviation angle of the substrate by card control is that α is within ±0.1 degree and β is within ±0.1 degree.

9. The method for manufacturing a super junction device according to claim 7, characterized in that: The epitaxial layer is a first conductive type epitaxial layer, and the method also includes the step of forming a second conductive type column, the step of forming the second conductive type column includes performing photolithography of a second conductive type region, and the photolithography alignment of the second conductive type region is aligned through the super junction alignment structure; the first conductive type and the second conductive type are opposite conductive types.

10. A super junction device, characterized in that: The super junction device is manufactured according to the manufacturing method of any one of claims 7 to 9.

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