Server and fan control method

Abstract

The invention provides a server and a fan control method, and belongs to the technical field of servers. The server and fan control method comprises the steps that a CPLD detects relevant information of a fan and feeds back the relevant information of the fan to a BMC of each half-width mainboard; the BMC of each half-width mainboard generates a PWM (Pulse Width Modulation) signal set for controlling each currently plugged fan according to the related information of the fan, and sends the PWM signal set to the CPLD; the CPLD detects the effectiveness of the BMC of each half-width mainboard and determines a fan control strategy according to the effectiveness detection result; and the CPLD controls each currently plugged fan according to the fan control strategy. According to the server and the fan control method provided by the invention, the purpose of fan control is achieved, and the problem of complete machine heat dissipation of the independent half-width mainboard server is solved.

Description

Technical Field

[0001] The present application relates to the technical field of servers, and in particular to a server and a fan control method. Background Art

[0002] 1U or 2U rack-mounted server motherboards are usually designed with dual CPUs. The two CPUs are interconnected through a high-speed bus, such as the UPI bus of the Intel platform, that is, a 2S configuration. The CPLD chip inside the board controls the power-on and power-off timing, and the BMC is used to implement out-of-band management. The BMC is used to detect the chip temperature inside the board and the chassis environment to control the fan speed and solve the heat dissipation problem of the entire machine.

[0003] In recent years, in order to achieve configuration diversity and some specific application scenarios, the dual CPU design of the server motherboard has been adopted, and the two CPUs are not interconnected, and the decoupling design is adopted. At this time, the heat dissipation problem of the server has become the focus of attention. Summary of the invention

[0004] In view of this, the present application provides a server and a fan control method to achieve the purpose of fan control and solve the heat dissipation problem of an independent half-width motherboard server.

[0005] Specifically, the present application is implemented through the following technical solutions: The first aspect of the present application provides a server, the server comprising a first half-width mainboard, a second half-width mainboard and a fan backplane; the first half-width mainboard and the second half-width mainboard have the same structure, each half-width mainboard comprises a BMC and a CPU connected to the BMC; the fan backplane comprises a CPLD and a plurality of fan slots for plugging fans connected to the CPLD, the BMC of each half-width mainboard is connected to the CPLD via an I2C buffer; wherein, The CPLD is used to detect fan-related information and feed back the fan-related information to the BMC of each half-width motherboard; wherein the fan-related information includes the fan plug-in status of each fan slot and the status parameters of each currently plugged-in fan; The BMC of each half-width motherboard is used to generate a PWM signal set for controlling each currently plugged in fan according to the fan related information, and send the PWM signal set to the CPLD; The CPLD is also used to detect the validity of the BMC of each half-width motherboard and determine the fan control strategy according to the validity detection result; wherein the fan control strategy includes controlling the fan according to its own control logic or controlling the fan according to the PWM signal set from the BMC; The CPLD is also used to control each currently plugged in fan according to the fan control strategy.

[0006] A second aspect of the present application provides a fan control method, which is applied to a server, wherein the server includes a first half-width mainboard, a second half-width mainboard and a fan backplane; the first half-width mainboard and the second half-width mainboard have the same structure, each half-width mainboard includes a BMC and a CPU connected to the BMC; the fan backplane includes a CPLD and a plurality of fan slots for plugging fans connected to the CPLD, and the BMC of each half-width mainboard is connected to the CPLD via an I2C buffer; wherein the method includes: The CPLD detects fan-related information and feeds back the fan-related information to the BMC of each half-width motherboard; wherein the fan-related information includes the fan plug-in status of each fan slot and the status parameters of each currently plugged-in fan; The BMC of each half-width motherboard generates a PWM signal set for controlling each currently plugged in fan according to the fan related information, and sends the PWM signal set to the CPLD; The CPLD detects the validity of the BMC of each half-width motherboard and determines a fan control strategy according to the validity detection result; wherein the fan control strategy includes controlling the fan according to its own control logic or controlling the fan according to a PWM signal set from the BMC; The CPLD controls each currently plugged in fan according to the fan control strategy.

[0007] The server and fan control method provided by the present application, in the first aspect, based on the CPLD on the fan backplane to detect the fan related information, and then based on the BMC on two independent half-width mainboards to independently control the fan, that is, through the BMC on the two half-width mainboards to independently generate the PWM signal set for controlling the fan, so as to determine the fan control strategy based on the CPLD on the fan backplane to detect the effectiveness of the two half-width mainboards, so that not only can the purpose of fan control be achieved, but also the whole machine heat dissipation problem of the independent half-width mainboard server can be solved. In addition, by using CPLD to decide the fan control strategy, not only can the fan control be more flexible, but also the consumption of logic resources can be reduced and the cost can be reduced. In the second aspect, by changing the full-width mainboard to two half-width mainboards, and for each half-width mainboard, the same structure is designed, including a CPU and a BMC connected to the CPU, and the CPUs of the two half-width mainboards are not interconnected, and a decoupling design mode is adopted. When a hardware failure occurs in a half-width mainboard, only the corresponding faulty half-width mainboard needs to be replaced separately, without replacing the entire full-width mainboard, which can save the consumption cost of the board; in the third aspect, there is no communication between the BMCs of the two half-width mainboards, which can save the cost of the communication source code development between the BMCs. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1A schematic diagram of the structure of the server provided for this application; Figure 2 A control principle diagram inside a CPLD shown as an exemplary embodiment of the present application; Figure 3 This is a flow chart of Example 1 of the fan control method provided in this application. DETAILED DESCRIPTION

[0009] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0010] The terms used in this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The singular forms of "a", "said" and "the" used in this application are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used in this article refers to and includes any or all possible combinations of one or more associated listed items.

[0011] It should be understood that although the terms first, second, third, etc. may be used in the present application to describe various information, these information should not be limited to these terms. These terms are only used to distinguish the same type of information from each other. For example, without departing from the scope of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0012] Specific embodiments are given below to introduce the technical solution of the present application in detail.

[0013] The following is a description of the components that may appear in this application: BMC: Baseboard Management Controller; CPU: Central Processing Unit; CPLD: Complex Programming logic device; I2C buffer: I2C bus buffer (Inter-Integrated Circuit Bus Buffer); PWM signal: Pulse Width Modulation signal (Pulse Width Modulation).

[0014] Figure 1 The structural diagram of the server provided for this application. Please refer to Figure 1 , the server includes a first half-width mainboard, a second half-width mainboard and a fan backplane; the first half-width mainboard and the second half-width mainboard have the same structure, each half-width mainboard includes a BMC and a CPU connected to the BMC; the fan backplane includes a CPLD and a plurality of fan slots for plugging fans connected to the CPLD, and the BMC of each half-width mainboard is connected to the CPLD via an I2C bus; wherein, The CPLD is used to detect fan-related information and feed back the fan-related information to the BMC of each half-width motherboard; wherein the fan-related information includes the fan plug-in status of each fan slot and the status parameters of each currently plugged-in fan; The BMC of each half-width motherboard is used to generate a PWM signal set for controlling each currently plugged in fan according to the fan related information, and send the PWM signal set to the CPLD; The CPLD is also used to detect the validity of the BMC of each half-width motherboard and determine the fan control strategy according to the validity detection result; wherein the fan control strategy includes controlling the fan according to its own control logic or controlling the fan according to the PWM signal set from the BMC; The CPLD is also used to control each currently plugged in fan according to the fan control strategy.

[0015] The following is an introduction to the specific structure of the server provided by this application. Figure 1 The server provided by the present application includes a first half-width motherboard, a second half-width motherboard and a fan backplane. It should be noted that the half-width motherboard is a motherboard size standard commonly used in servers. Compared with a standard full-width motherboard, its width is only half of the width of a standard full-width motherboard.

[0016] For further information, please refer to Figure 1 The first half-width motherboard and the second half-width motherboard have the same structure, both including BMC and CPU; wherein, BMC and CPU are connected via PECI interface. PECI interface is a dedicated single-line bus between processor and other chips or system stability monitoring devices. In addition to detecting the built-in temperature status of CPU, a temperature sensor is also placed inside the board. It should be noted that the general temperature sensor is I2C interface. In this way, BMC can read the temperature status of the server as one of the bases for controlling the PWM signal of the fan.

[0017] In the server provided by the present application, the first half-width motherboard and the second half-width motherboard are independent half-width motherboards, the CPU of the first half-width motherboard and the CPU of the second half-width motherboard are not interconnected, and the two CPUs are connected to the BMC on each half-width motherboard; that is, for the two half-width motherboards, the structures are exactly the same, and the CPU and BMC are independent of each other. In this way, the functions of the two half-width motherboards are independent of each other, so that they can be independently developed, tested and maintained, which can improve the overall maintainability, flexibility and scalability of the server.

[0018] For further information, please refer to Figure 1 ,There is no communication between the BMCs of the first half-width motherboard and the second half-width motherboard, which saves the cost of developing source code for communication between BMCs.

[0019] In addition, referring to the previous description, the structures of the two half-width motherboards are identical and their functions are independent of each other. Thus, when a hardware failure occurs in a half-width motherboard, only the corresponding faulty half-width motherboard needs to be replaced instead of the entire full-width motherboard, thus saving the cost of board materials.

[0020] Specifically, the fan backplane is used to manage and control the fans in the server, which is located in the fan slot area inside the server chassis, including the CPLD and a plurality of fan slots connected to the CPLD for plugging in fans. Among them, the fan slot refers to a position specifically used to install and connect the server fan, and these slots are usually located in the fan area inside the server chassis. It can be understood that the fan area includes the fan slot area.

[0021] It should be noted that a fan slot on the fan backplane is used to plug in a fan. For example, in one embodiment, there are 6 fan slots on the fan backplane, each of which is plugged with a fan, namely fan slot 1, fan slot 2, fan slot 3, fan slot 4, fan slot 5, and fan slot 6. Fan slot 1 is plugged with fan 1, fan slot 2 is plugged with fan 2, fan slot 3 is plugged with fan 3, ..., and fan slot 6 is plugged with fan 6.

[0022] It should be noted that the BMC of each half-width motherboard is connected to the CPLD of the fan backplane through an I2C buffer, so that effective communication and collaboration for fan control and monitoring can be achieved. Among them, the main function of the I2C buffer is to establish an I2C communication link between the BMC of the half-width motherboard and the CPLD of the fan backplane, and provide signal conversion and electrical isolation functions. Specifically, the BMC usually uses the I2C interface to communicate and control with external devices, and the CPLD may require a specific voltage or signal level to correctly receive and parse these communications. Therefore, by adding an I2C buffer, the signal level can be adjusted and signal isolation can be provided to ensure that the voltage isolation between the boards does not leak electricity, and ensure that the communication between the BMC of the half-width motherboard and the CPLD of the fan backplane is stable and reliable (data exchange and control). Among them, the signal level refers to the voltage level or voltage range used to represent and transmit digital signals. It should be noted that the I2C interface is an interface circuit for connecting to the I2C bus. Specifically, the I2C bus consists of two lines, namely the Clock line (clock line, a clock signal for synchronous data transmission) and the Data line (data line, used for actual data transmission).

[0023] Please continue to refer to Figure 1 The BMC of the first half-width motherboard is connected to an I2C buffer through an I2C interface, and the I2C buffer is connected to the CPLD through an I2C interface; the BMC of the second half-width motherboard is connected to another I2C buffer through an I2C interface, and the I2C buffer is connected to the CPLD through an I2C interface.

[0024] The following describes the implementation principle of the server's fan control: Specifically, as mentioned above, the CPLD is connected to the fan slot, and it can detect fan-related information. It should be noted that the fan-related information includes the fan plug-in status of each fan slot and the status parameters of each currently plugged in fan. Among them, the fan plug-in status is used to indicate whether the fan slot is currently plugged in with a fan, which includes plugged in with a fan and not plugged in with a fan; the fan status parameters include at least the fan speed, power and temperature.

[0025] Specifically, after detecting the fan-related information, the CPLD feeds back the fan-related information to the BMC of each half-width motherboard through the I2C bus.

[0026] Furthermore, after receiving the fan-related information, the BMC of each half-width motherboard generates a PWM signal set for controlling each currently plugged in fan according to the fan-related information, and sends the generated PWM signal set to the CPLD on the fan backplane through the I2C bus.

[0027] In specific implementation, the BMC can generate a PWM signal set for controlling each currently plugged in fan according to a preset fan control algorithm and strategy. For the specific implementation principle, please refer to the description in the relevant technology, which will not be repeated here.

[0028] It should be noted that the PWM signal set is a signal set composed of multiple PWM signals, which includes a PWM signal for controlling each fan currently plugged in. Further, it can be understood that the PWM signal used to control a fan can be used to adjust the speed and power of the fan. By adjusting the duty cycle of the PWM signal (i.e., the ratio of the high level duration to the cycle), the speed and power of the fan can be controlled. For example, in one embodiment, for a certain fan, the BMC needs to increase the speed of the fan to reduce the temperature. At this time, a PWM signal can be generated and sent to the CPLD to achieve dynamic fan control and adjustment.

[0029] It should be noted that since the first half-width motherboard and the second half-width motherboard are designed independently, after their respective BMCs receive fan-related information, they will generate a PWM signal for controlling the current fan, and then send the generated PWM signals to the CPLD according to their respective paths. The CPLD makes decisions based on actual conditions and determines the fan control strategy.

[0030] Specifically, the CPLD is also used to detect the validity of the BMC of each half-width motherboard and determine the fan control strategy according to the validity detection result.

[0031] Optionally, in a possible implementation, the validity of the BMC can be determined by detecting the status of the clock line and data line of the I2C bus. In specific implementation, the clock line on the I2C bus will periodically generate a pulse signal. By detecting the status of the clock line (for example, whether there is a normal clock pulse), it can be determined whether there is activity on the I2C bus; in normal communication, the signal on the data line will change according to the communication protocol (for example, sending address, data, etc.). By detecting the data transmission on the data line, it can be understood whether there is effective data interaction. In this way, the activity and response of the BMC can be indirectly detected by detecting the status of the clock line and the data line.

[0032] Optionally, in a possible implementation, the CPLD is specifically used to determine, when determining a fan control strategy based on a validity detection result, whether to control the fan according to its own control logic if the validity detection result indicates that both the BMC of the first half-width motherboard and the BMC of the second half-width motherboard are invalid; wherein the own control logic is to control each currently connected fan according to a preset speed.

[0033] Specifically, the preset rotation speed is set according to actual needs and is not limited in this embodiment.

[0034] Optionally, in a possible implementation, the CPLD is specifically used to determine, when determining a fan control strategy based on a validity detection structure, whether to control the fan according to a PWM signal set from the BMC if the validity detection result indicates that at least one of the BMCs of the first half-width motherboard and the second half-width motherboard is valid.

[0035] For example, when the validity detection result indicates that one of the BMCs of the first half-width motherboard and the BMCs of the second half-width motherboard is valid, the fan corresponding to the PWM signal is directly controlled according to each PWM signal in the PWM signal set from the currently valid BMC. For another example, when the validity detection result indicates that both the BMC of the first half-width motherboard and the BMC of the second half-width motherboard are valid, the fan corresponding to the PWM signal is controlled according to each PWM signal in the PWM signal set from any BMC.

[0036] In this way, when both half-width motherboards are invalid, the fan is controlled according to its own control logic. When one of the two half-width motherboards is valid, the fan is controlled according to the valid BMC PWM signal set, which can ensure that the control signal is valid and can still ensure the normal operation of the server fan when the BMC of one of the motherboards is invalid, thereby improving the fault tolerance rate. And when the BMCs of the two half-width motherboards are both valid, the fan is controlled by the PWM signal set of any BMC, and appropriate adjustments and decisions can be made according to the actual situation without being limited by the status or restrictions of a specific BMC, thereby improving the flexibility and applicability of the server.

[0037] Combined with the above example, when the validity detection result indicates that one of the BMCs of the first half-width motherboard and the BMC of the second half-width motherboard is valid, the CPLD controls the fan corresponding to the PWM signal according to each PWM signal in the PWM signal set from the currently valid BMC. For example, in one embodiment, if the BMC of the second half-width motherboard fails, the CPLD controls the fan corresponding to the PWM signal (fan 1, fan 2, fan 3, fan 4, fan 5, fan 6) according to each PWM signal (PWM11, PWM21, PWM31, PWM41, PWM51, PWM61) in the PWM signal set from the BMC of the first half-width motherboard. In other words, fan 1 is controlled by PWM11, fan 2 is controlled by PWM21, fan 3 is controlled by PWM31, fan 4 is controlled by PWM41, fan 5 is controlled by PWM51, and fan 6 is controlled by PWM61.

[0038] The server provided in this embodiment, firstly, detects fan-related information based on the CPLD on the fan backplane, and then independently controls the fan based on the BMC on two independent half-width mainboards, that is, the BMC on the two half-width mainboards independently generates a PWM signal set for controlling the fan, so as to determine the fan control strategy based on the effectiveness of the two half-width mainboards detected by the CPLD on the fan backplane, so that not only the purpose of fan control can be achieved, but also the heat dissipation problem of the independent half-width mainboard server can be solved. In addition, by using CPLD to decide the fan control strategy, not only the fan control can be made more flexible, but also the consumption of logic resources can be reduced, and the cost can be reduced. Secondly, by changing the full-width mainboard to two half-width mainboards, and designing each half-width mainboard with the same structure, both including a CPU and a BMC connected to the CPU, and making the CPUs of the two half-width mainboards not interconnected, a decoupling design mode is adopted, when a hardware failure occurs on a half-width mainboard, only the corresponding faulty half-width mainboard needs to be replaced separately, without replacing the entire full-width mainboard, which can save the consumption cost of the board; thirdly, there is no communication between the BMCs of the two half-width mainboards, which can save the cost of the communication source code development between the BMCs.

[0039] Optionally, in a possible implementation of the present application, the CPLD is specifically used to, when determining a fan control strategy according to the validity detection result, determine to control the fan according to a PWM signal set from the BMC if the validity detection result indicates that both the BMC of the first half-width motherboard and the BMC of the second half-width motherboard are valid; The CPLD is further used to determine whether there is a difference between a first PWM signal set from the BMC of the first half-width mainboard and a second PWM signal set from the BMC of the second half-width mainboard; The CPLD is further configured to control each fan currently plugged in by using a target PWM signal when there is a difference between the first PWM signal set and the second PWM signal set; wherein the target PWM signal is a PWM signal with a larger duty cycle among the PWM signals in the first PWM signal set for controlling the fan and the PWM signals in the second PWM signal set for controlling the fan; The CPLD is specifically used to determine, for each currently connected fan, a target half-width motherboard corresponding to the fan according to the correspondence between the motherboard and the fan slot when there is no difference between the first PWM signal set and the second PWM signal set, and to search for a target PWM signal for controlling the fan from the PWM signal set from the target half-width motherboard, and then control the fan using the target PWM signal.

[0040] It should be noted that whether there is a difference between the first PWM signal set from the BMC of the first half-width mainboard and the corresponding PWM signal in the second PWM signal set from the BMC of the second half-width mainboard can be judged based on whether the duty ratio difference between the two is greater than a preset threshold. If the duty ratio difference between all PWM signals is not greater than the preset threshold, it means that there is no difference between the two. If there is a duty ratio difference between at least one PWM signal greater than the preset threshold, it means that there is a difference between the two.

[0041] It should be noted that, optionally, in a possible implementation of the present application, the CPLD determines whether there is a difference between the first PWM signal set from the BMC of the first half-width mainboard and the second PWM signal set from the BMC of the second half-width mainboard, including: (11) For each fan currently plugged in, a first PWM signal for controlling the fan is obtained from a first PWM signal set from the BMC of the first half-width motherboard, and a second PWM signal for controlling the fan is obtained from a second PWM signal set from the BMC of the second half-width motherboard, and a duty cycle difference between the first PWM signal and the second PWM signal is compared to obtain a duty cycle difference corresponding to the fan.

[0042] It should be noted that the BMC of each half-width motherboard can generate a PWM signal to control the fan based on fan-related information. Each PWM signal corresponds to a duty cycle, where the duty cycle represents the ratio of the high level duration to the period. The duty cycle is usually expressed as a percentage. For example, a duty cycle of 50% means that the high level occupies half of the period.

[0043] For example, in one embodiment, there are 6 fans currently plugged in, namely, fan 1, fan 2, ..., fan 6. At this time, the first PWM signal set generated by the BMC of the first half-width motherboard includes 6 PWM signals; the second PWM signal set generated by the BMC of the second half-width motherboard also includes 6 PWM signals. The PWM signal sets generated by the BMCs of the two half-width motherboards are shown in Table 1: Table 1

[0044] Furthermore, for the first PWM signal set and the second PWM signal set, the duty cycle of the first PWM signal and the duty cycle of the second PWM signal used to control the same fan are compared, and the difference between the duty cycles is calculated to obtain the duty cycle difference corresponding to the fan. The duty cycle difference can reflect the effect and state of two different BMCs controlling the same fan, and a large duty cycle difference may indicate a difference in fan speed or control.

[0045] Furthermore, in combination with the example shown in Table 1, the duty cycle differences corresponding to each fan are calculated as shown in Table 2: Table 2 Duty cycle differences of various fans

[0046] (12) When the duty cycle differences corresponding to all currently connected fans are less than or equal to a preset threshold, it is determined that there is no difference between the first PWM signal set and the second PWM signal set.

[0047] It should be noted that the preset threshold is set according to actual needs and is not limited in this embodiment. For example, in one embodiment, the preset threshold is 20%.

[0048] (13) When a duty cycle difference corresponding to at least one fan among all the fans currently plugged in is greater than the preset threshold, it is determined that there is a difference between the first PWM signal set and the second PWM signal set.

[0049] Specifically, referring to Table 2, for example, in one embodiment, Difference 1, Difference 2, ..., Difference 6 are all less than or equal to a preset threshold value (20%), and it is determined that there is no difference between the first PWM signal set and the second PWM signal set. For another example, in another embodiment, Difference 1, Difference 2, Difference 3, Difference 4, and Difference 5 are less than or equal to a preset threshold value, but Difference 6 is greater than the preset threshold value, and it is determined that there is a difference between the first PWM signal set and the second PWM signal set.

[0050] Please continue to refer to Table 2. Optionally, when there is a difference between the first PWM signal set and the second PWM signal set, for each fan currently plugged in, a target PWM signal is used to control the fan; wherein the target PWM signal is a PWM signal with a larger duty cycle between the PWM signal in the first PWM signal set used to control the fan and the PWM signal in the second PWM signal set used to control the fan.

[0051] For example, in one embodiment, when there is a difference between the first PWM signal set and the second PWM signal set, the duty cycle of PWM11 is greater than PWM12, the duty cycle of PWM21 is greater than PWM22, the duty cycle of PWM31 is less than PWM32, the duty cycle of PWM41 is greater than PWM42, the duty cycle of PWM51 is greater than PWM52, and the duty cycle of PWM61 is less than PWM62, then PWM11 is used to control fan 1, PWM21 is used to control fan 2, PWM32 is used to control fan 3, PWM41 is used to control fan 4, PWM51 is used to control fan 5, and PWM62 is used to control fan 6.

[0052] Optionally, in a possible implementation, when there is no difference between the first PWM signal set and the second PWM signal set, for each fan currently plugged in, the target half-width motherboard corresponding to the fan is determined according to the correspondence between the motherboard and the fan slot, and the target PWM signal for controlling the fan is searched from the PWM signal set from the target half-width motherboard, and the fan is then controlled using the target PWM signal.

[0053] Specifically, when there is no difference between the first PWM signal set and the second PWM signal set, it means that the control logic of the BMC of the first half-width motherboard and the BMC of the second half-width motherboard are consistent at this time. According to the correspondence between the motherboard and the fan slot, the target half-width motherboard corresponding to the fan can be determined, and the target PWM signal for controlling the fan can be searched from the PWM signal set from the target half-width motherboard.

[0054] It should be noted that the correspondence between the motherboard and the fan slots represents the correspondence between the motherboard and the fans in position. For example, in one possible implementation, fan slots 1, 2, and 3 are closer to the first half-width motherboard, and fan slots 4, 5, and 6 are closer to the second half-width motherboard. Then, the first half-width motherboard corresponds to fan slots 1, 2, and 3, and the second half-width motherboard corresponds to fan slots 4, 5, and 6.

[0055] Combined with the above example, at this time, the PWM signals (PWM11, PWM21, PWM31) used to control Fan 1, Fan 2 and Fan 3 are searched from the PWM signal set from the first half-width motherboard, and then Fan 1, Fan 2 and Fan 3 are controlled according to the PWM signal.

[0056] Similarly, the PWM signals (PWM42, PWM52, PWM62) for controlling fans 4, 5 and 6 are searched from the PWM signal set from the second half-width mainboard, and fans 4, 5 and 6 are then controlled according to the PWM signals.

[0057] It should be noted that the server provided in this embodiment controls the fan by determining whether there is a difference between the first PWM signal set and the second PWM signal set, and selecting a PWM signal with a larger duty cycle to control the fan when there is a difference. This can optimize the control accuracy of the fan, ensure that the fan runs at a state closer to the target speed, and improve the heat dissipation efficiency. When there is no difference, based on the correspondence between the motherboard and the fan slot, the corresponding PWM signal is selected based on the correspondence principle to control the corresponding fan. In this way, the fan is controlled by its corresponding motherboard, ensuring the best fan control effect and improving the heat dissipation performance.

[0058] Figure 2The control principle diagram inside the CPLD is shown as an exemplary embodiment of the present application. Referring to the previous description, when performing fan control, the CPLD detects the validity of the BMC of the first half-width motherboard and the BMC of the second half-width motherboard. When both are invalid, the fan is controlled according to the CPLD's own control logic; when one of the two is valid, the fan is controlled according to the PWM signal set of the BMC of the valid half-width motherboard; when both are valid, it is determined whether there is a difference between the first PWM signal set from the BMC of the first half-width motherboard and the second PWM signal set from the BMC of the second half-width motherboard. When there is a difference, for one fan, the fan is controlled according to the PWM signal with a larger duty cycle in the PWM signal. When there is no difference, for one fan, the fan is controlled according to the PWM signal of the target half-width motherboard corresponding to the fan. In this way, the control accuracy of the fan can be optimized, ensuring that the fan runs at a state closer to the target speed, and improving the heat dissipation efficiency.

[0059] Optionally, in a possible implementation of the present application, the CPLD is also used to detect fan hot-plug events, and feed back the fan hot-plug events to the BMC of each half-width motherboard, so that the BMC of each half-width motherboard adjusts the PWM signals used to control each currently connected fan based on the fan hot-plug event.

[0060] Specifically, the CPLD is located on the fan backplane and is responsible for monitoring the hot-swap events of the fans in the fan slots. When the fans are inserted into or removed from the slots, the CPLD can detect these changes. The hot-swap events include the insertion and removal of the fans, which may cause changes in the number, position or status of the fans.

[0061] When the CPLD detects a fan hot-swap event, it will feed back the event information to the BMC on each half-width motherboard through the I2C interface. It should be noted that the fed-back event information may include information such as which fan is plugged in or out. After receiving the fan hot-swap event, the BMC of each half-width motherboard can adjust the PWM signal used to control each currently plugged in fan according to the hot-swap event information, wherein adjusting the PWM signal may involve updating the fan's control parameters, such as adjusting the speed, power, or start / stop status, to adapt to the new fan configuration or changes.

[0062] For example, in one embodiment, when a fan insertion event is detected, it is determined that a fan has been added and the number of fans has increased, and the rotation speed of each fan can be reduced; when a fan removal event is detected, it is determined that the number of fans has decreased, and the rotation speed of each fan can be increased to ensure that the overall server heat dissipation performance is not affected.

[0063] It should be noted that providing timely feedback of fan hot-swap events to the BMC through the CPLD can ensure that the BMC on each half-width motherboard can respond and adjust the fan control strategy in a timely manner, which helps to maintain stable operation and good heat dissipation of the fans in the entire server system.

[0064] Corresponding to the aforementioned server, the present application also provides a fan control method, which is introduced below: Figure 3 This is a flow chart of the first embodiment of the fan control method provided by this application. Please refer to Figure 3 The method is applied to a server, the server comprising a first half-width mainboard, a second half-width mainboard and a fan backplane; the first half-width mainboard and the second half-width mainboard have the same structure, each half-width mainboard comprises a BMC and a CPU connected to the BMC; the fan backplane comprises a CPLD and a plurality of fan slots for plugging fans connected to the CPLD, the BMC of each half-width mainboard is connected to the CPLD via an I2C buffer; wherein the method comprises: S301, the CPLD detects fan-related information and feeds back the fan-related information to the BMC of each half-width motherboard; wherein the fan-related information includes the fan plug-in status of each fan slot and the status parameters of each currently plugged-in fan.

[0065] S302: The BMC of each half-width motherboard generates a PWM signal set for controlling each currently plugged in fan according to the fan related information, and sends the PWM signal set to the CPLD.

[0066] S303, the CPLD detects the validity of the BMC of each half-width motherboard, and determines a fan control strategy according to the validity detection result; wherein the fan control strategy includes controlling the fan according to its own control logic or controlling the fan according to a PWM signal set from the BMC.

[0067] S304: The CPLD controls each currently connected fan according to the fan control strategy.

[0068] The description of steps S301-S304 has been described in detail above and will not be repeated here.

[0069] The fan control method provided in this embodiment, firstly, detects fan-related information based on the CPLD on the fan backplane, and then independently controls the fan based on the BMCs on two independent half-width mainboards, that is, the PWM signal set for controlling the fan is independently generated by the BMCs on the two half-width mainboards, so as to determine the fan control strategy based on the CPLD on the fan backplane detecting the effectiveness of the two half-width mainboards, so that not only the purpose of fan control can be achieved, but also the heat dissipation problem of the independent half-width mainboard server can be solved. In addition, by using CPLD to decide the fan control strategy, not only the fan control can be made more flexible, but also the consumption of logic resources can be reduced and the cost can be reduced. Secondly, by changing the full-width mainboard to two half-width mainboards, and designing each half-width mainboard with the same structure, both including a CPU and a BMC connected to the CPU, and making the CPUs of the two half-width mainboards not interconnected, a decoupling design mode is adopted, when a hardware failure occurs on a half-width mainboard, only the corresponding faulty half-width mainboard needs to be replaced separately, without replacing the entire full-width mainboard, which can save the consumption cost of the board; thirdly, there is no communication between the BMCs of the two half-width mainboards, which can save the cost of the communication source code development between the BMCs.

[0070] Based on the above embodiment, a fan control strategy is determined according to the effectiveness detection result, including: The step of determining the fan control strategy according to the effectiveness detection result includes: When the validity detection result indicates that the BMC of the first half-width motherboard and the BMC of the second half-width motherboard are both valid, determining to control the fan according to the PWM signal set from the BMC; The method of controlling the fan according to the PWM signal set from the BMC includes: Determine whether there is a difference between a first PWM signal set from the BMC of the first half-width mainboard and a second PWM signal set from the BMC of the second half-width mainboard; When there is a difference between the first PWM signal set and the second PWM signal set, for each fan currently plugged in, the fan is controlled by using a target PWM signal; wherein the target PWM signal is a PWM signal with a larger duty cycle among the PWM signals in the first PWM signal set for controlling the fan and the PWM signals in the second PWM signal set for controlling the fan; When there is no difference between the first PWM signal set and the second PWM signal set, for each currently plugged in fan, the target half-width motherboard corresponding to the fan is determined according to the correspondence between the motherboard and the fan slot, and the target PWM signal for controlling the fan is searched from the PWM signal set from the target half-width motherboard, and then the fan is controlled using the target PWM signal.

[0071] Optionally, the determining whether there is a difference between a first PWM signal set from the BMC of the first half-width mainboard and a second PWM signal set from the BMC of the second half-width mainboard includes: For each fan currently plugged in, a first PWM signal for controlling the fan is obtained from a first PWM signal set from the BMC of the first half-width motherboard, and a second PWM signal for controlling the fan is obtained from a second PWM signal set from the BMC of the second half-width motherboard, and a duty cycle difference between the first PWM signal and the second PWM signal is compared to obtain a duty cycle difference corresponding to the fan; When the duty cycle differences corresponding to all currently plugged in fans are less than or equal to a preset threshold, determining that there is no difference between the first PWM signal set and the second PWM signal set; When the duty cycle difference corresponding to at least one fan among all the currently plugged in fans is greater than the preset threshold, it is determined that there is a difference between the first PWM signal set and the second PWM signal set.

[0072] Optionally, determining the fan control strategy according to the effectiveness detection result includes: When the validity detection result indicates that the BMC of the first half-width motherboard and the BMC of the second half-width motherboard are both invalid, it is determined to control the fans according to the self-control logic; wherein the self-control logic controls each currently plugged in fan according to a preset speed.

[0073] Optionally, determining a fan control strategy according to the effectiveness detection result includes: When the validity detection result indicates that one of the BMC of the first half-width motherboard and the BMC of the second half-width motherboard is valid, determining to control the fan according to the PWM signal set from the BMC; The step of controlling the fan according to the PWM signal set from the BMC includes: The CPLD is further specifically used to control the fan corresponding to each PWM signal in the PWM signal set from the currently valid BMC.

[0074] Optionally, the method further includes: The CPLD detects a fan hot-plug event, and feeds back the fan hot-plug event to the BMC of each half-width motherboard, so that the BMC of each half-width motherboard adjusts the PWM signal for controlling each currently plugged fan based on the fan hot-plug event.

[0075] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A server, characterized in that: The server includes a first half-width mainboard, a second half-width mainboard and a fan backplane; the first half-width mainboard and the second half-width mainboard have the same structure, each half-width mainboard includes a BMC and a CPU connected to the BMC; the fan backplane includes a CPLD and a plurality of fan slots for plugging fans connected to the CPLD, and the BMC of each half-width mainboard is connected to the CPLD via an I2C buffer; wherein, The CPLD is used to detect fan-related information and feed back the fan-related information to the BMC of each half-width motherboard; wherein the fan-related information includes the fan plug-in status of each fan slot and the status parameters of each currently plugged-in fan; The BMC of each half-width motherboard is used to generate a PWM signal set for controlling each currently plugged in fan according to the fan related information, and send the PWM signal set to the CPLD; The CPLD is also used to detect the validity of the BMC of each half-width motherboard and determine the fan control strategy according to the validity detection result; wherein the fan control strategy includes controlling the fan according to its own control logic or controlling the fan according to the PWM signal set from the BMC; The CPLD is also used to control each currently plugged in fan according to the fan control strategy.

2. The server according to claim 1, characterized in that: The CPLD is specifically used to determine, when determining a fan control strategy according to the validity detection result, if the validity detection result indicates that the BMC of the first half-width motherboard and the BMC of the second half-width motherboard are both valid, to control the fan according to the PWM signal set from the BMC; The CPLD is further used to determine whether there is a difference between a first PWM signal set from the BMC of the first half-width mainboard and a second PWM signal set from the BMC of the second half-width mainboard; The CPLD is further configured to control each fan currently plugged in by using a target PWM signal when there is a difference between the first PWM signal set and the second PWM signal set; wherein the target PWM signal is a PWM signal with a larger duty cycle among the PWM signals in the first PWM signal set for controlling the fan and the PWM signals in the second PWM signal set for controlling the fan; The CPLD is specifically used to determine, for each currently connected fan, a target half-width motherboard corresponding to the fan according to the correspondence between the motherboard and the fan slot when there is no difference between the first PWM signal set and the second PWM signal set, and to search for a target PWM signal for controlling the fan from the PWM signal set from the target half-width motherboard, and then control the fan using the target PWM signal.

3. The server according to claim 2, characterized in that: The determining whether there is a difference between the first PWM signal set from the BMC of the first half-width mainboard and the second PWM signal set from the BMC of the second half-width mainboard includes: For each fan currently plugged in, a first PWM signal for controlling the fan is obtained from a first PWM signal set from the BMC of the first half-width motherboard, and a second PWM signal for controlling the fan is obtained from a second PWM signal set from the BMC of the second half-width motherboard, and a duty cycle difference between the first PWM signal and the second PWM signal is compared to obtain a duty cycle difference corresponding to the fan; When the duty cycle differences corresponding to all currently plugged in fans are less than or equal to a preset threshold, determining that there is no difference between the first PWM signal set and the second PWM signal set; When the duty cycle difference corresponding to at least one fan among all the currently plugged in fans is greater than the preset threshold, it is determined that there is a difference between the first PWM signal set and the second PWM signal set.

4. The server according to claim 1, characterized in that: The CPLD is specifically used to determine the fan control strategy according to the validity detection result. If the validity detection result indicates that the BMC of the first half-width motherboard and the BMC of the second half-width motherboard are both invalid, it is determined to control the fan according to its own control logic; wherein the own control logic is to control each currently plugged in fan according to a preset speed.

5. The server according to claim 1, characterized in that: The CPLD is specifically used to determine, when determining a fan control strategy according to the validity detection result, that the fan is controlled according to a PWM signal set from the BMC if the validity detection result indicates that one of the BMCs of the first half-width motherboard and the BMCs of the second half-width motherboard is valid; The CPLD is further specifically used to control the fan corresponding to each PWM signal in the PWM signal set from the currently valid BMC.

6. The server according to claim 1, characterized in that: The CPLD is also used to detect fan hot-plug events and feed back the fan hot-plug events to the BMC of each half-width motherboard, so that the BMC of each half-width motherboard adjusts the PWM signals used to control each currently plugged fan based on the fan hot-plug event.

7. A fan control method, characterized in that: The method is applied to a server, the server comprising a first half-width mainboard, a second half-width mainboard and a fan backplane; the first half-width mainboard and the second half-width mainboard have the same structure, each half-width mainboard comprises a BMC and a CPU connected to the BMC; the fan backplane comprises a CPLD and a plurality of fan slots for plugging fans connected to the CPLD, the BMC of each half-width mainboard is connected to the CPLD via an I2C buffer; wherein the method comprises: The CPLD detects fan-related information and feeds back the fan-related information to the BMC of each half-width motherboard; wherein the fan-related information includes the fan plug-in status of each fan slot and the status parameters of each currently plugged-in fan; The BMC of each half-width motherboard generates a PWM signal set for controlling each currently plugged in fan according to the fan related information, and sends the PWM signal set to the CPLD; The CPLD detects the validity of the BMC of each half-width motherboard and determines a fan control strategy according to the validity detection result; wherein the fan control strategy includes controlling the fan according to its own control logic or controlling the fan according to a PWM signal set from the BMC; The CPLD controls each currently plugged in fan according to the fan control strategy.

8. The method according to claim 7, characterized in that The step of determining the fan control strategy according to the effectiveness detection result includes: When the validity detection result indicates that the BMC of the first half-width motherboard and the BMC of the second half-width motherboard are both valid, determining to control the fan according to the PWM signal set from the BMC; The step of controlling the fan according to the PWM signal set from the BMC includes: Determine whether there is a difference between a first PWM signal set from the BMC of the first half-width mainboard and a second PWM signal set from the BMC of the second half-width mainboard; When there is a difference between the first PWM signal set and the second PWM signal set, for each fan currently plugged in, the fan is controlled by using a target PWM signal; wherein the target PWM signal is a PWM signal with a larger duty cycle among the PWM signals in the first PWM signal set for controlling the fan and the PWM signals in the second PWM signal set for controlling the fan; When there is no difference between the first PWM signal set and the second PWM signal set, for each currently plugged in fan, the target half-width motherboard corresponding to the fan is determined according to the correspondence between the motherboard and the fan slot, and the target PWM signal for controlling the fan is searched from the PWM signal set from the target half-width motherboard, and then the fan is controlled using the target PWM signal.

9. The method according to claim 8, characterized in that The determining whether there is a difference between the first PWM signal set from the BMC of the first half-width mainboard and the second PWM signal set from the BMC of the second half-width mainboard includes: For each fan currently plugged in, a first PWM signal for controlling the fan is obtained from a first PWM signal set from the BMC of the first half-width motherboard, and a second PWM signal for controlling the fan is obtained from a second PWM signal set from the BMC of the second half-width motherboard, and a duty cycle difference between the first PWM signal and the second PWM signal is compared to obtain a duty cycle difference corresponding to the fan; When the duty cycle differences corresponding to all currently plugged in fans are less than or equal to a preset threshold, determining that there is no difference between the first PWM signal set and the second PWM signal set; When the duty cycle difference corresponding to at least one fan among all the currently plugged in fans is greater than the preset threshold, it is determined that there is a difference between the first PWM signal set and the second PWM signal set.

10. The method according to claim 7, characterized in that The step of determining the fan control strategy according to the effectiveness detection result includes: When the validity detection result indicates that the BMC of the first half-width motherboard and the BMC of the second half-width motherboard are both invalid, it is determined to control the fans according to the self-control logic; wherein the self-control logic controls each currently plugged in fan according to a preset speed.

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