Data transmission method and data transmission system of storage device

Abstract

The invention relates to the technical field of data processing, in particular to a data transmission method and a data transmission system of a storage device, and when the storage device receives to-be-written data and parity check bits transmitted by a controller, a new parity check bit is regenerated based on the to-be-written data; and receiving parity check bits, comparing the parity check bits with the received parity check bits to obtain a check result, and when the check result meets a preset check condition, indicating that the data is correct, and transmitting the to-be-written data to a target storage position for storage by the storage device. The data transmission reliability of the storage device is effectively improved, the data integrity is ensured, the risk of data loss is reduced, and a powerful guarantee is provided for data storage and application.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a data transmission method and a data transmission system for a storage device. Background Art

[0002] Currently, the transmission speed of Nandflash is getting higher and higher. The data transmission channel between Nandflash and the controller includes a write channel and a read channel. However, when writing data based on the write channel between Nandflash and the controller, if there are problems such as signal interference, it will cause data bit flipping, damage data, and cause data loss, incompleteness and other problems, resulting in the quality of the data transmission channel between Nandflash and the controller not meeting the transmission speed requirements.

[0003] In order to solve the problem of incomplete written data caused by signal interference and other reasons, the existing technology reduces the effective bandwidth of the data to ensure the integrity of the data in an overall manner. However, reducing the effective bandwidth of the data to ensure the integrity of the data can easily lead to problems such as data transmission jams, unsmoothness, and prolonged response time. Summary of the invention

[0004] In order to overcome the shortcomings of the prior art, the present invention provides a data transmission method and a data transmission system for a storage device, which verifies the data written to the storage device by adding a check bit, thereby preventing data loss during transmission without reducing the effective bandwidth, thereby ensuring the integrity of the written data and improving the reliability of the data.

[0005] A first aspect of the present application provides a data transmission method for a storage device, which is applied to the storage device, and the method includes: Determine whether first data to be written and a first parity bit sent by the controller are received, where the first parity bit is generated by the controller based on the first data to be written; When it is determined that the first data to be written is received, generating a second parity bit based on the first data to be written; Performing a parity check on the first data to be written based on the first parity check bit and the second parity check bit to obtain a first check result; When it is determined that the first verification result meets the preset verification condition, the first data to be written is written to the target storage location.

[0006] In an optional implementation, generating a second parity bit based on the first data to be written includes: Calculate the number of 1s in the first data to be written according to the multiplexed RE high-speed differential PAD and a preset verification rule; When the check rule is odd check and the number of 1s is an even number, the second parity check bit is 1; when the check rule is odd check and the number of 1s is an odd number, the second parity check bit is 0; When the check rule is an even check and the number of 1s is an even number, the second parity check bit is 0; when the check rule is an even check and the number of 1s is an odd number, the second parity check bit is 1.

[0007] In an optional implementation, performing a parity check on the first to-be-written data based on the first parity check bit and the second parity check bit to obtain a first check result includes: comparing the first parity bit and the second parity bit; When it is determined that the first parity check bit and the second parity check bit are consistent, determining that the first verification result is a verification success; When it is determined that the first parity check bit and the second parity check bit are inconsistent, the first check result is determined to be a check failure.

[0008] In an optional implementation, before generating a second parity bit based on the first data to be written, the method further includes: detecting whether a first determination program instruction sent by the controller is received, where the first determination program instruction is generated by the controller after the first data to be written is sent; When the first determination program instruction is detected, it is determined that the first data to be written has been received, and then the operation of generating a second parity bit based on the first data to be written is performed.

[0009] A second aspect of the present application provides a data transmission method for a storage device, which is applied to a controller that interacts with the storage device for data. The method includes: Acquire second data to be written, and generate a third parity bit based on the second data to be written; Sending the second to-be-written data and the third parity bit to the storage device; When it is determined that the second data transmission to be written is completed, sending a second determination program instruction to the storage device; When it is determined that the storage device receives the second determination program instruction, the storage device is controlled to generate a fourth parity check bit based on the second data to be written, and a parity check is performed on the second data to be written according to the third parity check bit and the fourth parity check bit to obtain a second check result.

[0010] In an optional implementation, after sending the second determination program instruction to the storage device, the method further includes: Entering a state detection phase according to a preset condition to detect the second verification result; When it is detected that the second verification result is a verification failure, the storage device is controlled to perform a preset calibration operation to obtain a calibration result.

[0011] In an optional embodiment, the method further comprises: When it is determined that the calibration result is a calibration failure, continuing to perform the calibration operation; When it is determined that the calibration result is successful, the operation of sending the second to-be-written data and the third parity bit to the storage device is performed.

[0012] In an optional implementation, the preset condition is a timing condition or a random condition.

[0013] A third aspect of the present application provides a data transmission system, the system comprising: Storage devices and controllers; The storage device comprises a first memory, a first processor, and a first computer program stored in the first memory and executable on the first processor, wherein the first processor implements the steps of the data transmission method of the storage device according to any one of claims 1 to 4 when executing the first computer program; The controller includes a second memory, a second processor, and a second computer program stored in the second memory and executable on the second processor, and the second processor implements the steps of the data transmission method of the storage device described in any one of claims 5 to 8 when executing the second computer program.

[0014] In summary, the data transmission method and data transmission system of the storage device provided by the present application, determine the corresponding parity check bit before the data to be written is written into the storage device through the controller, and transmit the determined parity check bit together with the data to be written to the storage device, the storage device regenerates a new parity check bit based on the received data to be written, and performs a parity check on the data to be written based on the received parity check bit and the new parity check bit, and returns the check result obtained by the check to the controller, the controller detects the received check result according to preset conditions, if the check result is detected as a check failure, it indicates that there may be an error or data loss during the data transmission process, the storage device can re-execute the parity check operation on the data to be written, through the parity check, a single bit error occurring during the data transmission process can be detected, thereby preventing data loss, and the parity check can ensure that the data written to the storage device remains intact during the transmission process and will not be damaged due to problems such as signal interference, and at the same time, the parity check does not need to reduce the effective bandwidth of the data, so the data transmission speed can be maintained, and the reliability of the data is also improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a structural schematic diagram of a data transmission system shown in an embodiment of the present application; Figure 2 It is a flowchart of a data transmission method of a storage device shown in an embodiment of the present application; Figure 3 is another flowchart of a data transmission method of a storage device shown in an embodiment of the present application; Figure 4 This is a data interaction diagram of a data transmission method of a storage device shown in an embodiment of the present application; Figure 5 A schematic diagram of the structure of a storage device shown in an embodiment of the present application; Figure 6 A schematic diagram of the structure of a controller shown in an embodiment of the present application. DETAILED DESCRIPTION

[0016] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0017] The following will clearly and completely describe the concept, specific structure and technical effects of the present invention in combination with the embodiments and drawings, so as to fully understand the purpose, characteristics and effects of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, other embodiments obtained by technicians in this field without creative work are all within the scope of protection of the present invention. In addition, all the connection / connection relationships involved in the patent do not refer to the direct connection of components, but refer to the formation of a better connection structure by adding or reducing connection accessories according to the specific implementation situation. The various technical features in the invention can be combined interchangeably without conflicting with each other.

[0018] Reference Figure 1 , which is a structural diagram of a data transmission system shown in an embodiment of the present application.

[0019] Among them, the data transmission system 1 includes a storage device 10 and a controller 20. When the controller 20 needs to write data to the storage device 10, the controller 20 and the storage device 10 can reuse the RE high-speed differential PAD as a parity bit, that is, the controller 20 transmits the data to be written and its corresponding parity bit to the storage device 10. When the storage device 10 receives the data to be written, it regenerates a new parity bit, and performs a parity check on the data to be written with the new parity bit and the received parity bit to obtain a check result. If the check result is a successful check, the storage device 10 writes the received data to be written to the target storage location. When the check result is a failed check, the check result is returned to the controller 20 so that the controller 20 performs a calibration operation until the calibration result is a successful calibration. When the calibration result is a successful calibration, the controller 20 retransmits the data to be written to the storage device 10, and repeats the above-mentioned parity check and calibration operations until the storage device 10 writes the data to be written to the target storage location.

[0020] The storage device 10 refers to a non-volatile memory for data storage, which may include Nor Flash, embedded Multi Media Card (embedded Multi Media Card, eMMC), Universal Flash Storage (UFS) and SD NAND, etc.

[0021] In order to more clearly understand the inventive concept of the present application, the storage device 10 in the embodiments of the present application is described by taking Nandflash as an example.

[0022] Reference Figure 2As shown, it is a flow chart of a data transmission method of a storage device shown in an embodiment of the present application. The data transmission method of the storage device is applied to the storage device, and the data transmission method of the storage device includes the following steps.

[0023] S21, determining whether first data to be written and a first parity bit sent by the controller are received.

[0024] Refer to Figure 4 In some embodiments, in the communication channel between Nandflash and the controller, in the direction of writing to Nandflash, that is, when the controller writes data to Nandflash, in order to add additional PADs, the corresponding check bits are added without reducing the effective bandwidth of the data. The controller first receives the data to be written to Nandflash from its internal cache, external data source or upper-layer application, which is called the first data to be written. The first data to be written can be user data, system logs, configuration parameters, etc., depending on the purpose of Nandflash. Then, the controller can generate a corresponding parity bit based on the first data to be written, which is called the first parity bit. Specifically, the controller reuses the RE high-speed differential PAD as the parity bit, that is, the data transmission is 8 bits of data width (bit0 to bit7 respectively). After the RE high-speed differential PAD is introduced, the data bit width becomes 9 bits, that is, bit0 to bit8, where bit8 is used as the parity bit. For each data to be written that needs to transmit a data width of 8 bits, a corresponding parity bit is generated. When Nandflash receives each 8-bit data to be written, a parity check is performed immediately. For example, assuming that the data to be written needs to be transmitted with a data width of 8 bits, a corresponding parity check bit is generated and transmitted; assuming that the data to be written needs to be transmitted with a data width of 16 bits, two corresponding parity check bits are generated and transmitted, and so on. Furthermore, the controller can also pre-set the corresponding check rule (odd check or even check), and calculate the parity check bit of the first data to be written according to the RE high-speed differential PAD and the preset check rule, that is, calculate the number of 1s in the first data to be written, and determine whether the number of 1s is odd or even. On the basis that the check rule is odd check, if the number of 1s calculated is an odd number, it can be determined that the first parity check bit corresponding to the first data to be written is 0, and if the number of 1s calculated is an even number, it can be determined that the first parity check bit is 1. On the basis that the check rule is an even check, if the calculated number of 1s is an even number, it can be determined that the first parity check bit is 0, and if the calculated number of 1s is an odd number, it can be determined that the first parity check bit is 1.

[0025] When the first data to be written and its corresponding first parity bit are determined, the first data to be written and the generated first parity bit are sent to Nandflash together. When sending data, a data strobe signal (DSQ) is used as a data synchronization signal to ensure correct data transmission.

[0026] In some embodiments, the communication interface between the controller and Nandflash can be pre-configured, including data lines, address lines, and control lines. For example, the controller can establish a connection with Nandflash through 8 data lines (which can be parallel data lines, serial data lines, or high-speed differential data lines, etc.), and transmit the data to be written and the corresponding parity bits to Nandflash through the 8 data lines.

[0027] In an optional implementation, before generating the second parity bit based on the first data to be written, the method further includes: detecting whether a first determination program instruction sent by the controller is received, where the first determination program instruction is generated by the controller after the first data to be written is sent; When the first determination program instruction is detected, it is determined that the first data to be written has been received, and then the operation of generating a second parity bit based on the first data to be written is performed.

[0028] In some embodiments, when the controller transmits data to Nandflash, when it is determined that the data transmission is completed, the controller can generate a confirmation program instruction (called the first confirmation program instruction, hereinafter referred to as the first confirmation program instruction), and send the first confirmation program instruction to Nandflash, and Nandflash detects whether the first confirmation program instruction is received. When the first confirmation program instruction is received, it means that the data reception is completed, and the next operation can be executed to perform a parity check on the received first data to be written. After the controller sends the first confirmation program instruction, the controller can perform a status check phase according to the preset conditions, wherein the task of the status check phase is to detect the check result returned by Nandflash to ensure whether the data has been correctly written and stored. If any error or abnormality is detected, the controller can immediately take measures to repair or retransmit the data. The preset condition can be a timing condition (that is, a preset time period, for example, every 1 hour) or a random condition (that is, irregular).

[0029] Through the above optional implementation, by introducing the first confirmation program instruction, it is ensured that Nandflash performs parity check after receiving complete data, thereby improving the reliability of data transmission. At the same time, the controller performs a status check after sending the instruction, and detects the check result according to the preset conditions to ensure that the data is written correctly, thereby enhancing the accuracy of data storage and the stability of the system.

[0030] S22: When it is determined that the first data to be written is received, generate a second parity bit based on the first data to be written.

[0031] S23: Perform a parity check on the first data to be written based on the first parity check bit and the second parity check bit to obtain a first check result.

[0032] In some embodiments, when the controller sends the first data to be written to Nandflash, if Nandflash receives it correctly and successfully, the received data is the first data to be written. If Nandflash does not receive it correctly, the received data may not be the first data to be written. In order to verify that Nandflash can correctly receive the data to be written sent by the controller, assuming that the received data is the first data to be written sent by the controller, it is necessary to verify the first data to be written. Specifically, Nandflash first generates a new parity bit based on the received data to be written (the default is the first data to be written) according to the same implementation method as step S21, which is called the second parity bit. Similarly, every time Nandflash receives an 8-bit data to be written, it immediately performs a parity operation, that is, generates a new parity bit, and compares the newly generated parity bit with the received parity bit. In an embodiment of the present application, Nandflash compares the second parity bit with the first parity bit. When the first parity bit and the second parity bit are consistent, it means that the check result (referred to as the first check result) of the parity check performed by Nandflash on the first data to be written based on the first parity bit and the second parity bit is a successful check. When the first parity bit and the second parity bit are inconsistent, it means that the first check result bit check has failed.

[0033] It should be noted that for the same data, the generated parity bits are the same. Nandflash will perform parity check on each 8 bits of the first data to be written, that is, if each 8 bits in the data meets the parity check requirements, the check result is a successful check; otherwise, the check fails.

[0034] In other embodiments, during the data transmission process, an error within an acceptable range is allowed to occur in the data, and an error threshold can be pre-set, and the error threshold can be adjusted according to the width of the data to be written, that is, the error threshold is determined according to the width of the first data to be written and the preset data width segmentation interval, wherein the preset data width segmentation interval includes multiple data width intervals, each data width interval corresponds to an error threshold, and different data width intervals correspond to different error thresholds. For example, Nandflash can pre-set the first data width interval, the second data width interval, and the third data width interval, wherein the first data width interval corresponds to the first error threshold, the second data width interval corresponds to the second error threshold, and the third data width interval corresponds to the third error threshold. Exemplarily, assuming that the first data width interval is [8bit, 72bit], the first error threshold is set to 0; assuming that the second data width interval is [80bit, 160bit], the second error threshold is set to 1; assuming that the data width interval is [168bit, 240bit], the third error threshold is set to 2.

[0035] S24: When it is determined that the first verification result satisfies a preset verification condition, the first data to be written is written to a target storage location.

[0036] When the first verification result is obtained by verification according to step S23, if the first verification result satisfies the preset verification condition, that is, the data to be written meets the parity check requirement, and the number of successful verifications in the verification result of the parity check bit corresponding to each 8bit satisfies the allowable error threshold, it means that the first data to be written is correctly and successfully received, and the first data to be written can be stored in the target storage location, such as an internal storage unit, an external storage medium, etc. After completing the writing of the first data to be written, Nandflash can send a write confirmation signal to the controller, so that the controller confirms that the first data to be written has been successfully written to the storage device after receiving the write confirmation signal. If the first verification result does not meet the preset verification condition, that is, when the first verification result is a verification failure, Nandflash can return the verification result to the controller, so that the controller can read the status, that is, the corresponding verification failure flag can be read in the status check phase.

[0037] Exemplarily, assuming that the data to be written is 24 bits in width, the corresponding allowable error threshold is 0. If the check result of the parity check bit corresponding to each 8 bits in the first check result is a successful check, it means that the first check result meets the preset check condition; if the check result of the parity check bit corresponding to any 8 bits in the first check result is a failed check, it means that the first check result does not meet the preset check condition.

[0038] When there is a problem with the data channel, or the external environment is bad (for example, the temperature is too high or too low), etc., the sampling offset will be caused, which will cause the data received by Nandflash to be incorrect, that is, the first verification result does not meet the preset verification condition. When the first verification result does not meet the preset verification condition, the controller triggers the preset calibration operation, determines and corrects the sampling offset through the calibration operation to ensure that the data can be accurately transmitted between the controller and Nandflash. Specifically, the controller needs to clarify the sampling offset, and control the sampling point between Nandflash according to the sampling offset to ensure that its corresponding sampling point is consistent with the sampling point of Nandflash, or the sampling offset is within the preset allowable range, and outputs the calibration result after calibration. If the calibration result is a calibration failure, the controller continues to calibrate until the calibration result is a calibration success. When it is determined that the calibration result is a calibration success, the controller re-executes the operation of transmitting the first data to be written to Nandflash and subsequent operations, that is, the controller will perform data transmission and verification again until the first data to be written is successfully written to the target storage location of Nandflash. During the transmission process, the controller will continuously monitor the verification results to ensure that the data can be written to the target storage location of Nandflash accurately and without error. The calibration operation is automatically triggered to correct the sampling offset caused by data channel problems or external environment to ensure the accuracy of data transmission between the controller and Nandflash. By continuously monitoring the verification results and repeatedly calibrating until the data is successfully written, the reliability of the storage system and the accuracy of data writing are effectively improved.

[0039] In some embodiments, after the data is successfully written, the controller can also perform subsequent storage management operations, such as updating storage metadata, releasing temporary resources, etc. At the same time, the controller can also record relevant information of this calibration operation (such as calibration times, calibration success / failure flags, etc.) for subsequent analysis and optimization. It should be noted that during the entire calibration process, the controller needs to maintain access rights to Nandflash and ensure the continuity and stability of data transmission.

[0040] Compared with the prior art, the present application verifies the data written to Nandflash by adding a check bit, thereby preventing data loss during transmission without reducing the effective bandwidth, ensuring the integrity of the written data and improving the reliability of the data.

[0041] Reference Figure 2 As shown, it is another flow chart of a data transmission method of a storage device shown in an embodiment of the present application. The data transmission method of the storage device is applied to a controller that interacts with the storage device for data, and the data transmission method of the storage device includes the following steps.

[0042] S31, obtaining second data to be written, and generating a third parity bit based on the second data to be written.

[0043] According to the same implementation method as step S21, when the controller needs to write data (called the second data to be written) to Nandflash, the parity bit corresponding to the second data to be written is generated by multiplexing the RE high-speed differential PAD as the parity bit, which is called the third parity bit.

[0044] S32: Send the second data to be written and the third parity bit to the storage device.

[0045] After the controller determines the second data to be written and the third parity check bit corresponding thereto, the controller sends the second data to be written and the third parity check bit to Nandflash through the data line.

[0046] S33: When it is determined that the transmission of the second data to be written is completed, a second determination program instruction is sent to the storage device.

[0047] In some embodiments, when the controller transmits data to Nandflash, when it is determined that the data transmission is completed, the controller can generate a confirmation program instruction (called a second confirmation program instruction, hereinafter referred to as the second confirmation program instruction), and send the second confirmation program instruction to Nandflash, and Nandflash detects whether the second confirmation program instruction is received. When the second confirmation program instruction is received, it means that the data reception is completed, and the next operation can be executed to perform a parity check on the received second data to be written. After the controller sends the second confirmation program instruction, the controller can perform a status check phase according to a preset condition to detect the check result returned by Nandflash, wherein the preset condition can be a timing condition (that is, a preset time period, for example, every 1 hour) or a random condition (that is, irregular).

[0048] Similarly, after sending the second confirmation program instruction to Nandflash, the controller automatically enters the state detection phase to detect the second verification result returned by Nandflash, and performs a calibration operation when a verification failure flag is read.

[0049] S34, when it is determined that the storage device receives the second determination program instruction, controls the storage device to generate a fourth parity check bit based on the second data to be written, and performs a parity check on the second data to be written according to the third parity check bit and the fourth parity check bit to obtain a second check result.

[0050] According to the same implementation method as the above steps S22 to S23, when Nandflash receives the second confirmation program instruction, it indicates that the second data to be written has been received. Nandflash also generates a fourth parity bit by reusing the RE high-speed differential PAD as a parity bit, and performs a parity check on the second data to be written based on the newly generated fourth parity bit and the received third parity bit to obtain a second check result. When the second check result is a successful check, Nandflash can store the second data to be written to the target storage location. When the second check result is a failed check, the second check result is returned to the controller, and the controller can further perform a calibration operation.

[0051] Reference Figure 5 As shown, when the controller needs to write the data to be processed (referred to as the data to be written) into Nandflash, it will generate the parity check bit corresponding to the data to be written by reusing the RE high-speed differential PAD as the parity check bit, and send the parity check bit synchronously when sending the data to be written to Nandflash through the data line. When Nandflash receives the data to be written sent by the controller, it needs to verify the data to be written to avoid problems such as incomplete data. Specifically, Nandflash, like the controller, reuses the RE high-speed differential PAD as the parity check bit, generates a new parity check bit based on the received data to be written, and compares the new parity check bit with the received parity check bit. Since Nandflash allows the data to be written to have allowable errors during the transmission process, Nandflash can perform parity check on the data to be written according to the data width of the data to be written, the data width segmentation interval and the allowable misalignment threshold. When the check result is a successful check, the data to be written is stored in the corresponding target storage location. When the verification result is a verification failure, the verification result is returned to the controller so that the controller performs a calibration operation, that is, determines the sampling offset between the controller and Nandflash, controls the sampling point between the controller and Nandflash according to the sampling offset, to ensure that the corresponding sampling point is consistent with the sampling point of Nandflash, or the sampling offset is within the preset allowable range, and outputs the calibration result after calibration. When the calibration result is a calibration failure, the calibration operation is continued until the calibration result is a calibration success. When the calibration result is a calibration success, the controller resends the data to be written to Nandflash.

[0052] This application implements efficient and secure Nandflash data writing by performing parity check on the data during the communication process and using a calibration mechanism to ensure data integrity. The controller sends the data to be written and the corresponding parity bit to Nandflash at the same time. After receiving the data, Nandflash generates another parity bit for verification according to the built-in algorithm. If the verification is successful, the data is stored, otherwise it will be fed back to the controller for calibration. The calibration operation corrects the error in data transmission by adjusting the sampling offset between the controller and Nandflash, so that the sampling points of the two are consistent or within the allowable range, and ultimately ensures the accuracy of data transmission. If the calibration fails, repeat the calibration process until the calibration is successful, ensuring the reliability and security of the final data written to Nandflash.

[0053] In order to facilitate understanding of the inventive concept of the present application, an example is given below to describe the practical application of the embodiment of the present application. Assume that the controller needs to write a 24-bit data to be written to Nandflash, and assume that the data to be written is 10101010 11110000 01010101 (divided into three 8-bit data blocks: 10101010, 11110000, 01010101). The controller calculates the parity bit for each 8-bit data block according to the preset check rule (such as odd check). For 10101010, the number of 1s is 4 (even number), so the parity bit is 1 (odd check requires the check bit to make the total number of 1s an odd number); for 11110000, the number of 1s is 4 (even number), so the parity bit is 1; for 01010101, the number of 1s is 4 (even number), so the parity bit is 1, then the first parity bit sequence is 1 1 1. The controller sends the data to be written and the first parity bit to Nandflash, that is, 10101010 1 11110000 1 01010101 1. During the sending process, the data selection signal (DSQ) is used as a synchronization signal to ensure the correct transmission of the data. Nandflash receives the data and parity bit sent by the controller, that is, 10101010 1 11110000 1 01010101 1. Before Nandflash starts the verification, Nandflash waits for the first confirmation program instruction sent by the controller. When the controller determines that the data transmission is completed, it sends the first confirmation program instruction to Nandflash. After receiving the first confirmation program instruction, Nandflash starts to prepare for verification. Specifically, Nandflash generates a second parity bit for each 8-bit data block based on the received data to be written (assuming that the default is the first data to be written). For 10101010, the second parity bit is 1; for 11110000, the second parity bit is 1; for 01010101, the second parity bit is 1, then the second parity bit sequence is 1 1 1. Further, Nandflash compares the second parity bit with the first parity bit. In an embodiment of the present application, for 24 bits of data to be written, each first parity bit and each second parity bit need to be completely consistent before the verification result can be determined to be a successful verification. When the verification result is a successful verification, Nandflash writes the first data to be written to the target storage location and sends a write confirmation signal to the controller, indicating that the data has been successfully written. When the verification result is a verification failure (for example, due to a sampling offset caused by a data channel problem or an external environmental influence), the controller will perform a calibration operation, adjust the sampling point, and resend the data until the data is successfully written.

[0054] Reference Figure 5 As shown, the schematic diagram of the structure of the controller shown in the embodiment of the present application. In a preferred embodiment of the present application, the storage device 10 includes a memory 101, at least one processor 102 and at least one communication bus 103. Those skilled in the art should understand that Figure 5 The structure of the storage device shown does not constitute a limitation of the embodiments of the present application. The storage device 10 is a non-volatile memory used for data storage, which may include Nor Flash, embedded Multi Media Card (eMMC), Universal Flash Store (UFS) and SD NAND, etc.

[0055] Reference Figure 6 FIG. 2 is a schematic diagram of the structure of the controller shown in the embodiment of the present application. In a preferred embodiment of the present application, the controller 20 includes a memory 21, at least one processor 22 and at least one communication bus 23.

[0056] Those skilled in the art should understand that Figure 6 The structure of the controller shown does not constitute a limitation of the embodiments of the present application, and can be either a bus structure or a star structure. The controller 20 can also include more or less other hardware or software than shown in the figure, or a different arrangement of components. In some embodiments, the controller 20 is a device that can automatically perform numerical calculations and / or information processing according to pre-set or stored instructions, and its hardware includes but is not limited to microprocessors, application-specific integrated circuits, programmable gate arrays, digital processors, and embedded devices.

[0057] It should be noted that, for the convenience of description, the aforementioned method embodiments are all described as a series of action combinations, but those skilled in the art should be aware that the present invention is not limited by the described action sequence, because according to the present invention, certain steps can be performed in other sequences or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present invention.

[0058] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0059] The above is a specific description of the preferred implementation of the present invention, but the invention is not limited to the embodiments. Those skilled in the art can make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A data transmission method for a storage device, characterized in that: Applied to a storage device, the method comprises: Determine whether first data to be written and a first parity bit sent by the controller are received, where the first parity bit is generated by the controller based on the first data to be written; When it is determined that the first data to be written is received, generating a second parity bit based on the first data to be written; Performing a parity check on the first data to be written based on the first parity check bit and the second parity check bit to obtain a first check result; When it is determined that the first verification result meets the preset verification condition, the first data to be written is written to the target storage location.

2. The data transmission method of the storage device according to claim 1, characterized in that: Generating a second parity bit based on the first data to be written comprises: Calculate the number of 1s in the first data to be written according to the multiplexed RE high-speed differential PAD and a preset verification rule; When the check rule is odd check and the number of 1s is an even number, the second parity check bit is 1; when the check rule is odd check and the number of 1s is an odd number, the second parity check bit is 0; When the check rule is an even check and the number of 1s is an even number, the second parity check bit is 0; when the check rule is an even check and the number of 1s is an odd number, the second parity check bit is 1.

3. The data transmission method of the storage device according to claim 1, characterized in that: The performing a parity check on the first to-be-written data based on the first parity check bit and the second parity check bit to obtain a first check result includes: comparing the first parity bit and the second parity bit; When it is determined that the first parity check bit and the second parity check bit are consistent, determining that the first verification result is a verification success; When it is determined that the first parity check bit and the second parity check bit are inconsistent, the first check result is determined to be a check failure.

4. The data transmission method of the storage device according to claim 1, characterized in that: Before generating a second parity bit based on the first data to be written, the method further includes: detecting whether a first determination program instruction sent by the controller is received, where the first determination program instruction is generated by the controller after the first data to be written is sent; When the first determination program instruction is detected, it is determined that the first data to be written has been received, and then the operation of generating a second parity bit based on the first data to be written is performed.

5. A data transmission method for a storage device, characterized in that: A controller for interacting with a storage device for data transmission, the method comprising: Acquire second data to be written, and generate a third parity bit based on the second data to be written; Sending the second to-be-written data and the third parity bit to the storage device; When it is determined that the second data transmission to be written is completed, sending a second determination program instruction to the storage device; When it is determined that the storage device receives the second determination program instruction, the storage device is controlled to generate a fourth parity check bit based on the second data to be written, and a parity check is performed on the second data to be written according to the third parity check bit and the fourth parity check bit to obtain a second check result.

6. The data transmission method of the storage device according to claim 5, characterized in that: After sending the second determination program instruction to the storage device, the method further includes: Entering a state detection phase according to a preset condition to detect the second verification result; When it is detected that the second verification result is a verification failure, the storage device is controlled to perform a preset calibration operation to obtain a calibration result.

7. The data transmission method of the storage device according to claim 6, characterized in that: The method further comprises: When it is determined that the calibration result is a calibration failure, continuing to perform the calibration operation; When it is determined that the calibration result is successful, the operation of sending the second to-be-written data and the third parity bit to the storage device is performed.

8. The data transmission method of the storage device according to claim 6, characterized in that: The preset condition is a timing condition or a random condition.

9. A data transmission system, characterized in that: The system comprises: Storage devices and controllers; The storage device comprises a first memory, a first processor, and a first computer program stored in the first memory and executable on the first processor, wherein the first processor implements the steps of the data transmission method of the storage device according to any one of claims 1 to 4 when executing the first computer program; The controller includes a second memory, a second processor, and a second computer program stored in the second memory and executable on the second processor, and the second processor implements the steps of the data transmission method of the storage device described in any one of claims 5 to 8 when executing the second computer program.

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