Cache management method and system based on scalar memory automatic management strategy

Abstract

The invention discloses a cache management method and system based on a scalar memory automatic management strategy, and the method comprises the steps: firstly building a cache management strategy library, and achieving the automatic distribution, management and recovery of scalar memory cache resources; secondly, constructing a memory access feature model, performing quantitative modeling on memory access behaviors of key array variables in a program, and generating corresponding memory access feature vectors; and finally, based on the memory access feature vector, automatically selecting an optimal cache management strategy and configuring corresponding strategy parameters by utilizing a strategy and strategy parameter deduction model. The method can dynamically adapt to the memory access behavior change of the program, the scalar memory utilization efficiency and the program memory access speed are improved, the scalar memory management process is simplified, and the development complexity is reduced. Compared with the prior art, the scalar memory management method has the advantages that an efficient and automatic scalar memory management solution is provided under a complex heterogeneous many-core architecture, and the scalar memory management method has wide application prospects and remarkable practical value.

Description

Background Art

[0002] With the rapid development of scientific computing, artificial intelligence, and big data analysis, high-performance computing (HPC) plays a vital role in promoting technological progress and industrial upgrading. In HPC applications, memory access optimization is one of the key factors to improve performance. Efficient memory access management can not only reduce data transmission latency, but also improve cache hit rate, thereby significantly improving the overall operating efficiency of the system.

[0003] At present, the domestic heterogeneous many-core architecture is in a stage of rapid development, and a variety of high-performance processors with independent intellectual property rights have emerged. These architectures have achieved efficient task allocation and parallel computing capabilities by integrating various types of processing units. However, as the architecture becomes increasingly complex, its storage hierarchy has also become more complex, and the difficulty of on-chip cache management has increased significantly. Taking the domestic Maichuang architecture as an example, its on-chip cache structure includes two parts: scalar memory and array memory, which are responsible for storing scalar data and vector data respectively. Its multi-domain microarchitecture and hierarchical storage design make the management of on-chip cache particularly complex. Although the hthreads parallel programming model provides an interface for managing on-chip cache, the existing method still requires manual management by the user, and there are the following three main problems: First, the memory architecture is complex: MT-3000’s multi-domain microarchitecture and hierarchical storage design make manual management of scalar memory complex and error-prone.

[0004] Second, cache management is difficult: users need to write a lot of code to allocate and recycle cache and design complex data layout, which increases development difficulty and maintenance costs.

[0005] Third, it is difficult to optimize memory access performance: Since memory access behaviors are diverse and difficult to predict, manually optimizing cache strategies is difficult to achieve optimal performance, which limits the execution efficiency of the program.

[0006] The existing technology lacks an automated cache management strategy library that can dynamically adjust the cache management strategy according to the actual memory access behavior of the program, resulting in low cache utilization and poor memory access performance under complex computing tasks. Therefore, the scalar memory automated management strategy library and its memory access modeling method for the domestic Maichuang architecture have important practical significance. Summary of the invention

[0007] The technical problem to be solved by the present invention is to provide a cache management method and system based on a scalar memory automatic management strategy to address the deficiencies in the above-mentioned prior art, so as to solve the technical problems of complex scalar memory management and low program memory access efficiency.

[0008] The present invention adopts the following technical solutions: A cache management method based on a scalar memory automatic management strategy comprises the following steps: S1. Establish a cache management strategy library, developed based on the hthreads parallel programming model interface of the Maichuang architecture, for automatic allocation, management and recycling of scalar memory cache resources; S2. Establish a memory access feature model to quantitatively model the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors; S3. Establish a strategy and strategy parameter deduction model, automatically select the optimal cache management strategy based on the obtained memory access feature vector, and configure the corresponding strategy parameters.

[0009] Preferably, in step S1, the cache management policy library includes: Batch cache management strategy: read all data blocks within the access memory range into scalar memory at one time. Subsequent access to the data block is taken over by the batch cache management strategy, and all computing operations are performed in scalar memory. Single buffer cache management strategy, a user-defined size cache space is opened in the scalar memory to pre-fetch the data in a certain data block. The memory access behavior of the data block will trigger the cache hit judgment logic. If it does not hit, the data in the current buffer is selectively written back to the main memory, and the data within a certain range near the current memory access address is read into the buffer to continue the subsequent calculation operation; The direct mapping cache management strategy opens up a cache space of a user-defined size containing several cache lines in the scalar memory for prefetching data in a data block. The memory access behavior of the data block will trigger the cache hit judgment logic. If it does not hit, the data of the current cache line will be selectively written back to the main memory, and the data within a certain range near the current memory access address will be read into the corresponding cache line to continue subsequent computing operations.

[0010] Preferably, the configurable parameters of the single buffer cache management strategy are , which represents the logarithm of the cache size with base 2; its cache hit judgment logic is:

[0011] in, Indicates the address aligned according to the cache space size. Indicates the starting address of the current cache data block in the main memory, Indicates the end address of the current cache data block in the main memory, Represents a cache hit indicator.

[0012] Preferably, the configurable parameters of the direct-mapped cache management strategy are and , represents the base-2 logarithm of the cache line size, Indicates the logarithm of the number of cache groups with base 2. The cache hit judgment logic of this policy is:

[0013] in, Indicates the cache group index. Represents a cache tag array, storing the tag value of each cache line, Represents a cache hit indicator.

[0014] Preferably, step S2 specifically includes: S201. Define related basic concepts: data block refers to the memory area represented by the array variable referenced in the kernel function; stream refers to a subsequence of a memory access element sequence; step length refers to the distance between any two adjacent elements; S202, determining data block characteristics, where the characteristics of the data block are mainly defined by size boundaries; S203, establish a flow step length feature model, assuming that in a flow, the step length is a discrete random variable whose value is , ; S204, generating a memory access feature vector. According to the above definition, classify the memory access behavior of the key array variables in the program, and generate a corresponding memory access feature vector. The memory access feature vector includes the data block size, the number of memory accesses, the memory access step length, and the proportion of high-frequency memory access step lengths.

[0015] Preferably, based on the step length feature, define:

[0016]

[0017] in, is an arbitrarily small positive number, Represents the index of the high-frequency step, that is, the sequence number of the step with the highest frequency in the stream. Indicates the specific value of the high-frequency step size, Indicates step length Probability of occurrence; Proposition Indicates that there are high-frequency non-zero steps in the flow , Proposition Indicates that the step size is 1.

[0018] Preferably, according to the proposition and True or false, the flow is divided into: Regular sequence flow: When When true; Regular non-sequential flow: When When true; Irregular flow: When When true.

[0019] Preferably, step S3 is specifically: S301, designing a strategy selection unit to define a matching rule of a cache management strategy according to a memory access feature vector; S302, designing a policy parameter configuration unit, and configuring corresponding policy parameters according to the selected cache management policy; S303: Automatically configure the policy and policy parameters. Through the policy selection unit and the policy parameter configuration unit, the policy selection and policy parameter configuration are automatically implemented to ensure that the cache management policy can dynamically adapt to the changes in the program's memory access behavior.

[0020] Preferably, the matching rules of the cache management policy are as follows: If the data block size is smaller than the scalar memory space, select the batch cache management strategy; if the data block size is larger than the scalar memory space and the flow is a regular sequential flow, select the single buffer cache management strategy; in other cases, select the direct mapping cache management strategy; According to the selected cache management strategy, configure the corresponding strategy parameters as follows: When the batch cache management strategy is selected, no additional parameter configuration is required, and the data block is directly read into the scalar memory at one time; when the single buffer cache management strategy is selected, the buffer size parameter is configured. , which represents the logarithm of the cache space size with base 2; when the direct-mapped cache management strategy is selected, configure the cache line size and the number of cache groups , represent the base-2 logarithm of the cache line size and the number of cache groups, respectively.

[0021] In a second aspect, an embodiment of the present invention provides a cache management system based on a scalar memory automatic management strategy, including: Strategy module, establishes cache management strategy library, developed based on the parallel programming model interface of the Maichuang architecture hthreads, and is used to automatically allocate, manage and recycle cache resources of scalar memory; The quantization module establishes a memory access feature model to quantify the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors; The management module establishes a strategy and strategy parameter deduction model, automatically selects the optimal cache management strategy based on the obtained memory access feature vector, and configures the corresponding strategy parameters.

[0022] In a third aspect, a computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the cache management method based on the scalar memory automatic management strategy when executing the computer program.

[0023] In a fourth aspect, an embodiment of the present invention provides a computer-readable storage medium, including a computer program, which, when executed by a processor, implements the steps of the cache management method based on the scalar memory automatic management strategy.

[0024] In a fifth aspect, a chip comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the cache management method based on the scalar memory automatic management strategy when executing the computer program.

[0025] In a sixth aspect, an embodiment of the present invention provides an electronic device, comprising a computer program, which, when executed by the electronic device, implements the steps of the cache management method based on the scalar memory automatic management strategy.

[0026] Compared with the prior art, the present invention has at least the following beneficial effects: A cache management method based on scalar memory automatic management strategy, firstly, establishes a cache management strategy library to realize automatic allocation, management and recovery of scalar memory cache resources; secondly, constructs a memory access feature model to quantitatively model the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors; finally, based on the memory access feature vectors, the strategy and strategy parameter deduction model are used to automatically select the optimal cache management strategy and configure the corresponding strategy parameters; it can dynamically adapt to the changes in the program's memory access behavior, improve the scalar memory utilization efficiency and program memory access speed, simplify the scalar memory management process, and reduce development complexity; by designing a cache management strategy for scalar memory The library is omitted, and users do not need to manually write complex scalar memory management codes, which significantly reduces the complexity and development difficulty of scalar memory management; the automatic strategy selection and strategy parameter configuration based on memory access characteristics can more effectively match the actual memory access behavior of the program, improve cache hit rate and utilization, and reduce the performance loss caused by cache misses; dynamic adjustment of cache management strategy can achieve the best cache performance according to the memory access mode of different programs, and significantly improve the overall execution efficiency of parallel programs; compared with the prior art, the present invention provides an efficient and automated scalar memory management solution under complex heterogeneous many-core architecture, which has broad application prospects and significant practical value.

[0027] Furthermore, the present invention provides a dedicated scalar memory management solution for the multi-domain micro-architecture and hierarchical storage design of the domestic Maichuang architecture, which can effectively cope with the challenges brought by the complex memory architecture.

[0028] Furthermore, the present invention sets configurable parameters for the proposed single buffer cache management strategy , the optimal cache size is set according to the memory access characteristics of different array variables, and a balance is achieved between memory access acceleration and scalar memory usage efficiency. At the same time, the cache hit judgment logic of this strategy uses the locality principle to realize the reuse of data in the cache, improve the cache hit rate, and enhance the memory access speed of the program.

[0029] Furthermore, the present invention introduces configurable parameters into the direct-mapped cache management strategy. and , in order to adapt to the memory access characteristics of different array variables, optimize the size and number of cache lines, and achieve a balance between memory access performance and scalar memory utilization efficiency. In addition, the cache hit judgment logic of this strategy is based on the principle of locality, making full use of the data in the cache and improving the hit rate, thereby reducing memory access latency and speeding up program execution.

[0030] Furthermore, the present invention constructs a program memory access feature model, which can quantify the memory access mode of key array variables into key features such as data block size, memory access times, memory access step length, and high-frequency memory access step length ratio, so as to accurately characterize memory access behavior. The strategy selection and parameter configuration deduced based on this model can achieve the optimal memory access acceleration effect and improve program execution efficiency.

[0031] Furthermore, the present invention constructs a cache management strategy library and its strategy parameter deduction model, and deduces the optimal cache management strategy and the corresponding optimal parameter configuration based on the rules by analyzing the memory access characteristics of the program's key arrays. This method can efficiently derive the optimization solution without repeatedly running the program, has the advantages of being lightweight and efficient, and effectively improves the program's memory access performance.

[0032] Furthermore, the present invention adopts cache management strategy matching rules based on memory access characteristics, which can intelligently select the optimal cache management strategy according to the data block size and memory access mode, and optimize the cache resource utilization efficiency through automatic strategy parameter configuration. This method ensures that the batch cache management strategy is used first when the data block is small, thereby improving the data loading efficiency; for the regular sequential flow, the single buffer cache management strategy is adopted, and the cache management strategy is dynamically adjusted. Improve cache hit rate; in other complex memory access modes, select direct mapping cache management strategy and and Fine-tune configuration to reduce cache conflicts and memory access delays. This automated policy matching and parameter optimization mechanism can dynamically adjust memory behavior to avoid resource waste or performance bottlenecks caused by fixed policies, improve cache utilization efficiency, and reduce the overhead caused by cache misses, thereby significantly improving the overall memory access performance and execution efficiency of the program.

[0033] It can be understood that the beneficial effects of the second to sixth aspects mentioned above can be found in the relevant description of the first aspect mentioned above, and will not be repeated here.

[0034] In summary, the present invention effectively improves the utilization efficiency of scalar memory and the memory access performance of the program through automated strategy selection and strategy parameter configuration, and has broad application prospects and significant practical value.

[0035] The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 This is a schematic diagram of the MT-3000 on-chip heterogeneous many-core architecture; Figure 2 This is a schematic diagram of the MT-3000 memory architecture; Figure 3 This is a schematic diagram of the system architecture; Figure 4 It is a schematic diagram of the single buffer cache management strategy flow; Figure 5 Schematic diagram of main memory address mapping for direct-mapped cache management strategy; Figure 6 Decision flow chart for the strategy selection unit; Figure 7 A schematic diagram of a computer device provided by an embodiment of the present invention; Figure 8 The present invention is a block diagram of an electronic device provided according to an embodiment.

[0038] Among them, 60. computer equipment; 61. processor; 62. memory; 63. computer program; 600. electronic device; 610. processing unit; 620. storage unit; 6201. random access storage unit; 6202. cache storage unit; 6203. read-only storage unit; 6204. program / utility; 6205. program module; 630. bus; 640. display unit; 650. input / output interface; 660. network adapter; 700. external device. DETAILED DESCRIPTION

[0039] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] In the description of the present invention, it should be understood that the terms “include” and “comprises” indicate the presence of described features, wholes, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or collections thereof.

[0041] It should also be understood that the terms used in the present specification are only for the purpose of describing specific embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, unless the context clearly indicates otherwise, the singular forms "a", "an" and "the" are intended to include plural forms.

[0042] It should be further understood that the term "and / or" used in the present specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes these combinations. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in the present invention generally indicates that the associated objects are in an "or" relationship.

[0043] It should be understood that, although the terms first, second, third, etc. may be used to describe preset ranges, etc. in the embodiments of the present invention, these preset ranges should not be limited to these terms. These terms are only used to distinguish preset ranges from each other. For example, without departing from the scope of the embodiments of the present invention, the first preset range may also be referred to as the second preset range, and similarly, the second preset range may also be referred to as the first preset range.

[0044] The word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining" or "in response to detecting", depending on the context. Similarly, the phrases "if it is determined" or "if (stated condition or event) is detected" may be interpreted as "when it is determined" or "in response to determining" or "when detecting (stated condition or event)" or "in response to detecting (stated condition or event)", depending on the context.

[0045] Various structural schematic diagrams of the embodiments disclosed in the present invention are shown in the accompanying drawings. These figures are not drawn to scale, and some details are magnified and some details may be omitted for the purpose of clear expression. The shapes of various regions and layers shown in the figures and the relative sizes and positional relationships therebetween are only exemplary, and may deviate in practice due to manufacturing tolerances or technical limitations, and those skilled in the art may additionally design regions / layers with different shapes, sizes, and relative positions according to actual needs.

[0046] The present invention provides a cache management method based on scalar memory automatic management strategy, which optimizes the use efficiency of scalar memory and the memory access performance of the program by quantizing and modeling the memory access behavior of key array variables in the program, and automatically selecting and configuring the cache management strategy using the quantized memory access characteristics. The cache management strategy library is developed based on the domestic Maichuang hthreads parallel programming model interface, and is suitable for heterogeneous multi-core chips with multi-domain microarchitectures and complex storage hierarchies. It can effectively simplify the cache management process, realize automatic management and improve the execution efficiency of parallel programs.

[0047] Example 1 The present invention provides a cache management method based on a scalar memory automatic management strategy, comprising the following steps: S1. Establish a cache management strategy library based on the hthreads parallel programming model interface of the Maichuang architecture to automatically allocate, manage and recycle cache resources of scalar memory (SM); See also Figure 3 In the system architecture of the present invention, the cache management strategy library includes three cache management strategies: batch cache management strategy, single buffer cache management strategy and direct mapping cache management strategy, which are as follows: Batch cache management strategy: All data blocks within the access memory range are read into the scalar memory at one time. Subsequent access to the data blocks is taken over by the batch cache management strategy, and all computing operations are performed in the scalar memory. Single buffer cache management strategy: a user-defined size cache space is opened in the scalar memory to pre-fetch data in a certain data block. The program's memory access behavior for the data block will trigger the cache hit judgment logic. If it does not hit, the data in the current buffer will be selectively written back to the main memory, and the data within a certain range near the current memory access address will be read into the buffer to continue the subsequent calculation operation. The configurable parameters of this strategy are , which represents the logarithm of the cache size with base 2. The cache hit judgment logic is:

[0048]

[0049]

[0050] in, Indicates the address aligned according to the cache space size. Indicates the starting address of the current cache data block in the main memory, Indicates the end address of the current cache data block in the main memory, Represents the cache hit indicator. A value of 1 indicates a cache hit, and a value of 0 indicates a cache miss. The base-2 logarithm of the cache size Indicates a floor operation.

[0051] Direct-mapped cache management strategy: A user-defined cache space containing several cache lines is allocated in the scalar memory to pre-fetch data in a data block. The program's memory access to the data block will trigger the cache hit judgment logic. If it does not hit, the data in the current cache line will be selectively written back to the main memory, and the data within a certain range near the current memory access address will be read into the corresponding cache line to continue the subsequent calculation operation. The configurable parameters of this strategy are and ,in, represents the base-2 logarithm of the cache line size, Indicates the logarithm of the number of cache groups with base 2. The cache hit judgment logic of this strategy is:

[0052]

[0053]

[0054] in, Indicates the memory address currently being accessed. represents the base-2 logarithm of the cache line size, Represents the base-2 logarithm of the number of cache groups, Indicates the tag part of the memory address, which is used for cache hit judgment. Indicates the cache group index. Represents a cache tag array, which stores the tag value of each cache line. The initial value is Indicates invalidity. Indicates a round-down operation. Represents the cache hit indicator. A value of 1 indicates a cache hit, and a value of 0 indicates a cache miss.

[0055] S2. Establish a memory access feature model to quantitatively model the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors; The memory access feature modeling includes four parts: defining relevant basic concepts, determining data block features, establishing a stream step feature model, and generating memory access feature vectors. Specifically, it includes: S201. Define related basic concepts: data block refers to the memory area represented by the array variable referenced in the kernel function; stream refers to a subsequence of a memory access element sequence; step length refers to the distance between any two adjacent elements; S202, determine the characteristics of the data block. The characteristics of the data block are mainly defined by the size boundary, which is specifically expressed as:

[0056] in, Indicates the number of data blocks, Indicates the number of the data block. Indicates The size of the data block.

[0057] The capacity of scalar memory is expressed as:

[0058] Based on the above definition, different data blocks are classified and the proposition is defined. as follows:

[0059] Defining the Proposition , indicating that the access memory area of ​​the data block is smaller than the storage space of the scalar memory.

[0060] S203, establish a flow step length feature model, specifically described as: suppose in a flow, the step length is a discrete random variable whose value is , the probability of occurrence of different step lengths is:

[0061] in, Indicates step length No. possible values, Indicates step length The value is The probability of , and satisfy all The sum is 1.

[0062]

[0063] Based on the step length feature, define:

[0064]

[0065] in, is an arbitrarily small positive number, Represents the index of the high-frequency step, that is, the sequence number of the step with the highest frequency in the stream. Indicates the specific value of the high-frequency step size, Indicates step length The probability of occurrence. Indicates that there are high-frequency non-zero steps in the flow , Proposition Indicates that the step length is 1. According to the proposition and The true or false situation of the flow is divided into three categories: Regular sequence flow: when When true; Regular non-sequential flow: when When true; Irregular flow: when When true.

[0066] S204: Generate memory access feature vectors. According to the above definition, classify the memory access behaviors of key array variables in the program and generate corresponding memory access feature vectors. The memory access feature vectors include but are not limited to data block size, memory access times, memory access step length, and high-frequency memory access step length ratio.

[0067] S3. Establish a strategy and strategy parameter deduction model, automatically select the optimal cache management strategy based on the memory access feature vector, and configure corresponding strategy parameters.

[0068] See also Figure 6 ,The strategy selection unit judges the truth values ​​of propositions T, P and Q in turn according to the memory access feature vector, and selects the corresponding cache management strategy, which includes the following steps: S301, design a strategy selection unit, and define a matching rule for a cache management strategy according to the aforementioned memory access feature vector. The specific rules are as follows: S3011, if the data block size is smaller than the scalar memory space, select a batch cache management strategy; S3012, if the data block size is larger than the scalar memory space and the stream is a regular sequential stream, select a single buffer cache management strategy; S3013. In other cases, select a direct mapping cache management strategy.

[0069] S302, designing a policy parameter configuration unit, and configuring corresponding policy parameters according to the selected cache management policy; S3021. When the batch cache management strategy is selected, no additional parameter configuration is required, and the data block is directly read into the scalar memory at one time; S3022: When a single buffer cache management strategy is selected, configure the buffer size parameter , represents the logarithm of the cache size to base 2; S3023: When the direct-mapped cache management strategy is selected, configure the cache line size and the number of cache groups , represent the base-2 logarithm of the cache line size and the number of cache groups, respectively.

[0070] S303: Automatically configure the policy and policy parameters. Through the policy selection unit and the policy parameter configuration unit, the policy selection and policy parameter configuration are automatically implemented to ensure that the cache management policy can dynamically adapt to the changes in the program's memory access behavior.

[0071] It will be appreciated by those skilled in the art that various aspects of the present invention may be implemented as systems, methods or program products. Therefore, various aspects of the present invention may be specifically implemented in the following forms, namely: complete hardware implementation, complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software implementations, which may be collectively referred to herein as "circuits", "modules" or "platforms".

[0072] Example 2 The present invention provides a cache management system based on a scalar memory automatic management strategy, which can be used to implement the above-mentioned cache management method based on a scalar memory automatic management strategy. Specifically, the cache management system based on a scalar memory automatic management strategy includes a policy module, a quantization module and a management module.

[0073] Among them, the strategy module establishes a cache management strategy library, which is developed based on the hthreads parallel programming model interface of the Maichuang architecture and is used to automatically allocate, manage and recycle cache resources of scalar memory; The quantization module establishes a memory access feature model to quantify the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors; The management module establishes a strategy and strategy parameter deduction model, automatically selects the optimal cache management strategy based on the obtained memory access feature vector, and configures the corresponding strategy parameters.

[0074] Example 3 The present invention provides a terminal device, which includes a processor and a memory, wherein the memory is used to store a computer program, the computer program includes program instructions, and the processor is used to execute the program instructions stored in the computer storage medium. The processor may be a central processing unit (CPU), or other general-purpose processors, graphics processors (GPU), tensor processors (TPU), digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. It is the computing core and control core of the terminal, which is suitable for implementing one or more instructions, and is specifically suitable for loading and executing one or more instructions to implement the corresponding method flow or corresponding function; the processor described in the embodiment of the present invention can be used for the operation of the cache management method based on the scalar memory automatic management strategy, including: Establish a cache management strategy library, developed based on the hthreads parallel programming model interface of the Maichuang architecture, to automatically allocate, manage and recycle cache resources of scalar memory; establish a memory access feature model to quantitatively model the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors; establish a strategy and strategy parameter deduction model to automatically select the optimal cache management strategy based on the obtained memory access feature vectors and configure the corresponding strategy parameters.

[0075] See also Figure 7 , the terminal device is a computer device, and the computer device 60 of this embodiment includes: a processor 61, a memory 62, and a computer program 63 stored in the memory 62 and executable on the processor 61. When the computer program 63 is executed by the processor 61, the cache management method based on the scalar memory automatic management strategy in the embodiment is implemented. To avoid repetition, it is not described one by one here. Alternatively, when the computer program 63 is executed by the processor 61, the functions of each model / unit in the cache management system based on the scalar memory automatic management strategy in the embodiment are implemented. To avoid repetition, it is not described one by one here.

[0076] The computer device 60 may be a computing device such as a desktop computer, a notebook, a PDA, or a cloud server. The computer device 60 may include, but is not limited to, a processor 61 and a memory 62. Those skilled in the art will appreciate that Figure 7 This is only an example of the computer device 60 and does not constitute a limitation of the computer device 60. It may include more or fewer components than shown in the figure, or a combination of certain components, or different components. For example, the computer device may also include input and output devices, network access devices, buses, etc.

[0077] The processor 61 may be a central processing unit (CPU), or other general-purpose processors, graphics processing units (GPU), tensor processing units (TPU), digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.

[0078] The memory 62 may be an internal storage unit of the computer device 60, such as a hard disk or memory of the computer device 60. The memory 62 may also be an external storage device of the computer device 60, such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, etc., equipped on the computer device 60.

[0079] Furthermore, the memory 62 may include both an internal storage unit of the computer device 60 and an external storage device. The memory 62 is used to store computer programs and other programs and data required by the computer device. The memory 62 may also be used to temporarily store data that has been output or is to be output.

[0080] See also Figure 8The terminal device is an electronic device 600, which is in the form of a general-purpose computing device. The components of the electronic device may include, but are not limited to: at least one processing unit 610, at least one storage unit 620, a bus 630 connecting different platform components (including the storage unit 620 and the processing unit 610), a display unit 640, etc.

[0081] The storage unit stores program codes, which can be executed by the processing unit 610, so that the processing unit 610 performs the steps according to various exemplary embodiments of the present invention described in the above method section of this specification. For example, the processing unit 610 can perform the following steps: Figure 3 Follow the steps shown in .

[0082] The storage unit 620 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 6201 and / or a cache memory unit 6202 , and may further include a read-only memory unit (ROM) 6203 .

[0083] The storage unit 620 may also include a program / utility 6204 having a set (at least one) of program modules 6205, such program modules 6205 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0084] Bus 630 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0085] The electronic device 600 may also communicate with one or more external devices 700 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 600, and / or communicate with any device that enables the electronic device 600 to communicate with one or more other computing devices (e.g., routers, modems, etc.). Such communication may be performed via an input / output interface 650. Furthermore, the electronic device 600 may also communicate with one or more networks (e.g., local area networks, wide area networks, and / or public networks, such as the Internet) via a network adapter 660. The network adapter 660 may communicate with other modules of the electronic device 600 via a bus 630. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 600, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage platforms, etc.

[0086] Example 4 The present invention also provides a storage medium, specifically a computer-readable storage medium, which is a memory device in a terminal device for storing programs and data. It is understandable that the computer-readable storage medium here can include both the built-in storage medium in the terminal device and the extended storage medium supported by the terminal device, and can be any tangible medium containing or storing a program, which can be used by an instruction execution system, device or device or used in combination with it. The computer-readable storage medium provides a storage space, which stores the operating system of the terminal. In addition, one or more instructions suitable for being loaded and executed by a processor are also stored in the storage space, and these instructions can be one or more computer programs (including program codes). It should be noted that more specific examples of the computer-readable storage medium here include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory, a read-only memory, an erasable programmable read-only memory, an optical fiber, a portable compact disk read-only memory, an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0087] Computer readable storage media also include data signals propagated in baseband or as part of a carrier wave, which carry readable program code. Such propagated data signals can take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. The readable storage medium can also be any readable medium other than a readable storage medium, which can send, propagate or transmit a program for use by or in conjunction with an instruction execution system, device or device. The program code contained on the readable storage medium can be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, radio frequency, etc., or any suitable combination of the above.

[0088] Program code for performing the operations of the present invention may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network or a wide area network, or may be connected to an external computing device (e.g., through the Internet using an Internet service provider).

[0089] The processor may load and execute one or more instructions stored in the computer-readable storage medium to implement the corresponding steps of the cache management method based on the scalar memory automatic management strategy in the above embodiment; the processor may load and execute the following steps of one or more instructions in the computer-readable storage medium: Establish a cache management strategy library, developed based on the hthreads parallel programming model interface of the Maichuang architecture, to automatically allocate, manage and recycle cache resources of scalar memory; establish a memory access feature model to quantitatively model the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors; establish a strategy and strategy parameter deduction model to automatically select the optimal cache management strategy based on the obtained memory access feature vectors and configure the corresponding strategy parameters.

[0090] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. The components of the embodiments of the present invention described and shown in the drawings here can usually be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments in the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0091] See also Figure 1 It is the on-chip heterogeneous many-core architecture of the domestic MT-3000 chip; it adopts a multi-domain micro-architecture, in which the general domain is mainly responsible for running the operating system and managing the acceleration cluster. Each acceleration cluster contains 24 acceleration arrays, and each acceleration array consists of a control core and 16 acceleration cores. The control core is responsible for the overall control flow and processing scalar calculations that are difficult to vectorize.

[0092] See also Figure 2 , which is a hybrid memory architecture for the acceleration cluster. Each acceleration cluster is equipped with 32GB DDR4 main memory outside the chip, which is shared with the general domain. The on-chip storage hierarchy includes four layers. Except for registers, other layers need to be manually managed through the hthreads programming model interface. Each core is equipped with scalar memory and array memory, which together serve as on-chip caches, responsible for storing scalar data and vector data respectively.

[0093] The solution of the present invention is designed specifically for the scalar memory of the Maichuang platform, taking into full account the unique characteristics of scalar memory in the on-chip cache to improve its memory access efficiency in high-performance computing. The present invention provides a scalar memory automatic management strategy library for the domestic Maichuang architecture and its memory access modeling method, which mainly includes a scalar memory management strategy library, a memory access feature model, and a strategy and strategy parameter deduction model. These components are developed based on the hthreads parallel programming model interface of the domestic Maichuang architecture, and can dynamically manage the cache resources of the scalar memory at compile time or runtime.

[0094] In summary, the present invention provides a cache management method and system based on a scalar memory automatic management strategy. Through automatic strategy selection and parameter configuration, the present invention significantly improves the utilization efficiency of scalar memory and the memory access performance of the program, and has broad application prospects and significant practical value.

[0095] The technicians in the relevant field can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned functional units and modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiment can be integrated in a processing unit, or each unit can exist physically separately, or two or more units can be integrated in one unit. The above-mentioned integrated unit can be implemented in the form of hardware or in the form of software functional units. In addition, the specific names of the functional units and modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application. The specific working process of the units and modules in the above-mentioned system can refer to the corresponding process in the aforementioned method embodiment, which will not be repeated here.

[0096] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0097] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the present invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0098] In the embodiments provided by the present invention, it should be understood that the disclosed devices / terminals and methods can be implemented in other ways. For example, the device / terminal embodiments described above are only schematic. For example, the division of the modules or units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0099] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0100] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0101] If the integrated module / unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the present invention implements all or part of the processes in the above-mentioned embodiment method, and can also be completed by instructing the relevant hardware through a computer program. The computer program can be stored in a computer-readable storage medium, and the computer program can implement the steps of the above-mentioned various method embodiments when executed by the processor. Among them, the computer program includes computer program code, and the computer program code can be in source code form, object code form, executable file or some intermediate form. The computer-readable medium may include: any entity or device capable of carrying the computer program code, recording medium, U disk, mobile hard disk, disk, optical disk, computer memory, read-only memory (ROM), random access memory (RAM), electric carrier signal, telecommunication signal and software distribution medium, etc. It should be noted that the content contained in the computer-readable medium can be appropriately increased or decreased according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electric carrier signals and telecommunication signals.

[0102] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices, and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0103] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0104] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0105] The above contents are only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A cache management method based on a scalar memory automatic management strategy, characterized in that: The following steps are involved: S1. Establish a cache management strategy library, developed based on the hthreads parallel programming model interface of the Maichuang architecture, for automatic allocation, management and recycling of scalar memory cache resources; S2. Establish a memory access feature model to quantitatively model the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors; S3. Establish a strategy and strategy parameter deduction model, automatically select the optimal cache management strategy based on the obtained memory access feature vector, and configure the corresponding strategy parameters.

2. The cache management method based on scalar memory automatic management strategy according to claim 1, characterized in that: In step S1, the cache management policy library includes: Batch cache management strategy: read all data blocks within the access memory range into scalar memory at one time. Subsequent access to the data block is taken over by the batch cache management strategy, and all computing operations are performed in scalar memory. Single buffer cache management strategy, a user-defined size cache space is opened in the scalar memory to pre-fetch the data in a certain data block. The memory access behavior of the data block will trigger the cache hit judgment logic. If it does not hit, the data in the current buffer is selectively written back to the main memory, and the data within a certain range near the current memory access address is read into the buffer to continue the subsequent calculation operation; The direct mapping cache management strategy opens up a cache space of a user-defined size containing several cache lines in the scalar memory for prefetching data in a data block. The memory access behavior of the data block will trigger the cache hit judgment logic. If it does not hit, the data of the current cache line will be selectively written back to the main memory, and the data within a certain range near the current memory access address will be read into the corresponding cache line to continue subsequent computing operations.

3. The cache management method based on scalar memory automatic management strategy according to claim 2, characterized in that: The configurable parameters for the single buffer cache management strategy are , represents the logarithm of the cache size to base 2; The cache hit judgment logic is: in, Indicates the address aligned according to the cache space size. Indicates the starting address of the current cache data block in the main memory, Indicates the end address of the current cache data block in the main memory, Represents a cache hit indicator.

4. The cache management method based on scalar memory automatic management strategy according to claim 2, characterized in that: The configurable parameters for direct-mapped cache management policy are and , represents the base-2 logarithm of the cache line size, Indicates the logarithm of the number of cache groups with base 2. The cache hit judgment logic of this policy is: in, Indicates the cache group index. Represents a cache tag array, storing the tag value of each cache line, Represents a cache hit indicator.

5. The cache management method based on scalar memory automatic management strategy according to claim 1, characterized in that: Step S2 is specifically as follows: S201. Define related basic concepts: data block refers to the memory area represented by the array variable referenced in the kernel function; stream refers to a subsequence of a memory access element sequence; step length refers to the distance between any two adjacent elements; S202, determining data block characteristics, where the characteristics of the data block are mainly defined by size boundaries; S203, establish a flow step length feature model, assuming that in a flow, the step length is a discrete random variable whose value is , ; S204, generating a memory access feature vector. According to the above definition, classify the memory access behavior of the key array variables in the program, and generate a corresponding memory access feature vector. The memory access feature vector includes the data block size, the number of memory accesses, the memory access step length, and the proportion of high-frequency memory access step lengths.

6. The cache management method based on scalar memory automatic management strategy according to claim 5, characterized in that: Based on the step length feature, define: in, is an arbitrarily small positive number, Represents the index of the high-frequency step, that is, the sequence number of the step with the highest frequency in the stream. Indicates the specific value of the high-frequency step size, Indicates step length Probability of occurrence; Proposition Indicates that there are high-frequency non-zero steps in the flow , Proposition Indicates that the step size is 1.

7. The cache management method based on scalar memory automatic management strategy according to claim 6, characterized in that: According to the proposition and True or false, the flow is divided into: Regular sequence flow: When When true; Regular non-sequential flow: When When true; Irregular flow: When When true.

8. The cache management method based on scalar memory automatic management strategy according to claim 1, characterized in that: Step S3 is specifically as follows: S301, designing a strategy selection unit to define a matching rule of a cache management strategy according to a memory access feature vector; S302, designing a policy parameter configuration unit, and configuring corresponding policy parameters according to the selected cache management policy; S303: Automatically configure the policy and policy parameters. Through the policy selection unit and the policy parameter configuration unit, the policy selection and policy parameter configuration are automatically implemented to ensure that the cache management policy can dynamically adapt to the changes in the program's memory access behavior.

9. The cache management method based on scalar memory automatic management strategy according to claim 8, characterized in that: The matching rules of the cache management policy are as follows: If the data block size is smaller than the scalar memory space, select the batch cache management strategy; if the data block size is larger than the scalar memory space and the flow is a regular sequential flow, select the single buffer cache management strategy; in other cases, select the direct mapping cache management strategy; According to the selected cache management strategy, configure the corresponding strategy parameters as follows: When the batch cache management strategy is selected, no additional parameter configuration is required, and the data block is directly read into the scalar memory at one time; when the single buffer cache management strategy is selected, the buffer size parameter is configured. , which represents the logarithm of the cache space size with base 2; when the direct-mapped cache management strategy is selected, configure the cache line size and the number of cache groups , represent the base-2 logarithm of the cache line size and the number of cache groups, respectively.

10. A cache management system based on a scalar memory automatic management strategy, characterized in that: include: Strategy module, establishes cache management strategy library, developed based on the parallel programming model interface of the Maichuang architecture hthreads, and is used to automatically allocate, manage and recycle cache resources of scalar memory; The quantization module establishes a memory access feature model to quantify the memory access behavior of key array variables in the program and generate corresponding memory access feature vectors; The management module establishes a strategy and strategy parameter deduction model, automatically selects the optimal cache management strategy based on the obtained memory access feature vector, and configures the corresponding strategy parameters.

Images