Prefetch memory management unit for real-time virtual memory address translation

Abstract

The invention relates to a prefetch memory management unit for real-time virtual memory address translation. An MMU with prefetch functionality is provided. The MMU includes a first TLB, a burst buffer, a second TLB, and a control logic. The first TLB is configured to extract a first set of one or more first page table entries based at least in part on a virtual address and prior to receiving a request from a client to access a client address. The burst buffer stores a plurality of second page table entries from respective page tables associated with first page table addresses. A second translation lookaside buffer is configured to extract a first set of one or more second page table entries of the plurality of second page table entries from the burst buffer based at least in part on the virtual address and prior to receiving the request from the client to access a client address.

Description

[0001] Copyright Notice

[0002] A portion of the disclosure of this patent document contains material which is subject to copyright protection. The copyright owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright rights whatsoever. Technical Field

[0003] The present disclosure generally relates to methods, systems, and apparatus for real-time virtual memory address translation in a memory management unit. Background Art

[0004] Conventionally, real-time hardware access to dynamic random access memory (DRAM) is controlled by strict scheduling. At the same time, virtual memory management is useful for both application processors and Linux. Using virtual memory for hardware involves an extra memory access step to read the virtual memory page table, followed by memory access for the video client. Combining the use of virtual memory with strict deadlines for fetching data stored in memory often results in real-time applications (e.g., video processing) missing hard real-time deadlines.

[0005] Therefore, a memory management unit (MMU) is provided with pre-fetch functionality for real-time virtual address translation. Summary of the invention

[0006] In one aspect, the present disclosure relates to an apparatus comprising: a system memory; a memory management unit coupled to the system memory, the memory management unit comprising: a first translation lookaside buffer configured to fetch a first set of one or more first page table entries before receiving a request from a client to access data at a client address, wherein the client address is an address in a virtual memory space used by the client, and wherein the first set of one or more first page table entries is fetched based at least in part on the virtual address, wherein each first page table entry of the one or more first page table entries is associated with a respective page table address; a burst buffer a burst buffer configured to store a plurality of second page table entries from respective page tables associated with a first page table address; a second translation lookaside buffer configured to fetch a first set of one or more of the plurality of second page table entries from the burst buffer based at least in part on the virtual address and before receiving the request from the client to access data at the client address; and control logic configured to transmit the virtual address to the first translation lookaside buffer and the second translation lookaside buffer and cause the burst buffer to store the plurality of second page table entries based at least in part on the virtual address.

[0007] On the other hand, the present disclosure relates to a memory management unit, comprising: a first translation lookaside buffer, which is configured to prefetch a first group of one or more first page table entries based at least in part on a virtual address, wherein each first page table entry of the one or more first page table entries is associated with a corresponding page table address, and wherein the prefetching of the first group of one or more first page table entries occurs before a request to access data at a client address is received from a client, wherein the client address is an address in a virtual memory space used by the client; a burst buffer, which is configured to store a plurality of second page table entries from a corresponding page table associated with the first page table address; a second translation lookaside buffer, which is configured to prefetch a first group of one or more second page table entries of the plurality of second page table entries from the burst buffer based at least in part on the virtual address, wherein the prefetching of the first group of one or more second page table entries occurs before a request to access data at the client address is received from the client; and control logic, which is configured to transmit the virtual address to the first translation lookaside buffer and the second translation lookaside buffer, and cause the burst buffer to store the plurality of second page table entries based at least in part on the virtual address.

[0008] In yet another aspect, the present disclosure relates to a system comprising: a system memory; a processor coupled to the system memory; a non-transitory computer-readable storage device having encoded thereon a set of instructions executable by the processor to: transfer a virtual address to a first translation lookaside buffer and a second translation lookaside buffer; fetch a first set of one or more first page table entries prior to receiving a request from a client to access data at a client address, wherein the client address is an address in a virtual memory space used by the client, and wherein the first set of one or more first page table entries is fetched based at least in part on the virtual address, wherein the first set of one or more first page table entries is fetched based at least in part on the virtual address Each of the one or more first page table entries is associated with a corresponding page table address; the first group of one or more first page table entries is stored via the first translation lookaside buffer; a plurality of second page table entries is stored via a burst buffer at least partially based on the virtual address; a first group of one or more second page table entries of the plurality of second page table entries is extracted from the burst buffer via the second translation lookaside buffer at least partially based on the virtual address and before receiving the request from the client to access the data at the client address; and the first group of one or more second page table entries is stored via the second translation lookaside buffer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] A further understanding of the nature and advantages of particular embodiments may be achieved by reference to the remainder of the specification and drawings, wherein the same reference numerals are used to refer to similar components. In some instances, a sub-label is associated with a reference numeral to indicate one of multiple similar components. When reference is made to a reference numeral without specifying an existing sub-label, it is intended to refer to all such multiple similar components.

[0010] Figure 1 is a schematic block diagram of an architecture for a virtual memory prefetch MMU according to various embodiments;

[0011] Figure 2 is a schematic block diagram of an L2 TLB for prefetching an MMU according to various embodiments;

[0012] Figure 3 is a schematic diagram of an L1 TLB for prefetching according to various embodiments; and

[0013] Figure 4 is a schematic diagram of prefetch FIFO control logic according to various embodiments. DETAILED DESCRIPTION

[0014] Various embodiments describe a framework and implementation for real-time virtual memory address translation using a pre-fetch MMU.

[0015] In some embodiments, a device for prefetching an MMU is provided. The device includes a system memory and a memory management unit coupled to the system memory. The memory management unit includes a first translation lookaside buffer, a burst buffer, a second translation lookaside buffer, and control logic. The first translation lookaside buffer is configured to extract a first set of one or more first page table entries before receiving a request from a client to access data at a client address, wherein the client address is an address in a virtual memory space used by the client, and wherein the first set of one or more first page table entries is extracted based at least in part on the virtual address. The burst buffer stores a plurality of second page table entries from a corresponding page table associated with the first page table address. The second translation lookaside buffer is configured to extract a first set of one or more second page table entries from the burst buffer based at least in part on the virtual address and before receiving a request from the client to access data at the client address. The control logic is configured to transmit the virtual address to the first and second translation lookaside buffers, and cause the burst buffer to store the plurality of second page table entries.

[0016] In another embodiment, a prefetch MMU is provided. The prefetch MMU includes a first translation lookaside buffer, a burst buffer, a second translation lookaside buffer, and control logic. The first translation lookaside buffer is configured to prefetch a first group of one or more first page table entries based at least in part on a virtual address, and wherein the prefetching of the first group of one or more first page table entries occurs before a request to access data at a client address is received from a client, wherein the client address is an address in a virtual memory space used by the client. The burst buffer stores a plurality of second page table entries from a corresponding page table associated with the first page table address. The second translation lookaside buffer is configured to prefetch a first group of one or more second page table entries from a plurality of second page table entries based at least in part on a virtual address from the burst buffer, wherein the prefetching of the first group of one or more second page table entries occurs before a request to access data at a client address is received from a client. The control logic is configured to transmit the virtual address to the first and second translation lookaside buffers, and cause the burst buffer to store the plurality of second page table entries.

[0017] In another embodiment, a system for prefetching an MMU is provided. The system includes: a system memory; a processor coupled to the system memory; and a non-transitory computer-readable storage device having encoded thereon a set of instructions executable by the processor to perform various functions. In some instances, the set of instructions is executable by the processor to transfer a virtual address to a first translation lookaside buffer and a second translation lookaside buffer, and to extract a first set of one or more first page table entries before receiving a request from a client to access data at a client address, wherein the client address is an address in a virtual memory space used by the client, and wherein the first set of one or more first page table entries is extracted based at least in part on the virtual address, wherein each first page table entry in the one or more first page table entries is associated with a corresponding page table address. The instructions are further executable by the processor to store the first set of one or more first page table entries in a first translation lookaside buffer, and to store a plurality of second page table entries based at least in part on the virtual address via a burst buffer. The instructions are further executable by the processor to, based at least in part on the virtual address and before receiving a request from the client to access data at the client address, extract a first set of one or more second page table entries from the burst buffer, and store the first set of one or more second page table entries in a second translation lookaside buffer.

[0018] In the following description, for the purpose of explanation, many details are set forth to provide a thorough understanding of the described embodiments. However, it will be apparent to one skilled in the art that other embodiments may be practiced without some of these details. Several embodiments are described herein, and although various features are attributed to different embodiments, it should be understood that features described with respect to one embodiment may also be combined with other embodiments. However, similarly, any single feature or several features of any described embodiment should not be considered essential to every embodiment of the present invention, as other embodiments of the present invention may omit these features.

[0019] When an element is referred to herein as being "connected" or "coupled" to another element (this includes being connected or coupled mechanically, electrically, or communicatively), it is understood that the element may be directly connected to another element, or that there may be intermediate elements between the elements. Conversely, when an element is referred to as being "directly connected" or "directly coupled" to another element, it is understood that there are no intermediate elements in a "direct" connection between elements. However, the presence of a direct connection does not exclude other connections, in which there may be intermediate elements.

[0020] When an element is referred to herein as being "disposed" in some manner relative to another element (e.g., disposed on, between, below, adjacent, or in some other relative manner), it is understood that the element may be disposed directly relative to the other element (e.g., disposed directly on the other element) or that there may be intervening elements between the elements. Conversely, when an element is referred to as being "directly disposed" relative to another element, it is understood that there are no intervening elements in the "direct" instance. However, the presence of a direct placement does not exclude other instances where there may be intervening elements.

[0021] Likewise, when an element is referred to herein as a "layer," it is understood that the layer may be a single layer or may include multiple layers. For example, a conductive layer may include a plurality of different conductive materials or multiple layers of different conductive materials, and a dielectric layer may include a plurality of dielectric materials or multiple layers of dielectric materials. When a layer is described as being coupled or connected to another layer, it is understood that the coupled or connected layer may include intermediate elements present between the coupled or connected layers. Conversely, when a layer is referred to as being "directly" connected or coupled to another layer, it is understood that there are no intermediate elements between the layers. However, the presence of a directly coupled or connected layer does not exclude other connections where intermediate elements may be present.

[0022] In addition, the terms left, right, front, back, top, bottom, forward, backward, clockwise and counterclockwise are used for explanation purposes only and are not limited to any fixed direction or orientation. Instead, they are only used to indicate the relative position and / or direction between the various parts of an object and / or component.

[0023] In addition, for ease of description, the methods and processes described herein may be described in a particular order. However, it should be understood that unless the context otherwise dictates, intermediate processes may occur before and / or after any portion of the described process, and various additional processes may be reordered, added, and / or omitted according to various embodiments.

[0024] Unless otherwise stated, all numbers used herein to express quantities, dimensions, etc. should be understood as being modified by the term "about" in all instances. In this application, the use of the singular includes the plural unless otherwise specifically stated, and the use of the terms "and" and "or" means "and / or" unless otherwise stated. In addition, the use of the terms "including" and "having" as well as other forms such as "includes", "is included", and "has / have / had" should be considered non-exclusive. In addition, terms such as "element" or "component" cover elements and components comprising one unit as well as elements and components comprising more than one unit, unless otherwise specifically stated.

[0025] As used herein, the phrase "at least one of" preceding a series of items, and the terms "and" or "or" separating any items, modify the entire list, rather than each member of the list (i.e., each item). The phrase "at least one of" does not require selection of at least one of each item listed; rather, the phrase allows for a meaning that includes at least one of any of the items and / or at least one of any combination of items. For example, the phrase "at least one of A, B, and C" or "at least one of A, B, or C" each refers to only A, only B, or only C; and / or any combination of A, B, and C. In instances where selection of "at least one of each of A, B, and C" or, alternatively, "at least one of A, at least one of B, and at least one of C" is desired, it is explicitly described as such.

[0026] As used herein, the terms "machine-readable medium" and "computer-readable medium" refer to any medium that participates in providing data that causes a machine to operate in a specific manner. In many embodiments, computer-readable media is a non-transitory, physical, and / or tangible storage medium. In some embodiments, computer-readable media can take many forms, including but not limited to non-volatile media, volatile media, or the like. Non-volatile media include, for example, read-only memory, solid-state memory, optical and / or magnetic disks, and other non-volatile storage devices. Volatile media include, but are not limited to dynamic memory, such as DRAM.

[0027] Common forms of physical and / or tangible computer readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tape or any other magnetic media, CD-ROMs, any other optical media, punch cards, paper tape, any other physical media with patterns of holes, RAM, PROM and EPROM, FLASH-EPROM, any other memory chip or cartridge, the carrier wave described below, or any other media from which a computer can read instructions and / or code.

[0028] Typically, when a client attempts to access a DRAM address, multiple fetches are performed. First, a page table entry (PTE) for a particular virtual address is fetched, from which a translation (e.g., remapping) to a physical address is performed. Once the physical address is obtained, a second DRAM access is made to the physical address. For real-time hardware processing, this can result in missing real-time deadlines.

[0029] In a conventional method, in order to avoid missing real-time deadlines, a hardware client in physically mapped DRAM can be utilized, which does not directly interact with the application program running in virtual memory. In other methods, the CPU can copy data from user space to driver space to the physical memory block of DRAM at a high performance cost. In another alternative method, continuous physical memory can be allocated for use by both application programs and hardware. However, when multiple hardware cores use large continuous memory blocks, such systems will often run out of memory or suffer from memory fragmentation.

[0030] The proposed prefetch MMU framework describes an architecture and framework for a virtual address prefetch MMU. Specifically, an MMU is described in which virtual memory page table information is read by the MMU before real-time hardware (e.g., video client hardware) and / or other real-time hardware processing (e.g., real-time processing of audio data, satellite bitstreams, and / or cable bitstreams). As used herein, hard real-time hardware refers to a hardware system that is subject to real-time timing constraints (e.g., response time and other real-time deadlines). As used herein, "hard real-time" refers to a system (e.g., hardware and / or software) that is subject to a set of one or more strict deadlines, where missing a deadline is considered a system failure. Therefore, in order to meet hard real-time deadlines (or deadlines in other "soft" real-time systems), the MMU can predictably prefetch virtual memory PTEs so that the real-time hardware can meet its deadlines while also reading from the virtual memory space utilized by the application and operating system (e.g., Linux). As used herein, fetching refers to the process of retrieving data from a source (in this case, system memory such as DRAM). Therefore, prefetching refers to the process of extracting data from system memory for use by a client before the client makes a request for the data. MMU refers to a processor and corresponding logic that provides memory management functionality as described herein. In some examples, the MMU may manage all memory references, manage virtual memory address space, and provide translations between virtual memory addresses and physical memory addresses, as described below. System memory may refer to physical and / or virtual memory used by a computer system. System memory includes, but is not limited to, random access memory (RAM) (e.g., DRAM, static random access memory (SRAM)), read-only memory (ROM), storage devices such as hard drives or removable media, and the like. System memory, as used in the context of some of the following examples, may be contrasted with on-chip memory (e.g., on-chip cache memory, such as an L1 or L2 cache) as explicitly described and / or specified by the context.

[0031] Figure 1 1 is a schematic block diagram of an architecture for a virtual memory prefetch MMU 100 according to various embodiments. The prefetch MMU 100 includes a prefetch first-in-first-out (FIFO) control logic 105, a level 1 (L1) translation lookaside buffer (TLB) 110, a level 2 (L2) TLB 115, a dual burst buffer 120, an address filtering logic 125, and an address remapping logic 130. It should be noted that in Figure 1 Various portions and components of MMU 100 are schematically illustrated in FIG. 1 , and modifications to the various components and other arrangements of MMU 100 may be possible according to various embodiments.

[0032] In various embodiments, the prefetch FIFO control logic 105 is coupled to the L1 TLB 110, the L2 TLB 115, and the dual burst buffer 120. The prefetch FIFO control logic 105 may include two virtual address (VA) pointers, an Ld VA and an Rd VA. As will be described in more detail below, the prefetch FIFO control logic 105 may use the Ld VA pointer to manage loading the dual burst buffer 120 and / or the L1 TLB 110 from a system memory, such as a DRAM. The prefetch FIFO control logic 105 may use the Rd VA pointer to read PTEs from the dual burst buffer 120 into the L2 TLB 115. Thus, in various examples, the prefetch FIFO control logic 105 is configured to prefetch one or more VA PTEs to be loaded into the dual burst buffer 120, into the L1 TLB 110, and / or into the L2 TLB 115. As used herein, logic may refer to logic implemented in hardware (e.g., logic circuits), software, and / or hardware and software. Thus, in various embodiments, the prefetch FIFO control logic 105 may be implemented in hardware and / or software. In various embodiments, a page table entry may refer to an entry in a page table that provides a translation between VA and PA. More specifically, a page table entry may contain information about a particular page of physical memory, including the physical base address of the associated page of physical memory.

[0033] In various embodiments, logic in MMU 100 (e.g., prefetch FIFO control logic 105, and logic in L1 TLB 110 and / or L2 TLB 115) may include firmware, drivers, libraries, and / or other code, such as one or more computer programs provided by various embodiments, and / or may be designed to implement the methods described herein. By way of example only, one or more processes described herein may be implemented as code and / or instructions that can be executed by a computer (and / or a processor within a computer, such as MMU 100).

[0034] A set of these instructions and / or codes may be encoded and / or stored on a non-transitory computer-readable storage medium (e.g., on-chip memory). In other embodiments, the storage medium may be separate from the computer system (i.e., removable media, such as an optical disk, etc.), and / or provided in an installation package, such that the storage medium may be used to program, configure, and / or adapt the computer or processor on which the instructions / codes are stored. These instructions may take the form of executable code that can be executed by the computer system and / or the processor of the computer system, which then takes the form of executable code when compiled and / or installed on the computer system (e.g., using any of a variety of commonly available compilers, installation programs, compression / decompression utilities, etc.).

[0035] Substantial changes may be made depending on specific requirements. For example, customized hardware may also be used, such as programmable logic, single board computers, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), systems on a chip (SoCs), or other customized integrated circuits (ICs), and / or specific elements may be implemented in hardware, software, or both.

[0036] For the purpose of explanation, it is assumed that data access is linear, using a single pointer. The MMU 100 uses a single L2PTE once, accesses the corresponding page, and moves to the next page. It is assumed that there is no backtracking to the previous page, and the access is linear in VA address order. In addition, in various embodiments, each system command bus (SCB) client is described in the context of having a corresponding MMU 100 instance. It should be understood that in other embodiments, multiple SCB clients may exist simultaneously in a specific environment, and each SCB client is separate from each other, and each SCB client has a corresponding MMU instance. As used herein, an SCB client refers to an entity that makes a memory access request, such as an application, a hardware core, and / or an OS. As used herein, an SCB refers to a bus between a client and an MMU 100, which a client can use to access DRAM (e.g., send an access request to the MMU 100, etc.).

[0037] To accommodate hard real-time deadlines, the MMU 100 utilizes TLBs, in this example L1 and L2 TLBs 110, 115, coupled to the prefetch FIFO control logic 105. The L1 and L2 TLBs 110, 115 may be coupled to the prefetch FIFO control logic 105, and the L2 TLB 115 is further coupled to the dual burst buffer 120. In various examples, the TLB may be a memory cache (e.g., an associative cache) that stores translations of VA to physical addresses (PAs), referred to as PTEs. Thus, the PTEs contain a mapping of VAs to PAs.

[0038] In various embodiments, the client address may be received by the MMU and then filtered via address filtering logic 125. As used herein, a client address is a virtual address used by a client (e.g., an application, an OS, and / or a hardware core) to be translated by the MMU 100. In various examples, the address filtering logic 125 may be logic configured to filter addresses based on a virtual memory limit (vm-limit) register database (RDB) register to limit the virtual memory range. In various examples, the vm-limit establishes an upper limit for VAs above which they are not populated in the L1 TLB.

[0039] Then, L2 TLB 115 may be used to look up and obtain the PTE associated with the filtered VA, and address remapping logic 130 may remap the VA to a PA from which the requested data may be extracted. In various examples, address remapping logic 130 may include logic configured to remap the VA to the PA based on the PTE. For example, in some embodiments, remapping the VA may include converting a large (e.g., 40-bit) VA to a PA (e.g., a 35-bit PA) for addressing DRAM.

[0040] In some examples, L2 TLB 115 may generate a physical page address. VA may then be concatenated to VA bits [11:0] within the page, with the lower 12 bits of VA being retained. The upper 28 bits are used to look up the translation in the page table, and the output of the page table (e.g., PTE) provides the address where the associated page is located in physical DRAM. In this manner, address remapping logic 130 may map 40 bits to 35 bits.

[0041] In various embodiments, the dual burst buffer 120 may be a buffer sized to hold two sets of 8 "jword" (JW) bursts from a page table (e.g., as stored in DRAM). For example, in various embodiments, a PTE may be 32 bits. A 1JW may contain 8 PTEs, and thus a 1JW may be 256 bits in length. Accordingly, an 8JW burst may hold 64 PTEs. In various instances, the dual burst buffer 120 may be addressable with a VA counter, incremented by 1JW for reads and by 8JW for writes. In the depicted example, an 8JW burst is utilized, but in other instances, a 4JW or 2JW burst may be used for slower data traffic. In various embodiments, the dual burst buffer 120 is a FIFO buffer (interchangeably referred to as a "FIFO" or "prefetch FIFO"). Thus, as used herein, a burst buffer is a type of buffer used to store "bursts" of data extracted from system memory (e.g., DRAM). Thus, a burst buffer may refer to a quickly accessible buffer to which data transferred in a "burst mode" may be written and / or later read.

[0042] Thus, in various embodiments, pre-fetching of L1 and L2 PTEs may occur before a request to access data at a client address is received by MMU 100. As will be described in greater detail below, L1 TLB 110 and L2 TLB 115 may fetch PTEs associated with an initial VA selected from a virtual memory address space associated with a given client (e.g., a VA within a range of VAs used by the client / client address).

[0043] In various examples, to prefetch PTEs, the prefetch is a simple address generator that matches the access order of the client (e.g., SCB client, such as a video feeder device (VFD)) and generates a DRAM read to the page table and stores the resulting 8JW burst in the dual burst buffer 120. Each fetch from the page table at VA may return 8JW (e.g., 256 bytes) or 64 PTEs. The TLB may operate on each address burst created by the client (e.g., SCB client) and may use the VA to compare with entries in the TLB (e.g., L2 TLB 115 and / or L1 TLB 110), and upon a match, the resulting PTE will be used to remap the VA to the PA. In some examples, when there is a TLB miss, the next JW may be popped from the dual burst buffer 120 and loaded into the TLB (e.g., L2 TLB 115). Thus, in various embodiments, PTEs may be pre-fetched and stored in dual burst buffer 120 , and pushed into a TLB, in this example, L2 TLB 115 .

[0044] In some examples, for two-level page table functionality, each L1 TLB 110 entry may reference 4MB of PA memory. In this configuration, an L1 entry with a value of 4JW may hold 32 L1 page pointers (reference 128MB of memory), which may further be single-buffered. In other examples, the number of lines in the TLB (e.g., L1 TLB 110 and / or L2 TLB 115) may be determined based on the addressing mode. For example, an MPEG feeder (MFD) may utilize more lines in the TLB. For example, for an 8K video frame, the TLB may utilize 48 lines. In some other examples, bursts that cross page boundaries will require two address lookups for each SCB command. Special attention must be paid to the timeline to ensure that TLB misses between address cycles on the SCB are not interrupted by the need to fill the dual burst buffer 120. In some examples, an Rdy accept protocol design may be implemented to ensure that the client does not generate any SCB transactions until the MMU 100 has preloaded the first burst from DRAM.

[0045] The following will refer to Figures 2 to 4 The details of the L2 TLB, L1 TLB, and prefetch FIFO control logic 105 are described in more detail.

[0046] Figure 2 2 is a schematic block diagram of an L2 TLB 200 for prefetching an MMU according to various embodiments. The L2 TLB 200 includes a buffer line 205 and a multiplexer 210. Figure 2Various portions and components of L2 TLB 200 are schematically illustrated in , and modifications to the various components and other arrangements of L2 TLB 200 may be possible according to various embodiments.

[0047] In the depicted example, L2 TLB 200 is a single-line TLB with 1 JW of storage. In some examples, because the prefetch FIFO control logic can fill or "pop" more TLB entries from the dual burst buffer, fewer PTEs can be stored in L2 TLB 200 at a given time. In some examples, the pop signal can occur when either: 1) the line is empty, in which case the prefetch FIFO control logic can pop from the dual burst buffer (or other FIFO buffer) at startup; or 2) a miss condition occurs when L2 TLB 200 is full.

[0048] Thus, the buffer line 205 may be filled during startup and remain filled during operation until a miss condition occurs. In various instances, the buffer line 205 is a cache line (e.g., a line of a cache) of the L2 TLB 200. A cache line may refer to a memory block that is mapped to a cache (e.g., managed by a cache). In various instances, a miss condition occurs when an incoming VA from a client is not found (e.g., not filled) in the buffer line 205. For each miss, a new line may be loaded into the buffer line 205 by the prefetch FIFO control logic from, for example, the dual burst buffer described previously. In some instances, the L2 TLB 200 may omit a load counter because there is only one buffer line 205. In an alternative embodiment, the L2 TLB 200 may be a zero-line TLB (e.g., without a buffer line 205) and instead reads data directly from the FIFO buffer.

[0049] When new data arrives from a FIFO (e.g., a dual burst buffer or other FIFO buffer), a VA tag may be generated using a "matching VA" value. The VA tag may be a value representing the actual prefetch VA. The VA tag may be used to compare an incoming client address (e.g., a VA received from a client) with a prefetch address stored in a buffer line 205. For example, the upper bits of the client address (e.g., VA[39:15]) may be used to generate the VA tag. The VA tag may be compared with the upper bits of the incoming client VA. In the event of a match (e.g., a hit), three bits of the VA (e.g., VA[14:12]) may be used to select a PTE from the buffer line 205. For example, in various embodiments, the multiplexer 210 may be configured to select one of the eight PTEs stored in the buffer line 205 based on VA[14:12]. Thus, in some instances, the multiplexer 210 may be an 8:1 multiplexer (e.g., an 8PTE to 1PTE multiplexer). The PTE may be used to replace the upper bits (e.g., VA[39:15]) with the physical address bits. The "F" block may be used to indicate whether the buffer line 205 is full or empty. In the case where the buffer line 205 is empty, the AND logic block ensures that a hit condition is not generated (e.g., when the buffer line 205 is empty, F=0).

[0050] In some examples, the VA tags may be matched sequentially on a line-by-line basis. Thus, subsequently popped lines may be configured to have sequential VA tags. However, if there is an error, or if the page table becomes corrupted, the client address may generate a large number of miss conditions because the VA from the client does not match the VA from the prefetch FIFO. For example, in some embodiments, the error condition may include, but is not limited to, when a threshold number of miss conditions occur in a line (e.g., 16 misses occur in a line), L2 TLB 200 may be configured to stop processing and indicate an error condition (e.g., generate an error signal).

[0051] Figure 3 3 is a schematic diagram of an L1 TLB 300 for prefetching according to various embodiments. The L1 TLB 300 includes a first buffer line 305a, a second buffer line 305b, a third buffer line 305c, and a fourth buffer line 305d (collectively referred to as “buffer lines 305”) and a multiplexer 310. It should be noted that in Figure 3 Various portions and components of L1 TLB 300 are schematically illustrated in , and modifications to the various components and other arrangements of L1 TLB 300 may be possible according to various embodiments.

[0052] In the depicted example, L1 TLB 300 is a 4-line TLB with 2 PTEs stored per line. Thus, each buffer line 305 can store 16 PTEs (e.g., 16 PTEs per line). Thus, a 16:1 multiplexer 310 can be used to select a single PTE from a given buffer line 305a to 305d. It should be understood that in other examples, different arrangements can be utilized where a different number of PTEs can be stored in each line (e.g., 1 PTE line with 8 PTEs stored per line).

[0053] In various embodiments, L1 TLB 300 may be used to convert VA to a page table PA (e.g., an incoming client VA, or a VA to be prefetched and loaded into a dual burst buffer or other prefetch FIFO). For example, logic (outlined in dashed circles) may be used to calculate the PA of the L1 table pointer to fetch a 2JW burst from DRAM to be loaded into a buffer line (e.g., first buffer line 305a) in buffer line 305 in this example in the event of a miss. The L1 table pointer may be combined with the upper bits of VA to produce a 35-bit physical address (e.g., Fetch[34:0]) from which data may be fetched from DRAM to be filled into buffer line 305. The L1 pointer may form bits Fetch[34:20] of PA Fetch[34:0].

[0054] Therefore, to extract 2JW of data to load the buffer lines 305a to 305d of the L1 TLB 300, 2JW alignment may be enforced by the following operations:

[0055] L1 Fetch[34:0]=L1 Pointer[34:20]+VA[39:26].'000000'(Equation 1)

[0056] Where adders are represented by a '+' symbol and cascades are represented by a '.' symbol. In various examples, data is fetched from the DRAM at the PA calculated above. Therefore, the L1 TLB 300 can be configured to accept return data from the DRAM at the SCB rate to ensure that the SCB is not stalled by the fetch operation.

[0057] In various examples, once data is extracted from the DRAM, it may be stored in one or more buffer lines 305a-305b. Although four buffer lines are depicted, it should be understood that in other embodiments, more or fewer buffer lines may be utilized.

[0058] In various examples, based on VA, VA tag comparison can be utilized to select buffer lines 305a-305d, as previously described with respect to Figure 2As described above. For example, the VA[39:26] bits may be used as tags and compared with the VA tags associated with the corresponding buffer lines 305a-305d. In the event of a hit (e.g., a match), the corresponding matching buffer line 305a-305d may be selected. The multiplexer 310 may be configured to select from the 16 PTEs of the corresponding buffer line 305a-305d based on the VA[26-22] bits, where each PTE may correspond to a corresponding L2 page table address.

[0059] In some examples, the selected L1 PTE may be 32 bits, PTE[31:0]. The L2 page table address may include bits PTE[22:0] of PTE[31:0]. Since the size of the L2 PTE burst is 8JW, the L2 table pointer PA may be aligned with 8JW and generated as follows:

[0060] L2 PA[34:0]=PTE[22:0].VA[21:18].'00000000' (Equation 2)

[0061] Where '00000000' is needed because the L2 table entry is 8JW. The address is calculated to be 8 times larger than VA (e.g., shifted by 3 bits) in order to fetch a burst of 8JW. The L2 page table pointer PA calculated above can be sent to the SCB bus to be fetched (e.g., from DRAM and / or cache) and loaded into the pre-fetch FIFO. Therefore, the L2 page table pointer PA is the PA within the L2 page table for the 8JW burst of L2 PTEs. More generally, the pointer PA can refer to a PA that points to another address or PTE (e.g., a PA within a page table).

[0062] In some further embodiments, L1 TLB 300 may be configured to translate L2 page table pointer PA for one or more L2 TLBs. For example, in low data rate applications, L1 may maintain the entire VA space for all L2 operations so that there are no L1 miss conditions.

[0063] Figure 4 4 is a schematic diagram of an architecture 400 for prefetch FIFO control logic 405 according to various embodiments. In various embodiments, prefetch FIFO control logic 405 may be configured to fill a prefetch FIFO, such as a dual burst buffer, when a core (e.g., an MMU physical and / or logical core) is turned on, and manage reads / pops from the FIFO buffer to the L2 TLB.

[0064] In various examples, the Ld VA pointer may be configured to manage the loading of the prefetch FIFO buffer (e.g., a dual burst buffer) whenever there is available space (e.g., at startup or in the event of an L1 miss). It loads a burst of 8 JW at a time and counts [39:15] in the VA space. As previously described, in the VA to PA translation, bits [17:15] are used as the VA of the 8 JW for the L2 PTE data. In these examples, bits [17:15] are "000" because the burst is always 8 JW aligned. In some further embodiments, the Ld VA bit

[18] may determine whether the burst is loaded at the top or bottom of the dual burst buffer.

[0065] In various embodiments, when there is room for the load FIFO, Ld VA bits [39:15] may be sent to the L1 TLB. Figure 3 As described, the L1 TLB may convert VA to PA and send a burst to the SCB bus to fetch 8JW chunks from the L2 page table (e.g., which may be stored in DRAM and / or cache). In some examples, the Ld VA pointer is initialized with the same starting address as the client VA so that prefetches are aligned with a specific client. In various examples, based on available space, the Ld VA pointer may be incremented by +8JW each time a burst is requested. In some embodiments, in the event of an L1 miss condition (e.g., the PTE associated with the LdVA pointer and / or the client address is not stored in the L1 TLB), the L1 TLB may be configured to obtain a new burst of PTEs (e.g., a 2JW burst of L1 PTEs).

[0066] Instead, in various examples, Rd VA is incremented by 1JW, and a smaller L2 PTE 1JW of data is read for L2 TLB utilization. In some embodiments, Rd VA bits [14:12] may be "000", corresponding to 8 PTEs within a single 1W of data read from DRAM. For L2 TLB reads, bits from Rd VA [17:15] may point to the location closest to the 1JW within the burst. Bit Rd VA

[18] may determine whether to read the upper or lower half of the dual burst buffer.

[0067] In various embodiments, the entire Rd VA[39:15] may be sent to the L2 TLB as a "matching VA" to ensure that the incoming client VA is tagged against the matching VA (e.g., compared to the matching VA tag, as previously described). In some embodiments, the RdVA pointer may be initialized with the same starting address as the client VA. In some instances, the Rd VA pointer may be further incremented by +1JW on each request pop (if data is available in the FIFO). When the FIFO is empty, the Rd VA pointer is not incremented.

[0068] In some alternative embodiments, the prefetch FIFO control logic may support other addressing schemes besides the linear example described above. For example, in some embodiments, a decrementing VA scheme may be utilized (e.g., using a subtracting VA pointer). In other embodiments, a circular buffer VA scheme may be utilized (e.g., when the VA pointer reaches a wrap, reload a new VA start point and continue). In other embodiments, a stride VA scheme may be utilized (e.g., when the VA pointer reaches the end of the stride, increment the next stride amount).

[0069] Although some features and aspects have been described with respect to embodiments, those skilled in the art will recognize that many modifications are possible. For example, although various methods and processes described herein may be described with respect to specific structural and / or functional components for ease of description, the methods provided by various embodiments are not limited to any specific structural and / or functional architecture, but may be implemented in any suitable hardware configuration. Similarly, although some functionality is attributed to one or more system components, unless the context dictates otherwise, this functionality may be distributed among various other system components according to several embodiments.

[0070] In addition, although the procedures of the methods and processes described herein are described in a particular order for ease of description, various procedures may be reordered, added, and / or omitted according to various embodiments unless the context dictates otherwise. In addition, procedures described with respect to one method or process may be incorporated into other described methods or processes; similarly, system components described according to a particular structural architecture and / or with respect to one system may be organized in an alternative structural architecture and / or incorporated into other described systems. Therefore, although various embodiments with or without some features are described for ease of description and explanation of aspects of those embodiments, various components and / or features described herein with respect to specific embodiments may be replaced, added, and / or subtracted from other described embodiments unless the context dictates otherwise. Therefore, although several embodiments are described above, it should be understood that the present invention is intended to cover all modifications and equivalents within the scope of the appended claims.

Claims

1. A device comprising: System memory; a memory management unit coupled to the system memory, the memory management unit comprising: a first translation lookaside buffer configured to fetch a first set of one or more first page table entries prior to receiving a request from a client to access data at a client address, wherein the client address is an address in a virtual memory space used by the client, and wherein the first set of one or more first page table entries is fetched based at least in part on the virtual address, wherein each first page table entry of the one or more first page table entries is associated with a respective page table address; a burst buffer configured to store a plurality of second page table entries from a corresponding page table associated with the first page table address; a second translation lookaside buffer configured to fetch, from the burst buffer, a first set of one or more of the plurality of second page table entries based at least in part on the virtual address and before receiving the request from the client to access data at the client address; and Control logic is configured to transmit the virtual address to the first translation lookaside buffer and the second translation lookaside buffer and cause the burst buffer to store the plurality of second page table entries based at least in part on the virtual address.

2. The apparatus of claim 1, wherein the burst buffer is configured to store a burst of table entries, wherein the plurality of second page table entries comprises sixteen page table entries.

3. The apparatus of claim 1 , wherein the first translation lookaside buffer is configured to translate the virtual address into a first pointer physical address of the system memory, wherein the first set of one or more first page table entries are fetched by the first translation lookaside buffer from the first pointer physical address.

4. The apparatus of claim 1 , wherein the second translation lookaside buffer is configured to generate a virtual address tag based at least in part on the virtual address, and wherein the virtual address tag is associated with the first set of one or more second page table entries, wherein the second translation lookaside buffer is configured to receive the client address and compare the virtual address tag to a first portion of the client address.

5. The apparatus of claim 4 , wherein in response to determining that the virtual address tag matches the first portion of the client address, the second translation lookaside buffer is configured to select a corresponding second page table entry of the one or more second page table entries stored at the second translation lookaside buffer based at least in part on a second portion of the client address that is different from the first portion.

6. The apparatus of claim 5, further comprising address remapping logic configured to remap the client address to a physical address of the system memory based at least in part on the respective second page table entry selected by the second translation lookaside buffer.

7. The apparatus of claim 5, wherein in response to determining that the virtual address tag does not match the first portion of the client address, the second translation lookaside buffer is configured to extract a second set of one or more second page table entries from the burst buffer, wherein the second set of one or more second page table entries is different from the first set.

8. The apparatus of claim 7, wherein in response to determining that the virtual address tag does not match the first portion of the client address, determining whether the first set of one or more first page table entries stored in the first translation lookaside buffer are associated with the client address.

9. The apparatus of claim 8 , wherein in response to determining that none of the first set of one or more first page table entries is associated with the client address, a second pointer physical address of the system memory is generated based at least in part on the client address, and a second set of one or more first page table entries is retrieved based on the second pointer physical address.

10. A memory management unit, comprising: a first translation lookaside buffer configured to prefetch a first set of one or more first page table entries based at least in part on a virtual address, wherein each first page table entry of the one or more first page table entries is associated with a respective page table address, and wherein the prefetching of the first set of one or more first page table entries occurs before a request is received from a client to access data at a client address, wherein the client address is an address in a virtual memory space used by the client; a burst buffer configured to store a plurality of second page table entries from a corresponding page table associated with the first page table address; a second translation lookaside buffer configured to prefetch a first set of one or more second page table entries of the plurality of second page table entries from the burst buffer based at least in part on the virtual address, wherein the prefetching of the first set of one or more second page table entries occurs before a request is received from the client to access data at a client address; and Control logic is configured to transmit the virtual address to the first translation lookaside buffer and the second translation lookaside buffer and cause the burst buffer to store the plurality of second page table entries based at least in part on the virtual address.

11. The memory management unit of claim 10, wherein the first translation lookaside buffer is configured to translate the virtual address into a first pointer physical address of the system memory, wherein the first set of one or more first page table entries are fetched by the first translation lookaside buffer from the first pointer physical address.

12. The memory management unit of claim 10 , wherein the second translation lookaside buffer is configured to generate a virtual address tag based at least in part on the virtual address, and wherein the virtual address tag is associated with the first set of one or more second page table entries, wherein the second translation lookaside buffer is configured to receive the client address and compare the virtual address tag to a first portion of the client address.

13. The memory management unit of claim 12 , wherein in response to determining that the virtual address tag matches the first portion of the client address, the second translation lookaside buffer is configured to select a corresponding second page table entry of the one or more second page table entries stored at the second translation lookaside buffer based at least in part on a second portion of the client address that is different from the first portion.

14. The memory management unit of claim 12, wherein in response to determining that the virtual address tag does not match the first portion of the client address, the second translation lookaside buffer is configured to extract a second set of one or more second page table entries from the burst buffer, wherein the second set of one or more second page table entries is different from the first set.

15. The memory management unit of claim 12 , wherein in response to determining that the virtual address tag does not match the first portion of the client address, it is determined whether the first set of one or more first page table entries stored in the first translation lookaside buffer are associated with the client address, wherein in response to determining that none of the first set of one or more first page table entries are associated with the client address, a second pointer physical address of the system memory is generated based at least in part on the client address, and a second set of one or more first page table entries is retrieved based on the second pointer physical address.

16. A system comprising: System memory; a processor coupled to the system memory; a non-transitory computer-readable storage device having encoded thereon a set of instructions executable by the processor to: transferring the virtual address to the first translation lookaside buffer and the second translation lookaside buffer; fetching a first set of one or more first page table entries prior to receiving a request from a client to access data at a client address, wherein the client address is an address in a virtual memory space used by the client, and wherein the first set of one or more first page table entries is fetched based at least in part on the virtual address, wherein each first page table entry of the one or more first page table entries is associated with a respective page table address; storing, via the first translation lookaside buffer, the first set of one or more first page table entries; storing, via a burst buffer, a plurality of second page table entries based at least in part on the virtual address; fetching, from the burst buffer via the second translation lookaside buffer, a first set of one or more second page table entries of the plurality of second page table entries based at least in part on the virtual address and before receiving the request from the client to access data at the client address; and The first set of one or more second page table entries is stored via the second translation lookaside buffer.

17. The system of claim 16, wherein the set of instructions is further executable by the processor to: The virtual address is translated into a first pointer physical address of the system memory via the first translation lookaside buffer, wherein the first set of one or more first page table entries is fetched by the first translation lookaside buffer from the first pointer physical address of the system memory.

18. The system of claim 17, wherein the set of instructions is further executable by the processor to: generating a virtual address tag based at least in part on the virtual address, and wherein the virtual address tag is associated with the first set of one or more second page table entries; receiving the client address from the client; and The virtual address tag is compared to a first portion of the client address via the second translation lookaside buffer.

19. The system of claim 17, wherein the set of instructions is further executable by the processor to: The method further comprises: selecting, via the second translation lookaside buffer and in response to determining that the virtual address tag matches the first portion of the client address, a corresponding second page table entry of the one or more second page table entries stored at the second translation lookaside buffer based at least in part on a second portion of the client address that is different from the first portion.

20. The system of claim 19, wherein the set of instructions is further executable by the processor to: In response to determining that the virtual address tag does not match the first portion of the client address, a second set of one or more second page table entries is retrieved from the burst buffer via the second translation lookaside buffer, wherein the second set of one or more second page table entries is different from the first set.

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