Circuit area optimization method based on AND XOR majority diagram

Abstract

The invention discloses a circuit area optimization method based on an AND XOR majority diagram, and relates to a digital logic circuit area optimization method. According to the method, an input integrated circuit is converted into an AIG netlist, then cutting and replacement are carried out in the AIG netlist according to AIG equivalent structures of XOR gate nodes and majority logic gate nodes, equivalent gate nodes are covered on the AIG netlist according to a cutting result, and the AIG netlist is finally converted into an AXMIG netlist through mapping. Area optimization of the AND gate not limited to two inputs can be carried out, the optimization effect is good, and an integrated circuit can have good comprehensive performance. As the area of the circuit is closely related to the number of mapping gates of the logic netlist, the simple logic netlist generally corresponds to a smaller circuit area, and the aim of optimizing the area of the circuit is fulfilled by simplifying the logic netlist.

Description

Technical Field

[0001] The invention relates to a method for optimizing the area of ​​a digital logic circuit, and in particular to a method for optimizing the area of ​​a circuit based on an XOR majority graph. Background Art

[0002] In integrated circuit design, a very important link is the logic synthesis of integrated circuits. Logic synthesis is generally divided into three parts, namely translation, optimization, and mapping. Among them, an important indicator of logic synthesis optimization is how to control the area of ​​the integrated circuit. The optimization problem of reducing the area of ​​the integrated circuit has become a key problem that needs to be solved in integrated circuit design.

[0003] The performance of integrated circuit area optimization depends largely on electronic design automation (EDA) tools. The existing digital logic circuit logic synthesis basically uses Boolean logic with "AND, OR, NOT" as the basic operation set, and the "NAND, NOR" logic derived from it. These logics are collectively called traditional Boolean logic (TB). Most EDA tools are developed from TB logic. In addition to TB logic, Boolean functions can also be implemented using Reed-Muller (RM) logic based on "AND, XOR". Existing studies have shown that RM logic has better performance in integrated circuit synthesis. For arithmetic circuits such as communication circuits and parity check circuits with modulo-2 addition and modulo-2 multiplication functions, the circuit area, speed, power consumption and other performance are greatly improved. In addition, the synthesized circuit netlist is convenient for testing. In recent years, the research on integrated circuit area optimization has mainly focused on TB logic, such as the rewrite algorithm based on the And Inverter Graph (AIG) to reduce local graph nodes to reduce the overall circuit gate nodes to achieve the effect of circuit area optimization, and the balance algorithm, which regards AIG as an unoptimized balanced tree and performs balance optimization. By using the basic properties of logical operations such as associative law, commutative law and distributive law to compress the number of levels, the purpose of circuit delay optimization is achieved. The reconstruction algorithm mainly involves the optimization of shared nodes. If a function can use the existing nodes in the graph for corresponding calculations, the existing nodes in the graph are directly used for connection and sharing without rebuilding new sub-nodes. Most of the integrated circuit area optimization methods written above have been integrated into EDA tools (such as MIS, ABC, etc.), but the problem faced by these methods is that the usage scenarios are single. For multiple application scenarios such as high performance, low energy consumption, and small area, the tools developed based on TB logic cannot effectively solve the problem of multi-scenario optimization.

[0004] Currently, integrated circuit logic synthesis optimization attempts to use TB logic, MR logic, and multiple logics to combine for logic synthesis optimization. Among them, the logic optimization of AND XOR graph (AXIG) is a method of optimizing circuit area by combining TB logic and RM logic. Most of the AND XOR graphs used are based on Boolean functions. In order to convert the principle, the two-input XOR gate structure in AIG is represented by an XOR gate node, so as to optimize and reduce the circuit area. Figure 1 As shown in the figure, this structure is a local circuit of the AIG netlist, which consists of three AND gate nodes. The top node is called the root node, and the two fan-in nodes below the root node are the left child node and the right child node of the root node. The two inputs of the left child node and the right child node are both a and b. The solid line indicates that there is no inverter input, and the dotted line indicates that the input passes through an inverter. Although such AXIG is optimized for area relative to AIG, all nodes in the AIG diagram are limited to two-input AND gates and can only be Boolean functions. The principle is to convert the XOR gate. Even if the polarity of the node fan-in and fan-out is changed, the two-input AND gate is only replaced with a two-input NAND gate, NOR gate and OR gate. However, there are limitations in the implementation of three-input gates and more input gates, so the XOR gate structure that can be represented is not complete, and the area optimization effect needs to be improved. In addition, the optimization of the logic function for AIG requires further research on the representation structure of the logic function. Summary of the invention

[0005] The present invention aims at the limitations of the prior art in the area optimization of integrated circuits, and provides a circuit area optimization method based on an XOR majority graph, which further reduces the circuit area by simultaneously introducing two input nodes (XOR gate) and three input nodes (majority logic gate MAJ), thereby improving the comprehensive performance of the integrated circuit. The optimization method can achieve area optimization at the same time, has a good optimization effect, and can make the integrated circuit have higher comprehensive performance when applied to the integrated circuit.

[0006] In order to achieve the above-mentioned object of the invention, the present invention provides the following technical solutions.

[0007] A circuit area optimization method based on XOR majority graph comprises the following steps:

[0008] 1) Convert the digital logic circuit to be processed into a logic netlist structure, that is, use a directed acyclic graph data structure to display it and convert the integrated circuit into an AIG logic representation.

[0009] 2) Define the XOR structure and majority logic structure in the AIG logic representation. Specifically, a two-input node (XOR gate) and a majority logic gate (MAJ) are proposed as nodes. The logic function expression of the majority gate is , which can also be expressed as Therefore, it is possible to use Boolean functions as well as The method of Boolean logic optimization based on logic algebra is to find the structural representation that satisfies these two Boolean functions in the AIG structure, and use XOR gates and majority logic gates as mapping substitutes.

[0010] 3) Cut the AIG graph generated by the integrated circuit into independent AIG substructures, and set appropriate cutting conditions to ensure that all sub-AIG networks meet the constraints;

[0011] 4) Replace the AIG logic netlist after cutting, search for the AIG structure suitable for conversion into sub-XOR gate nodes and MAJ gate nodes, and perform corresponding replacement operations. For the sub-AIG structure with more than 3 input variables, partially search and replace the two-input XOR gate or three-input majority logic gate that meets the conditions;

[0012] 5) Map the converted AXMIG netlist into a circuit and output it. The output circuit is the area-optimized circuit.

[0013] In step 2), the specific steps of defining the XOR structure and the majority logic structure in the AIG logic representation may be:

[0014] 2-1) Consider the case of input variable negation: For an XOR gate whose input and output are both original variables, if there is a negated variable in the input variable, the input variable can be the negated variable of one variable, or the negated variable of two variables. There are four transformation forms available, and Then eight transformation forms will be obtained. At the same time, the XOR gate corresponds to the AIG structure inside the XOR gate, which corresponds to the input variable (input), that is, the leaf node of the directed acyclic graph, taking the inverse variable;

[0015] 2-2) Consider the order of input variables: In the case of different order of input variables, The input variables can get two cases, and The input variable can get six different situations; and finally when the output variable is negated, The output variables and The output variables can all produce 2 different transformation forms;

[0016] 2-3) Consider the inversion of the output variable: Under various input and output conditions, the two-input Boolean logic function The corresponding AIG graph structure can produce a total of 16 different transformations, and a three-input Boolean logic function The corresponding AIG graph structure can produce a total of 96 different transformation situations.

[0017] In step 3), the specific steps of cutting the AIG graph generated by the integrated circuit may be:

[0018] 3-1) Consider the AIG graph as a tree structure, where the top node is the root node, and the input nodes of a node are the left and right child nodes. Starting from the root node, the AIG Boolean logic structure is cut into independent AIG substructures. The advantage of this cutting method is that these substructures are independent of each other and will not contain each other.

[0019] 3-2) Reduce the size of the sub-network obtained by cutting during cutting, set the maximum number of input variables of the sub-AIG obtained by cutting appropriately during the cutting process, and all cutting is feasible. When an AIG netlist is cut from top to bottom, all sub-AIG networks meet the constraints, and the cutting of the entire AIG is completed.

[0020] In step 4), the specific steps of replacing the cut AIG logic netlist may be:

[0021] 4-1) Identification and processing of invalid cuts: After completing the cutting of AIG, the obtained sub-AIG network is regarded as a potential sub-AXMIG candidate; invalid cuts are identified and excluded, that is, those sub-AIG networks whose internal nodes are connected not only to the inside of the cut but also to external nodes; invalid cuts are not further processed;

[0022] 4-2) Convert according to the number of inputs, including:

[0023] 4-2-1) Replacement of two-input and three-input sub-AIG:

[0024] For a sub-AIG network with 2 inputs, search its internal structure to determine whether it is consistent with the internal structure of the AIG corresponding to the two-input XOR gate node (such as a specific structure composed of an AND gate and an inverter); if consistent, use the XOR gate node to replace the sub-AIG network;

[0025] For the sub-AIG network with 3 inputs, search its internal structure to determine whether it is consistent with the internal structure of the AIG corresponding to the three-input MAJ gate node; if consistent, use the MAJ gate node to replace the sub-AIG network;

[0026] 4-2-2) Partial search and replacement of multiple input sub-AIGs:

[0027] For sub-AIG networks with more than 3 input variables, a partial search is performed to identify whether there is a sub-structure that satisfies the AIG structure corresponding to the two-input XOR gate or the three-input MAJ gate; if a sub-structure that meets the conditions is found, the corresponding gate is replaced (XOR gate or MAJ gate), and the remaining AND gates are not processed; if a sub-structure that meets the conditions is not found in the entire sub-AIG network, the search for the sub-AIG is exited and no replacement is performed.

[0028] Compared with the existing technology, the advantage of the present invention is that by adding a three-input node type to the AIG graph, the area optimization of AND gates not limited to two inputs can be performed, the optimization effect is good, and the integrated circuit can have good comprehensive performance. A new digital logic circuit area optimization method is proposed by using three-input nodes to represent any logic function, by converting the integrated circuit to be processed into an AIG general netlist, and then arranging the AIG structure of two-input nodes and three-input nodes, and then cutting the circuit area based on AIG, based on the replacement of two-input nodes and three-input nodes, the AIG logic netlist is successfully converted into an AXMIG logic netlist. The optimization algorithm utilizes the search for AIG substructures suitable for XOR gate implementation, equivalent transformation of XOR gates with traditional AND gates, OR gates, and logical functions, AIG cutting, coverage of sub-AIG cutting, mapping of XOR gates to appropriate coverage, and conversion of AIG to AXMIG suitable for XOR gate mapping. Because the area of ​​a circuit is closely related to the number of mapped gates in a logic netlist, a simple logic netlist usually corresponds to a smaller circuit area. The purpose of circuit area optimization is achieved by simplifying the logic netlist, and a good optimization effect is achieved. Application to integrated circuits can enable integrated circuits to have higher comprehensive performance. Experimental results show that the AXMIG obtained by the method of the present invention reduces the area by 24.93% and 19.75% respectively compared with the existing AIG and AXIG. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is the logical function Schematic diagram of the corresponding AIG structure.

[0030] Figure 2 The following is a schematic diagram of an AIG structure corresponding to a two-input XOR gate node. (a) is a schematic diagram of the AIG structure in which input a is XORed with input b through a NOT gate; (b) is a schematic diagram of the AIG structure in which input a is XORed with input b; (c) is a schematic diagram of the AIG structure in which input a is XORed with input b and then passes through a NOT gate.

[0031] Figure 3The following are some AIG structure diagrams corresponding to the three-input majority logic gate nodes. Among them, (a) is the AIG structure diagram of input a and input b passing through a MAJ gate, (b) is the AIG structure diagram of input a passing through a NOT gate and input b passing through a MAJ gate, and (c) is the AIG structure diagram of input a and input b passing through a MAJ gate and then a NOT gate.

[0032] Figure 4 Different replacement methods using the same circuit. (a) is a schematic diagram of an effective cutting method, (b) is a schematic diagram of an invalid cutting method, and (c) is a schematic diagram of an invalid cutting method.

[0033] Figure 5 This is the area optimization result after cutting and covering the circuit using the method proposed by the present invention. DETAILED DESCRIPTION

[0034] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the following embodiments will further illustrate the present invention in conjunction with the accompanying drawings. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. On the contrary, the present invention covers any substitution, modification, equivalent method and scheme made on the essence and scope of the present invention as defined by the claims.

[0035] An embodiment of the present invention provides a circuit area optimization method based on an XOR majority graph, comprising the following steps:

[0036] Step 1: Convert the digital logic circuit to be processed into a logic netlist structure, that is, use a directed acyclic graph data structure to display and convert the integrated circuit into an AIG logic representation.

[0037] Step 2: Define the XOR structure and majority logic structure in AIG. Specifically, a majority logic gate (MAJ) is proposed as a node. The logic function expression of the majority gate is , which can also be expressed as Therefore, it is possible to use Boolean functions as well as The method of Boolean logic optimization based on logic algebra is to find the structural representation that satisfies these two Boolean functions in the AIG structure, and use XOR gates and majority logic gates as mapping substitutes.

[0038] 2-1: For an XOR gate whose input and output are both original variables, if there is a negated variable in the input variable, the input variable can be the negated variable of one variable, and the two variables can be negated variables. In this way, There are four transformation forms available, and Then eight transformation forms will be obtained. At the same time, the XOR gate corresponds to the AIG structure inside the XOR gate, which corresponds to the input variable (input), that is, the leaf node of the directed acyclic graph, taking the inverse variable;

[0039] 2-2: When the order of input variables is different, The input variables can get two cases, and The input variable can get six different situations; and finally when the output variable is negated, The output variables and The output variables can all produce two different transformation forms.

[0040] 2-3: Two-input Boolean logic functions in various input and output situations The corresponding AIG graph structure can produce a total of 16 different transformations, and a three-input Boolean logic function The corresponding AIG graph structure can produce a total of 96 different transformation situations.

[0041] Figure 2 The following is a schematic diagram of an AIG structure corresponding to a two-input XOR gate node. (a) is a schematic diagram of the AIG structure in which input a is XORed with input b through a NOT gate; (b) is a schematic diagram of the AIG structure in which input a is XORed with input b; (c) is a schematic diagram of the AIG structure in which input a is XORed with input b and then passes through a NOT gate. Figure 3 The following are some AIG structure diagrams corresponding to the three-input majority logic gate nodes. Among them, (a) is the AIG structure diagram of input a and input b passing through a MAJ gate, (b) is the AIG structure diagram of input a passing through a NOT gate and input b passing through a MAJ gate, and (c) is the AIG structure diagram of input a and input b passing through a MAJ gate and then a NOT gate.

[0042] Step 3: Cut the AIG graph generated by the integrated circuit:

[0043] 3-1: Consider the AIG graph as a tree structure, where the top node is the root node, and the input nodes of a node are the left and right child nodes. Starting from the root node, the AIG Boolean logic structure is cut into independent AIG substructures. The advantage of this cutting method is that these substructures are independent of each other and will not contain each other.

[0044] 3-2: Reduce the size of the sub-network obtained by cutting during cutting, set the maximum number of input variables of the sub-AIG obtained by cutting appropriately during the cutting process, and all cutting is the feasible cutting. When an AIG netlist is cut from top to bottom and all sub-AIG networks meet the constraints, the cutting of the entire AIG is completed.

[0045] Step 4: Replace the AIG logic netlist:

[0046] 4-1: Identification and processing of invalid cuts: After completing the cut of AIG, the sub-AIG network obtained by the cut should be converted into a suitable sub-AXMIG. In the set of sub-AIGs obtained by the cut, search for AIG structures suitable for conversion into sub-XOR gate nodes and MAJ gate nodes. For those sub-AIG structures, the fan-out is not only connected to the internal nodes of the cut, but also connected to the external nodes. Such nodes are called invalid cuts and are not processed.

[0047] 4-2: Convert according to the number of inputs: For valid AIG cuts, convert according to the number of inputs of the sub-AIG netlist:

[0048] 4-2-1: If the number of inputs of the identified sub-AIG netlist is 2, it is necessary to search the internal sub-AIG structure to see if it is consistent with the internal structure of the AIG corresponding to a two-input gate XOR gate node. The internal structure of this sub-AIG uses AND gates as nodes. Dotted lines represent connections through an inverter, while solid lines represent direct connections. If the internal structure of the sub-AIG is consistent with one of the above-mentioned situations, use an XOR gate node to directly replace the sub-AIG netlist here. Similarly, when the number of inputs of the sub-AIG netlist is 3, it is necessary to search the internal sub-AIG structure to see if it is consistent with the internal structure of the AIG corresponding to a three-input gate MAJ gate node. If it is consistent with one of the above-mentioned situations, use the MAJ gate node to replace it.

[0049] 4-2-2: If the number of input variables of the identified sub-AIG structure that needs to be covered is greater than 3, it is necessary to perform arbitrary searches on the sub-AIG structures consisting of 2 and 3 input variables. If the AIG structure corresponding to the two-input XOR gate or the three-input majority logic gate is satisfied, the gate is directly replaced, and the remaining AND gates are not processed. If the internal structure corresponding to the two-input AND gate and the three-input MAJ gate cannot be found, the search for this sub-AIG is exited.

[0050] Step 5: Map the converted AXMIG netlist into a circuit and output it. The output circuit is the area-optimized circuit.

[0051] Figure 4 Different alternative methods of using the same circuit.

[0052] A circuit area optimization method based on XOR majority graph comprises the following steps:

[0053] Step 1 Figure 4 The figure shows the different coverages obtained by different cutting methods of the AIG netlist of the same circuit. This AIG netlist consists of 10 AND gates, represented by numbers 1 to 10, with five inputs a, b, c, d, e. The dotted edge shows the logical inversion, and each square represents a cut. Figure 4 After performing different cuts on a in the figure, we can get different cuts C1, C2, and C3 with root nodes 1, 5, and 6. First, determine whether each cut is a valid cut. A valid cut is when the output of the cut is only connected to one internal node or output node. An invalid cut is when the output of the cut is connected to multiple internal nodes. As shown in the figure, Figure 4 The cut of (a) in the figure is a valid cut, but Figure 4 The output of cut C3 in (b) is output to two different internal nodes, so Figure 4 The cut in (b) is an invalid cut.

[0054] Step 2: After the cutting is completed, start to judge the structure of each valid cutting, and replace the AIG subgraph with the AXMIG subgraph. Figure 4 For the cut in (a) of the figure, first determine the number of input variables of the cut. For cut C1, it can be concluded that there are three input variables, then search the internal structure of C1. If it is found that it is consistent with the internal structure of the MAJ gate, use a MAJ gate to replace C3; for cuts C2 and C3, the inputs are both two. Start searching the internal structure of the cut from the root node of each cut. If it is found that this cut is consistent with the internal structure of the XOR gate, use an XOR gate to replace cuts C2 and C3, traverse all convertible cuts in the AIG netlist, replace each convertible cut in the AIG with an XOR gate or a MAJ gate, and convert the entire AIG netlist into an AXMIG netlist, such as Figure 5 shown.

[0055] Step 3: Take AXMIG as a circuit and output it. The output circuit is the optimized circuit.

[0056] In order to evaluate the performance of the AXMIG structure, it is compared with AIG and AXIG; it can be implemented in C++ language, the operating system used is CentOS7.0, the CPU clock frequency is 3.11GHz, and the memory is 4GB. The PC is applied to the MCNC standard circuit for testing. To ensure the consistency of experimental parameters, the ABC tool is used to convert the input circuit into an AIG network before implementing the other two structures to ensure that the starting point of all structures (AIG, AXIG, AXMIG) is the same. The experimental results are shown in Table 1. In order to simulate the signal changes in the actual circuit, the signal probability is randomly generated, and these probabilities are assigned to the circuits represented by the three structures respectively, so that the input signal probability is consistent in all structures. The area of ​​the circuit represented by each structure is calculated, and the area optimization value of the AXMIG structure relative to the AIG and AXIG structures is compared.

[0057] Table 1 lists the circuit names and the corresponding input / output numbers, the areas of the AIG, AXIG and AXMIG structures, and the optimized values ​​of the areas of AXMIG compared with the AIG and AXIG structures respectively. The last row is the average improvement of the area of ​​AXMIG compared with the AIG and AXIG structures.

[0058] Table 1 Area comparison of three structures

[0059]

[0060] The statistical results show that the average area of ​​AXMIG is reduced by 24.93% and 19.75% respectively compared with AIG and AXIG. It can be seen from Table 1 that AXMIG is significantly better than AIG and AXIG in terms of area improvement, with an average improvement of more than 20%. The average area improvement of AXMIG is more than 15% compared with AXIG, which is due to the introduction of XOR gates and majority logic gate structures, proving that the circuit using the method proposed by the present invention can achieve a more favorable improvement in the area performance of the circuit.

[0061] From the analysis of the data in Table 1, it can be seen that the area of ​​most circuits is significantly reduced, among which the circuit area of ​​C5315 is significantly reduced, and the average reduction percentage increases. It can be seen that the method of the present invention has advantages in circuit area optimization and can effectively optimize the circuit area.

[0062] In integrated circuit design, area optimization is crucial. The technical solution of the present invention can significantly reduce the circuit area by reducing the number of logic gates and simplifying the logic netlist, thereby reducing costs, improving production efficiency and reliability. It is suitable for high-performance, low-energy integrated circuit design, especially in arithmetic circuits such as communication circuits and parity check circuits, and can significantly improve the area, speed and power consumption performance of the circuit. By introducing two-input nodes (exclusive OR gate XOR) and three-input nodes (majority logic gate MAJ), the present invention can expand the functions of EDA tools and make them more efficient in processing complex logic circuits. The present invention can be integrated into existing EDA tools, such as MIS, ABC, etc., to improve the performance of these tools in integrated circuit area optimization, bringing new ideas and technical means to the field of integrated circuit design.

[0063] The above embodiments are only preferred embodiments of the present invention and cannot be considered to limit the scope of the present invention. All equivalent changes and improvements made within the scope of the present invention should still fall within the scope of the present invention.

Claims

1. A circuit area optimization method based on XOR majority graph, characterized in that The following steps are involved: 1) Convert the digital logic circuit to be processed into a logic netlist structure, that is, use a directed acyclic graph data structure to display and convert the integrated circuit into an AIG logic representation; 2) Define the XOR structure and majority logic structure in the AIG logic representation. Specifically, a majority logic gate MAJ is proposed as a node. The logic function expression of the majority gate is , or expressed as ; Therefore, it is possible to use Boolean functions simultaneously as well as A method for Boolean logic optimization is proposed for logic algebra, which seeks a structural representation that satisfies these two Boolean functions in the AIG structure, and uses XOR gates and majority logic gates as mapping substitutes; 3) Cut the AIG graph generated by the integrated circuit into independent AIG substructures, and set appropriate cutting conditions to ensure that all sub-AIG networks meet the constraints; 4) Replace the AIG logic netlist after cutting, search for the AIG structure suitable for conversion into sub-XOR gate nodes and MAJ gate nodes, and perform corresponding replacement operations. For the sub-AIG structure with more than 3 input variables, partially search and replace the two-input XOR gate or three-input majority logic gate that meets the conditions; 5) Map the converted AXMIG netlist into a circuit and output it. The output circuit is the area-optimized circuit.

2. A circuit area optimization method based on XOR majority graph as claimed in claim 1, characterized in that In step 2), the specific steps of defining the XOR structure and the majority logic structure in the AIG logic representation are: 2-1) Consider the case of negation of input variables: For an XOR gate whose input and output are both original variables, if there is a negation variable in the input variable, the input variable is the negation variable of one variable, and the two variables are negated variables. Four transformation forms are obtained, and Then eight transformation forms will be obtained. At the same time, the XOR gate corresponds to the AIG structure inside the XOR gate, which corresponds to the input variable of the leaf node of the directed acyclic graph taking the inverse variable; 2-2) Consider the order of input variables: In the case of different order of input variables, The input variables of The input variable gets six different situations; and finally when the output variable is negated, The output variables and The output variable produces two different transformation forms; 2-3) Consider the inversion of the output variable: Under various input and output conditions, the two-input Boolean logic function The corresponding AIG graph structure produces a total of 16 different transformations, and a three-input Boolean logic function The corresponding AIG graph structure produces a total of 96 different transformations.

3. A circuit area optimization method based on XOR majority graph as claimed in claim 1, characterized in that In step 3), the specific steps of cutting the AIG graph generated by the integrated circuit are: 3-1) Consider the AIG graph as a tree structure, where the top node is the root node, and the input nodes of a node are the left and right child nodes. Starting from the root node, the AIG Boolean logic structure is cut into independent AIG substructures; these substructures are independent of each other and will not contain each other; 3-2) Reduce the size of the sub-network obtained by cutting during cutting, set the maximum number of input variables of the sub-AIG obtained by cutting appropriately during the cutting process, and all cutting is feasible cutting; when an AIG netlist is cut from top to bottom, all sub-AIG networks meet the constraints, and the cutting of the entire AIG is completed.

4. A circuit area optimization method based on XOR majority graph as claimed in claim 1, characterized in that In step 4), the specific steps of replacing the cut AIG logic netlist are: 4-1) Identification and processing of invalid cutting: After completing the cutting of AIG, the obtained sub-AIG network is regarded as a potential sub-AXMIG candidate; invalid cutting is identified and excluded, that is, those sub-AIG networks whose internal nodes are connected not only to the inside of the cutting but also to the external nodes; invalid cutting is not further processed; 4-2) Convert according to the number of inputs, including: 4-2-1) Replacement of two-input and three-input sub-AIG: For a sub-AIG network with 2 inputs, search its internal structure to determine whether it is consistent with the internal structure of the AIG corresponding to the two-input XOR gate node; if consistent, use the XOR gate node to replace the sub-AIG network; For the sub-AIG network with 3 inputs, search its internal structure to determine whether it is consistent with the internal structure of the AIG corresponding to the three-input MAJ gate node; if consistent, use the MAJ gate node to replace the sub-AIG network; 4-2-2) Partial search and replacement of multiple input sub-AIGs: For sub-AIG networks with more than 3 input variables, a partial search is performed to identify whether there is a sub-structure that satisfies the AIG structure corresponding to the two-input XOR gate or the three-input MAJ gate; if a sub-structure that meets the conditions is found, the corresponding gate is replaced, and the remaining AND gates are not processed; if a sub-structure that meets the conditions is not found in the entire sub-AIG network, the search for the sub-AIG is exited and no replacement is performed.

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