Pixel circuit sharing storage capacitor and writing method

Abstract

The invention discloses a pixel circuit sharing a storage capacitor and a writing method, the pixel circuit comprises a first sub-pixel circuit and a second sub-pixel circuit, and the first sub-pixel circuit and the second sub-pixel circuit have the same circuit structure; each of the first sub-pixel circuit and the second sub-pixel circuit comprises a storage capacitor, and one end of the storage capacitor is coupled with a second source drain electrode of a second transistor of the first sub-pixel circuit; the other end of the storage capacitor is coupled to the second sub-pixel circuit; the first sub-pixel circuit and the second sub-pixel circuit share the storage capacitor. The array substrate has the advantages that the two ends of one storage capacitor are coupled to the two vertically adjacent sub-pixel circuits respectively, normal writing and displaying of the multiple sub-pixel circuits are completed, and therefore the use number of the storage capacitors is reduced, and the aperture opening ratio is increased.

Description

Technical Field

[0001] The present invention relates to the field of pixel display technology, and in particular to a pixel circuit and a writing method for a shared storage capacitor. Background Art

[0002] Field sequential or color sequential display driving technology directly utilizes the RGB three-color light source to mix colors through the residual effect of human visual pause to achieve full-color display effect. No color filter is required, which improves the utilization rate of the light source on the one hand and reduces the power consumption of the light source on the other hand. The backlight can be turned on only after all the screen data is written and the liquid crystal is deflected to a stable state, otherwise there will be a chaotic picture, so a lot of time needs to be reserved for the liquid crystal to deflect before the backlight is turned on. This makes it difficult to achieve high brightness and high frequency display within the average time, and at the same time, the requirements for backlight brightness specifications and life are increased, which increases the cost.

[0003] While achieving high refresh rate and high brightness, it is also necessary to ensure the aperture ratio of the pixel circuit; therefore, the present invention proposes a pixel circuit and a writing method with a shared storage capacitor to improve the aperture ratio of the pixel circuit. Summary of the invention

[0004] The purpose of the present invention is to provide a pixel circuit and a writing method for a shared storage capacitor, thereby improving the aperture ratio of the pixel circuit.

[0005] The purpose of the present invention is to achieve a pixel circuit with a shared storage capacitor through the following technical scheme, including a first sub-pixel circuit and a second sub-pixel circuit, wherein the circuit structures of the first sub-pixel circuit and the second sub-pixel circuit are the same; the first sub-pixel circuit and the second sub-pixel circuit share a storage capacitor.

[0006] Further, the first sub-pixel circuit includes a first transistor of the first sub-pixel circuit, a pre-storage capacitor, a second transistor, a storage capacitor and a pixel electrode; a first source and drain of the first transistor of the first sub-pixel circuit is coupled to the data signal line, a gate of the first transistor of the first sub-pixel circuit is coupled to the first row gate signal line, a second source and drain of the first transistor of the first sub-pixel circuit is coupled to one end of the pre-storage capacitor; and the other end of the pre-storage capacitor is coupled to the first common signal line; The first source and drain of the second transistor of the first sub-pixel circuit are coupled to the second source and drain of the first transistor of the first sub-pixel circuit, the gate of the second transistor of the first sub-pixel circuit is coupled to the first transfer signal line, the second source and drain of the second transistor of the first sub-pixel circuit is coupled to one end of the pixel electrode; the other end of the pixel electrode is coupled to the first common signal line; one end of the storage capacitor is coupled to the second source and drain of the second transistor of the first sub-pixel circuit; the other end of the storage capacitor is coupled to the second sub-pixel circuit.

[0007] Further, the second sub-pixel circuit includes a first transistor of the second sub-pixel circuit, a second pre-storage capacitor, a second transistor, a storage capacitor, and a second pixel electrode; a first source and drain of the first transistor of the second sub-pixel circuit is coupled to the data signal line, a gate of the first transistor of the second sub-pixel circuit is coupled to the second row gate signal line, a second source and drain of the first transistor of the second sub-pixel circuit is coupled to one end of the second pre-storage capacitor; and the other end of the second pre-storage capacitor is coupled to the second common signal line; The first source and drain of the second transistor of the second sub-pixel circuit are coupled to the second source and drain of the first transistor of the second sub-pixel circuit, the gate of the second transistor of the second sub-pixel circuit is coupled to the second transfer signal line, the second source and drain of the second transistor of the second sub-pixel circuit is coupled to one end of the second pixel electrode; the other end of the second pixel electrode is coupled to the first common signal line; one end of the storage capacitor is coupled to the second source and drain of the second transistor of the second sub-pixel circuit; the other end of the storage capacitor is coupled to the first sub-pixel circuit.

[0008] Furthermore, the pixel circuit further includes a third sub-pixel circuit, and the third sub-pixel circuit includes a third transistor and a third pixel electrode; The gate of the third transistor is coupled to the placement signal line; the first source and drain of the third transistor are coupled to the third common signal line; the second source and drain of the third transistor are coupled to one end of the storage capacitor, and the second source and drain of the third transistor are also coupled to one end of the third pixel electrode; the other end of the third pixel electrode is coupled to the third common signal line.

[0009] Furthermore, the first common signal line and the second common signal line are the same common signal line; the first transfer signal line and the second transfer signal line are the same signal line.

[0010] Furthermore, the first sub-pixel circuit also includes a fourth transistor, the first source and drain of the fourth transistor are coupled to the second source and drain of the second transistor, the second source and drain of the fourth transistor are coupled to the first common signal line, and the gate of the fourth transistor is coupled to the reset signal line.

[0011] The second sub-pixel circuit also includes a fourth transistor of the second sub-pixel circuit, the first source and drain of the fourth transistor of the second sub-pixel circuit are coupled to the second source and drain of the second transistor of the second sub-pixel circuit, the second source and drain of the fourth transistor of the second sub-pixel circuit are coupled to the second common signal line, and the gate of the fourth transistor of the second sub-pixel circuit is coupled to the second reset signal line.

[0012] Furthermore, the reset signal line and the second reset signal line are the same signal line.

[0013] The present invention also provides a pixel circuit writing method for a shared storage capacitor, comprising: Acquire the pixel voltage of the target pixel circuit at the nth frame; Based on the pixel voltage, the data signal voltage required when the potential of the pixel electrode is changed to the pixel voltage during the charge transfer process is calculated according to the charge conservation principle; The calculated data signal voltage is written into the pre-storage capacitor.

[0014] Further, when the pixel circuit includes a first sub-pixel circuit and a second sub-pixel circuit, the writing method includes: Acquire a first pixel voltage of a first sub-pixel circuit and a second pixel voltage of a second sub-pixel circuit in an n-th frame; Based on the first pixel voltage and the second pixel voltage, calculating, according to the charge conservation principle, a first data signal voltage required when the potential of the pixel electrode is changed to the pixel voltage during the charge transfer process; Based on the first pixel voltage and the second pixel voltage, calculating, according to the charge conservation principle, a second data signal voltage required when the potential of the second pixel electrode is changed to the pixel voltage during the charge transfer process; The calculated first data signal voltage is written into the pre-storage capacitor, and the second data signal voltage is written into the second pre-storage capacitor.

[0015] Further, the method for calculating the first data signal voltage includes: generating a first amount of transferred charge based on the first pixel voltage, the second pixel voltage, the pixel electrode, and the storage capacitor; Based on the first transferred charge amount, the first pixel voltage and the pre-storage capacitor, calculating the potential of the pre-storage electrode required before the charge transfer stage, the potential being the first data signal voltage; Further, the method for calculating the second data signal voltage includes: generating a second amount of transferred charge based on the first pixel voltage, the second pixel voltage, the second pixel electrode, and the storage capacitor; Based on the second transferred charge amount, the second pixel voltage and the second pre-storage capacitor, the potential of the second pre-storage electrode required before the charge transfer stage is calculated, and the potential is the second data signal voltage.

[0016] Further, when the pixel voltage of the n-1th frame exists in the storage capacitor, the method for calculating the data signal voltage includes: Acquire the pixel voltage of the target pixel circuit at the nth frame; Generate a transfer charge amount based on a pixel voltage of the nth frame, a pixel voltage of the (n-1th) frame, a pixel electrode, and a storage capacitor; Based on the transferred charge amount, the pixel voltage of the nth frame, the pixel voltage of the (n-1)th frame and the pre-storage capacitor, the potential of the pre-storage electrode required before the charge transfer is calculated, and the potential is the data signal voltage.

[0017] Furthermore, the writing method further includes: Acquiring a third pixel voltage of a third sub-pixel circuit; Based on the first pixel voltage and the third pixel voltage, calculating a first transferred charge amount of the potential of the pixel electrode during the charge transfer process according to the charge conservation principle; Based on the second pixel voltage and the third pixel voltage, calculating the second transferred charge amount of the potentials of the second pixel electrode and the third pixel electrode during the charge transfer process according to the charge conservation principle; The first data signal voltage and the second data signal voltage are calculated according to the charge conservation principle based on the first pixel voltage, the second pixel voltage, the third pixel voltage, the first transferred charge amount, the second transferred charge amount, the pre-storage capacitor and the second pre-storage capacitor.

[0018] The present invention has the following advantages: The present invention couples the two ends of a storage capacitor to a plurality of sub-pixel circuits respectively, and the data signal line inputs different data signal voltages to the first sub-pixel circuit and the second sub-pixel circuit respectively according to the calculation results in the nth frame, thereby completing the normal writing and display of the plurality of pixel circuits by inputting different data signal voltages; thereby reducing the number of storage capacitors used and improving the aperture ratio.

[0019] The present invention also includes a third sub-pixel circuit, wherein the third sub-pixel circuit and the first sub-pixel circuit share a storage capacitor, and the third sub-pixel circuit and the second sub-pixel circuit share a second storage capacitor; firstly, the pixel voltage required by each sub-pixel circuit is obtained, and the potentials of the pixel electrode, the second pixel electrode and the third pixel electrode are respectively calculated according to the first pixel voltage, the second pixel voltage and the third voltage to reach the first transferred charge amount and the second transferred charge amount; according to the charge conservation principle, the equation of charge conservation of the third pixel point is obtained, and the first data signal voltage input into the pre-storage capacitor and the second data signal voltage input into the second pre-storage capacitor are calculated thereby; the input first data signal voltage and the second data signal voltage satisfy that in the reset stage, when the third transistor is turned off, the charge amount transferred to the third pixel electrode by the storage capacitor, the second storage capacitor, the pixel electrode, the second pixel electrode and the third pixel electrode due to the charge conservation principle can reach the third pixel voltage, thereby completing the writing of the third pixel voltage; Simply put, the writing of three pixel voltages can be achieved through two sub-pixel circuits. It can be understood that the writing of three pixel voltages, which originally required three complete sub-pixel circuits to complete, can now be completed through two complete sub-pixel circuits, plus a transistor and a capacitor. This reduces the use of multiple transistors and capacitors, reduces costs and improves the aperture ratio of the pixel circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 is a circuit diagram of Embodiment 1 of the present invention; Figure 2 is a timing diagram of the first embodiment of the present invention; Figure 3 is a circuit diagram of Embodiment 2 of the present invention; Figure 4 is a timing diagram of the second embodiment of the present invention; Figure 5 is a circuit diagram of Embodiment 3 of the present invention; Figure 6 This is a timing diagram of the third embodiment of the present invention. DETAILED DESCRIPTION

[0021] The present invention is further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0022] It should be noted that the directions or positional relationships indicated by "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is usually placed when in use, or are the directions or positional relationships commonly understood by those skilled in the art. Such terms are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0023] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features and technical solutions in the embodiments may be combined with each other. Example

[0024] See also Figure 1 The first embodiment of the present invention provides a pixel circuit with a shared storage capacitor, including a first sub-pixel circuit and a second sub-pixel circuit, wherein the first sub-pixel circuit and the second sub-pixel circuit have the same circuit structure; the first sub-pixel circuit and the second sub-pixel circuit share a storage capacitor Cs2.

[0025] In the first embodiment, the first sub-pixel circuit includes a first transistor T1, a pre-storage capacitor Cs1, a second transistor T2, a storage capacitor Cs2 and a pixel electrode Clc; a first source and a drain of the first transistor T1 of the first sub-pixel circuit are coupled to a data signal line Data, a gate of the first transistor T1 of the first sub-pixel circuit is coupled to a first row gate signal line Scan1, a second source and a drain of the first transistor T1 of the first sub-pixel circuit is coupled to one end of the pre-storage capacitor Cs1; the other end of the first pre-storage capacitor Cs1-1 is coupled to a first common signal line Com1; The first source and drain of the second transistor T2 of the first sub-pixel circuit are coupled to the second source and drain of the first transistor T1 of the first sub-pixel circuit, the gate of the second transistor T2 of the first sub-pixel circuit is coupled to the first transfer signal line Tran1, the second source and drain of the second transistor T2 is coupled to one end of the pixel electrode Clc; the other end of the pixel electrode Clc is coupled to the common signal line Com; one end of the storage capacitor Cs2 is coupled to the second source and drain of the second transistor T2, and the other end of the storage capacitor Cs2 is coupled to the second sub-pixel circuit; the first sub-pixel circuit and the second sub-pixel circuit share the same storage capacitor Cs2.

[0026] In this embodiment, the second sub-pixel circuit includes a first transistor T1' of the second sub-pixel circuit, a second pre-storage capacitor Cs1', a second transistor T2', a storage capacitor Cs2, and a second pixel electrode Clc'; a first source and drain of the first transistor T1' of the second sub-pixel circuit is coupled to the data signal line Data, a gate of the first transistor T1' of the second sub-pixel circuit is coupled to the second row gate signal line Scan2, a second source and drain of the first transistor T1' of the second sub-pixel circuit is coupled to one end of the second pre-storage capacitor Cs1'; and the other end of the second pre-storage capacitor Cs1' is coupled to the second common signal line Com2; The first source and drain of the second transistor T2' of the second sub-pixel circuit are coupled to the second source and drain of the first transistor T1' of the second sub-pixel circuit, the gate of the second transistor T2' of the second sub-pixel circuit is coupled to the second transfer signal line Tran2, the second source and drain of the second transistor T2' of the second sub-pixel circuit is coupled to one end of the second pixel electrode Clc'; the other end of the second pixel electrode Clc' is coupled to the first common signal line Com2; one end of the storage capacitor Cs2 is coupled to the second source and drain of the second transistor T2' of the second sub-pixel circuit; the other end of the storage capacitor Cs2 is coupled to the first sub-pixel circuit.

[0027] At work, if Figure 2 As shown, the timing diagram of the pixel circuit is configured as: Backlight on stage: The first row gate signal line Scan1 jumps to a high level, the first transistor T1 is turned on, so that the data signal line Data writes the first data signal voltage of the first sub-pixel circuit of the nth frame into the pre-storage capacitor Cs1; After writing is completed, the row gate signal line Scan1 jumps to a normal level; the normal level is the common signal level Vcom, and the common signal level Vcom will not turn the transistor on or off; The second row gate signal line Scan2 jumps to a high level, and the data signal line Data writes the second data signal voltage of the second sub-pixel circuit into the second pre-storage capacitor Cs1'; After writing is completed, the second row gate signal line Scan2 and the data signal line Data both jump to normal level; Backlight off stage: The first transfer signal line Tran1 jumps to a high level, the second transistor T2 is turned on, and the first data signal voltage Vd1n in the pre-storage capacitor Cs1 is transferred to the storage capacitor Cs2 and the pixel electrode Clc through the second transistor T2; The second transfer signal line Tran2 jumps to a high level, the second transistor T2' is turned on, and the second data signal voltage in the second pre-storage capacitor Cs1' is transferred to the second storage capacitor Cs2' and the pixel electrode Clc' through the second transistor T2'; The first data voltage and the second data voltage transfer charges to the storage capacitor Cs2, the pixel electrode Clc and the second pixel electrode, so that the potential of the pixel electrode Clc reaches the first pixel voltage and the potential of the second pixel electrode Clc' reaches the second pixel voltage according to the charge conservation principle; After the transfer is completed, the first transfer signal line Tran1 and the second transfer signal line Tran2 jump to a normal level.

[0028] In this embodiment, the first common signal line Com1 and the second common signal line Com2 can be the same signal line or prepared separately as two signal lines; the first transfer signal line Tran1 and the second transfer signal line Tran2 can be the same signal line or prepared separately as two signal lines.

[0029] In this embodiment, the first sub-pixel circuit and the second sub-pixel circuit share the storage capacitor Cs2, and the charge conservation principle is used to correctly write two pixel voltages according to different data signal voltage inputs under different pixel voltage requirements.

[0030] This embodiment adopts a pixel circuit writing method of a shared storage capacitor when the pixel voltage of the n-1th frame exists in the storage capacitor Cs2. In this embodiment, the capacitance values ​​of the pre-storage capacitor Cs1 and the second pre-storage capacitor Cs1' are equal, and the capacitance values ​​of the pixel electrode Clc and the second pixel electrode Clc' are equal; Based on the charge sharing, the equations at the first pixel electrode and the second pixel electrode are obtained respectively, and the equations are as follows: (V1dn-V1n)*C1=(V1n-V2n-V1n-1+V2n-1)*C2+(V1n-V1n-1)*C; (V2dn-V2n)*C1=(V2n-V1n-V2n-1+V1n-1)*C2+(V2n-V2n-1)*C; Where: V1n: the first pixel voltage of the nth frame; V2n: the second pixel voltage of the nth frame; V1n-1: the first pixel voltage of the n-1th frame; V2n-1: the second pixel voltage of the n-1th frame; Vd1n: the first pixel voltage of the nth frame corresponds to the first data signal voltage; Vd2n: the second pixel voltage of the nth frame corresponds to the second data signal voltage; C1: capacitance value of the pre-storage capacitor Cs1 / the second pre-storage capacitor Cs1'; C2: Capacitance of storage capacitor Cs2; C: capacitance value of pixel electrode Clc / second pixel electrode Clc'; Referring to the right side of the first equation above, a first transfer charge amount required when the potential of the pixel electrode Clc changes to the first pixel voltage during the charge transfer process is obtained based on the first pixel voltage, the second pixel voltage, the storage capacitor Cs2 and the pixel electrode Clc; Combined with the left side of the first equation, based on the first transferred charge amount, the first pixel voltage and the pre-storage capacitor Cs1, the first data signal voltage can be calculated. The expression of the first data signal voltage corresponding to the first pixel of the nth frame is: Vd1n=V1n*(C+ C1+ C2) / C1-C2*V2n / C1-V1n-1*(C+C2) / C1+C2*V2n-1 / C1.

[0031] Referring to the right side of the second equation, based on the first pixel voltage, the second pixel voltage, the storage capacitor Cs2 and the second pixel electrode Clc', the second transfer charge amount required when the potential of the second pixel electrode Clc' changes to the second pixel voltage during the charge transfer process is obtained; According to the left side of the second equation, based on the second transferred charge amount, the first pixel voltage, the second pixel voltage and the second pre-storage capacitor Cs1', the second data signal voltage can be calculated. The expression of the data signal voltage corresponding to the second pixel of the nth frame is: Vd2n=V2n*(C+ C1+ C2) / C1-C2*V1n / C1-V2n-1*(C+C2) / C1+C2*V2n-1 / C1.

[0032] Therefore, the present invention couples the two ends of a storage capacitor Cs2 to two upper and lower adjacent sub-pixel circuits respectively, and at the same time, the data signal line Data inputs different data signal voltages to the two sub-pixel circuits according to the calculation results in the nth frame, thereby completing the normal writing and display of the two sub-pixel circuits; thereby achieving the two sub-pixel circuits sharing one storage capacitor, reducing the number of storage capacitors used and thereby improving the aperture ratio. Example

[0033] like Figure 3 As shown, in the second embodiment, the first sub-pixel circuit also includes a fourth transistor T4, the gate of the fourth transistor T4 is coupled to the reset signal line Reset1, the first source and drain of the fourth transistor T4 are coupled to the first common signal line Com1, and the first source and drain of the fourth transistor T4 are coupled to the second source and drain of the fourth transistor T4.

[0034] The second sub-pixel circuit also includes a fourth transistor T4' of the second sub-pixel circuit, a first source and drain of the fourth transistor T4' of the second sub-pixel circuit is coupled to the second source and drain of the second transistor T2' of the second sub-pixel circuit, a second source and drain of the fourth transistor T4' of the second sub-pixel circuit is coupled to the second common signal line Com2, and a gate of the fourth transistor T4' of the second sub-pixel circuit is coupled to the second reset signal line Reset2.

[0035] Furthermore, in some specific embodiments, the reset signal line Reset1 and the second reset signal line Reset2 are the same signal line; the first common signal line Com1, the second common signal line Com2 and the third common signal line Com3 are the same common signal line.

[0036] When working in the second embodiment, Figure 4 As shown, the timing diagram of the pixel circuit is configured as follows during the backlight off phase: Backlight off stage: The reset signal line Reset1 of the first sub-pixel circuit jumps to a high level, and the fourth transistor T4 of the first sub-pixel circuit is turned on; the reset signal line Reset1 completes the resetting of the storage capacitor Cs2 and the pixel electrode Clc through the fourth transistor T4; After the reset is completed, the reset signal line Reset1 jumps to a normal level, and at the same time, the level of the first transfer signal line Tran1 jumps to a high level; That is, the fourth transistor T4 is turned off, the second transistor T2 is turned on, and the first data signal voltage of the pre-storage capacitor Cs1 is transferred to the pixel electrode Clc and the storage capacitor Cs2 through the second transistor T2, so that the potential of the pixel electrode Clc is the first pixel voltage; Meanwhile, the second sub-pixel circuit performs the same process as the first sub-pixel circuit in the backlight off stage, and completes the resetting of the second pixel electrode Clc'. After the resetting is completed, the voltage of the second pixel electrode Clc' is the second pixel voltage.

[0037] In this embodiment, because there is a fourth transistor T4 in the first sub-pixel circuit, the storage capacitor Cs2 and the pixel electrode Clc can be reset; similarly, there is a fourth transistor T4' in the second sub-pixel circuit that can reset the storage capacitor Cs2 and the second pixel electrode Clc', so the first sub-pixel circuit and the second sub-pixel circuit are not affected by the signal voltage of the previous frame. Therefore, in the backlight-on stage, when writing the data signal voltage, the equations at the first pixel electrode and the second pixel electrode in the nth frame are derived according to the conservation principle of charge sharing, and the equations are as follows: (V1dn-V1n)*C1=(V1n-V2n)*C2+V1n*C; (V2dn-V2n)*C1=(V2n-V1n)*C2+V2n*C; Referring to the derivation process of the first embodiment and the above equation, the expression of the first data signal voltage in the nth frame is obtained as follows: Vd1n=(C*V1n + C1*V1n + C2*V1n - C2*V2n - C*Vc) / C1; Referring to the second equation above, the second data signal voltage can be calculated as follows: Vd2n=(C*V2n - C2*V1n + C1*V2n + C2*V2n - C*Vc) / C1; In this embodiment, although a fourth transistor T4 is added to the first sub-pixel circuit or a fourth transistor T4' is added to the second sub-pixel circuit, the calculation of the first pixel voltage corresponding to the data signal voltage and the second pixel voltage corresponding to the second data signal voltage is simplified.

[0038] Example See also Figure 5 In the third embodiment, the pixel circuit further includes a third sub-pixel circuit, and the third sub-pixel circuit includes a third transistor T3 and a third pixel electrode Clc'; the capacitance value of the third pixel electrode Clc' is the same as the capacitance value of the pixel electrode Clc or the second pixel electrode Clc'; The gate of the third transistor T3 is coupled to the placement signal line Set; the first source and drain of the third transistor T3 are coupled to the third common signal line Com3; the second source and drain of the third transistor T3 are coupled to one end of the storage capacitor Cs2, and the second source and drain of the third transistor T3 is also coupled to one end of the third pixel electrode Clc”; the other end of the third pixel electrode Clc” is coupled to the third common signal line Com3; In this embodiment, the first pixel voltage and the second pixel voltage are both driven by respective complete corresponding sub-pixel circuits, and the third pixel voltage is obtained by coupling the first pixel voltage and the second pixel voltage through the storage capacitor Cs2 and the second storage capacitor Cs2'.

[0039] In the backlight-on phase, the first data signal voltage and the second data signal voltage are respectively written into the pre-storage capacitor Cs1 of the first sub-pixel circuit and the second pre-storage capacitor Cs1' of the second sub-pixel circuit through the data signal line Data; In the transition of the backlight off phase, the set signal line Set jumps to a high level, the third transistor T3 is turned on, so that the third pixel point at the third pixel electrode Clc" is reset; After the reset is completed, the set signal line Set jumps to a normal level, and the first transfer signal line Tran1 jumps to a high level. At this time, the third transistor T3 is turned off, the second transistor T2 is turned on, and the charge in the pre-storage capacitor Cs1 in the first sub-pixel circuit is transferred to the pixel electrode Clc and the storage capacitor Cs2. The equation for charge transfer is as follows: (V1dn-V1n)*C1=(V1n-V3n-V1n-1+Vc)*C2+(V1n-V1dn)*C; At the same time, the second transfer signal line Tran2 jumps to a high level, and the second pre-storage capacitor Cs1' in the second sub-pixel circuit of the second transistor T2' also starts to transfer charges to the second pixel electrode Clc' and the second storage capacitor Cs2'. The equation for charge transfer is as follows: (V2dn-V2n)*C1=(V2n-V3n-V2n-1+Vc)*C3+(V2n-V2n-1)*C; After the transfer is completed, the first transfer signal line Tran1 and the second transfer signal line Tran2 both jump to the normal level. According to the charge conservation principle, the equation at the third pixel point can be obtained: (Vm-V1n-1)*C2+(Vc-V2n-1)*C2=(V3n-V1n)*C2+(V3n-V2n)*C2+(V3n-Vc)*C; Where: V3n: the third pixel voltage of the nth frame; V3n-1: the third pixel voltage of the n-1th frame.

[0040] According to the above three equations, the first data signal voltage corresponding to the first sub-pixel circuit of the nth frame can be obtained: V1dn=(C*V1n + C1*V1n + C2*V1n - C2*V3n + C2*Vc - C*V1n-1 - C2*V1n-1) / C1; The second sub-pixel circuit of the nth frame corresponds to the second data signal voltage: V2dn=(C*V2n - C2*V3n + C1*V2n + C2*V2n + C2*Vc - C*V2n-1 - C2*V2n-1) / C1; In this embodiment, it is equivalent to completing the driving of three pixel electrodes through two pixel circuits, and the third sub-pixel circuit is formed by the third transistor T3 and the third pixel capacitor Clc'; at this time, the first sub-pixel circuit and the third sub-pixel circuit share the storage capacitor Cs2, and the second sub-pixel circuit and the third sub-pixel circuit share the second storage capacitor Cs2'; the first sub-pixel circuit and the second sub-pixel circuit implement the writing of the three pixel voltages, which can be understood as the three pixel voltages that originally required three pixel circuits to complete can now be completed by only two pixel circuits; In this embodiment, the pixel voltage required by each sub-pixel circuit is first obtained, and the potentials of the pixel electrode Clc, the second pixel electrode Clc' and the third pixel electrode Clc" are respectively calculated according to the first pixel voltage, the second pixel voltage and the third voltage to reach the first transferred charge amount and the second transferred charge amount; the equation of charge conservation of the third pixel point is obtained according to the principle of charge conservation, thereby calculating the first data signal voltage input into the pre-storage capacitor Cs1 and the second data signal voltage input into the second pre-storage capacitor Cs1'; the input first data signal voltage and the second data signal voltage meet the requirement that the storage capacitor Cs2, the second stored charge Cs2', the pixel electrode Clc, the second pixel electrode Clc' and the third pixel electrode Clc" can reach the third pixel voltage requirement due to the principle of charge conservation when the third transistor T3 is turned off in the reset phase, thereby realizing the writing of the third pixel voltage; thereby reducing the use of multiple transistors and capacitors, reducing costs and improving the aperture ratio of the pixel circuit; At the same time, the third transistor T3 not only constitutes the third sub-pixel circuit, but also cooperates with the jump of the placement signal line Set to complete the resetting of the third pixel electrode Clc″.

[0041] Example The present invention also provides a fourth embodiment, which is a method for writing into a pixel circuit with a shared storage capacitor, which is applied to the first to third embodiments, including a circuit obtained by deforming the first, second and third embodiments; S1, obtaining the pixel voltage of the target pixel circuit in the nth frame; Specifically, a first pixel voltage of a first sub-pixel circuit and a second pixel voltage of a second sub-pixel circuit in an n-th frame are acquired; V1n=(C1^2*Vd1n + C^2*V1n-1 + C*C1*Vd1n + C1*C2*Vd1n + C1*C2*Vd2n + C*C1*V1n-1 + 2*C*C2*V1n-1 + C1*C2*V1n-1 - C1*C2*V2n-1) / ((C + C1)*(C + C1 + 2*C2)); V2n=(C1^2*Vd2n + C^2*V2n-1 + C*C1*Vd2n + C1*C2*Vd1n + C1*C2*Vd2n -C1*C2*V1n-1 + C*C1*V2n-1 + 2*C*C2*V2n-1 + C1*C2*V2n-1) / ((C + C1)*(C + C1 + 2*C2)); S2. Based on the pixel voltage, the data signal voltage required when the potential of the pixel electrode is changed to the pixel voltage during the charge transfer process is calculated according to the charge conservation principle; Specifically, based on the first pixel voltage and the second pixel voltage, a first data signal voltage required when the potential of the pixel electrode Clc changes to the first pixel voltage during the charge transfer process is calculated according to the charge conservation principle; The method for calculating the first data signal voltage includes: Generate a first transfer charge amount based on the first pixel voltage, the second pixel voltage, the pixel electrode Clc and the storage capacitor Cs2; Based on the first transferred charge amount, the first pixel voltage and the pre-storage capacitor Cs1, the potential of the pre-storage electrode required before the charge transfer stage is calculated, and the potential is the first data signal voltage; Vd1n=V1n*(C+ C1+ C2) / C1-C2*V2n / C1-V1n-1*(C+C2) / C1+C2*V2n-1 / C1; Based on the first pixel voltage and the second pixel voltage, calculating the second data signal voltage required when the potential of the second pixel electrode Clc' changes to the pixel voltage during the charge transfer process according to the charge conservation principle; The method for calculating the second data signal voltage includes: generating a second transfer charge amount based on the first pixel voltage, the second pixel voltage, the second pixel electrode Clc' and the storage capacitor Cs2; Based on the second transferred charge amount, the second pixel voltage and the second pre-storage capacitor Cs1', the potential of the second pre-storage electrode required before the charge transfer stage is calculated, and the potential is the second data signal voltage; Vd2n=V2n*(C+ C1+ C2) / C1-C2*V1n / C1-V2n-1*(C+C2) / C1+C2*V2n-1 / C1.

[0042] S3, writing the calculated data signal voltage into the pre-storage capacitor; Specifically, the calculated first data signal voltage is written into the pre-storage capacitor Cs1, and the second data signal voltage is written into the second pre-storage capacitor Cs1'.

[0043] Furthermore, the writing method further includes: S101, obtaining a third pixel voltage of a third sub-pixel circuit; V3n=(C^2*Vc + C1*C2*V1n + C1*C2*V3n + C*C1*Vc + 3*C*C2*Vc + 2*C1*C2*Vc - C1*C2*V1n-1 - C1*C2*V2n-1) / (C^2 + C*C1 + 3*C*C2 + 2*C1*C2); S102, based on the first pixel voltage and the third pixel voltage, calculating the potential of the pixel electrode Clc and the first transferred charge amount of the third pixel electrode Clc" during the charge transfer process according to the charge conservation principle; Based on the second pixel voltage and the third pixel voltage, calculating the second transferred charge amount of the potentials of the second pixel electrode Clc′ and the third pixel electrode Clc″ during the charge transfer process according to the charge conservation principle; S103, calculating the first data signal voltage and the second data signal voltage according to the charge conservation principle based on the first pixel voltage, the second pixel voltage, the third pixel voltage, the first transferred charge amount, the second transferred charge amount, the pre-storage capacitor Cs1 and the second storage capacitor Cs1'; V1dn=(C*V1n + C1*V1n + C2*V1n - C2*V3n + C2*Vc - C*V1n-1 - C2*V1n-1) / C1; V2dn=(C*V2n + C1*V2n + C2*V2n - C2*V3n+ C2*Vc - C*V3n-1 - C2*V3n-1) / C1.

[0044] S104 , writing the calculated first data signal voltage into the pre-storage capacitor Cs1 , and writing the second data signal voltage into the second pre-storage capacitor Cs1 ′.

[0045] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for those skilled in the art, several modifications and improvements can be made without departing from the invention, and these all belong to the protection scope of the invention.

Claims

1. A pixel circuit with a shared storage capacitor, characterized in that: comprising a first sub-pixel circuit and a second sub-pixel circuit, wherein the first sub-pixel circuit and the second sub-pixel circuit have the same circuit structure; The first sub-pixel circuit and the second sub-pixel circuit share a storage capacitor (Cs2).

2. The pixel circuit with a shared storage capacitor according to claim 1, characterized in that: The first sub-pixel circuit comprises a first transistor (T1) of the first sub-pixel circuit, a pre-storage capacitor (Cs1), a second transistor (T2), a storage capacitor (Cs2) and a pixel electrode (Clc); a first source and drain of the first transistor (T1) of the first sub-pixel circuit is coupled to a data signal line (Data), a gate of the first transistor (T1) of the first sub-pixel circuit is coupled to a first row gate signal line (Scan1), a second source and drain of the first transistor (T1) of the first sub-pixel circuit is coupled to one end of the pre-storage capacitor (Cs1); and the other end of the pre-storage capacitor (Cs1) is coupled to a first common signal line (Com1); The first source and drain of the second transistor (T2) of the first sub-pixel circuit are coupled to the second source and drain of the first transistor (T1) of the first sub-pixel circuit, the gate of the second transistor (T2) of the first sub-pixel circuit is coupled to the first transfer signal line (Tran1), the second source and drain of the second transistor (T2) of the first sub-pixel circuit is coupled to one end of the pixel electrode (Clc); the other end of the pixel electrode (Clc) is coupled to the first common signal line (Com1); one end of the storage capacitor (Cs2) is coupled to the second source and drain of the second transistor (T2); the other end of the storage capacitor (Cs2) is coupled to the second sub-pixel circuit.

3. The pixel circuit with a shared storage capacitor according to claim 2, characterized in that: The second sub-pixel circuit comprises a first transistor (T1') of the second sub-pixel circuit, a second pre-storage capacitor (Cs1'), a second transistor (T2'), a storage capacitor (Cs2) and a second pixel electrode (Clc'); a first source and drain of the first transistor (T1') of the second sub-pixel circuit is coupled to a data signal line (Data), a gate of the first transistor (T1') of the second sub-pixel circuit is coupled to a second row gate signal line (Scan2), a second source and drain of the first transistor (T1') of the second sub-pixel circuit is coupled to one end of the second pre-storage capacitor (Cs1'); and the other end of the second pre-storage capacitor (Cs1') is coupled to a second common signal line (Com2); The first source and drain of the second transistor (T2') of the second sub-pixel circuit are coupled to the second source and drain of the first transistor (T1') of the second sub-pixel circuit, the gate of the second transistor (T2') of the second sub-pixel circuit is coupled to the second transfer signal line (Tran2), the second source and drain of the second transistor (T2') of the second sub-pixel circuit is coupled to one end of the second pixel electrode (Clc'); the other end of the second pixel electrode (Clc') is coupled to the first common signal line (Com2); one end of the storage capacitor (Cs2) is coupled to the second source and drain of the second transistor (T2') of the second sub-pixel circuit; the other end of the storage capacitor (Cs2) is coupled to the first sub-pixel circuit.

4. The pixel circuit with a shared storage capacitor according to claim 3, characterized in that: The pixel circuit further includes a third sub-pixel circuit, the third sub-pixel circuit including a third transistor (T3) and a third pixel electrode (Clc"); The gate of the third transistor (T3) is coupled to the set signal line (Set); the first source and drain of the third transistor (T3) are coupled to the third common signal line (Com3); the second source and drain of the third transistor (T3) are coupled to one end of the storage capacitor (Cs2), and the second source and drain of the third transistor (T3) are also coupled to one end of the third pixel electrode (Clc"); the other end of the third pixel electrode (Clc") is coupled to the third common signal line (Com3).

5. The pixel circuit with a shared storage capacitor according to claim 4, characterized in that: The first sub-pixel circuit also includes a fourth transistor (T4), a first source and drain of the fourth transistor (T4) coupled to the second source and drain of the second transistor (T2), the second source and drain of the fourth transistor (T4) coupled to the first common signal line (Com1), and a gate of the fourth transistor (T4) coupled to a reset signal line (Reset1).

6. A method for writing into a pixel circuit with a shared storage capacitor, applied to any pixel circuit according to claim 1 to claim 5, characterized in that: include: Acquire the pixel voltage of the target pixel circuit at the nth frame; Based on the pixel voltage, the data signal voltage required when the potential of the pixel electrode is changed to the pixel voltage during the charge transfer process is calculated according to the charge conservation principle; The calculated data signal voltage is written into the pre-storage capacitor.

7. The method for writing into a pixel circuit with a shared storage capacitor according to claim 6, characterized in that: When the pixel circuit includes a first sub-pixel circuit and a second sub-pixel circuit, the writing method includes: Acquire a first pixel voltage of a first sub-pixel circuit and a second pixel voltage of a second sub-pixel circuit in an n-th frame; Based on the first pixel voltage and the second pixel voltage, calculating, according to the charge conservation principle, a first data signal voltage required when the potential of the pixel electrode (Clc) changes to the first pixel voltage during the charge transfer process; Based on the first pixel voltage and the second pixel voltage, calculating the second data signal voltage required when the potential of the second pixel electrode (Clc') is changed to the pixel voltage during the charge transfer process according to the charge conservation principle; The calculated first data signal voltage is written into the pre-storage capacitor (Cs1), and the second data signal voltage is written into the second pre-storage capacitor (Cs1').

8. The method for writing into a pixel circuit with a shared storage capacitor according to claim 7, characterized in that: The method for calculating the first data signal voltage includes: generating a first transfer charge amount based on the first pixel voltage, the second pixel voltage, the pixel electrode (Clc) and the storage capacitor (Cs2); Based on the first transferred charge amount, the first pixel voltage and the pre-storage capacitor (Cs1), calculating the potential of the pre-storage electrode required before the charge transfer stage, the potential being the first data signal voltage; The method for calculating the second data signal voltage includes: generating a second amount of transferred charge based on the first pixel voltage, the second pixel voltage, the second pixel electrode (Clc') and the storage capacitor (Cs2); Based on the second transferred charge amount, the second pixel voltage and the second pre-storage capacitor (Cs1'), the potential of the second pre-storage electrode required before the charge transfer stage is calculated, and the potential is the second data signal voltage.

9. The method for writing into a pixel circuit with a shared storage capacitor according to claim 6, characterized in that: When the pixel voltage of the n-1th frame exists in the storage capacitor (Cs2), the method for calculating the data signal voltage includes: Acquire the pixel voltage of the target pixel circuit at the nth frame; Generate a transfer charge amount based on a pixel voltage of the nth frame, a pixel voltage of the n-1th frame, a pixel electrode (Clc) and a storage capacitor (Cs2); Based on the transferred charge amount, the pixel voltage of the nth frame, the pixel voltage of the n-1th frame and the pre-storage capacitor (Cs1), the potential of the pre-storage electrode required before charge transfer is calculated, and the potential is the data signal voltage.

10. The method for writing into a pixel circuit with a shared storage capacitor according to claim 6, characterized in that: The writing method further comprises: Acquiring a third pixel voltage of a third sub-pixel circuit; Based on the first pixel voltage and the third pixel voltage, calculating the potential of the pixel electrode (Clc) and the first transferred charge amount of the third pixel electrode (Clc") during the charge transfer process according to the charge conservation principle; Based on the second pixel voltage and the third pixel voltage, calculating the second transferred charge amount of the potentials of the second pixel electrode (Clc') and the third pixel electrode (Clc") during the charge transfer process according to the charge conservation principle; Based on the first pixel voltage, the second pixel voltage, the third pixel voltage, the first transferred charge amount, the second transferred charge amount, the pre-storage capacitor (Cs1) and the second pre-storage capacitor (Cs1'), the first data signal voltage and the second data signal voltage are calculated according to the charge conservation principle.

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