Electronic circuit, memory device and method for compensating for data distortion caused by channel loss

Abstract

The invention provides an electronic circuit, a memory device and a method for compensating for data distortion caused by channel loss. The electronic circuit comprises a data input end, a time sequence adjusting circuit, a first logic circuit, a second logic circuit, a multiplexer and a data output end. The timing adjustment circuit receives data from the data input end. The timing adjustment circuit includes two paths for applying a first delay and a second delay to generate first and second delay data. The first logic circuit and the second logic circuit respectively receive the first delay data and the second delay data to generate first logic output signals and second logic output signals. The first logic output signal expands a pulse width corresponding to a first logic value, the second logic output signal expands a pulse width corresponding to a second logic value, and the multiplexer is used for selecting at least one of the first logic output signal and the second logic output signal according to the equalization feedback signal so as to provide a multiplexed output signal. The data output end outputs balanced data according to the multiplexed output signal.

Description

Technical Field

[0001] The present disclosure relates to memory and data storage technology, and more particularly to an electronic circuit, a memory device, and a method for compensating for data distortion caused by channel loss. Background Art

[0002] Integrated circuit memories are widely used in electronic products to store and transmit data. In recent years, the market demand for memory devices with high storage capacity and high-speed data transmission has been increasing. Summary of the invention

[0003] The present disclosure provides technology related to decision feedback equalization (DFE) in semiconductor devices. The present disclosure allows pulse width tuning (Tuning) at the complementary metal-oxide-semiconductor (CMOS) level to optimize the data valid window.

[0004] The present disclosure relates to an electronic circuit, comprising a data input terminal, a timing adjustment circuit, a first logic circuit, a second logic circuit, a multiplexer and a data output terminal. The data input terminal is used to receive data. The timing adjustment circuit is used to receive data from the data input terminal, wherein the timing adjustment circuit comprises a first path and a second path. The first path is used to apply a first delay to the data to generate first delayed data, and the second path is used to apply a second delay to the data to generate second delayed data, and the first delay is different from the second delay. The first logic circuit is used to receive the first delayed data and the second delayed data, and to generate a first logic output signal, wherein the first logic output signal extends the pulse width corresponding to the first logic value in the data. The second logic circuit is used to receive the first delayed data and the second delayed data, and to generate a second logic output signal, wherein the second logic output signal extends the pulse width corresponding to the second logic value in the data. The multiplexer is used to select at least one of the first logic output signal or the second logic output signal according to the balanced feedback signal to provide a multiplexed output signal. The data output terminal is used to output balanced data according to the multiplexed output signal.

[0005] In some embodiments, the first logic circuit includes an OR gate, and the first logic value includes a logic level 1, wherein the second logic circuit includes an AND gate, and the second logic value includes a logic level 0.

[0006] In some embodiments, the first path includes a first group of one or more inverters, and the second path includes a second group of one or more inverters.

[0007] In some embodiments, the number of inverters in the first group of inverters is different from the number of inverters in the second group of inverters.

[0008] In some embodiments, the first path further includes a first group of one or more capacitors, the second path further includes a second group of one or more capacitors, and the number of capacitors in the first group of capacitors is different from the number of capacitors in the second group of capacitors.

[0009] In some embodiments, at least one capacitor in the first group of the capacitors is variable, or at least one capacitor in the second group of the capacitors is variable.

[0010] In some embodiments, the electronic circuit further comprises a first sampler and at least one second sampler, wherein the first sampler is used to provide a first logic output signal to the first multiplex input circuit, and the second sampler is used to provide a second logic output signal to the second multiplex input circuit.

[0011] In some embodiments, the electronic circuit further includes at least one sampler for providing a multiplexed output signal to the data output terminal.

[0012] In some embodiments, the timing adjustment circuit further includes a third path, the third path is used to apply a third delay to generate third delay data, and the third delay is different from the first delay and the second delay. The electronic circuit further includes: a third logic circuit and a fourth logic circuit. The third logic circuit is used to receive the first delay data and the third delay data, and to generate a third logic output signal. The fourth logic circuit is used to receive the first delay data and the third delay data, and to generate a fourth logic output signal. The multiplexer is used to select to provide a multiplexed output signal according to the balanced feedback signal and at least one of the first logic output signal, the second logic output signal, the third logic output signal, and the fourth logic output signal.

[0013] In some embodiments, the equalization feedback signal includes one or more bits of equalization data in the previous one or more clock cycles.

[0014] In some embodiments, the multiplexer is a first multiplexer, the balanced feedback signal is a first balanced feedback signal, and the multiplexed output signal is a first multiplexed output signal. The electronic circuit further includes a second multiplexer for providing a second multiplexed output signal based on the second feedback signal and based on one of the first logic output signal and the second logic output signal. The first multiplexer is used to receive the second multiplexed output signal as the first balanced feedback signal. The first multiplexed output signal is synchronized with the first clock signal, and the second multiplexed output signal is synchronized with the second clock signal, and the first clock signal and the second clock signal have the same rate but different phases.

[0015] The present disclosure also relates to a memory device, comprising a memory interface circuit, a memory array, a data buffer circuit and a control logic circuit. The data buffer circuit comprises an input buffer and an equalization circuit. The control logic circuit is coupled to the memory interface circuit, the memory array and the data buffer circuit. The equalization circuit comprises a data input terminal, a timing adjustment circuit, a first logic circuit, a second logic circuit, a multiplexer and a data output terminal. The data input terminal is used to receive data from the input buffer. The timing adjustment circuit is used to receive data from the data input terminal, wherein the timing adjustment circuit comprises a first path and a second path, the first path is used to apply a first delay to the data to generate a first delayed data, the second path is used to apply a second delay to the data to generate a second delayed data, and the first delay is different from the second delay. The first logic circuit is used to receive the first delayed data and the second delayed data, and to generate a first logic output signal, wherein the first logic output signal extends the pulse width corresponding to the first logic value in the data. The second logic circuit is used to receive the first delayed data and the second delayed data, and to generate a second logic output signal, wherein the second logic output signal extends the pulse width corresponding to the second logic value in the data. The multiplexer is used to select at least one of the first logic output signal or the second logic output signal according to the balanced feedback signal to provide a multiplexed output signal. The data output terminal is used to output balanced data according to the multiplexed output signal.

[0016] In some embodiments, the first logic circuit includes an OR gate, and the first logic value includes a logic level 1, wherein the second logic circuit includes an AND gate, and the second logic value includes a logic level 0.

[0017] In some embodiments, the first path includes a first group of one or more inverters, and the second path includes a second group of one or more inverters.

[0018] In some embodiments, the first path further includes a first group of one or more capacitors, and the second path further includes a second group of one or more capacitors.

[0019] In some embodiments, at least one capacitor in the first group of the capacitors is variable, or at least one capacitor in the second group of the capacitors is variable.

[0020] In some embodiments, the equalization circuit further includes a first sampler and at least one second sampler, wherein the first sampler is used to provide a first logic output signal to the first multiplex input circuit, and the second sampler is used to provide a second logic output signal to the second multiplex input circuit.

[0021] In some embodiments, the equalization circuit further includes at least one sampler for providing a multiplexed output signal to the data output terminal.

[0022] In some embodiments, the timing adjustment circuit further includes a third path, the third path is used to apply a third delay to generate third delay data, and the third delay is different from the first delay and the second delay. The equalization circuit further includes a third logic circuit and a fourth logic circuit. The third logic circuit is used to receive the first delay data and the third delay data, and to generate a third logic output signal. The fourth logic circuit is used to receive the first delay data and the third delay data, and to generate a fourth logic output signal. The multiplexer is used to select to provide a multiplexed output signal according to the equalization feedback signal and at least one of the first logic output signal, the second logic output signal, the third logic output signal, and the fourth logic output signal.

[0023] In some embodiments, the equalization feedback signal includes one or more bits of equalization data in the previous one or more clock cycles.

[0024] In some embodiments, the multiplexer is a first multiplexer, the equalization feedback signal is a first equalization feedback signal, and the multiplexed output signal is a first multiplexed output signal. The equalization circuit further includes a second multiplexer for providing a second multiplexed output signal according to the second feedback signal and according to one of the first logic output signal and the second logic output signal. The first multiplexer is for receiving the second multiplexed output signal as the first equalization feedback signal. The first multiplexed output signal is synchronized with a first clock signal, and the second multiplexed output signal is synchronized with a second clock signal, the first clock signal and the second clock signal having the same rate but different phases.

[0025] The present disclosure also relates to a method for compensating for data distortion caused by channel loss, comprising: receiving data from a data input end; applying a first delay to the data to generate first delayed data and applying a second delay to the data to generate second delayed data, wherein the first delay is different from the second delay; generating a first logic output signal according to the first delayed data and the second delayed data, wherein the first logic output signal extends the pulse width of the data corresponding to the first logic value; generating a second logic output signal according to the first delayed data and the second delayed data, wherein the second logic output signal extends the pulse width of the data corresponding to the second logic value; selecting at least one of the first logic output signal or the second logic output signal according to an equalization feedback signal to provide a multiplexed output signal; and outputting equalized data at a data output end according to the multiplexed output signal.

[0026] The details of one or more embodiments of the present disclosure are described in the accompanying drawings and subsequent descriptions. The technical features, aspects and advantages of the present disclosure are clearly defined through the implementation methods, drawings and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1FIG. 1 is a schematic diagram of a system including a memory device according to some embodiments of the present disclosure.

[0028] Figure 2 Schematic diagram of a memory device according to some embodiments of the present disclosure.

[0029] Figure 3A Schematic diagram of waveforms of a system according to some embodiments of the present disclosure.

[0030] Figure 3B Schematic diagram of waveforms of a system according to some embodiments of the present disclosure.

[0031] Figure 4A and Figure 4B Schematic diagram of a timing adjustment circuit according to some embodiments of the present disclosure.

[0032] Figure 4C FIG. 4 is a schematic diagram of path delay of a timing adjustment circuit according to some embodiments of the present disclosure.

[0033] Figure 5 Schematic diagram of pulse width compensation according to some embodiments of the present disclosure.

[0034] Figure 6 to Figure 9 is a schematic diagram of a DFE circuit according to some embodiments of the present disclosure.

[0035] Fig.10 The present invention is a flowchart of a method according to some embodiments of the present invention.

[0036] The drawings are not drawn to scale and like reference numerals throughout the drawings represent similar elements.

[0037] Description of reference numerals:

[0038] 1000: Methods

[0039] 1002-1012: Steps

[0040] 100: System

[0041] 110: Memory device

[0042] 112: Device controller

[0043] 113: Processor

[0044] 114: Internal memory

[0045] 116: Memory

[0046] 120: Host device

[0047] 122: Host controller

[0048] 200: Memory device

[0049] 202: Memory interface circuit

[0050] 204: Control Logic Circuit

[0051] 206: Column decoder

[0052] 210: Memory Array

[0053] 215: Bit line

[0054] 220: Page buffer circuit

[0055] 230: Data cache circuit

[0056] 240: Data buffer circuit

[0057] 242: Input data buffer

[0058] 244: Output data buffer

[0059] 300: System

[0060] 302: Output buffer

[0061] 303: Channel

[0062] 304: Input buffer

[0063] 306: DFE

[0064] 308: Waveform

[0065] 309: Waveform

[0066] 310: Waveform

[0067] 320: Waveform

[0068] 400A: Timing adjustment circuit

[0069] 400B: Timing adjustment circuit

[0070] 401: Input Data

[0071] 402: Inverter

[0072] 403: Inverter

[0073] 411: Fast Output

[0074] 412: Slow output

[0075] 600: DFE circuit

[0076] 601: Input

[0077] 602: Delay Line

[0078] 603: OR gate

[0079] 604: AND Gate

[0080] 605a1: Sampler

[0081] 605a2: Sampler

[0082] 606: Multiplexer

[0083] 607: Output

[0084] 700: DFE circuit

[0085] 701: Input

[0086] 702: Delay Line

[0087] 703: OR gate

[0088] 704: AND gate

[0089] 705a1: Sampler

[0090] 705a2: Sampler

[0091] 705b1: Sampler

[0092] 705b2: Sampler

[0093] 706a: Multiplexer

[0094] 706b: Multiplexer

[0095] 707a-707b: Output

[0096] 800: DFE circuit

[0097] 801: Input

[0098] 802: Delay Line

[0099] 803: OR gate

[0100] 804: AND Gate

[0101] 805a: Sampler

[0102] 805b: Sampler

[0103] 806a: Multiplexer

[0104] 806b: Multiplexer

[0105] 807a: Output

[0106] 807b: Output

[0107] 900: DFE circuit

[0108] 901: Input

[0109] 902: Delay Line

[0110] 903a: OR gate

[0111] 903b: OR gate

[0112] 904a: AND gate

[0113] 904b: AND gate

[0114] 905a1-905a4: Sampler

[0115] 905b1-905b4: Samplers 906a: Multiplexers

[0116] 906b: Multiplexer

[0117] 907a: Output

[0118] 907b: Output

[0119] C1: Capacitor

[0120] C2: Capacitor

[0121] CLK0: clock signal

[0122] CLK90: clock signal

[0123] CLK180: clock signal

[0124] CLK270: clock signal

[0125] delay: delay

[0126] RX: Receiver

[0127] SEL: Select signal

[0128] s0: select pin

[0129] s1: select pin

[0130] TX: Transmitter

[0131] T: Pulse width

[0132] T′: Pulse width DETAILED DESCRIPTION

[0133] A semiconductor device (e.g., a memory device) can receive data from a host device (e.g., a personal computer) through a data transmission channel. The data transmission channel usually has noise or interference, so that the waveform of the data sampled by the semiconductor device is distorted. One type of interference is "inter-symbol interference (ISI)". For ISI, when a first data symbol (e.g., a bit) with a voltage level (e.g., a logic level "0") is sampled by a clock too early, it will cause a second data symbol with a different voltage level (e.g., a logic level "1") to have a narrower pulse width when sampled by a clock too late. The narrower pulse width of the second data symbol will increase the probability of data errors.

[0134] In order to mitigate the effects of ISI, some semiconductor devices use equalization circuits, such as decision feedback equalization (DFE) circuits, to adjust the waveform of the received input data based on one or more symbols previously output by the DFE circuit. Therefore, the symbols output subsequently can take the previous symbols into account to compensate for the narrower pulse width. Since the level of ISI usually changes with different data transmission channels and different transmission speeds, the compensation for the pulse width (referred to herein as the "compensation space") needs to be adjusted according to different transmission protocols. Accordingly, it can be expected that the DFE can compensate for the pulse width more flexibly. In addition, in view of the growing demand for high data density and small size memory devices, the DFE ideally has a streamlined structure.

[0135] The present disclosure provides techniques for addressing the above challenges. In some embodiments, the DFE includes a timing adjustment circuit, such as a delay line, for providing different delays to input data on different timing paths, wherein the delay amount on each path can be adjusted. The DFE also includes a logic circuit for adjusting the pulse width of the input data according to a basic logic arithmetic. Through one or more of the following features, the present disclosure provides a highly flexible and low-complexity DFE architecture.

[0136] The technology of the present disclosure can be applied to any suitable circuit or device, such as a semiconductor device. For illustrative purposes, a "memory device" is used as an example of a semiconductor device. For example, the technology of the present disclosure can be applied to various types of non-volatile memories, such as: NOR flash memory, NAND flash memory, erasable programmable read-only memory (EPROM), static random access memory (SRAM), resistive random access memory (RRAM), ferroelectric random access memory (FeRAM), magnetoresistive random access memory (MRAM), etc. The technology of the present disclosure can be applied to various types of memories, such as: single-level cell devices, multi-level cell devices such as two-level cell devices, triple-level cell devices, quad-level cell devices, or penta-level cell devices. In addition, the technology of the present disclosure can be applied to various types of devices and systems, such as secure digital cards, embedded multimedia cards (eMMC), solid-state drives (SSD), embedded systems or computing network devices.

[0137] Figure 1 1 is a schematic diagram of a system 100 according to some embodiments of the present disclosure, including a memory device. The system includes a memory device 110 and a host device 120. The memory device 110 includes a device controller 112 and a memory 116. The device controller 112 includes a processor 113 and an internal memory 114. In some embodiments, the memory device 110 includes a plurality of memories 116 coupled to the device controller 112.

[0138] In some embodiments, the memory device 110 is a storage device. For example, the memory device 110 may be an embedded multimedia card, a memory card, a solid state drive, or other suitable storage. In some embodiments, the memory device 110 is a smart device, a digital camera, or a media player. In some embodiments, the memory device is a client device and is coupled to the host device 120. For example, the memory device 110 is a memory card in the host device 120 (e.g., a digital camera or a media player).

[0139] The device controller is a general-purpose microprocessor or a dedicated microcontroller. In some embodiments, the device controller 112 is a memory controller of the memory device 110. The following paragraphs will be described according to the embodiment in which the device controller 112 is a memory controller. However, the techniques described in the following paragraphs are also applicable to the implementation mode in which the device controller 112 is another type of controller different from the memory controller.

[0140] The processor 113 is used to execute various instructions and process data. The aforementioned instructions may include firmware instructions and / or software instructions, which may be firmware codes and / or other software codes stored in the secondary memory. The aforementioned data includes program data corresponding to the firmware or other software executed by the processor, or other suitable data. In some embodiments, the processor 113 is a general-purpose microprocessor or a dedicated microcontroller. The processor 113 may also be a central processing unit (CPU).

[0141] The processor 113 accesses instructions and data in the internal memory 114. In some embodiments, the internal memory 114 is a static random access memory (SRAM) or a dynamic random access memory (DRAM). For example, in some embodiments, when the memory device 110 is an embedded multimedia card, a memory card, or a smart watch, the internal memory 114 is a static random access memory. In some embodiments, when the memory device 110 is a digital camera or a media player, the internal memory 114 is a dynamic random access memory.

[0142] In some embodiments, the internal memory is a cache memory including: Figure 1 The device controller 112 is shown. The internal memory 114 stores instruction codes corresponding to instructions executed by the processor 113 and / or contains data required by the processor 113 at runtime.

[0143] The device controller 112 transfers the instruction code and / or data from the memory 116 to the internal memory 114. The memory 116 may be a semiconductor device. In some embodiments, the memory 116 is a non-volatile memory for long-term storage, such as NAMD flash memory or other applicable non-volatile memory. In an embodiment where the memory 116 is a NAND flash memory, the memory device 110 is a flash memory device, such as a flash memory card, and the device controller 112 is a NAND flash memory controller. For example, in some embodiments, when the memory device 110 is an embedded multimedia card or a memory card, the memory 116 is a NAND flash memory. In some embodiments, when the memory device 110 is a digital camera, the memory 116 is a memory card. In some embodiments, when the memory device 110 is a media player, the memory 116 is a hard disk.

[0144] The memory 116 includes a plurality of memory blocks. The memory 116 may be a two-dimensional memory including two-dimensional memory blocks, or a three-dimensional memory including three-dimensional memory blocks.

[0145] Figure 2 FIG. 2 is a schematic diagram of a memory device 200 according to some embodiments of the present disclosure. The memory device 200 may be implemented as Figure 1 The memory device 200 includes a memory array 210. The memory array 210 may include a plurality of memory cells connected in series to a plurality of row word lines and a plurality of column bit lines.

[0146] The memory cell includes a memory transistor used as a storage unit. The memory transistor may include a silicon-oxide-nitride-oxide-silicon (SONOS) transistor, a floating gate transistor, a nitride read only memory (NROM) transistor, or any suitable metal-oxide-semiconductor (MOS) device that can store charge as a non-volatile memory.

[0147] The memory device 200 includes a memory interface circuit 202. The memory interface circuit 202 has a plurality of input / output terminals for receiving data. The source of the received data may be a controller, such as Figure 1The memory device 200 includes a data buffer circuit 240 for buffering data through the memory interface circuit 202. The data buffer circuit 240 includes an input data buffer 242 for buffering / transmitting data from the controller (e.g., Figure 1 The data buffer circuit 240 further includes an output data buffer 244 for buffering / outputting data from the memory array 210 to the host device (such as the device controller 112 or the host controller 122 shown in FIG. 1 ) through the data buffer circuit 240. The data buffer circuit 240 also includes an output data buffer 244 for buffering / outputting data from the memory array 210 through the memory interface circuit 202 to the host device (such as the device controller 112 or the host controller 122 shown in FIG. Figure 1 data of the host device 120 shown.

[0148] In some embodiments, the memory device 200 further includes a row decoder 206 (Xβdecoder, row decoder) and a column decoder (Y-decoder, not shown). Each memory cell is coupled to the row decoder 206 via its own word line, and is coupled to the column decoder via its own bit line 215. Accordingly, each memory cell can be selected through the row decoder 206 and the column decoder by a read or write process of the respective word line and bit line.

[0149] The memory device 200 includes a page buffer circuit 220, which includes a plurality of page buffers. Each page buffer is connected to the memory array 210 via a respective bit line 215. In some embodiments, the page buffer is connected to a row decoder via a data line associated with a corresponding bit line 215, and is connected to a corresponding row of memory cells in the memory array 210. The page buffer is used to empty the voltage of the corresponding bit line to perform an operation on the memory cell coupled to the corresponding bit line, such as reading, writing / programming, and erasing. The page buffer may include at least one latch circuit.

[0150] In some embodiments, the memory device 200 further includes a data buffer circuit 230. The data buffer circuit 230 is coupled between the page buffer circuit 220 and the data buffer circuit 240. During a programming or erasing process, the data buffer circuit 230 is used to store data from the data buffer circuit 240 (e.g., from the input data buffer 242) and / or output data to the memory array 210 through the page buffer circuit 220. During a reading process, the data buffer circuit 230 is used to store data from the memory array through the page buffer circuit 220 and / or output data to the data buffer circuit 240 (e.g., to the output data buffer 244).

[0151] In some embodiments, the memory device 200 further includes a control logic circuit 204. The control logic circuit 204 is coupled to components in the memory device 200, including a row decoder 206 and a column decoder, a data buffer circuit 240, a page buffer circuit 220, and a data cache circuit 230. The control logic circuit 204 is used to receive data from a memory controller (e.g., Figure 1 The control logic circuit 204 may receive the command, address information and / or data from the device controller 112 or the host controller 122 shown. The control logic circuit 204 may process the command, address information and data, for example, to generate physical address information (e.g., a block or page in the memory array 210). The control logic circuit 204 may include a circuit system, such as an integrated circuit that integrates multiple logic elements, circuits and / or components.

[0152] In some embodiments, the control logic circuit 204 includes a data register, an SRAM buffer, an address generator, a mode logic circuit and a state machine circuit. The mode logic circuit is used to determine whether there is a read or program process and provide the determination result to the state machine circuit.

[0153] During a write program, a data register in the control logic circuit 204 can record input data from the memory interface circuit 202. The address generator in the control logic circuit 204 can generate a corresponding physical address to store data in a specified memory cell in the memory array 210. The address generator is in the column decoder 206 and the row decoder, and can be controlled to select a specified memory cell through a corresponding word line and bit line. As long as there is power, the SRAM buffer can maintain the input data from the data register in its own memory. The state machine circuit can process the write signal from the SRAM buffer and provide a control signal to the voltage generator, which can provide a write voltage to the column decoder 206 and / or the row decoder. The row decoder is used to output a write voltage to the word line to store the input data in the specified memory cell.

[0154] During a read process, the state machine circuit may provide control signals to the voltage generator and the page buffer circuit 220. The voltage generator provides a read voltage to the column decoder 206 and the row decoder to select a memory cell. The page buffer may sense a low power signal (e.g., a current signal) via a bit line 215 coupled to the page buffer and the selected memory cell. The low power signal represents a data bit ("1" or "0") stored in the selected memory cell. The sense amplifier may amplify the swing of the low power signal to a recognizable logic level so that the data bit can be correctly interpreted by a logic circuit inside or outside the memory device 200. In some embodiments, the page buffer circuit 220 and / or the data buffer circuit 230 are included in the sense amplifier. The data buffer circuit 240 (e.g., the output data buffer 244) may receive the voltage amplified by the sense amplifier and output the amplified power signal to a logic circuit inside or outside the memory device 200 through the memory interface circuit 202.

[0155] Figure 3A 308 is a waveform 309 of a channel distorted by ISI and compensated by DFE according to some embodiments of the present disclosure. Distortion and compensation both occur in the system 300, which can be equivalent to Figure 1 System 100 is shown.

[0156] As shown in the figure, at the transmission end TX, the system 100 includes an output buffer 302 for outputting data on a channel 303. At the receiving end RX, the system 100 includes an input buffer 304 for receiving data from the channel 303 and the DFE 306 and compensating for waveform distortion. It can be seen from the eye diagram of the waveform 308 that the channel 303 generates ISI in adjacent symbols, causing the symbol pulse to have relatively long tails and less steep rising and falling edges. This phenomenon is contrary to the desired pulse shape of "having a nearly vertical rising and falling edge". On the other hand, after the waveform compensation by the DFE 306, it can be seen that the waveform 309 has a sharper edge.

[0157] Figure 3BThe effect of ISI on symbol pulse width without compensation by DFE is shown in some embodiments of the present disclosure. Typically, in a system such as system 300, symbols obtained from an input buffer are processed and stored by analog-to-digital conversion. Due to the effect of ISI on the symbol waveform, some symbols have narrower pulse widths in the digital domain after being converted. For example, waveform 310 shows the distortion effect caused by ISI. After analog-to-digital conversion, waveform 320 has narrower pulses due to stronger ISI effects and wider pulses due to weaker ISI effects. In the absence of ISI effects, the two pulses should have the same or similar widths.

[0158] The above waveform distortion can be mitigated by DFE. As described below, DFE uses timing adjustment circuits and logic circuit systems to respectively extend the pulse width of the logic level "0" before the logic level "1" and extend the pulse width of the logic level "1" before the logic level "0". Then, DFE uses one or more multiplexers to selectively output symbols with extended pulse widths.

[0159] Figure 4A and Figure 4B 1 and 2. The timing adjustment circuits 400A and 400B are shown in accordance with some embodiments of the present disclosure. Each timing adjustment circuit 400A and 400B receives input data 401 and provides a fast output 411 (e.g., fast out) and a slow output 412 from two paths, respectively. Each path includes a plurality of inverters 402 and 403 (or buffers).

[0160] Please read first Figure 4AIn the path between the input data 401 and the fast output 411, the timing adjustment circuit 400A has one or more capacitors C1, and the capacitors C1 are coupled to the output terminals of all the inverters 402. Similarly, in the path between the input data 401 and the slow output 412, the timing adjustment circuit 400A has one or more capacitors C2. The capacitors C2 are coupled to the output terminals of some or all of the inverters 403. The capacitors C1 and C2 may include one or more metal oxide semiconductor (MOS) capacitors, one or more metal-insulator-metal (MIM) capacitors, one or more metal-oxide-semiconductor capacitors (MOSCAPs) or one or more multilayer ceramic capacitors (MOSCAPs). The inverters (buffers) 402 and 403 may include the same structure and apply the same amount of delay to the signals passing through the corresponding paths. In addition, each capacitor C1 and C2 may apply a delay to the signals passing through the corresponding paths. Accordingly, when the number of inverters (buffers) 402 is equal to the number of inverters (buffers) 403, the difference in capacitance between capacitors C1 and C2 will cause different delays on the two paths. For example, in the case where there are four identical inverters (buffers) 402 and 403 in each path, making the capacitance of capacitor C1 smaller than the capacitance of capacitor C2 will make the delay on the fast path smaller than the delay on the slow path. Therefore, the time when input data 401 traveling on the fast path reaches the fast output 411 will be earlier than the time when input data 401 traveling on the slow path reaches the slow output 412.

[0161] Please continue to refer to Figure 4B , the timing adjustment circuit 400B includes M inverters (buffers) 402 on the fast path, and N inverters (buffers) 403 on the slow path, where M and N are different positive integers, and M is less than N. Therefore, when each inverter (buffer) 402, 403 applies the same amount of delay to the signal flowing through the corresponding path, the input data 401 traveling on the fast path will experience less delay than the input data 401 traveling on the slow path. In other words, the time when the input data 401 traveling on the fast path arrives at the fast output 411 will be earlier than the time when the input data 401 traveling on the slow path arrives at the slow output 412.

[0162] Figure 4C A schematic diagram for illustrating that a timing adjustment circuit (eg, timing adjustment circuits 400A and 400B) applies different delays on two paths in some embodiments of the present disclosure. Figure 4CAs shown, by the relative amount of delay, the time when the data arrives at the fast output 411 will be earlier than the time when the data arrives at the slow output 412. The relative delay can be achieved by different capacitance values ​​on the two paths (e.g., different numbers of inverters in the timing adjustment circuit 400A or the timing adjustment circuit 400B in each path). In addition to the timing adjustment circuits 400A and 400B, other timing adjustment circuits may have similar effects as relative delay. For example, by using different numbers of inverters (buffers) in combination with different capacitance values ​​on the two paths, the partial timing adjustment circuit provides a relative delay between the two paths. By using the same number of inverters (buffers) in combination with different numbers of capacitors on the two paths, the partial timing adjustment circuit provides a relative delay between the two paths. By using the same number of inverters (buffers) in combination with different numbers of capacitors on the two paths, the partial timing adjustment circuit provides a relative delay between the two paths. By using the same number of inverters (buffers) in combination with different structures, quantities or driving strengths on the two paths, the partial timing adjustment circuit provides a relative delay between the two paths. Various implementations of the timing adjustment circuit, such as combinations of the above embodiments, are possible. For the sake of brevity, they are not described in detail here.

[0163] In some embodiments, the relative delay between the fast path and the slow path is adjustable / variable. For example, in the timing adjustment circuit 400A, some or all of the capacitors C1 and C2 may be adjustable MOS capacitors, whose capacitance values ​​may be controlled by switches. The relative delay may be adjusted accordingly by adjusting the capacitance values ​​of some or all of the capacitors. In another embodiment, in the phase adjustment circuits 400A and 400B, the drive strength (e.g., drive voltage level) of some or all of the inverters (buffers) 402 and 403 may be adjusted by an adjustable driver to change the delay caused by the inverters (buffers).

[0164] Although Figure 4A to Figure 4C The timing adjustment circuit described in has only two paths, and the timing adjustment circuit can have multiple paths, each path applying a different delay between the data input and the data output. For example, the timing adjustment circuit has three paths, each path applying a different delay. The path with the smallest delay can be called a fast path, and the corresponding output can be called a fast output. The path with an intermediate delay can be called a medium-speed path, and the corresponding output can be called a medium-speed output. The path with the largest delay can be called a slow path, and the corresponding output can be called a slow output. Since those skilled in the art can understand the structure and operation of the timing adjustment circuit with more than two paths based on the above description, it will not be repeated here.

[0165] Figure 5 FIG. 1 is a schematic diagram of pulse width compensation after logic operation in some embodiments of the present disclosure. Figure 5Four different scenarios are described: (1) logic level "1" is preceded by logic level "0"; (2) logic level "0" is preceded by logic level "0"; (3) logic level "0" is preceded by logic level "1"; and (4) logic level "1" is preceded by logic level "1". Each scenario involves a signal A and a signal B having the same sign value, where signal B is delayed by a delay delay from signal A. Therefore, in these scenarios, signal A provided by the timing adjustment circuit can be used as a fast output, and signal B provided by the timing adjustment circuit can be used as a slow output. In scenarios (1) and (2), an "OR" operation is performed on signals A and B. In scenarios (3) and (4), an "AND" operation is performed on signals A and B.

[0166] In scenario (1), the change from logic level "0" to logic level "1" makes signals A and B susceptible to ISI. Due to ISI, the logic level "1" symbol in each signal has a narrower / reduced pulse width T', which is opposite to the unreduced pulse width T when there is no ISI-induced distortion. After the "OR" operation, the pulse width of the output signal (A or B) is "T'+delay". Therefore, the OR operation effectively extends the pulse width of the logic level "1" of the fast output (signal A) by an amount equal to the delay delay.

[0167] In scenario (2), since signals A and B remain at logic level "0", ISI does not reduce the pulse width of the second symbol, so the pulse width T of the second symbol of logic level "0" does not decrease in both signals A and B. After the "OR" operation, the pulse width T of the logic level "0" of the fast output (signal A) can remain unchanged.

[0168] In scenario (3), the change from logic level "1" to "0" will make signals A and B susceptible to ISI. Due to ISI, each logic level "0" symbol in the signal will have a reduced pulse width T', which is the opposite of the pulse width (not reduced) when there is no ISI distortion. After the "AND" operation, the output signal (A or B) has a pulse width of "T'+delay". Accordingly, the "AND" operation effectively extends the pulse width of the logic level "0" of the fast output (signal A), where the extension amount is equal to the delay amount.

[0169] In scenario (4), since signals A and B remain at logic level "1", ISI does not reduce the pulse width of the second symbol, so the pulse width T of the second symbol of logic level "1" does not decrease in both signals A and B. After the "AND" operation, the pulse width T of the logic level "1" of the fast output (signal A) can remain unchanged.

[0170] According to the above scenarios (1) to (4), when a signal symbol is preceded by a bit of logic level "0", the signal (such as Figure 5 The signal A shown) and the delayed version of the signal (such as: Figure 5 Similarly, when a signal symbol is preceded by a bit of logic level "1", the signal (such as Figure 5 The signal A shown) and the delayed version of the signal (such as: Figure 5 The signal B) shown in the figure is ANDed to reduce the pulse width reduction caused by ISI. Figure 6 to Figure 9 In the embodiments described above, the present disclosure will respectively provide DFE circuits 600-900 consistent with the aforementioned mechanisms. Each DFE circuit 600-900 can be implemented in Figure 2 In the memory device 200 shown, for example, a portion of the data buffer circuit 240 is shown.

[0171] It is important to note that the delay between the two paths can be used to meet certain requirements. For example, the delay can be large enough to fully compensate for the reduced pulse width. On the other hand, the delay is generally configured to be no more than one UI (UI represents the period of each bit of input data), otherwise the slow output pulse (such as Figure 5 The signal B shown may arrive too late to participate in the rapid output (such as Figure 5 In some embodiments, for a data rate of 4 Gb / s (one UI=250 picoseconds), the delay is configured to be approximately 125 picoseconds (ps), so that the slow output pulses can overlap with the fast output pulses.

[0172] Figure 6 FIG. 6 is a schematic diagram of a DFE circuit 600 according to some embodiments of the present disclosure. The DFE circuit 600 receives data from an input terminal 601 and outputs equalized data at an output terminal 607 after compensation.

[0173] The DFE circuit 600 includes a delay line 602, which is similar to the timing adjustment circuits 400A and 400B, and is used to generate a fast output and a slow output. Each of the fast output and the slow output is input to an OR gate 603 (or an equivalent logic circuit) and is input to an AND gate 604 (or an equivalent logic circuit). The OR gate 603 can extend the pulse width of the logic level "1" distorted by the ISI, and the AND gate 604 can extend the pulse width of the logic level "0" distorted by the ISI.

[0174] The logic operation outputs of the OR gate 603 and the AND gate 604 are input to the samplers 605a1 and 605a2 (slicer circuits) respectively. The samplers 605a1 and 605a2 can be strong arm latch circuits and can each include a flip-flop circuit to synchronize the outputs of the OR gate 603 and the AND gate 604 with the clock signal CLK0.

[0175] The outputs of the samplers 605a1 and 605a2 are provided as inputs of a one-bit MUX, and the output of the one-bit MUX is provided to an output terminal 607 and is selected by a one-bit selection signal SEL. For example, when the value of the selection signal SEL is a logic level "0", the signal at the "0" input pin of the multiplexer 606 (corresponding to the output of the OR gate 603) is transmitted to the output terminal 607. Conversely, when the value of the selection signal SEL is a logic level "1", the signal at the "1" input pin of the multiplexer 606 (corresponding to the output of the AND gate 604) is transmitted to the output terminal 607.

[0176] The output signal at the output terminal 607 will be fed back to the multiplexer 606 and provided to the selection pin s0 as the selection signal SEL. That is, the multiplexer 606 selects whether to output the signal at the input pin "0" or the signal at the input pin "1" according to the value of the previous bit of the output data at the output terminal 607. With this configuration, when the previous bit of the output terminal 607 is a logic level "0", the multiplexer 606 selects the signal at the output input pin "0" (corresponding to the output of the OR gate 603). Figure 5 In the scenarios (1) and (2) shown, the output of the OR gate 603 can expand the pulse width of the current bit's logic level "1" (due to the change from "0" to "1", ISI distortion will be easily generated), while keeping the pulse width of the current bit's logic level "0" unchanged (because the logic value does not change, it is not affected by ISI distortion). Similarly, when the previous bit at the output terminal 607 is logic level "1", the multiplexer 606 selects the signal at the output input pin "1" (corresponding to the output of the AND gate 604). Figure 5 In the scenarios (3) and (4) shown, the output of AND gate 604 can expand the pulse width of the current bit logic level "0" (because the change from "1" to "0" will easily cause ISI distortion), while keeping the pulse width of the current bit logic level "1" (because the logic value does not change, it is not affected by ISI distortion). Accordingly, the output data of output terminal 607 is used as the balanced output, and DFE circuit 600 can compensate for the waveform distortion caused by ISI.

[0177] As mentioned above, the selection signal SEL is fed back from the output terminal 607 as the previous bit of the output signal. In order to enable the multiplexer 606 to make a selection in time, the "multiplexer delay" of the multiplexer 606 is configured to be less than one UI. The aforementioned "multiplexer delay" refers to the delay time from "the time when the feedback signal reaches the selection pin s0" to "the time when the multiplexer 606 selects the output".

[0178] Figure 7 FIG. 7 is a schematic diagram of a DFE circuit 700 according to some embodiments of the present disclosure. The DFE circuit 700 receives input data from an input terminal 701 and outputs balanced data at output terminals 707a to 707d (collectively referred to as output terminals 707, with only 707a to 707b shown in the figure) after compensation. As described below, the circuit for outputting balanced data at output terminals 707c and 707d is substantially the same as the circuit for outputting balanced data at output terminals 707a and 707b. Therefore, Figure 7 Output terminals 707c and 707d are omitted.

[0179] Similar to the operation of the DFE circuit 600, the delay line 702, the OR gate 703 and the AND gate 704 in the DFE circuit 700 provide two logic operation outputs, respectively extending the pulse width of the logic level "1" and "0" distorted by the ISI. Similar to the operation of the DFE circuit 600, the two logic operation outputs of the OR gate 703 and the AND gate 704 are respectively provided to the samplers 705a1 and 705a2 to be synchronized with the clock signal CLK0, and then respectively input to the multiplexer 706a as inputs "0" and "1". The multiplexer 706a then selectively outputs data at the output terminal 707a as the signal at its "0" or "1" input.

[0180] Unlike the DFE circuit 600, the DFE circuit 700 has three additional “sampler-multiplexer” combinational circuits. For example, the two logic operation outputs of the OR gate 703 and the AND gate 704 are provided to the samplers 705b1 and 705b2 respectively to synchronize with the clock signal CLK90, and then input to the multiplexer 706b as inputs “0” and “1” respectively. The multiplexer 706b then selectively outputs data at the output terminal 707b as the signal at its input “0” or “1”.

[0181] Similarly, the DFE circuit 700 has samplers (e.g., 705c1, 705c2, omitted in the figure) to synchronize with a clock signal (e.g., CLK180, omitted in the figure) and then input to a multiplexer (e.g., 706c, omitted in the figure) as inputs "0" and "1", respectively. The multiplexer 706c then selectively outputs data at an output terminal 707c as a signal at its input "0" or "1". The DFE circuit 700 also has samplers (e.g., 705d1, 705d2, omitted in the figure) to synchronize with a clock signal (e.g., CLK270, omitted in the figure) and then input to a multiplexer (e.g., 706d, omitted in the figure) as inputs "0" and "1", respectively. The multiplexer 706d then selectively outputs data at an output terminal 707d as a signal at its input "0" or "1". For simplicity, the aforementioned components and their connections are represented by the symbol "x2" and are not shown in detail. Figure 7 .

[0182] In order to make multiplexers 706a-706d make selections, the output data of output terminal 707a is fed back to the selection pin s0 of multiplexer 706b. Accordingly, the selection of multiplexer 706b is based on the previous bit of the output data of output terminal 707a. Similarly, the output data of output terminals 707b, 707c, and 707d are fed back to the selection pin s0 of multiplexers 706c, 706d, and 706a, respectively.

[0183] The clock signals CLK0, CLK90, CLK180, and CLK270 together constitute a four-phase clock. The clock signals CLK0, CLK90, CLK180, and CLK270 have the same frequency, but the phases differ by 90 degrees. For example, in one clock cycle, the clock signal CLK0 is asserted at the beginning of the clock cycle and lasts for a quarter of the clock cycle. The clock signals CLK90, CLK180, and CLK270 are then asserted and each lasts for a quarter of the clock cycle. By making the frequency of the clock signals CLK0, CLK90, CLK180, and CLK270 one-fourth of the data rate of the input data at the input terminal 701, the DFE circuit 700 is configured to have a quarter-rate equalized output (relative to the full-rate equalized output in the DFE circuit 600), where the equalized data can be provided sequentially at the four output terminals 707a to 707d. The output data rate at each output terminal 707 a - 707 d is one quarter of the input data rate at the input terminal 701 .

[0184] As described above, in the DFE circuit 700, the selection signal SEL of each multiplexer is fed back from the output of the adjacent multiplexer. In order to enable each multiplexer to make a selection in time, the delay (multiplexer delay) of the feedback signal from the time it arrives to the time it selects the pin s0 is configured to be less than one UI. For example, the multiplexer delay of the multiplexer 706a is less than one UI (equal to the duration from the rising edge of CLK0 to the subsequent rising edge of CLK90). Similarly, the multiplexer delay of the multiplexers 706b to 706d is less than one UI.

[0185] In addition to full-rate and quarter-rate configurations, in other embodiments, data can be output synchronously at different clock rates. For example, in some embodiments, the DFE circuit has eight "sampler-multiplexer" combination circuits, where the samplers are driven by an eight-phase clock. In a multi-rate configuration embodiment, the output data at each output terminal has a frequency lower than the full-rate configuration. This will reduce the time constraints of further data processing (such as analog-to-digital conversion).

[0186] Figure 8 FIG. 8 is a schematic diagram of a DFE circuit 800 according to some embodiments of the present disclosure. The DFE circuit 800 receives data from an input terminal 801 and outputs equalized data at output terminals 807a to 807d (referred to as output terminals 807 herein, only 807a to 807b are shown in the figure) after compensation. Similar to the operation of the DFE circuits 600 and 700, the delay line 802, the OR gate 803 and the AND gate 804 in the DFE circuit 800 provide two logic operation outputs, which respectively extend the pulse width of the logic level "1" and "0" distorted by the ISI. Similar to the DFE circuit 700, the DFE circuit 800 provides a quarter-rate equalized output at the output terminal 807, and the output signal is synchronized with the clock signals CLK0, CLK90, CLK180 and CLK270 respectively.

[0187] The difference between DFE circuits 700 and 800 lies in the configuration of the multiplexer and its corresponding number of samplers. Figure 8As shown, the logic operation of the OR gate 803 and the AND gate 804 is first input to the multiplexer 806a, and then the output of the multiplexer 806a is provided to the sampler 805a. Similarly, the logic operation of the OR gate 803 and the AND gate 804 is first input to the multiplexer 806b, and then the output of the multiplexer 806b is provided to the sampler 805b. The same configuration applies to the other two "sampler-multiplexer" combinations. The configuration advantage of the DFE circuit 800 is that the number of samplers can be reduced, thereby reducing the circuit size and circuit power consumption. However, in order for the multiplexer in the DFE circuit 800 to make a selection in time, the multiplexer delay plus the corresponding sampler delay is configured to be less than one UI. In other words, the multiplexer delay in the DFE circuit 800 is configured to be less than "one UI minus the sampler delay". Compared to the DFE circuit 700 , which is commonly referred to as a loop-unrolled architecture, the timing configuration of the DFE circuit 800 may be more restricted.

[0188] Although the DFE circuit 800 is a quarter rate configuration, the same architecture can also be applied to a DFE circuit configured at a full rate (e.g., one multiplexer and one sampler) or other number of rates (e.g., other number of multiplexers and samplers). The clock frequency of the full rate configuration can be four times that of the quarter rate configuration, and other number of rate configurations can have respective clock frequencies corresponding to different phases.

[0189] Fig. 9 FIG. 9 is a schematic diagram of a DFE circuit 900 according to some embodiments of the present disclosure. The DFE circuit 900 receives input data from an input terminal 901 and outputs equalized data at output terminals 907a-907d (referred to as output terminals 907 herein, only 907a-907b are shown in the figure) after compensation. The DFE circuit 900 is similar to the DFE circuits 700 and 800 in its quarter-rate configuration, wherein the output terminals 907 are synchronized with clock signals CLK0, CLK90, CLK180, and CLK270, respectively. The DFE circuit 900 is also similar to the DFE circuit 700 of the loop unrolling architecture, wherein the multiplexers 906a-906d (only 906a-906b are shown in the figure) are preceded by samplers 905a1-905a4, 905b1-905b4, 905c1-905c4 (omitted in the figure), and 905d1-905d4 (omitted in the figure), respectively.

[0190] The delay line 902 of the DFE circuit 900 is different from the DFE circuits 600 to 800 in that the DFE circuit 900 has a medium-speed output in addition to a fast output and a slow output. Accordingly, the DFE circuit 900 has two sets of logic circuits. The first set of logic circuits includes an OR gate 903a and an AND gate 904a, and the second set of logic circuits includes an OR gate 903b and an AND gate 904b. The first set of logic circuits can expand the pulse width distorted by ISI according to the relative delay between the fast output and the medium-speed output. The second set of logic circuits can expand the pulse width distorted by ISI according to the relative delay between the medium-speed output and the slow output. When the two relative delays are different, the delay line 902 and the OR gate 903a, the AND gate 904a, the OR gate 903b and the AND gate 904b can provide two levels of pulse width expansion (e.g., large expansion and small expansion) together to compensate for the logic level "1" and the logic level "0" distorted by ISI.

[0191] Pulse width extension with multiple levels can improve equalization performance because the ISI distortion from the immediately previous symbol will likely be different from the ISI distortion from earlier symbols. For example, assuming A, B, and C represent "current symbol, symbol before A, symbol before B", respectively, when {CBA} = {010}, the ISI distortion of A may be weaker than when {CBA} = {110}. In order to account for this difference and more accurately compensate for the ISI distortion of A, a two-bit multiplexer can be used to select the appropriate level of pulse width extension according to {CB}, as described in the following paragraphs.

[0192] The outputs of the OR gate 903a, the AND gate 904a, the OR gate 903b and the AND gate 904b are respectively input to the samplers 905a1-905a4, and then the outputs of the samplers 905a1-905a4 are provided to the two-bit multiplexer 906a as input. Similarly, the outputs of the OR gate 903a, the AND gate 904a, the OR gate 903b and the AND gate 904b are respectively input to the samplers 905a1-905a4, and then provided to the two-bit multiplexer as input. The outputs of the OR gate 903a, the AND gate 904a, the OR gate 903b and the AND gate 904b are respectively input to the samplers 905b1-905b4, and then provided to the two-bit multiplexer as input. Similarly (therefore the diagram is omitted), the outputs of OR gate 903a, AND gate 904a, OR gate 903b and AND gate 904b are respectively input to samplers 905c1-905c4, and then provided to a two-bit multiplexer 906c as input. The outputs of OR gate 903a, AND gate 904a, OR gate 903b and AND gate 904b are respectively input to samplers 905d1-905d4, and then provided to a two-bit multiplexer 906d as input.

[0193] Each two-bit multiplexer 906a-906d can selectively compensate for ISI distortion based on the first two bits of the output data. Taking multiplexer 906a as an example, its two selection pins {s1, s0} receive the selection signal SEL fed back from the output terminals {data out 2, data out 3} (omitted by the symbol "x2" in the figure). Due to the use of a quarter rate configuration, the signal fed back from the output terminal (data out 3) is the symbol before the current symbol, and the signal fed back from the output terminal (data out 2) is the symbol before the output terminal (data out 3). Multiplexers 906b-906d can similarly receive feedback from two corresponding output terminals.

[0194] The architecture of DFE circuit 900 may be referred to as a two-tap DFE architecture, in which two bits of the output signal are fed back. In contrast, the architecture of DFE circuits 600 to 800 may be referred to as a one-tap DFE architecture, in which one bit of the output signal is fed back. In addition to two-tap and one-tap DFE architectures, in some embodiments, an output signal feedback of "n>2" bits may be provided as a selection signal for an n-bit multiplexer with 2n inputs. In an n-tap DFE architecture, a delay line (or more generally, a phase adjustment circuit) may be provided to generate 2n-1 different relative delays, corresponding to 2 n-1 Different levels of pulse width stretching, ISI distortion for logic level "1", and corresponding to 2 n-1 Different levels of pulse width stretching for ISI distortion of logic level “0”. In addition, the n-tap DFE architecture can have 2n-1 AND gates and 2n-1 OR gates.

[0195] The features of the aforementioned DFE circuits 600-900 can be combined with each other. For example, some embodiments are dual-tap, full-rate DFE architectures, while other embodiments are single-tap, non-loop unrolling architectures. Those skilled in the art can understand the aforementioned embodiment architectures and changes from the aforementioned DFE circuits 600-900 after reading the present disclosure.

[0196] Although the aforementioned DFE circuits 600-900 use an OR gate and an AND gate to extend the pulse width, other logic gates, such as NAND, NOR, XOR, XNOR or a combination thereof, may be used to replace the OR gate and the AND gate. In addition, other circuits, such as adjusting the PMOS / NMOS drive strength of the inverter, may also achieve the effect of pulse width extension. After reading the contents of this disclosure, those skilled in the art will be able to implement DFE circuits with modified different logic circuits based on the DFE circuits 600-900.

[0197] Fig.10 1 is a flow chart of a method 1000 according to some embodiments of the present disclosure. The method 1000 may be executed by, for example, any one of the DFE circuits 600 to 900. By executing the method 1000, the memory device may compensate for the data waveform distortion caused by ISI.

[0198] In step 1002, data is received from a data input terminal. The data input terminal may be, for example, input terminal 601, 701, 801 or 901.

[0199] In step 1004, a first delay is applied to the data to generate first delayed data, and a second delay is applied to the data to generate second delayed data, wherein the first delay is different from the second delay.

[0200] In step 1006, a first logic output signal is generated according to the first delayed data and the second delayed data, wherein the first logic output signal extends a pulse width corresponding to a first logic value in the data.

[0201] In step 1008, a second logic output signal is generated according to the first delayed data and the second delayed data, wherein the second logic output signal extends a pulse width corresponding to a second logic value in the data.

[0202] In step 1010, at least one of (1) a first logic output signal or (2) a second logic output signal is selected according to the equalization feedback signal to provide a multiplexed output signal.

[0203] In step 1012, the equalized data is outputted at a data output terminal according to the multiplexed output signal. The data output terminal may be, for example, any one of the output terminals 607, 707a-707d, 807a-807d, or 907a-907d.

[0204] The present disclosure may be implemented as one or more computer software products, such as one or more program instruction modules encoded on a computer-readable medium and executed or controlled by a data processing device. The computer-readable medium may be a machine-readable storage device, a machine-readable storage substrate, a memory device, or one or more combinations thereof. The aforementioned data processing device includes all devices, equipment, and machines for processing data, such as one or more program processors or computers. In addition to hardware, the aforementioned device may include program code that establishes an execution environment for the computer program in question, such as processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of the above.

[0205] The system may include all devices, equipment and machines used to process data, including, for example, a programmable processor, a computer or multiple processors or computers. In addition to hardware, the system may also include program code that establishes an execution environment for the computer program in question, such as processor firmware, a protocol stack, a database management system, an operating system, or a combination of one or more of the above.

[0206] A computer program (also called a program, software, APP, script or program code) can be written in any form of programming language (including compiled or interpreted languages) and can be deployed in any form, including as a standalone program or as a module, component, subroutine or other unit suitable for use in a computing environment. A computer program does not necessarily correspond to a file in a file system. A program can be stored in a part of a file containing other programs or data (such as one or more scripts stored in a markup language file), a single file dedicated to related programs, or multiple coordinated files (such as files storing one or more modules, subroutines or partial program codes). A computer program can be deployed on one computer or multiple computers for execution, which are located at one site or distributed at multiple sites and connected by a communication network.

[0207] The processes and logic flows described in the present disclosure may be performed by one or more programmable processors executing one or more computer programs to perform the functions described in the present disclosure. The processes and logic flows may also be performed by dedicated logic circuits, and the device may be implemented as a dedicated logic circuit, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0208] For example, processors suitable for executing computer programs include general and special microprocessors, and any one or more processors of any type of digital computer. Generally speaking, the processor will receive instructions and data from a read-only memory, a random access memory, or both. The basic elements of a computer may include a processor for executing instructions and one or more memory devices for storing instructions and data. Generally speaking, a computer may also include one or more large-capacity storage devices for storing data, such as a magnetic disk, a magneto-optical disk, or an optical disk, or may be operably coupled to receive data from one or more large-capacity storage devices for storing data and / or transmit data to it. However, a computer may not require such a device. Computer-readable media suitable for storing computer program instructions and data may include all forms of non-volatile memory, media, and memory devices, including, for example, semiconductor memory devices, such as EPROM, EEPROM, and flash memory devices, magnetic disks. The processor and memory may include or be implemented as a dedicated logic circuit.

[0209] Although the present disclosure describes many details, these details should not be interpreted as limitations on the scope of the claimed invention or the content that may be claimed, but should be interpreted as descriptions of features peculiar to a particular embodiment. Certain features described in the context of a single embodiment of the present disclosure may also be implemented in a combination of embodiments. Relatively speaking, the various features described in the context of a single embodiment may also be implemented individually in multiple embodiments or in any suitable sub-combination. In addition, although the features may be described as working in certain combinations in the foregoing text, and even claimed as such, in some cases, one or more features in the claimed combination may still be deleted from the combination, and the claimed combination may be for a sub-combination or a variant of a sub-combination. Similarly, although the operation mode is depicted in a specific order in the drawings, this should not be understood as requiring these operations to be performed in the specific order shown or in a continuous order, or being understood to require all operations to be performed to achieve the desired results.

[0210] Only some examples and embodiments are disclosed herein, and the described examples and embodiments may be changed, modified and enhanced based on the disclosed content.

Claims

1. An electronic circuit comprising: A data input terminal, used for receiving data; a timing adjustment circuit for receiving the data from the data input terminal, wherein the timing adjustment circuit comprises a first path and a second path, the first path is used to apply a first delay to the data to generate a first delayed data, the second path is used to apply a second delay to the data to generate a second delayed data, and the first delay is different from the second delay; a first logic circuit, for receiving the first delayed data and the second delayed data, and for generating a first logic output signal, wherein the first logic output signal extends a pulse width corresponding to a first logic value in the data; a second logic circuit, for receiving the first delayed data and the second delayed data, and for generating a second logic output signal, wherein the second logic output signal extends a pulse width corresponding to a second logic value in the data; a multiplexer for selecting at least one of the first logic output signal or the second logic output signal according to an equalization feedback signal to provide a multiplexed output signal; as well as A data output terminal is used to output a balanced data according to the multiplexed output signal. 2 . The electronic circuit of claim 1 , wherein the first logic circuit comprises an OR gate, and the first logic value comprises a logic level 1, and wherein the second logic circuit comprises an AND gate, and the second logic value comprises a logic level 0. 3 .

3. The electronic circuit of claim 1, wherein the first path comprises a first group of one or more inverters, and wherein the second path comprises a second group of the one or more inverters. 4 . The electronic circuit of claim 3 , wherein a number of inverters of the first group of inverters is different from a number of inverters of the second group of inverters.

5. The electronic circuit of claim 3, wherein the first path further comprises a first group of one or more capacitors, the second path further comprises a second group of the one or more capacitors, and the number of capacitors in the first group of the capacitors is different from the number of capacitors in the second group of the capacitors. 6 . The electronic circuit of claim 5 , wherein at least one capacitor in the first group of capacitors is variable, or at least one capacitor in the second group of capacitors is variable.

7. The electronic circuit according to claim 1, further comprising: a first sampler, configured to provide the first logic output signal to a first multiplex input circuit; and At least one second sampler is used to provide the second logic output signal to a second multiplex input circuit. 8 . The electronic circuit according to claim 1 , further comprising at least one sampler for providing the multiplexed output signal to the data output terminal.

9. The electronic circuit according to claim 1, wherein the timing adjustment circuit further comprises a third path, the third path is used to apply a third delay to generate a third delay data, the third delay is different from the first delay and the second delay; The electronic circuit further comprises: a third logic circuit, for receiving the first delayed data and the third delayed data, and for generating a third logic output signal; and a fourth logic circuit, for receiving the first delayed data and the third delayed data, and for generating a fourth logic output signal; The multiplexer is used for selectively providing the multiplexed output signal according to the balanced feedback signal and at least one of the first logic output signal, the second logic output signal, the third logic output signal and the fourth logic output signal.

10. The electronic circuit of claim 1, wherein the equalization feedback signal comprises one or more bits of the equalization data in one or more previous clock cycles.

11. The electronic circuit of claim 1 , wherein the multiplexer is a first multiplexer, the balanced feedback signal is a first balanced feedback signal, and the multiplexed output signal is a first multiplexed output signal; The electronic circuit further comprises a second multiplexer for providing a second multiplexed output signal according to a second feedback signal and one of the first logic output signal and the second logic output signal; The first multiplexer is used to receive the second multiplex output signal as the first balanced feedback signal; The first multiplexed output signal is synchronized with a first clock signal, and the second multiplexed output signal is synchronized with a second clock signal. The first clock signal and the second clock signal have the same rate but different phases.

12. A memory device comprising: a memory interface circuit; a memory array; a data buffer circuit, comprising an input buffer and an equalization circuit; and a control logic circuit coupled to the memory interface circuit, the memory array and the data buffer circuit, wherein the equalization circuit comprises: A data input terminal, used for receiving data from the input buffer; a timing adjustment circuit for receiving the data from the data input terminal, wherein the timing adjustment circuit comprises a first path and a second path, the first path is used to apply a first delay to the data to generate a first delayed data, the second path is used to apply a second delay to the data to generate a second delayed data, and the first delay is different from the second delay; a first logic circuit, for receiving the first delayed data and the second delayed data, and for generating a first logic output signal, wherein the first logic output signal extends a pulse width corresponding to a first logic value in the data; a second logic circuit, for receiving the first delayed data and the second delayed data, and for generating a second logic output signal, wherein the second logic output signal extends a pulse width corresponding to a second logic value in the data; a multiplexer for selecting at least one of the first logic output signal or the second logic output signal according to an equalization feedback signal to provide a multiplexed output signal; as well as A data output terminal is used to output a balanced data according to the multiplexed output signal. 13 . The memory device of claim 12 , wherein the first logic circuit comprises an OR gate and the first logic value comprises a logic level 1, wherein the second logic circuit comprises an AND gate and the second logic value comprises a logic level 0.

14. The memory device of claim 12, wherein the first path comprises a first set of one or more inverters, and wherein the second path comprises a second set of the one or more inverters.

15. The memory device of claim 14, wherein the first path further comprises a first group of one or more capacitors, and wherein the second path further comprises a second group of the one or more capacitors.

16. The memory device of claim 15, wherein at least one capacitor in the first group of capacitors is variable, or at least one capacitor in the second group of capacitors is variable.

17. The memory device of claim 12, further comprising: a first sampler, configured to provide the first logic output signal to a first multiplex input circuit; and At least one second sampler is used to provide the second logic output signal to a second multiplex input circuit.

18. The memory device of claim 12, further comprising at least one sampler for providing the multiplexed output signal to the data output terminal.

19. The memory device according to claim 12, wherein the timing adjustment circuit further comprises a third path, the third path is used to apply a third delay to generate a third delay data, the third delay is different from the first delay and the second delay; The equalization circuit further comprises: a third logic circuit, for receiving the first delayed data and the third delayed data, and for generating a third logic output signal; and a fourth logic circuit, for receiving the first delayed data and the third delayed data, and for generating a fourth logic output signal; The multiplexer is used for selectively providing the multiplexed output signal according to the balanced feedback signal and at least one of the first logic output signal, the second logic output signal, the third logic output signal and the fourth logic output signal.

20. The memory device of claim 12, wherein the equalization feedback signal comprises one or more bits of the equalization data in one or more previous clock cycles.

21. The memory device of claim 12, wherein the multiplexer is a first multiplexer, the equalization feedback signal is a first equalization feedback signal, and the multiplexed output signal is a first multiplexed output signal; The equalization circuit further comprises a second multiplexer for providing a second multiplexed output signal according to a second feedback signal and one of the first logic output signal and the second logic output signal; The first multiplexer is used to receive the second multiplex output signal as the first balanced feedback signal; The first multiplexed output signal is synchronized with a first clock signal, and the second multiplexed output signal is synchronized with a second clock signal. The first clock signal and the second clock signal have the same rate but different phases.

22. A method for compensating for data distortion caused by channel loss, comprising: Receiving data from a data input terminal; Applying a first delay to the data to generate a first delayed data and applying a second delay to the data to generate a second delayed data, wherein the first delay is different from the second delay; Generate a first logic output signal according to the first delayed data and the second delayed data, wherein the first logic output signal extends a pulse width corresponding to a first logic value in the data; Generate a second logic output signal according to the first delayed data and the second delayed data, wherein the second logic output signal extends a pulse width corresponding to a second logic value in the data; selecting at least one of the first logic output signal or the second logic output signal according to an equalization feedback signal to provide a multiplexed output signal; and According to the multiplexed output signal, a balanced data is outputted at a data output terminal.

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