Manufacturing method of ultrathin chip stack
Through the combination of temporary bonding glue and carrier tape, the ultimate thinning of the Si substrate is achieved, solving the problem of limited thinning of particles caused by the increase in the thickness of the functional layer in the prior art, and achieving the maximum improvement of the performance of the package.
Patent Information
- Application Number
- CN202411984118.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-31
- Publication Date
- 2025-05-02
AI Technical Summary
In the existing three-dimensional chip stacking process, as the thickness of the functional layer increases, the thickness of the particles being thinned is limited, resulting in the improvement of the packaging performance due to the increase in the thickness of the functional layer.
By designing a manufacturing method for ultra-thin chip stacking, the combination of temporary bonding glue and carrier tape is used to achieve the ultimate thinning of the Si substrate, and the carrier plate is removed through laser decomposition technology to ensure the rigidity of the particles during transport and patching.
The ultimate thinning of the Si substrate thickness is achieved without being limited by the thickness of the functional layer, thereby greatly improving the storage capacity and performance of the package.
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Figure CN119920707A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of chips, in particular to a method for manufacturing an ultra-thin chip stack. Background Art
[0002] The three-dimensional stacking of chip particles is a packaging process that can both reduce the size of the chip package and improve its performance. It is widely used in the packaging process of memory chips (NAND, DRAM, etc.). Its main process flow is as follows: Figure 1 As shown in the figure, after the memory chip wafer is thinned and cut into particles (die), DAF is attached to the back, and then the particles are stacked one by one on an organic or inorganic substrate (substrate). The electrical and information interconnection between particles and between particles and substrates is achieved through wire bonding.
[0003] When the thickness of the package is constant, the thinner the thickness of the particles, that is, the thickness of the Si substrate and the DAF film, the more particles can be stacked, and the more advantageous the performance, such as storage capacity, will be.
[0004] However, the storage capacity of chips such as 3D NAND and 3D DRAM is also constantly increasing by increasing the number of functional layers. For example, major NAND manufacturers have launched 3D NAND wafers with more than 200 layers, and the thickness of the functional layer is about 10-20 um. In the future, the number of functional layers is expected to exceed 1,000 layers, and the thickness is expected to exceed 50 um. The functional layer of tens of um thick requires a certain thickness of Si substrate to support the rigidity of the particles themselves, so that they can not bend or be damaged in many processes such as particle transportation and particle attachment. Therefore, under the current three-dimensional stacking process, the increase in the thickness of the functional layer will restrict the thickness that can be thinned, so that the performance of the package cannot be maximized. Summary of the invention
[0005] The present invention provides a method for manufacturing an ultra-thin chip stack in order to overcome the deficiencies of the prior art.
[0006] To achieve the above object, a method for manufacturing an ultra-thin chip stack is designed, comprising the following steps: S1, provides a wafer; S2, temporarily bonding the wafer to one side surface of the carrier by using a temporary bonding adhesive; S3, thinning the silicon substrate of the wafer; S4, applying a DAF film on the surface of the silicon substrate of the wafer; S5, cutting into a number of wafer particles; S6, bonding the wafer particles to the substrate; S7, installing the carrier tape on the other side surface of the carrier board; S8, laser irradiation, causing the temporary bonding adhesive to decompose; S9, removing the carrier board by the carrier tape; S10, cleaning; S11, repeating steps S6 to S10 until the required number of layers are stacked.
[0007] The method further includes the following steps: S12, plastic encapsulation; S13, cutting into individual chips.
[0008] The temporary bonding adhesive is made of a material that can be debonded by laser.
[0009] The carrier tape is made of a material that can transmit ultraviolet light, the carrier board material is glass, and ultraviolet light is used for irradiation in step S8.
[0010] The carrier tape is made of a material that can transmit infrared light, and the carrier board material is made of glass or silicon. In step S8, infrared light is used for irradiation.
[0011] Compared with the prior art, the present invention can reduce the thickness of the Si substrate of the stacked particles to the limit without being affected by the thickness of the functional layer on the particle surface, thereby maximally improving the storage capacity and other performances of the package. BRIEF DESCRIPTION OF THE DRAWINGS
[0012] Figure 1 It is a schematic diagram of the prior art before the improvement of the present invention.
[0013] Figure 2 It is a schematic diagram of the present invention.
[0014] Figure 3 It is a partial enlarged view of step S8 of the present invention. DETAILED DESCRIPTION
[0015] The present invention will be further described below with reference to the accompanying drawings.
[0016] like Figures 2 to 3 As shown, the manufacturing method of the ultra-thin chip stack in this embodiment includes the following steps: S1, provide a wafer 1; S2, temporarily bond the wafer 1 to one side surface of the carrier 3 through temporary bonding glue 2; S3, thin the silicon substrate 1-1 of the wafer 1; S4, attach DAF film 4 to the surface of the silicon substrate 1-1 of the wafer 1; S5, cut into a number of wafer particles 5; S6, attach the wafer particles 5 to the substrate 6; S7, install a carrier tape 7 on the other side surface of the carrier 3; S8, irradiate with laser 9 to decompose the temporary bonding glue 2; S9, remove the carrier 3 through the carrier tape 7; S10, clean; S11, repeat steps S6 to S10 until the required number of layers are stacked. S12, plastic encapsulation; S13, cut into single chips 8.
[0017] The temporary bonding adhesive 2 is made of a material that can be debonded by laser. Preferably, a material that can generate gas after laser irradiation is selected during specific use, so that the carrier 3 is easy to peel off. After laser irradiation, step S9 uses the carrier tape 7 to peel off and remove the carrier 3 of the particles.
[0018] In step S8, the laser is ultraviolet light or infrared light. When ultraviolet light is used, the carrier 7 is made of a material that can transmit ultraviolet light, and the carrier 3 is made of glass. When infrared light is used, the carrier 7 is made of a material that can transmit infrared light, and the carrier 3 is made of glass or silicon.
[0019] In step S5, the thinned wafer is cut together with the temporary carrier 3, and in step S6, the wafer is mounted together with the carrier 3. This ensures that the ultra-thin chip can still maintain rigidity and is not damaged during transportation and mounting.
[0020] When the silicon substrate is thinned in step S3, it is further thinned through a temporary bonding process, and the carrier plays a supporting role to ensure that the Si substrate can be uniformly thinned to less than 5 µm, with TTV < 1 µm.
Claims
1. A method for manufacturing an ultra-thin chip stack, characterized in that: The steps include: S1, providing a wafer (1); S2, temporarily bonding the wafer (1) to a side surface of a carrier (3) by means of a temporary bonding adhesive (2); S3, thinning the silicon substrate (1-1) of the wafer (1); S4, applying a DAF film (4) to the surface of the silicon substrate (1-1) of the wafer (1); S5, cutting into a plurality of wafer particles (5); S6, attaching the wafer particles (5) to the substrate (6); S7, installing a carrier tape (7) on the other side surface of the carrier plate (3); S8, irradiating with laser (9) to decompose the temporary bonding glue (2); S9, removing the carrier plate (3) by means of the carrier tape (7); S10, cleaning; S11, repeating steps S6 to S10 until the required number of layers are stacked.
2. The method for manufacturing an ultra-thin chip stack according to claim 1, characterized in that: The method further comprises the following steps: S12, plastic encapsulation; S13, cutting into individual chips (8).
3. The method for manufacturing an ultra-thin chip stack according to claim 1, characterized in that: The temporary bonding glue (2) is made of a material that can be debonded by laser.
4. The method for manufacturing an ultra-thin chip stack according to claim 1, characterized in that: The carrier tape (7) is made of a material that can transmit ultraviolet light, and the carrier plate (3) is made of glass. In step S8, ultraviolet light is used for irradiation.
5. The method for manufacturing an ultra-thin chip stack according to claim 1, characterized in that: The carrier tape (7) is made of a material that can transmit infrared light, and the carrier plate (3) is made of glass or silicon. In step S8, infrared light is used for irradiation.
Citation Information
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