Vapor phase etching apparatus, method for removing oxide film on surface of silicon wafer, and method for manufacturing epitaxial silicon wafer

Abstract

Provided are a vapor phase etching device capable of more uniformly removing an oxide film formed on the surface of a silicon wafer, a method for removing an oxide film on the surface of a silicon wafer, and a method for manufacturing an epitaxial silicon wafer. A gas phase etching apparatus includes a gas introduction pipe for introducing an etching gas from a blow-out port located in a reaction container, and a wafer mounting stage exposed to the etching gas and located below the blow-out port of the gas introduction pipe. And a gas discharge pipe for discharging the etching gas to the outside of the reaction container from a suction port located below the stage for placing the wafer in the reaction container, the gas discharge pipe further comprising two or more rectifying plates provided on the side walls in the reaction container and erected between the side walls, and a plurality of rectifying plates, which are disposed below the blow-out opening of the gas introduction pipe and above the suction opening of the gas discharge pipe, and which have a plurality of through-holes for rectifying the etching gas, each rectifying plate being disposed below the blow-out opening of the gas introduction pipe and above the suction opening of the gas discharge pipe.

Description

Technical Field

[0001] The invention relates to a gas phase etching device, a method for removing an oxide film on a silicon wafer surface and a method for manufacturing an epitaxial silicon wafer. Background Art

[0002] In recent years, epitaxial silicon wafers obtained by forming a silicon epitaxial layer on the surface of a large polished silicon wafer have been used in cutting-edge semiconductor device processes. It is known that in the manufacturing process of epitaxial silicon wafers, due to the high-temperature process when forming the silicon epitaxial layer, dopants such as boron added to the wafer diffuse into the gas phase, causing the diffused dopants to mix into the epitaxial layer. The problem of auto-doping occurs.

[0003] In order to solve this problem, it is known that there is a technology of preventing the diffusion of dopants by forming an oxide film on the back side of a silicon wafer before forming a silicon epitaxial layer. On the other hand, when an oxide film is formed on the back side of a silicon wafer, the oxide film is sometimes formed to the edge of the front side. If a silicon epitaxial layer is formed on the oxide film, it becomes a cause of particles on the silicon wafer, so the oxide film formed on the edge of the silicon wafer is usually removed. For example, a method for removing an oxide film is disclosed in patent document 1, wherein after an oxide film is formed on the back side of a semiconductor wafer, the semiconductor wafer is transported into the chamber of a vapor etching device having a chamber with a horizontal ceiling, and after the wafer formed with the oxide film is placed horizontally with the back side facing downward on a stage arranged horizontally in the chamber, an etching gas is supplied to the semiconductor wafer, and the redundant oxide film formed on the edge of the semiconductor wafer is removed by vapor etching.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: Japanese Patent Application Publication No. 2012-222014 Summary of the invention

[0007] Problems to be solved by the invention

[0008] By using the oxide film removal method described in patent document 1, the oxide film formed on the surface of the silicon wafer can be uniformly removed. However, with the high precision of semiconductor technology in recent years, it is increasingly required to improve the accuracy of vapor etching. Therefore, the object of the present invention is to provide a vapor etching device that can more uniformly remove the oxide film formed on the surface of the silicon wafer, a method for removing the oxide film on the surface of the silicon wafer, and a method for manufacturing an epitaxial silicon wafer.

[0009] Solutions to Solve Problems

[0010] To solve the above problems, the inventors conducted intensive research and found that by appropriately providing a rectifying plate in a gas phase etching apparatus, the etching gas can be uniformly contacted with the wafer surface. That is, the gist of the present invention is as follows.

[0011] (1) A vapor etching device comprising:

[0012] A gas introduction pipe is used to introduce etching gas from a blowing port located in the reaction container.

[0013] a wafer placement stage which is exposed to the etching gas and is located below the blowing port of the gas introduction pipe, and

[0014] a gas exhaust pipe for exhausting the etching gas to the outside of the reaction container from an intake port located in the reaction container and below the wafer placement stage,

[0015] The gas phase etching device further comprises two or more rectifying plates, which are arranged on the side walls in the reaction container and are spanned between the side walls and have a plurality of through holes to rectify the etching gas.

[0016] Each of the rectifying plates is disposed at a position below the outlet of the gas introduction pipe and at a position above the inlet of the gas discharge pipe.

[0017] (2) The vapor etching device according to (1), wherein the rectifying plate includes a first rectifying plate and a second rectifying plate which are separated from each other and arranged in parallel,

[0018] The first rectifying plate is disposed at a position above the placement surface of the wafer placement stage.

[0019] The second rectifying plate is provided at a position below the placement surface of the wafer placement stage.

[0020] (3) The vapor etching device according to (1) or (2), wherein the rectifying plate further includes a third rectifying plate that is separated from and arranged in parallel with the first rectifying plate and the second rectifying plate,

[0021] The third rectifying plate is provided between the first rectifying plate and the mounting surface of the wafer mounting stage.

[0022] (4) The vapor etching apparatus according to any one of (1) to (3), wherein the surface of the rectifying plate is formed of an acid-resistant resin.

[0023] (5) The vapor etching apparatus according to (4), wherein the acid-resistant resin is formed using any one of polyvinyl chloride, polyvinylidene chloride, polyethylene, polypropylene, and polytetrafluoroethylene.

[0024] (6) The vapor etching apparatus according to any one of (1) to (5), wherein the gas introduction pipe is provided upward from the bottom surface in the reaction container.

[0025] (7) A method for removing an oxide film on a silicon wafer surface, which is a method using the vapor phase etching apparatus according to any one of (1) to (6), wherein:

[0026] A silicon wafer is placed on the stage surface of the wafer placement stage.

[0027] A gas containing hydrogen fluoride is introduced from the gas introduction pipe.

[0028] (8) A method for removing an oxide film from a silicon wafer surface according to (7), wherein the configuration of the rectifying plate is pre-adjusted so that the coefficient of variation of the deviation of the gas flow rate at each point on the peripheral portion of the silicon wafer surface is less than 20%.

[0029] (9) A method for manufacturing an epitaxial silicon wafer, comprising:

[0030] an oxide film removal step, comprising placing a silicon wafer on a stage of the vapor etching apparatus according to any one of (1) to (6), introducing a gas containing hydrogen fluoride from the gas introduction pipe, and removing the oxide film on the silicon wafer; and

[0031] The epitaxial growth process grows a silicon epitaxial layer on the surface of the silicon wafer after the oxide film is removed.

[0032] Effects of the Invention

[0033] According to the present invention, a vapor phase etching apparatus, a vapor phase etching method, and a method for producing an epitaxial silicon wafer can be provided, which are capable of more uniformly removing an oxide film formed on the surface of a silicon wafer.

[0034] In addition, the oxide film can be removed more uniformly, which leads to an improvement in the yield when manufacturing wafers and the yield when manufacturing devices from the wafers.

[0035] The improvement of yield rate can increase the manufacturing efficiency of semiconductor products, produce more high-quality products, and contribute to promoting technological innovation and sustainable development of the industry.

[0036] The improvement in yield reduces the waste of materials consumed in the manufacturing process of semiconductor products and also contributes to the effective use of resources.

[0037] Furthermore, the improvement in yield reduces wasteful energy consumed in the manufacturing process of semiconductor products, and as a result, also contributes to the reduction of greenhouse gas emissions.

[0038] That is, the present invention can contribute to, for example, "Goal 9: Building industry, innovation, and infrastructure", "Goal 12: Ensuring sustainable consumption and production", and "Goal 13: Response to climate change" in the Sustainable Development Goals (SDGs).

[0039] Brief description of the attached figure

[0040] Figure 1 This is a schematic diagram showing the outline of the structure of the vapor etching device according to this embodiment.

[0041] Figure 2 This is a schematic diagram showing an example of a rectifying plate according to the present embodiment.

[0042] Figure 3 This is a schematic diagram showing an example of a rectifying plate according to the present embodiment.

[0043] Figure 4 This is a diagram showing the distribution of the gas flow rate just above the silicon wafer calculated in Comparative Example 1.

[0044] Figure 5 This is a diagram showing the distribution of the gas flow rate just above the silicon wafer calculated in Comparative Example 2.

[0045] Figure 6 This is a diagram showing the distribution of the gas flow rate just above the silicon wafer calculated in Comparative Example 3.

[0046] Figure 7 This is a diagram showing the distribution of the gas flow rate just above the silicon wafer calculated in Example 1-1.

[0047] Figure 8 This is a diagram showing the distribution of the gas flow rate just above the silicon wafer calculated in Example 1-2.

[0048] Fig. 9 This is a diagram showing the distribution of the gas flow rate just above the silicon wafer calculated in Example 1-3. DETAILED DESCRIPTION

[0049] Before describing the implementation mode, the process of the inventors completing the present invention is described. The previously known end oxide film removal device (WREM; Williamson Rogers Edge-etch Module) removes the oxide film formed on the front of the silicon wafer while uniformly removing the oxide film formed on the edge of the silicon wafer. The end oxide film removal device introduces the hydrofluoric acid gas generated by bubbling the hydrofluoric acid solution as an etching gas into the reaction container of the device, and etches the oxide film within the range of the supply control rate. Here, with the increase in the diameter of the wafer, the restrictions on the piping position and the various device components become strict, and it is difficult to etch while rotating the silicon wafer in the circumferential direction, so the silicon wafer is left stationary and gas phase etching is performed. The inventors believe that, considering the increasing demand for high precision of semiconductor processes in recent years, the demand for further uniform removal of oxide films in the silicon oxide film removal process has increased, and the quantification of gas phase etching conditions has been attempted. Therefore, the gas flow rate distribution of the entire in-plane area of ​​the surface of a silicon wafer with a diameter of 300 mm when using a known end oxide film removal device was studied by numerical simulation. It should be noted that the details of the calculation conditions and the like of the numerical simulation will be described in detail in the examples.

[0050] According to the research of the present inventor, it is confirmed that when the oxide film is vapor-phase etched using the previously known end face oxide film removal device, a relatively large unevenness is found in the gas flow rate distribution on the surface of the silicon wafer. Therefore, an attempt is made to improve the gas flow rate distribution on the surface of the silicon wafer by setting a rectifier plate between the side walls in the reaction vessel of the end face oxide film removal device. It should be noted that the rectifier plate is a perforated metal plate-shaped rectifier plate with through holes evenly provided. By setting a rectifier plate in the reaction vessel, the gas flow rate on the surface of the silicon wafer is reduced. However, if the gas flow rate distribution is analyzed in detail, it is clear that whether the rectifier plate is set on the upstream side between the gas inlet pipe and the silicon wafer, or on the downstream side between the silicon wafer and the gas exhaust pipe, in any case, the gas flow rate distribution becomes uneven compared to the case where the rectifier plate is not set. Furthermore, the present inventor conducted in-depth research and found that by setting more than two rectifier plates in the frame, the gas flow rate distribution on the surface of the silicon wafer can be uniformized. The embodiment of the gas phase etching device according to the present invention completed by the above numerical simulation is described in detail.

[0051] (Vapor Etching Equipment)

[0052] Below, refer to Figure 1The gas phase etching device 100 of the present embodiment is described in detail. The gas phase etching device 100 of the present invention comprises: a gas introduction pipe 300, which is arranged in a reaction vessel 110 and introduces an etching gas 200; a wafer loading stage 400, which is exposed to the etching gas 200 and is arranged at a position below the blowing port 310 of the gas introduction pipe 300; and a gas exhaust pipe 500, which discharges the etching gas 200, and the suction port 510 is arranged at a position below the loading surface of the wafer loading stage 400. The gas phase etching device 100 is characterized in that it further comprises two or more rectifying plates 700, which are arranged on the side walls in the reaction vessel 110 and are spanned between the side walls, and have a plurality of through holes to rectify the etching gas 200, and any rectifying plate 700 is arranged at a position below the blowing port 310 of the gas introduction pipe 300, and is arranged at a position above the suction port 510 of the gas exhaust pipe 500. The placement surface of the wafer placement stage 400 can place the silicon wafer 800. It should be noted that a transfer port (not shown) for transferring wafers is provided in the reaction container 110. Hereinafter, the details of each structure of the vapor etching apparatus 100 will be described.

[0053] <Reaction container>

[0054] The reaction vessel 110 has a horizontal ceiling, side walls and bottom surface. The etching gas 200 is introduced into the interior of the reaction vessel 110 and circulated. From the viewpoint of improving etching efficiency, it is preferred to reduce the cross-sectional area of ​​the horizontal plane of the reaction vessel, and of course, the cross-sectional area is at least larger than the area of ​​the main surface of the silicon wafer. The material of the reaction vessel can be the same material used in the reaction vessel of a general end oxide film removal device.

[0055] <Gas introduction pipe>

[0056] The gas introduction pipe 300 is disposed in the reaction container 110. The etching gas 200 can be introduced from the blowing port 310 located at the end of the gas introduction pipe 300. Figure 1 As shown, the gas introduction pipe 300 is preferably arranged upward from the bottom surface of the reaction container 110. By arranging the gas introduction pipe 300 in this way, the etching gas 200 introduced from the blowing port 310 collides with the ceiling of the reaction container 110 and then diffuses in a manner that spreads to the entire reaction container 110, so that the gas flow rate near the silicon wafer can be made uniform. However, the setting position of the gas introduction pipe 300 is not limited to this, and it can also be set from the ceiling of the reaction container 110 toward the bottom surface, and it can also be set on the wall surface. The setting position is arbitrary.

[0057] <Gas Exhaust Pipe>

[0058] The gas exhaust pipe 500 has a suction port 510 disposed below the placement surface of the wafer placement stage 400. The gas exhaust pipe 500 can exhaust the etching gas 200 introduced from the gas introduction pipe 300 from the reaction chamber 110.

[0059] <<Etching Gas>>

[0060] As described above, the etching gas 200 is introduced into the reaction vessel 110 from the blowing port 310 of the gas introduction pipe 300, and the etching gas 200 is discharged from the suction port 510 of the gas discharge pipe 500 to the outside of the reaction vessel 110. There is no particular limitation on the type of the etching gas 200 as long as it can remove the oxide film on the surface of the silicon wafer. For example, fluorocarbons such as CF4 and CHF3 can also be used, but from the perspective of selectively etching SiO2 without etching Si, hydrofluoric acid gas is preferably used. There is no limitation on the introduction form of the etching gas 200. For example, when hydrofluoric acid gas is used as the etching gas 200, the etching gas 200 is preferably introduced into the reaction vessel 110 by bubbling a hydrofluoric acid solution, and the oxide film formed on the surface of the silicon wafer 800 is etched within the range of the supply control rate (roughly 0.04 m / s or less in terms of gas flow rate).

[0061] <Wafer mounting stage>

[0062] The wafer loading stage 400 is a stage for loading the silicon wafer 800, and the material is preferably an acid-resistant resin. Examples of acid-resistant resins include polyvinyl chloride, polyvinylidene chloride, polyethylene, polypropylene, polytetrafluoroethylene, and the like. In addition, in order to perform etching on the peripheral portion of the back side of the wafer, the shape of the stage may be made smaller than the wafer size, so that the edge of the silicon wafer 800 protrudes and the peripheral portion of the back side of the wafer is exposed. In this case, by adjusting the diameter of the stage, the area of ​​the region to be etched on the peripheral portion of the back side of the wafer can be adjusted. The wafer loading stage 400 may also be capable of rotating the wafer, but Figure 1 The method is to place the wafer at rest without rotating the wafer. Even in this case, by providing the rectifying plate 700, the gas flow rate distribution on the wafer surface can be made uniform.

[0063] <Rectifier Plate>

[0064] The rectifying plate 700 rectify the etching gas 200 introduced from the gas inlet pipe 300. In the present embodiment, two or more rectifying plates 700 are arranged in the reaction vessel 110. The rectifying plate 700 is preferably arranged to be erected between the side walls in the reaction vessel 110 and arranged horizontally. There is no limitation on the arrangement method. For example, a mounting portion, a fixing portion, a protrusion, a supporting portion, a coupling device, etc. may be provided on the side wall of the reaction vessel 110, and the rectifying plate 700 may be fixed using them. Any rectifying plate 700 is arranged at a position below the blowing port 310 of the gas inlet pipe 300, and is arranged at a position above the suction port 510 of the gas exhaust pipe 500.

[0065] like Figure 1 As shown in the figure, the rectifying plate 700 preferably includes a first rectifying plate 710 and a second rectifying plate 720 which are separated from each other and arranged in parallel. It is preferred that the first rectifying plate 710 is provided at a position above the mounting surface of the wafer mounting stage 400, and the second rectifying plate 720 is provided at a position below the mounting surface of the wafer mounting stage 400. In addition, it is preferred that the rectifying plate 700 further includes a third rectifying plate 730 which is separated from the first rectifying plate 710 and the second rectifying plate 720 and arranged in parallel, and the third rectifying plate 730 is preferably provided between the first rectifying plate 710 and the mounting surface of the wafer mounting stage 400.

[0066] In addition, the material of the rectifying plate 700 is preferably an acid-resistant resin. Examples of the acid-resistant resin include polyvinyl chloride, polyvinylidene chloride, polyethylene, polypropylene, and polytetrafluoroethylene.

[0067] -Through hole-

[0068] The rectifying plate 700 has a plurality of through holes, and the etching gas 200 is rectified by passing through the through holes, so that the gas flow rate is uniformed on the wafer surface and the edge of the wafer. The form of the through holes provided on the rectifying plate 700 is not particularly limited, and for example, a perforated metal plate may be used. It should be noted that in addition to the through holes for rectification, a hole portion for avoiding interference with components in the reaction container 110 such as the gas introduction pipe 300 and the wafer mounting stage 400 may also be provided on the rectifying plate 700.

[0069] Figure 2 1 and 1 are specific examples of top views of the first rectifying plate 710 and the second rectifying plate 720, respectively. Figure 3 9 and 9 are another specific example of a top view of the first rectifying plate 710 and the second rectifying plate 720. The hole portion 920 is provided to avoid interference between the rectifying plates 710 and 720 and the gas introduction pipe 300. In addition, a plurality of through holes 910 are evenly provided in the surface of each rectifying plate. Figure 2 , Figure 3In any of the examples, the through holes are arranged in a grid pattern, and the through holes are preferably arranged uniformly. In addition, the second rectifying plate 720 is further provided with a hole portion 930 for avoiding interference with the wafer placement stage 400.

[0070] The diameter of the through hole 910 is not particularly limited, and can be set to be, for example, 2 mm or more and 10 mm or less. For example, it can be set to φ5 mm. The shape of each hole of the through hole 910 is not limited. Figure 2 , 3 In the example of the through hole 910, the through hole 910 is circular, but may be elliptical or polygonal. The distance between the outer edges of adjacent holes in the through hole 910 is not particularly limited, and may be set to be greater than 2 mm and less than 25 mm, and may be set to 10 mm as an example. In each rectifier plate, the shape, size, and configuration relationship of the through hole 910 may be the same or different.

[0071] As described above, by using the vapor etching apparatus according to this embodiment, the gas flow rate distribution on the surface of the silicon wafer installed in the apparatus can be made uniform, so that the oxide film can be removed more uniformly than before.

[0072] (Vapor phase etching method)

[0073] The gas phase etching method of the present invention is a method for removing an oxide film on the surface of a silicon wafer, which is a method for performing gas phase etching using the gas phase etching device of the present invention, wherein a silicon wafer is placed on a table of a wafer placement stage, and a gas containing hydrogen fluoride is introduced from the aforementioned gas inlet.

[0074] At this time, it is preferred to pre-adjust the configuration of the rectifier plate so that the coefficient of variation of the above-mentioned deviation of the gas flow rate at each point on the peripheral portion of the silicon wafer surface is less than 20%. For example, the setting position of the rectifier plate can be adjusted in the up and down direction, or a rectifier plate with different through hole sizes can be used. The value of the coefficient of variation and the variance required for calculating the coefficient of variation can be obtained by numerically calculating the gas flow rate distribution. It should be noted that the method for calculating the variance and the coefficient of variation is generally known, and is specifically shown below.

[0075]

Mathematical formula 1

[0076]

[0077] In the above formula, n is the number of samples.

[0078] (Method for manufacturing epitaxial silicon wafer)

[0079] In the manufacturing method of the epitaxial silicon wafer of the present invention, it is characterized in that the oxide film on the surface of the silicon wafer is removed using the above-mentioned vapor phase etching device of the present invention. More specifically, it includes: an oxide film removal step, in which a silicon wafer is placed on the stage of the vapor phase etching device, and a gas containing hydrogen fluoride is introduced from the aforementioned gas inlet to remove the oxide film of the aforementioned silicon wafer; and an epitaxial growth step, in which a silicon epitaxial layer is grown on the surface of the front side of the silicon wafer after the oxide film is removed. It should be noted that the silicon wafer can be a conventionally known silicon wafer, and can also be obtained by conventionally known methods. The epitaxial silicon wafer obtained by this manufacturing method has excellent flatness of the front side and edge of the silicon epitaxial layer because the oxide film on the front side and edge of the wafer is removed more evenly.

[0080] Hereinafter, examples of the present invention will be described, but the present invention is not limited to the examples.

[0081] Example

[0082] For ease of explanation, refer to Figure 1 . The gas flow velocity distribution on the front surface of the silicon wafer 800 when the silicon wafer 800 having a diameter of 300 mm is placed on the wafer loading stage 400 in the above-mentioned vapor etching device 100 (hereinafter referred to as "the gas flow velocity distribution on the silicon wafer") is calculated. The finite volume method is used in the calculation.

[0083] (Comparative Example 1)

[0084] The gas velocity distribution on the silicon wafer 800 without the rectifying plate is calculated in the gas phase etching device 100. In addition, the gas velocity distribution at a height of 1 mm from the surface of the front side of the silicon wafer 800 (hereinafter referred to as "the gas velocity distribution directly above the silicon wafer") is shown in FIG. Figure 4 .for Figures 5 to 9 Same here.

[0085] (Comparative Example 2)

[0086] In the gas phase etching device 100, the gas flow velocity distribution on the silicon wafer 800 is calculated in a state where only the second rectifying plate 720 is provided, which is located below the silicon wafer and is provided between the wafer mounting stage 400 and the suction port 510 of the gas exhaust pipe 500. The second rectifying plate 720 is in the shape of a perforated metal plate except for the hole portion (920, 930) for avoiding interference with the components in the reaction vessel 110. The aperture of the through hole 910 of the second rectifying plate 720 is φ5 mm, and the distance between the outer edges of the holes is uniform and is 10 mm (the distance between the centers of the holes is 15 mm). The gas flow velocity distribution directly above the silicon wafer of Comparative Example 2 is shown in FIG. Figure 5 .

[0087] (Comparative Example 3)

[0088] In the gas phase etching apparatus 100, the gas flow velocity distribution on the silicon wafer 800 is calculated in a state where only the first rectifying plate 710 is provided above the silicon wafer and between the wafer loading stage 400 and the blowing port 310 of the gas introduction pipe 300. The conditions of the through hole 910 other than the hole portion (920, 930) for avoiding interference with the components in the reaction container 110 are the same as those of the second rectifying plate 720 in Comparative Example 2. The gas flow velocity distribution directly above the silicon wafer of Comparative Example 3 is shown in FIG. Figure 6 .

[0089] (Example 1-1)

[0090] In the gas phase etching apparatus 100, the gas flow velocity distribution on the silicon wafer 800 is calculated in a state where a first rectifying plate 710 is provided above the silicon wafer and between the wafer loading stage 400 and the blowing port 310 of the gas introduction pipe 300, and a second rectifying plate 720 is provided below the silicon wafer and between the wafer loading stage 400 and the suction port 510 of the gas exhaust pipe 500. The conditions of the through hole 910 other than the hole portion (920, 930) for avoiding interference with the components in the reaction vessel 110 are the same as those of the second rectifying plate 720 and the first rectifying plate 710 in Comparative Examples 1 and 2. The gas flow velocity distribution directly above the silicon wafer of Example 1-1 is shown in Figure 7 .

[0091] (Example 1-2)

[0092] In the gas phase etching apparatus 100 of Example 1-1, the third rectifying plate 730 is further arranged between the wafer loading stage 400 and the first rectifying plate 710, and the gas flow velocity distribution on the silicon wafer 800 is calculated. The conditions of the through hole 910 other than the hole portion (920, 930) for avoiding interference with the components in the reaction container 110 are the same as those of the first rectifying plate 710 and the second rectifying plate 720. The gas flow velocity distribution directly above the silicon wafer of Example 1-2 is shown in Figure 8 .

[0093] (Example 1-3)

[0094] The gas flow velocity distribution on the silicon wafer 800 was calculated in a state where the second rectifying plate 720 disposed between the gas phase etching apparatus 100 of Example 1-2 and the suction port 510 of the gas discharge pipe 500 was removed. The gas flow velocity distribution directly above the silicon wafer of Example 1-3 is shown in FIG. Fig. 9 .

[0095] (Example 2-1)

[0096] The hole diameter of each rectifying plate in Example 1-1 was changed from φ5mm to φ1mm, and the distance between the outer edges of the holes was changed to 14mm to maintain the center-to-center distance of the holes at 15mm. Apart from this, the gas flow rate distribution on the silicon wafer 800 was calculated in the same manner as in Example 1-1.

[0097] (Example 2-2)

[0098] The hole diameter of each rectifying plate in Example 1-1 is changed from φ5mm to φ3mm. At the same time, in order to maintain the center-to-center distance of the holes at 15mm, the distance between the outer edges of the holes is changed to 12mm. Apart from this, the gas flow rate distribution on the silicon wafer 800 is calculated in the same manner as in Example 1-1.

[0099] (Example 2-3)

[0100] The hole diameter of each rectifying plate in Example 1-1 was changed from φ5mm to φ8mm, and the distance between the outer edges of the holes was changed to 7mm to maintain the center-to-center distance of the holes at 15mm. Apart from this, the gas flow rate distribution on the silicon wafer 800 was calculated in the same manner as in Example 1-1.

[0101] (Example 3-1)

[0102] The gas flow velocity distribution on the silicon wafer 800 was calculated in the same manner as in Example 1-1, except that the center-to-center distance between the holes of each rectifying plate in Example 1-1 was changed from 15 mm to 20 mm and the distance between the outer edges of the holes was changed to 15 mm.

[0103] (Example 3-2)

[0104] The gas flow velocity distribution on the silicon wafer 800 was calculated in the same manner as in Example 1-1, except that the center-to-center distance between the holes of each rectifying plate in Example 1-1 was changed from 15 mm to 30 mm and the distance between the outer edges of the holes was changed to 25 mm.

[0105] In addition, the rectifying plate setting conditions, through hole conditions and the calculated gas flow rates at each point on the peripheral portion of the silicon wafer surface in the above-mentioned embodiments and comparative examples are shown in the following Table 1. The average velocity, variance and coefficient of variation are recorded as the gas flow rate in Table 1. It should be noted that the average velocity, variance and coefficient of variation of the gas flow rate are calculated based on the gas flow rate of 2880 points generated by the intersection of 4 scales set at 1 mm each in the area 147 to 150 mm from the center of the wafer in the radial direction, 10 scales set at 1 mm each in the area 1 to 10 mm from the front side in the height direction of the wafer, and 72 scales set at 5° each in the 360° range of the circumferential direction of the wafer.

[0106]

Table 1

[0107]

[0108] ※Distance between the outer edges of the holes

[0109] <Evaluation>

[0110] First, from Figures 4 to 9 As shown in the gas flow rate distribution, it can be seen that the gas flow rate can be greatly changed by setting the rectifying plate either above or below the silicon wafer, but only one plate cannot fully suppress the deviation of the gas flow rate. On the other hand, it can be confirmed that by setting more than two rectifying plates, the deviation of the gas flow rate can be suppressed. It should be noted that although the average speed without the rectifying plate is faster than other levels, it is believed that this is because there is a part of uneven flow from top to bottom. In addition, according to the calculation results of Examples 2-1 to 2-3 and Examples 3-1 to 3-2, it was confirmed that the smaller the aperture and the narrower the hole spacing, the lower the coefficient of variation of the gas flow rate.

[0111] Industrial Applicability

[0112] According to the present invention, a vapor phase etching apparatus, a vapor phase etching method, and a method for producing an epitaxial silicon wafer can be provided, which are capable of more uniformly removing an oxide film formed on the surface of a silicon wafer.

[0113] Explanation of symbols

[0114] 100 Vapor etching device

[0115] 110 reaction vessel

[0116] 200 Etching Gas

[0117] 300 Gas inlet pipe

[0118] 310 Blowing Outlet

[0119] 400 Wafer loading stage

[0120] 500 Gas exhaust pipe

[0121] 510 suction port

[0122] 710, 720, 730 rectifier plate

[0123] 910 Through hole

[0124] 920, 930 hole

Claims

1. A vapor etching device, comprising: A gas introduction pipe is used to introduce etching gas from a blowing port located in the reaction container. a wafer placement stage which is exposed to the etching gas and is located below the blowing port of the gas introduction pipe, and a gas exhaust pipe for exhausting the etching gas to the outside of the reaction container from an intake port located in the reaction container and below the wafer placement stage, The gas phase etching device further comprises two or more rectifying plates, which are arranged on the side walls in the reaction container and are spanned between the side walls and have a plurality of through holes to rectify the etching gas. Each of the rectifying plates is disposed at a position below the outlet of the gas introduction pipe and at a position above the inlet of the gas discharge pipe.

2. vapor etching device according to claim 1, wherein, The rectifying plate includes a first rectifying plate and a second rectifying plate which are separated from each other and arranged in parallel. The first rectifying plate is disposed at a position above the placement surface of the wafer placement stage. The second rectifying plate is provided at a position below the placement surface of the wafer placement stage.

3. vapor phase etching device according to claim 2, wherein, The rectifying plate further includes a third rectifying plate that is separated from and arranged in parallel with the first rectifying plate and the second rectifying plate. The third rectifying plate is provided between the first rectifying plate and the mounting surface of the wafer mounting stage.

4. vapor phase etching device according to claim 1, wherein, The surface of the rectifying plate is formed of an acid-resistant resin.

5. vapor phase etching device according to claim 4, wherein, The acid-resistant resin is formed of any one of polyvinyl chloride, polyvinylidene chloride, polyethylene, polypropylene, and polytetrafluoroethylene.

6. vapor phase etching device according to claim 1, wherein, The gas introduction pipe is provided upward from the bottom surface in the reaction container.

7. A method for removing an oxide film on a silicon wafer surface, using the vapor phase etching apparatus according to any one of claims 1 to 6, wherein: A silicon wafer is placed on the stage surface of the wafer placement stage. A gas containing hydrogen fluoride is introduced from the gas introduction pipe.

8. The method for removing an oxide film on a silicon wafer surface according to claim 7, wherein: The arrangement of the rectifying plates is adjusted in advance so that the coefficient of variation of the gas flow rate at each point on the peripheral portion of the surface of the silicon wafer becomes 20% or less.

9. A method for manufacturing an epitaxial silicon wafer, comprising: an oxide film removal step, placing a silicon wafer on a stage of the vapor etching apparatus according to any one of claims 1 to 6, introducing a gas containing hydrogen fluoride from the gas introduction pipe to remove the oxide film on the silicon wafer, and The epitaxial growth process grows a silicon epitaxial layer on the surface of the silicon wafer after the oxide film is removed.

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