Preparation method of semiconductor interconnection structure

Abstract

According to the preparation method of the semiconductor interconnection structure provided by the invention, the passivation layer can be formed on the surface of the metal seed layer on the side wall of the upper part of the groove and the surface of the metal seed layer on the top of the dielectric layer by passivating the surface of the metal seed layer, and the metal layer cannot be formed on the surface of the passivation layer in the subsequent electroplating process. The forming rate of the metal layer on the side wall of the upper portion of the groove can be reduced, so that the forming rate of the metal layer on the upper portion of the groove is slower than that of the metal layer on the lower portion of the groove, and the sealing speed of the top of the groove is reduced. Meanwhile, the passivation layer can be reduced into metal which is the same as the metal layer in material, namely, the passivation layer can be decomposed into metal ions in electroplating liquid, and the metal ions can be reduced into metal at the bottom of the groove in the process of executing the electroplating process, so that deposition of the metal layer at the lower part of the groove can be accelerated; therefore, the metal layer is gradually deposited from the bottom of the groove to the top, and defects such as gaps or holes in the metal layer are avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a method for preparing a semiconductor interconnection structure. Background Art

[0002] With the continuous development of semiconductor technology, the characteristic size of semiconductor integrated circuit devices is constantly shrinking. Due to the miniaturization of device size, the size of the trench or through hole as the interconnection structure is also constantly shrinking, making the aspect ratio of the trench or through hole larger and larger. Therefore, when the trench or through hole is filled with a metal seed layer, an overhang will be generated at the top opening of the trench or through hole. Specifically, Figure 1 As shown, a dielectric layer 11 is formed on a substrate 10, and a groove 11a is formed in the dielectric layer 11. When a metal seed layer 12 is deposited in the groove 11a, an overhang (such as Figure 1 as shown in the dashed box). Figure 2 As shown, when the groove 11a is subsequently filled with the metal layer 13, the top of the groove 11a will be sealed in advance before the metal layer 13 fills the groove 11a. Figure 3 As shown, since the top of the trench 11a is sealed in advance when the metal layer is filled, a hole 13a or a gap is generated inside the metal layer 13, thereby affecting the conductivity and reliability of the interconnection structure. Summary of the invention

[0003] The object of the present invention is to provide a method for preparing a semiconductor interconnect structure to solve the void or gap defects generated when a metal layer is filled in a trench.

[0004] In order to solve the above technical problems, the present invention provides a method for preparing a semiconductor interconnect structure, comprising:

[0005] Providing a substrate, wherein a dielectric layer is formed on the substrate, and a groove is formed in the dielectric layer;

[0006] forming a metal seed layer, wherein the metal seed layer covers the sidewalls and bottom of the trench and the top of the dielectric layer, and the thickness of the metal seed layer on the upper sidewall of the trench is greater than the thickness of the metal seed layer on the lower sidewall of the trench;

[0007] Passivating the surface of the metal seed layer to form a passivation layer on the surface of the metal seed layer on the upper sidewall of the trench and on the surface of the metal seed layer on the top of the dielectric layer;

[0008] The substrate is placed in an electroplating solution and an electroplating process is performed to fill a metal layer in the groove. The material of the metal layer is the same as that of the metal seed layer, and the electroplating solution has a reducing property on the passivation layer. The passivation layer is reduced during the electroplating process.

[0009] Optionally, in the method for preparing the semiconductor interconnect structure, the material of the metal layer and the material of the metal seed layer both include copper, and when performing the electroplating process, copper is gradually deposited from the bottom of the trench to form the metal layer.

[0010] Optionally, in the method for preparing the semiconductor interconnect structure, the passivation treatment performed on the surface of the metal seed layer includes oxidation treatment and / or nitridation treatment.

[0011] Optionally, in the method for preparing the semiconductor interconnect structure, the oxidation treatment is performed by a rapid thermal oxidation process or a plasma oxidation process; and the nitridation treatment is performed by a plasma nitridation process.

[0012] Optionally, in the method for preparing the semiconductor interconnect structure, the process gas used in the rapid thermal oxidation process includes oxygen or ozone, the process gas used in the plasma oxidation process includes oxygen plasma; and the process gas used in the plasma nitridation process includes nitrogen plasma.

[0013] Optionally, in the method for preparing the semiconductor interconnect structure, an angle is formed between the incident direction of the process gas and the surface of the substrate, and the angle is an acute angle.

[0014] Optionally, in the method for preparing the semiconductor interconnect structure, when the surface of the metal seed layer is passivated, the substrate is rotated around the central axis of the substrate.

[0015] Optionally, in the method for preparing the semiconductor interconnect structure, before forming the metal seed layer, the method further includes:

[0016] A barrier layer is formed, wherein the barrier layer covers the sidewall and bottom of the trench and the top of the dielectric layer, and the metal seed layer covers the barrier layer.

[0017] Optionally, in the method for preparing the semiconductor interconnect structure, the electroplating solution includes copper sulfate and hydrochloric acid.

[0018] Optionally, in the method for preparing the semiconductor interconnect structure, the aspect ratio of the trench is greater than 4.

[0019] In the preparation method of the semiconductor interconnect structure provided by the present invention, by passivating the surface of the metal seed layer, a passivation layer can be formed on the surface of the metal seed layer on the upper side wall of the groove and the surface of the metal seed layer on the top of the dielectric layer. When the electroplating process is subsequently performed, no metal layer will be formed on the surface of the passivation layer, which can reduce the formation rate of the metal layer on the upper side wall of the groove, so that the formation rate of the metal layer on the upper part of the groove is slower than the formation rate of the metal layer on the lower part of the groove, thereby slowing down the sealing speed of the top of the groove, and promoting the full deposition of the metal layer in the groove. At the same time, since the electroplating solution has a reducing property on the passivation layer, the material of the metal layer is the same as that of the metal seed layer, so the passivation layer can be reduced to the same metal as the material of the metal layer, that is, the passivation layer can be decomposed into metal ions in the electroplating solution, and in the process of performing the electroplating process, the metal ions can be reduced to metal at the bottom of the groove, thereby accelerating the deposition of the metal layer at the lower part of the groove, thereby realizing the gradual deposition of the metal layer from the bottom of the groove to the top, and avoiding defects such as gaps or holes in the metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figures 1 to 3 It is a schematic diagram of the steps of forming a metal layer in the prior art;

[0021] Figure 4 is a schematic flow chart of a method for preparing a semiconductor interconnect structure provided by an embodiment of the present invention;

[0022] Figure 5 to Figure 12 is a schematic cross-sectional view of a structure formed in a method for preparing a semiconductor interconnect structure provided by an embodiment of the present invention;

[0023] The following are the descriptions of the reference numerals:

[0024] 10-substrate; 11-dielectric layer; 11a-groove; 12-metal seed layer; 13-metal layer; 13a-hole;

[0025] 100 - substrate; 110 - dielectric layer; 110a - trench; 120 - barrier layer; 130 - metal seed layer; 140 - passivation layer; 150 - metal layer; 150a - metal ions. DETAILED DESCRIPTION

[0026] The following is a further detailed description of the method for preparing the semiconductor interconnect structure proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0027] Figure 4 FIG. 1 is a flow chart of a method for preparing a semiconductor interconnect structure provided by an embodiment of the present invention. Figure 4As shown, this embodiment provides a method for preparing a semiconductor interconnect structure, comprising:

[0028] Step S1: providing a substrate, wherein a dielectric layer is formed on the substrate, and a groove is formed in the dielectric layer;

[0029] Step S2: forming a metal seed layer, wherein the metal seed layer covers the sidewalls and bottom of the trench and the top of the dielectric layer, and the thickness of the metal seed layer on the upper sidewall of the trench is greater than the thickness of the metal seed layer on the lower sidewall of the trench;

[0030] Step S3: performing a passivation treatment on the surface of the metal seed layer to form a passivation layer on the surface of the metal seed layer on the upper sidewall of the trench and on the surface of the metal seed layer on the top of the dielectric layer;

[0031] Step S4: placing the substrate in a plating solution and performing an electroplating process to fill the groove with a metal layer, wherein the material of the metal layer is the same as that of the metal seed layer, and the plating solution has a reducing property on the passivation layer, and the passivation layer is reduced during the electroplating process.

[0032] Figure 5 to Figure 12 FIG. 1 is a schematic cross-sectional view of a structure formed in a method for preparing a semiconductor interconnect structure provided by an embodiment of the present invention. Figure 5 to Figure 12 The method for preparing the semiconductor interconnect structure provided in this embodiment is described in more detail.

[0033] refer to Figure 5 As shown, step S1 is performed to provide a substrate 100, on which a dielectric layer 110 is formed, and a groove 110a is formed in the dielectric layer 110. The material of the substrate 100 may include any suitable base material known to those skilled in the art, for example, the substrate 100 in this embodiment may be a silicon substrate. The substrate 100 may have structures formed by the front-end process, such as shallow trenches, gates, source and drain electrodes, contact holes or through holes, etc., and may also have device structures that require electrical extraction, such as transistors, etc.

[0034] In this embodiment, the material of the dielectric layer 110 may include but is not limited to silicon oxide or silicon nitride. It should be noted that an intermediate layer may also be provided between the dielectric layer 110 and the substrate 100, which is not specifically limited here. It should be noted that the material of the dielectric layer 110 may be selected according to actual device requirements. The groove 110a penetrates a portion of the thickness of the dielectric layer 110.

[0035] For example, the number of the grooves 110a formed in the dielectric layer 110 may be multiple, and the multiple grooves 110a are arranged at intervals in the dielectric layer 110. The multiple grooves 110a may be arranged at equal intervals in the dielectric layer 110, or may be arranged at unequal intervals. Figure 5 It is only taken as an example that one trench 110 a is formed in the dielectric layer 110 , and the actual number of the trenches 110 a is not limited thereto.

[0036] Exemplarily, the cross-sectional shape of the groove 110a can be set according to actual needs. Preferably, in this embodiment, the cross-sectional shape of the groove 110a can include any shape that can be filled, such as a rectangle or a U-shape. In this embodiment, the groove 110a is preferably a groove with a high aspect ratio. For example, the aspect ratio of the groove 110a can be greater than 4.

[0037] Next, refer to Figure 7 As shown, step S2 is performed to form a metal seed layer 130, the metal seed layer 130 covers the sidewalls and bottom of the trench 110a and the top of the dielectric layer 110, and the thickness of the metal seed layer 130 on the upper sidewall of the trench 110a is greater than the thickness of the metal seed layer 130 on the lower sidewall of the trench 110a. Since the trench 110a is a trench with a high aspect ratio, during the process of forming the metal seed layer 130, the thickness of the metal seed layer 130 on the upper sidewall of the trench 110a is greater than the thickness of the metal seed layer 130 on the lower sidewall of the trench 110a, that is, an overhang is formed on the upper sidewall of the trench 110a.

[0038] The metal seed layer 130 may be made of copper and may be formed by a physical vapor deposition process. The metal seed layer 130 may be used to grow a metal body. The thickness of the metal seed layer 130 may be controlled between 2 nm and 50 nm; the thickness of the metal seed layer 130 may be defined according to the process.

[0039] refer to Figure 6 As shown, before forming the metal seed layer 130, a barrier layer 120 can be formed first, and the barrier layer 120 covers the sidewalls and bottom of the groove 110a and the top of the dielectric layer 110, that is, the barrier layer 120 covers the surface of the groove 110a and extends to cover the top of the dielectric layer 110, and the metal seed layer 130 covers the barrier layer 120.

[0040] Optionally, the material of the barrier layer 120 may be, but is not limited to, titanium, titanium nitride, titanium tungsten, tungsten nitride, cobalt nitride or any combination thereof. It should be noted that the material of the barrier layer 120 may be selected according to actual device requirements.

[0041] The barrier layer 120 may be formed by, but is not limited to, an atmospheric pressure chemical vapor deposition (APCVD) process, a low pressure chemical vapor deposition (LPCVD) process, a plasma enhanced chemical vapor deposition (PECVD) process, a high-density plasma chemical vapor deposition (HDPCVD) process, a radical enhanced chemical vapor deposition (RECVD) process or an atomic layer deposition (ALD) process. The barrier layer 120 may be used to prevent metal from diffusing into the dielectric layer 110 and the substrate 100.

[0042] Next, refer to Fig. 9 As shown, step S3 is performed to passivate the surface of the metal seed layer 130 to form a passivation layer 140 on the surface of the metal seed layer 130 on the upper sidewall of the groove 110a and on the surface of the metal seed layer 130 on the top of the dielectric layer 110. It should be noted that the passivation treatment referred to in this embodiment refers to the structure itself reacting with the reactive medium to generate the passivation layer 140 attached to the surface of the structure. By passivating the surface of the metal seed layer 130, a portion of the thickness of the metal seed layer 130 on the upper sidewall of the groove 110a and a portion of the thickness of the metal seed layer 130 on the top of the dielectric layer 110 can be converted into the passivation layer 140.

[0043] In this embodiment, the passivation treatment performed on the surface of the metal seed layer 130 includes oxidation treatment, and the passivation layer 140 may be an oxide layer, and the material of the passivation layer may be, for example, a copper oxide layer. Fig. 9 As shown, the surface of the metal seed layer 130 can be oxidized by a rapid thermal oxidation process (RTO) or a plasma oxidation process, so that the metal seed layer 130 with a partial thickness on the upper side wall of the groove 110a and the top of the dielectric layer 110 is oxidized and consumed to form a passivation layer 140.

[0044] The rapid thermal oxidation process is achieved by using an oxidation furnace or a rapid thermal annealing chamber, using oxygen (O2) or ozone (O3) as a process gas to perform thermal oxidation treatment on the metal seed layer 130 on the upper part of the groove 110a and the metal seed layer 130 on the top of the dielectric layer 110, thereby forming a passivation layer 140 on the surface of the metal seed layer 130 on the upper sidewall of the groove 110a and the surface of the metal seed layer 130 on the top of the dielectric layer 110. The plasma oxidation process refers to using a plasma chemical vapor deposition machine, using oxygen plasma as a process gas, to perform plasma oxidation treatment on the metal seed layer 130 on the upper part of the groove 110a and the metal seed layer 130 on the top of the dielectric layer 110, thereby forming a passivation layer 140 on the surface of the metal seed layer 130 on the upper sidewall of the groove 110a and the surface of the metal seed layer 130 on the top of the dielectric layer 110.

[0045] In another embodiment, the passivation treatment performed on the surface of the metal seed layer 130 includes a nitridation treatment, and the passivation layer 140 may be a nitride layer, and the material of the passivation layer may be, for example, copper nitride. Specifically, the nitridation treatment may be performed using a plasma nitridation process, so that a portion of the thickness of the metal seed layer 130 on the upper sidewall of the groove 110a and the top of the dielectric layer 110 is consumed by nitridation to form the passivation layer 140. The plasma nitridation process refers to using a plasma chemical vapor deposition machine and nitrogen plasma as a process gas to perform plasma nitridation treatment on the metal seed layer 130 on the upper part of the groove 110a and the metal seed layer 130 on the top of the dielectric layer 110, thereby forming the passivation layer 140 on the surface of the metal seed layer 130 on the upper sidewall of the groove 110a and the surface of the metal seed layer 130 on the top of the dielectric layer 110.

[0046] In another embodiment, the passivation treatment performed on the surface of the metal seed layer 130 includes oxidation treatment and nitridation treatment, and the passivation layer 140 may be a nitride oxide layer, and the material of the passivation layer may be, for example, copper oxynitride. Specifically, the surface of the metal seed layer 130 may be oxidized first, and then nitrided; or, the surface of the metal seed layer 130 may be passivated using a mixed gas of oxygen and nitrogen as a process gas; or, the surface of the metal seed layer 130 may be passivated using a mixed plasma of oxygen plasma and nitrogen plasma as a process gas, so that the metal seed layer 130 with a thickness of a portion of the upper sidewall of the groove 110a and the top of the dielectric layer 110 is consumed by nitridation to form the passivation layer 140.

[0047] refer to Figure 8 As shown, there is an angle between the incident direction of the working gas used in the oxidation treatment and the nitridation treatment and the surface of the substrate 100, and the angle is an acute angle. Figure 8 The oblique arrow above the metal seed layer 130 indicates the incident direction of the process gas. The angle between the specific incident direction of the process gas and the surface of the substrate 100 can be set according to the actual morphology of the groove 110a.

[0048] Exemplarily, the angle between the specific incident direction of the process gas and the surface of the substrate 100 may be between 15° and 75°, so as to control the passivation region on the surface of the metal seed layer 130 at the upper part of the groove 110a and the surface of the metal seed layer 130 at the top of the dielectric layer 110. For example, the angle may be 15°, 20°, 25°, 30°, 40°, 45°, 55°, 70° or 75°, etc. In this embodiment, the angle between the incident direction of the process gas and the surface of the substrate 100 may be set according to the morphological characteristics of the groove 110a, so as to further improve the control and effect of the passivation region of the metal seed layer 130.

[0049] In this embodiment, by controlling the incident direction of the process gas, the passivation region of the metal seed layer 130 can be accurately controlled to form a passivation layer 140 that meets the requirements. Fig. 9 As shown, a partial thickness of the metal seed layer 130 on the upper side wall of the groove 110a is passivated, and the metal seed layer 130 on the lower side wall and the bottom of the groove 110a is not passivated. When the electroplating process is subsequently performed, the metal layer 150 will not be formed on the surface of the passivation layer 140, which can reduce the formation rate of the metal layer 150 on the upper side wall of the groove 110a, so that the formation rate of the metal layer 150 on the upper part of the groove 110a is slower than the formation rate of the metal layer 150 on the lower part of the groove 110a, thereby slowing down the sealing speed of the top of the groove 110a, and promoting the sufficient deposition of the metal layer 150 in the groove 110a, thereby improving the filling effect of the metal layer 150.

[0050] In this embodiment, when the passivation treatment is performed, the substrate 100 is also rotated around the central axis of the substrate 100, which can be clockwise or counterclockwise, to achieve uniform passivation, so as to form a passivation layer 140 with uniform thickness on the surface of the metal seed layer 130 on the upper side wall of the groove 110a and the surface of the metal seed layer 130 on the top of the dielectric layer 110. The substrate 100 can be rotated by arranging a motor or a mechanical arm under the substrate 100.

[0051] Next, refer to Fig.12As shown, step S4 is performed to place the substrate 100 in an electroplating solution and perform an electroplating process to fill the groove 110a with a metal layer 150, wherein the material of the metal layer 150 is the same as that of the metal seed layer 130, and the electroplating solution has a reducing property on the passivation layer 140, and the passivation layer 140 is reduced during the electroplating process. Specifically, the material of the metal layer 150 is copper (CU), that is, the material of the metal layer 150 is the same as that of the metal seed layer 130, and can form an integrated metal structure with the metal seed layer 130.

[0052] In this embodiment, the metal layer 150 can fill the trench 110a and extend to the outside of the trench 110a to cover the metal seed layer on the top of the dielectric layer. The metal layer 150 can be used as a conductive layer or a metal plug of a semiconductor interconnect structure.

[0053] Specifically, the process of placing the substrate 100 in the electroplating solution and performing the electroplating process includes the following three stages: Fig.10 As shown, in the first stage, the metal layer 150 is filled in the lower part of the groove 110a, and the passivation layer 140 of a part of the thickness is reduced by the electroplating solution. Since the passivation layer 140 is formed on the surface of the metal seed layer 130 on the upper sidewall of the groove 110a and the surface of the metal seed layer 130 on the top of the dielectric layer 110, the metal layer 150 will not be formed on the surface of the passivation layer 140, so the metal layer 150 is only deposited on the lower sidewall and bottom of the groove 110a. Further, the electroplating solution includes copper sulfate and hydrochloric acid, and the electroplating solution also includes additives, and the additives include a leveling agent, an inhibitor and an accelerator.

[0054] Since the electroplating solution includes copper sulfate, and the passivation layer 140 is an oxide layer, a nitride layer, or a nitride oxide layer, the electroplating solution has a reducing property on the passivation layer 140, so during the electroplating process, the passivation layer 140 is reduced to metal. Since the material of the metal layer 150 is the same as that of the metal seed layer 130, the passivation layer 140 can be reduced to the same metal as the material of the metal layer 150, that is, the passivation layer 140 is dissolved in the electroplating solution, and the passivation layer 140 can be decomposed into metal ions 150a in the electroplating solution. Specifically, as shown in FIG. Fig.10 As shown, in the first stage, a partial thickness of the passivation layer 140 is decomposed by the electroplating solution to form metal ions 150a. The metal ions 150a are located inside the groove. During the electroplating process, the metal ions 150a can easily reach the bottom of the groove 110a and be reduced to metal, that is, the copper ions can obtain electrons at the bottom of the groove 110a and be reduced to a metal state, thereby accelerating the deposition of the metal layer 150 at the bottom of the groove 110a.

[0055] like Fig.11As shown, in the second stage, the metal layer 150 fills the lower part of the groove 110a, and the passivation layer 140 is completely dissolved by the electroplating solution. Due to the existence of the passivation layer 140 in the upper part of the groove 110a, the formation rate of the metal layer 150 in the upper part of the groove 110a is slower than the formation rate of the metal layer 150 in the lower part of the groove 110a, thereby slowing down the sealing speed of the top of the groove 110a. Therefore, after the lower part of the groove 110a is filled with the metal layer 150, the upper part of the groove 110a, that is, the top of the groove 110a, still has a large opening, which can promote the full deposition of the metal layer 150 in the groove 110a.

[0056] like Fig.12 As shown, in the third stage, the metal layer 150 fills up the trench 110a. Since the passivation layer 140 is completely dissolved, the metal seed layer 130 on the upper sidewall of the trench 110a and the metal seed layer 130 on the top of the dielectric layer 110 are exposed. Therefore, in this stage, the metal layer 150 is deposited on the surface of the metal seed layer 130 on the upper sidewall of the trench 110a, so that the metal layer 150 fills up the trench 110a. In addition, the metal layer 150 can also extend to the surface of the metal seed layer 130 on the top of the dielectric layer 110. During the electroplating process, since the metal layer 150 will not be formed on the surface of the passivation layer 140, the formation rate of the metal layer 150 in the upper part of the groove 110a can be slower than the formation rate of the metal layer 150 in the lower part of the groove 110a, so that the metal layer 150 can be gradually deposited from the bottom of the groove 110a to the top, that is, when performing the electroplating process, copper can be gradually deposited from the bottom of the groove 110a to the top to form the metal layer 150, thereby avoiding defects such as gaps or holes in the metal layer 150, thereby improving the conductivity and reliability of the interconnection structure.

[0057] In addition, since the material of the metal layer 150 is the same as that of the metal seed layer 130 , the electroplating solution has a reducing property to the passivation layer 140 , and therefore, there is no need to add a removal step, thereby simplifying the preparation process.

[0058] From the above, it can be seen that in the method for preparing the semiconductor interconnect structure provided by the embodiment of the present invention, by passivating the surface of the metal seed layer, a passivation layer can be formed on the surface of the metal seed layer on the upper side wall of the groove and the surface of the metal seed layer on the top of the dielectric layer. When the electroplating process is subsequently performed, no metal layer will be formed on the surface of the passivation layer, which can reduce the formation rate of the metal layer on the upper side wall of the groove, so that the formation rate of the metal layer on the upper part of the groove is slower than the formation rate of the metal layer on the lower part of the groove, thereby slowing down the sealing speed of the top of the groove. At the same time, the passivation layer can be reduced to a metal of the same material as the metal layer, that is, the passivation layer can be decomposed into metal ions in the electroplating solution. In the process of performing the electroplating process, the metal ions can be reduced to metal at the bottom of the groove, thereby accelerating the deposition of the metal layer at the lower part of the groove, thereby realizing the gradual deposition of the metal layer from the bottom of the groove to the top, and avoiding defects such as gaps or holes in the metal layer.

[0059] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A method for preparing a semiconductor interconnect structure, characterized in that: include: Providing a substrate, wherein a dielectric layer is formed on the substrate, and a groove is formed in the dielectric layer; forming a metal seed layer, wherein the metal seed layer covers the sidewalls and bottom of the trench and the top of the dielectric layer, and the thickness of the metal seed layer on the upper sidewall of the trench is greater than the thickness of the metal seed layer on the lower sidewall of the trench; Passivating the surface of the metal seed layer to form a passivation layer on the surface of the metal seed layer on the upper sidewall of the trench and on the surface of the metal seed layer on the top of the dielectric layer; The substrate is placed in an electroplating solution and an electroplating process is performed to fill a metal layer in the groove. The material of the metal layer is the same as that of the metal seed layer, and the electroplating solution has a reducing property on the passivation layer. The passivation layer is reduced during the electroplating process.

2. The method for preparing a semiconductor interconnect structure according to claim 1, wherein: The material of the metal layer and the material of the metal seed layer both include copper. When the electroplating process is performed, copper is gradually deposited from the bottom of the trench to form the metal layer.

3. The method for preparing a semiconductor interconnect structure according to claim 1, wherein: The passivation treatment performed on the surface of the metal seed layer includes oxidation treatment and / or nitridation treatment.

4. The method for preparing a semiconductor interconnect structure according to claim 3, characterized in that: The oxidation treatment is performed by adopting a rapid thermal oxidation process or a plasma oxidation process; and the nitridation treatment is performed by adopting a plasma nitridation process.

5. The method for preparing a semiconductor interconnect structure according to claim 4, characterized in that: The process gas used in the rapid thermal oxidation process includes oxygen or ozone, the process gas used in the plasma oxidation process includes oxygen plasma, and the process gas used in the plasma nitridation process includes nitrogen plasma.

6. The method for preparing a semiconductor interconnect structure according to claim 5, characterized in that: An angle is formed between the incident direction of the working gas and the surface of the substrate, and the angle is an acute angle.

7. The method for preparing a semiconductor interconnect structure according to claim 1, wherein: When the surface of the metal seed layer is passivated, the substrate is rotated around the central axis of the substrate.

8. The method for preparing a semiconductor interconnect structure according to claim 1, wherein: Before forming the metal seed layer, the method further includes: A barrier layer is formed, wherein the barrier layer covers the sidewall and bottom of the trench and the top of the dielectric layer, and the metal seed layer covers the barrier layer.

9. The method for preparing a semiconductor interconnect structure according to claim 1, wherein: The electroplating solution includes copper sulfate and hydrochloric acid.

10. The method for preparing a semiconductor interconnect structure according to claim 1, wherein: The aspect ratio of the trench is greater than 4.

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