Double-sided heat dissipation structure of power semiconductor device and preparation method of double-sided heat dissipation structure

Abstract

The invention discloses a double-sided heat dissipation structure of a power semiconductor device and a preparation method of the double-sided heat dissipation structure. The double-sided heat dissipation structure comprises a first-class hot end substrate 10, a first conductor layer, a first-class cold end substrate 15, a first-class cold end substrate third line layer 16, a plurality of power semiconductor chips 18, a plurality of thermal interface materials 30, a second-class cold end substrate sixth line layer 29, a plurality of second-class cold end substrates 28, a second conductor layer, a third conductor layer and a second-class hot end substrate 23 which are sequentially arranged from bottom to top, the lower surface of the first thermal interface material is connected with a third circuit layer 16 of the first-class cold-end substrate through a copper clamp 21, and the second conductor layer and the third conductor layer are arranged in parallel. According to the invention, the cold-end substrate is directly integrated on the lower surface of the power chip to avoid the problem of large contact thermal resistance caused by a thermal interface material, and meanwhile, the cold-end substrate is integrated on the upper surface of the power chip to realize double-sided efficient heat dissipation of the power chip.

Description

Technical Field

[0001] The present invention belongs to the technical field of heat dissipation of power semiconductor devices, and in particular relates to a double-sided heat dissipation structure of a power semiconductor device and a preparation method thereof. Background Art

[0002] In the rapidly developing field of power semiconductor technology, power semiconductor chips are core components for power conversion and control, and their performance stability and reliability are directly related to the operating efficiency and safety of the entire electronic system. However, with the continuous evolution of modern electronic systems towards high integration and high power density, the heat generated by power semiconductor chips during operation has increased dramatically, and the heat dissipation problem has become a key bottleneck restricting further improvement of their performance. In addition, local thermal failure of power chips may cause mechanical failure of heterogeneous interconnection interfaces, including interface thermal stress failure, mechanical embrittlement / weakening, chemical reactions at the interconnection interface, and impurity diffusion, which seriously affect the performance, reliability and service life of power devices.

[0003] Power semiconductor devices mostly use the traditional fin heat dissipation method, that is, metal fins are installed on the lower surface of the substrate through thermal interface materials to accelerate the transfer and dissipation of heat by increasing the heat dissipation area. Although this method has alleviated the heat dissipation pressure of the chip to a certain extent, the introduction of the fin structure also brings disadvantages that cannot be ignored. On the one hand, the heat conduction path between the fin and the chip is long, and the thermal resistance of the fin material is often high, which to a certain extent hinders the rapid heat dissipation and reduces the heat dissipation efficiency. On the other hand, the fin heat dissipation method mainly relies on the heat dissipation area on the chip surface, while ignoring the three-dimensional heat conduction characteristics inside the chip, which makes the heat unevenly distributed inside the chip, exacerbating the local overheating phenomenon. More importantly, the traditional heat dissipation method is often limited to the single-sided heat dissipation of the chip, and the heat is mainly conducted outward through one side of the lower surface of the chip. In high power density application scenarios, this heat dissipation method may cause the chip temperature to rise sharply, seriously affecting its working stability and service life, and further restricting the performance improvement of power semiconductor devices. In addition, the single-sided heat dissipation method may also cause uneven temperature distribution inside the chip, resulting in local hot spots, further exacerbating the heat dissipation problem of the chip. Summary of the invention

[0004] In order to solve the above technical problems, the present invention proposes a double-sided heat dissipation structure of a power semiconductor device and a preparation method thereof, which directly integrates a cold end substrate on the lower surface of the power chip to avoid the problem of large contact thermal resistance caused by the thermal interface material, and also integrates a cold end substrate on the upper surface of the power chip to achieve double-sided efficient heat dissipation of the power chip. This method can greatly reduce the temperature extremes of the power chip in high power density scenarios, solve the problem of local overheating failure of the chip, and achieve double-sided heat dissipation of the power semiconductor device.

[0005] The present invention provides a double-sided heat dissipation structure of a power semiconductor device, comprising: a first type of hot end substrate, a first conductor layer, a first type of cold end substrate, a third circuit layer of the first type of cold end substrate, a plurality of power semiconductor chips, a plurality of thermal interface materials, a sixth circuit layer of a second type of cold end substrate, a plurality of second type of cold end substrates, a second conductor layer, a third conductor layer and a second type of hot end substrate are sequentially arranged from bottom to top, wherein the lower surface of the first thermal interface material is connected to the third circuit layer of the first type of cold end substrate through a copper clip, and the second conductor layer and the third conductor layer are arranged in parallel.

[0006] Optionally, the first conductor layer includes: a plurality of regularly arranged hot-end substrate circuit layers, a plurality of N-type semiconductors, a plurality of P-type semiconductors and a plurality of cold-end substrate circuit layers, wherein a class of N-type semiconductors and a class of P-type semiconductors are alternately arranged between the class of hot-end substrate circuit layers and the class of cold-end substrate circuit layers, and a certain gap is left between the class of N-type semiconductors and the class of P-type semiconductors, and the regular arrangement is: the lower end of the class of N-type first semiconductors is aligned with the right edge of the first circuit layer of the class of hot-end substrates, the upper end of the class of N-type first semiconductors is aligned with the left edge of the first circuit layer of the class of cold-end substrates, the upper end of the class of P-type first semiconductors is aligned with the right side of the first circuit layer of the class of cold-end substrates, and the lower end of the class of P-type first semiconductors is aligned with the left edge of the second circuit layer of the class of hot-end substrates.

[0007] Optionally, the third circuit layer of the first-type cold-end substrate is provided with a plurality of circuit layers of the first-type cold-end substrate, wherein a first solder layer is provided on the first circuit layer of the first-type cold-end substrate, an upper surface of the first solder layer is connected to a lower surface of a first power semiconductor chip, an upper surface of the first power semiconductor chip is connected to an upper surface of a second circuit layer of the first-type cold-end substrate via a bonding wire, and an upper surface of the first power semiconductor chip is also connected to one end of a copper clip via a second welding layer;

[0008] The other end of the copper clip is connected to the third circuit layer of a type of cold end substrate through a second welding layer;

[0009] The third circuit layer of the first type of cold end substrate is further provided with a first solder layer, the upper surface of the first solder layer is connected to the lower surface of the second power semiconductor chip, the upper surface of the second power semiconductor chip is connected to the upper surface of the fourth circuit layer of the first type of cold end substrate through a bonding wire, and the upper surface of the second power semiconductor chip is also connected to one end of the copper clip through a second solder layer;

[0010] The other end of the copper clip is connected to the fifth circuit layer of a type of cold end substrate through a second welding layer.

[0011] Optionally, power terminals are also provided on the first welding layer on the first circuit layer of the first type of cold end substrate and the fifth circuit layer of the first type of cold end substrate.

[0012] Optionally, the second conductor layer and the third conductor layer both include: a number of regularly arranged second-type hot-end substrate circuit layers, a number of second-type N-type semiconductors, a number of second-type P-type semiconductors and a number of second-type cold-end substrate circuit layers, wherein the second-type N-type semiconductors and the second-type P-type semiconductors are alternately arranged between the second-type hot-end substrate circuit layers and the second-type cold-end substrate circuit layers, and a certain gap is left between the second-type N-type semiconductors and the second-type P-type semiconductors, and the regular arrangement is: the lower end of the second-type N-type first semiconductor is aligned with the left edge of the first circuit layer of the second-type hot-end substrate, the upper end of the second-type N-type first semiconductor is aligned with the right edge of the first circuit layer of the second-type cold-end substrate, the upper end of the second-type P-type first semiconductor is aligned with the left side of the second circuit layer of the second-type cold-end substrate, and the lower end of the second-type P-type first semiconductor is aligned with the right edge of the second circuit layer of the second-type hot-end substrate.

[0013] Optionally, the thickness of the first type of hot end substrate, the first type of cold end substrate, and the second type of hot end substrate are all 0.5 to 3.0 mm, and the thickness of the second type of cold end substrate is 0.2 to 0.8 mm.

[0014] Optionally, the heights of the first type N-type semiconductor and the first type P-type semiconductor are both 1 to 5 mm, and the heights of the second type N-type semiconductor and the second type P-type semiconductor are both 0.2 to 1 mm. The directions of the currents passing through the N-type semiconductor and the P-type semiconductor are opposite, forming a certain temperature difference between the upper and lower surfaces of the semiconductor.

[0015] Optionally, the material of the power semiconductor chip is one of gallium nitride, silicon carbide and silicon;

[0016] The thermal interface material is one of thermal conductive silicone grease, nano silver and nano copper;

[0017] The material of the first solder layer and the second solder layer is one or more of gold-tin, tin-lead, tin-silver-copper, tin-bismuth, nano-silver, and nano-copper;

[0018] The material of the bonding wire is one of aluminum wire, aluminum ribbon and copper wire.

[0019] The present invention also provides a method for preparing a double-sided heat dissipation structure of a power semiconductor device, comprising:

[0020] S1, obtaining a first type of hot end substrate, a first type of N-type semiconductor, a first type of P-type semiconductor, a first type of cold end substrate, a second type of hot end substrate, a second type of N-type semiconductor, a second type of P-type semiconductor, and a second type of cold end substrate;

[0021] S2, interconnecting the lower surfaces of the first type of N-type semiconductor and the first type of P-type semiconductor with the first circuit layer on the upper surface of the first type of hot end substrate, interconnecting the upper surfaces of the first type of N-type semiconductor and the first type of P-type semiconductor with the second circuit layer on the lower surface of the first type of cold end substrate, interconnecting the upper surfaces of the second type of N-type semiconductor and the second type of P-type semiconductor with the fourth circuit layer on the lower surface of the second type of hot end substrate, and interconnecting the lower surfaces of the second type of N-type semiconductor and the second type of P-type semiconductor with the fifth circuit layer on the upper surface of the second type of cold end substrate;

[0022] S3, interconnecting the power semiconductor chip and the lower surface of the power terminal with the third circuit layer on the upper surface of a type of cold end substrate through the first solder layer;

[0023] The upper surface of the power semiconductor chip is electrically connected to the third circuit layer on the upper surface of a type of cold end substrate through bonding wires;

[0024] S4, interconnecting the lower surface of the left end of the copper clip with the upper surface of the power semiconductor chip through the second solder layer, and interconnecting the lower surface of the right end of the copper clip with the third circuit layer on the upper surface of a type of cold end substrate through the second solder layer;

[0025] S5. Interconnect the sixth circuit layer on the lower surface of the second type cold end substrate and the upper surface of the left end of the copper clip through a thermal interface material, thereby obtaining a double-sided heat dissipation structure for a power semiconductor device.

[0026] Compared with the prior art, the present invention has the following advantages and technical effects:

[0027] 1. Aiming at the problems of low heat dissipation efficiency and large thermal resistance of the existing metal fin heat dissipation method, the present invention proposes a double-sided heat dissipation structure for power semiconductor devices. The problem of large contact thermal resistance caused by thermal interface materials is avoided by directly integrating a cold end substrate on the lower surface of the power chip. At the same time, a cold end substrate is also integrated on the upper surface of the power chip to achieve double-sided efficient heat dissipation of the power chip.

[0028] 2. The present invention integrates a plurality of N-type semiconductors, P-type semiconductors and a cold-end substrate structure into a hot-end substrate above the power chip, and is therefore applicable to the field of double-sided heat dissipation of multi-chip power devices, and can integrate a plurality of cold-end substrates in the copper clip area on the upper surface of a plurality of chips.

[0029] 3. In the conventional structure, the upper surface of the chip is connected to the bonding wire, which is relatively thin and difficult to conduct heat. Therefore, this structure cannot enable the chip to dissipate heat from the upper surface. The present invention changes the bonding wire on the upper surface of the chip to a copper clip connection. Unlike the bonding wire, the area where the copper clip contacts the chip is a plane. Therefore, multiple cold end substrates can be integrated in the copper clip area, and in conjunction with the cold end substrate under the chip, the chip heat can be transferred bidirectionally, which greatly improves the heat dissipation performance of the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0031] Figure 1 1 is a double-sided heat dissipation structure diagram of a power semiconductor device according to an embodiment of the present invention, wherein 10 is a type-I hot end substrate, 11 is a type-I hot end substrate first circuit layer, 12 is a type-I N-type semiconductor, 13 is a type-I P-type semiconductor, 14 is a type-I cold end substrate second circuit layer, 15 is a type-I cold end substrate, 16 is a type-I cold end substrate third circuit layer, 17 is a first solder layer, 18 is a power semiconductor chip, 19 is a power terminal, 20 is a bonding wire, 21 is a copper clip, 22 is a second solder layer, 23 is a type-II hot end substrate, 24 is a type-II hot end substrate fourth circuit layer, 25 is a type-II N-type semiconductor, 26 is a type-II P-type semiconductor, 27 is a type-II cold end substrate fifth circuit layer, 28 is a type-II cold end substrate, 29 is a type-II cold end substrate sixth circuit layer, and 30 is a thermal interface material. DETAILED DESCRIPTION

[0032] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0033] It should be noted that the steps shown in the flowcharts of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and that, although a logical order is shown in the flowcharts, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0034] This embodiment proposes a double-sided heat dissipation structure for a power semiconductor device, such as Figure 1 As shown, specifically including:

[0035] From bottom to top, a first type of hot end substrate 10, a first conductor layer, a first type of cold end substrate 15, a third circuit layer 16 of the first type of cold end substrate, a plurality of power semiconductor chips 18, a plurality of thermal interface materials 30, a sixth circuit layer 29 of the second type of cold end substrate, a plurality of second type of cold end substrates 28, a second conductor layer, a third conductor layer and a second type of hot end substrate 23 are arranged in sequence, wherein the lower surface of the first thermal interface material is connected to the third circuit layer 16 of the first type of cold end substrate through a copper clip 21, and the second conductor layer and the third conductor layer are arranged in parallel.

[0036] Specifically, the double-sided heat dissipation structure includes: a first type of hot end substrate 10, a first type of N-type semiconductor 12, a first type of P-type semiconductor 13, a first type of cold end substrate 15, a power semiconductor chip 18, a power terminal 19, a bonding wire 20, a copper clip 21, a second type of hot end substrate 23, a second type of N-type semiconductor 25, a second type of P-type semiconductor 26, and a second type of cold end substrate 28. A first type of N-type semiconductor and a first type of P-type semiconductor are alternately arranged between the first type of hot end substrate and the first type of cold end substrate, and a second type of N-type semiconductor and a second type of P-type semiconductor are alternately arranged between the second type of hot end substrate and the second type of cold end substrate. The lower surface of the power semiconductor chip and the power terminal is interconnected with the upper surface of the cold end substrate, the lower surface of the left end of the copper clip is interconnected with the upper surface of the power semiconductor chip, the lower surface of the right end is interconnected with the upper surface of the cold end substrate, and the upper surface of the left end of the copper clip is interconnected with the lower surface of the second type of cold end substrate.

[0037] Furthermore, the first conductor layer includes: a plurality of hot-end substrate circuit layers, a plurality of N-type semiconductors 12, a plurality of P-type semiconductors 13 and a plurality of cold-end substrate circuit layers arranged regularly, wherein a plurality of N-type semiconductors 12 and a plurality of P-type semiconductors 13 are alternately arranged between the hot-end substrate circuit layers and the cold-end substrate circuit layers, a certain gap is left between the N-type semiconductors 12 and the P-type semiconductors 13, and the regular arrangement is: the lower end of the N-type first semiconductor is aligned with the right edge of the first circuit layer of the hot-end substrate, the upper end of the N-type first semiconductor is aligned with the left edge of the first circuit layer of the cold-end substrate, the upper end of the P-type first semiconductor is aligned with the right side of the first circuit layer of the cold-end substrate, and the lower end of the P-type first semiconductor is aligned with the left edge of the second circuit layer of the hot-end substrate.

[0038] Specifically, a second circuit layer is arranged on the lower surface of a type of cold end substrate, and a third circuit layer is arranged on the upper surface; the upper surfaces of a type of N-type semiconductor and a type of P-type semiconductor are interconnected with the second circuit layer; the lower surfaces of the power semiconductor chip and the power terminal are interconnected with the third circuit layer through the first solder layer; and the lower surface of the right end of the copper clip is interconnected with the third circuit layer through the second solder layer.

[0039] Further, the third circuit layer 16 of the first type of cold end substrate is provided with a plurality of circuit layers of the first type of cold end substrate, wherein a first solder layer is provided on the first circuit layer of the first type of cold end substrate, the upper surface of the first solder layer is connected to the lower surface of the first power semiconductor chip, the upper surface of the first power semiconductor chip is connected to the upper surface of the second circuit layer of the first type of cold end substrate through a bonding wire 20, and the upper surface of the first power semiconductor chip is also connected to one end of the copper clip through a second welding layer;

[0040] The other end of the copper clip is connected to the third circuit layer of a type of cold end substrate through a second welding layer;

[0041] The third circuit layer of the first type cold end substrate is also provided with a first solder layer, the upper surface of the first solder layer is connected to the lower surface of the second power semiconductor chip, the upper surface of the second power semiconductor chip is connected to the upper surface of the fourth circuit layer of the first type cold end substrate through a bonding wire 20, and the upper surface of the second power semiconductor chip is also connected to one end of the copper clip through a second solder layer;

[0042] The other end of the copper clip is connected to the fifth circuit layer of a type of cold end substrate through a second welding layer.

[0043] Furthermore, power terminals are also provided on the first welding layer on the first circuit layer of a type of cold end substrate and the fifth circuit layer of a type of cold end substrate.

[0044] Furthermore, the second conductor layer and the third conductor layer both include: a plurality of regularly arranged second-type hot-end substrate circuit layers (second-type hot-end substrate fourth circuit layers 24), a plurality of second-type N-type semiconductors 25, a plurality of second-type P-type semiconductors 26 and a plurality of second-type cold-end substrate circuit layers (second-type cold-end substrate fifth circuit layers 27), wherein the second-type N-type semiconductors 25 and the second-type P-type semiconductors 26 are alternately arranged between the second-type hot-end substrate circuit layers and the second-type cold-end substrate circuit layers, and a certain gap is left between the second-type N-type semiconductors 25 and the second-type P-type semiconductors 26, and the regular arrangement is: the lower end of the second-type N-type first semiconductor is aligned with the left edge of the first circuit layer of the second-type hot-end substrate, the upper end of the second-type N-type first semiconductor is aligned with the right edge of the first circuit layer of the second-type cold-end substrate, the upper end of the second-type P-type first semiconductor is aligned with the left side of the second circuit layer of the second-type cold-end substrate, and the lower end of the second-type P-type first semiconductor is aligned with the right edge of the second circuit layer of the second-type hot-end substrate.

[0045] Specifically, a fifth circuit layer is arranged on the upper surface of the second type cold end substrate, a sixth circuit layer is arranged on the lower surface, the lower surfaces of the second type N-type semiconductors and the second type P-type semiconductors are interconnected with the fifth circuit layer, and the upper surface of the left end of the copper clip is interconnected with the sixth circuit layer on the lower surface of the second type cold end substrate through a thermal interface material.

[0046] Furthermore, the thickness of the first type hot end substrate 10, the first type cold end substrate 15, and the second type hot end substrate 23 are all 0.5-3.0 mm, and the thickness of the second type cold end substrate 28 is 0.2-0.8 mm.

[0047] Furthermore, the heights of the first type N-type semiconductor 12 and the first type P-type semiconductor 13 are both 1 to 5 mm, and the heights of the second type N-type semiconductor 25 and the second type P-type semiconductor 26 are both 0.2 to 1 mm. The current directions passing through the N-type semiconductor and the P-type semiconductor are opposite, forming a certain temperature difference between the upper and lower surfaces of the semiconductor.

[0048] Further, the material of the power semiconductor chip 18 is one of gallium nitride, silicon carbide, and silicon;

[0049] The thermal interface material 30 is one of thermal conductive silicone grease, nano silver, and nano copper;

[0050] The materials of the first solder layer 17 and the second solder layer 22 are one or more of gold-tin, tin-lead, tin-silver-copper, tin-bismuth, nano-silver, and nano-copper;

[0051] The material of the bonding wire 20 is one of aluminum wire, aluminum ribbon, and copper wire.

[0052] This embodiment also provides a method for preparing a double-sided heat dissipation structure of a power semiconductor device, comprising:

[0053] S1, obtaining a first type of hot end substrate 10, a first type of N-type semiconductor 12, a first type of P-type semiconductor 13, a first type of cold end substrate 15, a second type of hot end substrate 23, a second type of N-type semiconductor 25, a second type of P-type semiconductor 26, and a second type of cold end substrate 28;

[0054] S2, interconnecting the lower surface of a type of N-type semiconductor 12 and a type of P-type semiconductor 13 with the first circuit layer of the upper surface of a type of hot end substrate 10, interconnecting the upper surface of a type of N-type semiconductor 12 and a type of P-type semiconductor 13 with the second circuit layer of the lower surface of a type of cold end substrate 15, interconnecting the upper surface of a type of N-type semiconductor 25 and a type of P-type semiconductor 26 with the fourth circuit layer of the lower surface of a type of hot end substrate 23, and interconnecting the lower surface of a type of N-type semiconductor 25 and a type of P-type semiconductor 26 with the fifth circuit layer of the upper surface of a type of cold end substrate 28;

[0055] S3, interconnecting the lower surface of the power semiconductor chip 18 and the power terminal 19 with the third circuit layer on the upper surface of the first type of cold end substrate 15 through the first solder layer 17;

[0056] The upper surface of the power semiconductor chip 18 is electrically connected to the third circuit layer on the upper surface of a type of cold end substrate 15 through a bonding wire 20;

[0057] S4, interconnecting the lower surface of the left end of the copper clip 21 with the upper surface of the power semiconductor chip 18 through the second solder layer 22, and interconnecting the lower surface of the right end of the copper clip 21 with the third circuit layer on the upper surface of the first type of cold end substrate through the second solder layer 22;

[0058] S5. The sixth circuit layer on the lower surface of the second type cold end substrate 23 and the upper surface of the left end of the copper clip 21 are interconnected through the thermal interface material 30, thereby obtaining a double-sided heat dissipation structure of the power semiconductor device.

[0059] The present embodiment is described in detail below with reference to the accompanying drawings:

[0060] Embodiment 1

[0061] like Figure 1As shown, the first embodiment of the present invention provides a double-sided heat dissipation structure of a silicon carbide power device and a preparation method thereof, wherein the high-efficiency active heat dissipation structure comprises: a first-class hot-end substrate 10, a first-class N-type semiconductor 12, a first-class P-type semiconductor 13, a first-class cold-end substrate 15, a power semiconductor chip 18, a power terminal 19, a bonding wire 20, a copper clip 21, a second-class hot-end substrate 23, a second-class N-type semiconductor 25, a second-class P-type semiconductor 26, a second-class cold-end substrate 28, a first-class hot-end substrate 10 and a first-class A type of N-type semiconductor 12 and a type of P-type semiconductor 13 are alternately arranged between the cold-end substrates 15, a type of N-type semiconductor 25 and a type of P-type semiconductor 26 are alternately arranged between the type of hot-end substrate 23 and the type of cold-end substrate, the lower surface of the power semiconductor chip 18 and the power terminal 19 are interconnected with the upper surface of the cold-end substrate, the lower surface of the left end of the copper clip 21 is interconnected with the upper surface of the power semiconductor chip, the lower surface of the right end is interconnected with the upper surface of the cold-end substrate 15, and the upper surface of the left end of the copper clip is interconnected with the lower surface of the type of cold-end substrate;

[0062] Preferably, the thickness of the first type hot end substrate, the first type cold end substrate, and the second type hot end substrate are all 2.0 mm, and the thickness of the second type cold end substrate is 0.5 mm;

[0063] Preferably, the height of the first type of N-type semiconductor and the first type of P-type semiconductor are both 2 mm, the height of the second type of N-type semiconductor and the second type of P-type semiconductor are both 0.8 mm, and the currents passing through the N-type semiconductor and the P-type semiconductor are in opposite directions, forming a certain temperature difference between the upper and lower surfaces of the semiconductor;

[0064] Preferably, the first type of hot end substrate, the first type of cold end substrate, the second type of hot end substrate, and the second type of cold end substrate are all ceramics, and the material thereof is alumina;

[0065] Preferably, a first circuit layer is disposed on the upper surface of a type of hot end substrate, and a type of N-type semiconductor and a type of P-type semiconductor are interconnected with the first circuit layer on their lower surfaces;

[0066] Preferably, a second circuit layer is arranged on the lower surface of a cold end substrate, a third circuit layer is arranged on the upper surface, an N-type semiconductor and a P-type semiconductor are interconnected on the upper surface with the second circuit layer, a power semiconductor chip and a power terminal are interconnected on the lower surface with the third circuit layer through a first solder layer, and a copper clip is interconnected on the lower surface of the right end with the third circuit layer through a second solder layer;

[0067] Preferably, a fourth circuit layer is arranged on the lower surface of the second type hot end substrate, and the upper surfaces of the second type N-type semiconductor and the second type P-type semiconductor are interconnected with the fourth circuit layer; a fifth circuit layer is arranged on the upper surface of the second type cold end substrate, and a sixth circuit layer is arranged on the lower surface, and the lower surfaces of the second type N-type semiconductor and the second type P-type semiconductor are interconnected with the fifth circuit layer, and the upper surface of the left end of the copper clip is interconnected with the sixth circuit layer on the lower surface of the second type cold end substrate through a thermal interface material;

[0068] Preferably, the power semiconductor chip is made of silicon carbide, the upper surface of which is interconnected with the lower surface of the left end of the copper clip through a second solder layer, and the upper surface of which is electrically connected to the third circuit layer on the upper surface of a cold end substrate through a bonding wire;

[0069] Preferably, the thermal interface material is thermally conductive silicone grease, the first solder layer is nanosilver, and the second solder layer is tin-silver-copper;

[0070] Preferably, the bonding wire is an aluminum wire;

[0071] Embodiment 1 of the present invention further provides a method for preparing a double-sided heat dissipation structure of a power semiconductor device, the method comprising the following steps:

[0072] The first step is to provide a first type of hot end substrate 10, a first type of N-type semiconductor 12, a first type of P-type semiconductor 13, a first type of cold end substrate 15, a second type of hot end substrate 23, a second type of N-type semiconductor 25, a second type of P-type semiconductor 26, and a second type of cold end substrate 28, interconnect the lower surfaces of the first type of N-type semiconductor and the first type of P-type semiconductor with the first circuit layer 11 on the upper surface of the first type of hot end substrate, and interconnect the upper surfaces of the second type of N-type semiconductor and the second type of P-type semiconductor with the fourth circuit layer 24 on the lower surface of the second type of hot end substrate;

[0073] In the second step, the upper surfaces of the first type of N-type semiconductors and the first type of P-type semiconductors are interconnected with the second circuit layer 14 on the lower surface of the first type of cold-end substrate, and the lower surfaces of the second type of N-type semiconductors and the second type of P-type semiconductors are interconnected with the fifth circuit layer 27 on the upper surface of the second type of cold-end substrate;

[0074] The third step is to interconnect the power semiconductor chip 18 and the lower surface of the power terminal 19 with the third circuit layer 16 on the upper surface of a type of cold end substrate through the first solder layer 17;

[0075] In the fourth step, the upper surface of the power semiconductor chip 18 is electrically connected to the third circuit layer on the upper surface of a type of cold end substrate through the bonding wire 20;

[0076] Step 5: interconnect the lower surface of the left end of the copper clip with the upper surface of the power semiconductor chip through the second solder layer 22, and interconnect the lower surface of the right end of the copper clip with the third circuit layer on the upper surface of the first type of cold end substrate through the second solder layer;

[0077] In the sixth step, the sixth circuit layer 29 on the lower surface of the second type cold end substrate and the upper surface of the left end of the copper clip are interconnected through the thermal interface material 30, thereby obtaining a double-sided heat dissipation structure of the power semiconductor device.

[0078] Embodiment 2

[0079] like Figure 1As shown, the second embodiment of the present invention provides a double-sided heat dissipation structure of a silicon carbide power device and a preparation method thereof, wherein the high-efficiency active heat dissipation structure comprises: a first-class hot-end substrate 10, a first-class N-type semiconductor 12, a first-class P-type semiconductor 13, a first-class cold-end substrate 15, a power semiconductor chip 18, a power terminal 19, a bonding wire 20, a copper clip 21, a second-class hot-end substrate 23, a second-class N-type semiconductor 25, a second-class P-type semiconductor 26, a second-class cold-end substrate 28, a first-class hot-end substrate 10 and a first-class A type of N-type semiconductor 12 and a type of P-type semiconductor 13 are alternately arranged between the cold-end substrates 15, a type of N-type semiconductor 25 and a type of P-type semiconductor 26 are alternately arranged between the type of hot-end substrate 23 and the type of cold-end substrate, the lower surface of the power semiconductor chip 18 and the power terminal 19 are interconnected with the upper surface of the cold-end substrate, the lower surface of the left end of the copper clip 21 is interconnected with the upper surface of the power semiconductor chip, the lower surface of the right end is interconnected with the upper surface of the cold-end substrate 15, and the upper surface of the left end of the copper clip is interconnected with the lower surface of the type of cold-end substrate;

[0080] Preferably, the thickness of the first type hot end substrate, the first type cold end substrate, and the second type hot end substrate are all 3.0 mm, and the thickness of the second type cold end substrate is 0.8 mm;

[0081] Preferably, the height of the first type of N-type semiconductor and the first type of P-type semiconductor are both 1 mm, the height of the second type of N-type semiconductor and the second type of P-type semiconductor are both 0.2 mm, and the currents passing through the N-type semiconductor and the P-type semiconductor are in opposite directions, forming a certain temperature difference between the upper and lower surfaces of the semiconductor;

[0082] Preferably, the first type of hot end substrate, the first type of cold end substrate, the second type of hot end substrate, and the second type of cold end substrate are all ceramics, and the material thereof is aluminum nitride;

[0083] Preferably, a first circuit layer is disposed on the upper surface of a type of hot end substrate, and a type of N-type semiconductor and a type of P-type semiconductor are interconnected with the first circuit layer on their lower surfaces;

[0084] Preferably, a second circuit layer is arranged on the lower surface of a cold end substrate, a third circuit layer is arranged on the upper surface, an N-type semiconductor and a P-type semiconductor are interconnected on the upper surface with the second circuit layer, a power semiconductor chip and a power terminal are interconnected on the lower surface with the third circuit layer through a first solder layer, and a copper clip is interconnected on the lower surface of the right end with the third circuit layer through a second solder layer;

[0085] Preferably, a fourth circuit layer is arranged on the lower surface of the second type hot end substrate, and the upper surfaces of the second type N-type semiconductor and the second type P-type semiconductor are interconnected with the fourth circuit layer; a fifth circuit layer is arranged on the upper surface of the second type cold end substrate, and a sixth circuit layer is arranged on the lower surface, and the lower surfaces of the second type N-type semiconductor and the second type P-type semiconductor are interconnected with the fifth circuit layer, and the upper surface of the left end of the copper clip is interconnected with the sixth circuit layer on the lower surface of the second type cold end substrate through a thermal interface material;

[0086] Preferably, the power semiconductor chip is made of gallium nitride, the upper surface of which is interconnected with the lower surface of the left end of the copper clip through a second solder layer, and the upper surface of which is electrically connected to the third circuit layer on the upper surface of a type of cold end substrate through a bonding wire;

[0087] Preferably, the thermal interface material is nano copper, the first solder layer is tin-silver-copper, and the second solder layer is tin-bismuth;

[0088] Preferably, the bonding wire is a copper wire;

[0089] The second embodiment of the present invention further provides a method for preparing a double-sided heat dissipation structure of a power semiconductor device, the preparation method comprising the following steps:

[0090] The first step is to provide a first type of hot end substrate 10, a first type of N-type semiconductor 12, a first type of P-type semiconductor 13, a first type of cold end substrate 15, a second type of hot end substrate 23, a second type of N-type semiconductor 25, a second type of P-type semiconductor 26, and a second type of cold end substrate 28, interconnect the lower surfaces of the first type of N-type semiconductor and the first type of P-type semiconductor with the first circuit layer 11 on the upper surface of the first type of hot end substrate, and interconnect the upper surfaces of the second type of N-type semiconductor and the second type of P-type semiconductor with the fourth circuit layer 24 on the lower surface of the second type of hot end substrate;

[0091] In the second step, the upper surfaces of the first type of N-type semiconductors and the first type of P-type semiconductors are interconnected with the second circuit layer 14 on the lower surface of the first type of cold-end substrate, and the lower surfaces of the second type of N-type semiconductors and the second type of P-type semiconductors are interconnected with the fifth circuit layer 27 on the upper surface of the second type of cold-end substrate;

[0092] The third step is to interconnect the power semiconductor chip 18 and the lower surface of the power terminal 19 with the third circuit layer 16 on the upper surface of a type of cold end substrate through the first solder layer 17;

[0093] In the fourth step, the upper surface of the power semiconductor chip 18 is electrically connected to the third circuit layer on the upper surface of a type of cold end substrate through the bonding wire 20;

[0094] Step 5: interconnect the lower surface of the left end of the copper clip with the upper surface of the power semiconductor chip through the second solder layer 22, and interconnect the lower surface of the right end of the copper clip with the third circuit layer on the upper surface of the first type of cold end substrate through the second solder layer;

[0095] In the sixth step, the sixth circuit layer 29 on the lower surface of the second type cold end substrate and the upper surface of the left end of the copper clip are interconnected through the thermal interface material 30, thereby obtaining a double-sided heat dissipation structure of the power semiconductor device.

[0096] Embodiment 3

[0097] like Figure 1As shown, the third embodiment of the present invention provides a double-sided heat dissipation structure of a silicon carbide power device and a preparation method thereof, wherein the high-efficiency active heat dissipation structure comprises: a first-class hot-end substrate 10, a first-class N-type semiconductor 12, a first-class P-type semiconductor 13, a first-class cold-end substrate 15, a power semiconductor chip 18, a power terminal 19, a bonding wire 20, a copper clip 21, a second-class hot-end substrate 23, a second-class N-type semiconductor 25, a second-class P-type semiconductor 26, a second-class cold-end substrate 28, a first-class hot-end substrate 10 and a first-class A type of N-type semiconductor 12 and a type of P-type semiconductor 13 are alternately arranged between the cold-end substrates 15, a type of N-type semiconductor 25 and a type of P-type semiconductor 26 are alternately arranged between the type of hot-end substrate 23 and the type of cold-end substrate, the lower surface of the power semiconductor chip 18 and the power terminal 19 are interconnected with the upper surface of the cold-end substrate, the lower surface of the left end of the copper clip 21 is interconnected with the upper surface of the power semiconductor chip, the lower surface of the right end is interconnected with the upper surface of the cold-end substrate 15, and the upper surface of the left end of the copper clip is interconnected with the lower surface of the type of cold-end substrate;

[0098] Preferably, the thickness of the first type hot end substrate, the first type cold end substrate, and the second type hot end substrate are all 1.0 mm, and the thickness of the second type cold end substrate is 0.3 mm;

[0099] Preferably, the height of the first type of N-type semiconductor and the first type of P-type semiconductor are both 4 mm, the height of the second type of N-type semiconductor and the second type of P-type semiconductor are both 0.6 mm, and the currents passing through the N-type semiconductor and the P-type semiconductor are in opposite directions, forming a certain temperature difference between the upper and lower surfaces of the semiconductor;

[0100] Preferably, the first type of hot end substrate, the first type of cold end substrate, the second type of hot end substrate, and the second type of cold end substrate are all ceramics, and the material thereof is beryllium oxide;

[0101] Preferably, a first circuit layer is disposed on the upper surface of a type of hot end substrate, and a type of N-type semiconductor and a type of P-type semiconductor are interconnected with the first circuit layer on their lower surfaces;

[0102] Preferably, a second circuit layer is arranged on the lower surface of a cold end substrate, a third circuit layer is arranged on the upper surface, an N-type semiconductor and a P-type semiconductor are interconnected on the upper surface with the second circuit layer, a power semiconductor chip and a power terminal are interconnected on the lower surface with the third circuit layer through a first solder layer, and a copper clip is interconnected on the lower surface of the right end with the third circuit layer through a second solder layer;

[0103] Preferably, a fourth circuit layer is arranged on the lower surface of the second type hot end substrate, and the upper surfaces of the second type N-type semiconductor and the second type P-type semiconductor are interconnected with the fourth circuit layer; a fifth circuit layer is arranged on the upper surface of the second type cold end substrate, and a sixth circuit layer is arranged on the lower surface, and the lower surfaces of the second type N-type semiconductor and the second type P-type semiconductor are interconnected with the fifth circuit layer, and the upper surface of the left end of the copper clip is interconnected with the sixth circuit layer on the lower surface of the second type cold end substrate through a thermal interface material;

[0104] Preferably, the power semiconductor chip is made of silicon, the upper surface of which is interconnected with the lower surface of the left end of the copper clip through a second solder layer, and the upper surface of which is electrically connected to the third circuit layer on the upper surface of a cold end substrate through a bonding wire;

[0105] Preferably, the thermal interface material is nanosilver, the first solder layer is gold-tin, and the second solder layer is tin-bismuth;

[0106] Preferably, the bonding wire is an aluminum ribbon;

[0107] Embodiment 3 of the present invention further provides a method for preparing a double-sided heat dissipation structure of a power semiconductor device, the method comprising the following steps:

[0108] The first step is to provide a first type of hot end substrate 10, a first type of N-type semiconductor 12, a first type of P-type semiconductor 13, a first type of cold end substrate 15, a second type of hot end substrate 23, a second type of N-type semiconductor 25, a second type of P-type semiconductor 26, and a second type of cold end substrate 28, interconnect the lower surfaces of the first type of N-type semiconductor and the first type of P-type semiconductor with the first circuit layer 11 on the upper surface of the first type of hot end substrate, and interconnect the upper surfaces of the second type of N-type semiconductor and the second type of P-type semiconductor with the fourth circuit layer 24 on the lower surface of the second type of hot end substrate;

[0109] In the second step, the upper surfaces of the first type of N-type semiconductors and the first type of P-type semiconductors are interconnected with the second circuit layer 14 on the lower surface of the first type of cold-end substrate, and the lower surfaces of the second type of N-type semiconductors and the second type of P-type semiconductors are interconnected with the fifth circuit layer 27 on the upper surface of the second type of cold-end substrate;

[0110] The third step is to interconnect the power semiconductor chip 18 and the lower surface of the power terminal 19 with the third circuit layer 16 on the upper surface of a type of cold end substrate through the first solder layer 17;

[0111] In the fourth step, the upper surface of the power semiconductor chip 18 is electrically connected to the third circuit layer on the upper surface of a type of cold end substrate through the bonding wire 20;

[0112] Step 5: interconnect the lower surface of the left end of the copper clip with the upper surface of the power semiconductor chip through the second solder layer 22, and interconnect the lower surface of the right end of the copper clip with the third circuit layer on the upper surface of the first type of cold end substrate through the second solder layer;

[0113] In the sixth step, the sixth circuit layer 29 on the lower surface of the second type cold end substrate and the upper surface of the left end of the copper clip are interconnected through the thermal interface material 30, thereby obtaining a double-sided heat dissipation structure of the power semiconductor device.

[0114] The above are only preferred specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A double-sided heat dissipation structure for a power semiconductor device, characterized in that: include: Arranged in order from bottom to top are a first type of hot end substrate (10), a first conductor layer, a first type of cold end substrate (15), a third circuit layer (16) of the first type of cold end substrate, a plurality of power semiconductor chips (18), a plurality of thermal interface materials (30), a sixth circuit layer (29) of the second type of cold end substrate, a plurality of second type of cold end substrates (28), a second conductor layer, a third conductor layer and a second type of hot end substrate (23), wherein the lower surface of the first thermal interface material is connected to the third circuit layer (16) of the first type of cold end substrate via a copper clip (21), and the second conductor layer and the third conductor layer are arranged in parallel.

2. A double-sided heat dissipation structure for a power semiconductor device according to claim 1, characterized in that: The first conductor layer comprises: a plurality of hot end substrate circuit layers, a plurality of N-type semiconductors (12), a plurality of P-type semiconductors (13) and a plurality of cold end substrate circuit layers arranged in a regular manner, wherein a plurality of N-type semiconductors (12) and a plurality of P-type semiconductors (13) are alternately arranged between the hot end substrate circuit layers and the cold end substrate circuit layers, and a certain gap is left between the N-type semiconductors (12) and the P-type semiconductors (13), and the regular arrangement is as follows: the lower end of the N-type first semiconductor is aligned with the right edge of the first circuit layer of the hot end substrate, the upper end of the N-type first semiconductor is aligned with the left edge of the first circuit layer of the cold end substrate, the upper end of the P-type first semiconductor is aligned with the right side of the first circuit layer of the cold end substrate, and the lower end of the P-type first semiconductor is aligned with the left edge of the second circuit layer of the hot end substrate.

3. A double-sided heat dissipation structure for a power semiconductor device according to claim 2, characterized in that: The third circuit layer (16) of the first type of cold end substrate is provided with a plurality of circuit layers of the first type of cold end substrate, wherein a first solder layer is provided on the first circuit layer of the first type of cold end substrate, the upper surface of the first solder layer is connected to the lower surface of the first power semiconductor chip, the upper surface of the first power semiconductor chip is connected to the upper surface of the second circuit layer of the first type of cold end substrate via a bonding wire (20), and the upper surface of the first power semiconductor chip is also connected to one end of a copper clip via a second solder layer; The other end of the copper clip is connected to the third circuit layer of a type of cold end substrate through a second welding layer; The third circuit layer of the first type of cold end substrate is also provided with a first solder layer, the upper surface of the first solder layer is connected to the lower surface of the second power semiconductor chip, the upper surface of the second power semiconductor chip is connected to the upper surface of the fourth circuit layer of the first type of cold end substrate via a bonding wire (20), and the upper surface of the second power semiconductor chip is also connected to one end of the copper clip via a second solder layer; The other end of the copper clip is connected to the fifth circuit layer of a type of cold end substrate through a second welding layer.

4. A double-sided heat dissipation structure for a power semiconductor device according to claim 3, characterized in that: A power terminal (19) is also provided on the first welding layer on the first circuit layer of the first type of cold end substrate and the fifth circuit layer of the first type of cold end substrate.

5. A double-sided heat dissipation structure for a power semiconductor device according to claim 4, characterized in that: The second conductor layer and the third conductor layer both comprise: a plurality of second-type hot-end substrate circuit layers, a plurality of second-type N-type semiconductors (25), a plurality of second-type P-type semiconductors (26) and a plurality of second-type cold-end substrate circuit layers arranged in a regular manner, wherein the second-type N-type semiconductors (25) and the second-type P-type semiconductors (26) are alternately arranged between the second-type hot-end substrate circuit layers and the second-type cold-end substrate circuit layers, and a certain gap is left between the second-type N-type semiconductors (25) and the second-type P-type semiconductors (26), and the regular arrangement is: the lower end of the second-type N-type first semiconductor is aligned with the left edge of the second-type hot-end substrate first circuit layer, the upper end of the second-type N-type first semiconductor is aligned with the right edge of the second-type cold-end substrate first circuit layer, the upper end of the second-type P-type first semiconductor is aligned with the left side of the second-type cold-end substrate second circuit layer, and the lower end of the second-type P-type first semiconductor is aligned with the right edge of the second-type hot-end substrate second circuit layer.

6. A double-sided heat dissipation structure for a power semiconductor device according to claim 1, characterized in that: The thickness of the first-class hot end substrate (10), the first-class cold end substrate (15), and the second-class hot end substrate (23) are all 0.5 to 3.0 mm, and the thickness of the second-class cold end substrate (28) is 0.2 to 0.8 mm.

7. A double-sided heat dissipation structure for a power semiconductor device according to claim 5, characterized in that: The heights of the first type N-type semiconductor (12) and the first type P-type semiconductor (13) are both 1 to 5 mm, and the heights of the second type N-type semiconductor (25) and the second type P-type semiconductor (26) are both 0.2 to 1 mm. The directions of the currents passing through the N-type semiconductor and the P-type semiconductor are opposite, forming a certain temperature difference between the upper and lower surfaces of the semiconductor.

8. A double-sided heat dissipation structure for a power semiconductor device according to claim 7, characterized in that: The material of the power semiconductor chip (18) is one of gallium nitride, silicon carbide and silicon; The thermal interface material (30) is one of thermal conductive silicone grease, nano silver and nano copper; The materials of the first solder layer (17) and the second solder layer (22) are one or more of gold-tin, tin-lead, tin-silver-copper, tin-bismuth, nano-silver, and nano-copper; The material of the bonding wire (20) is one of aluminum wire, aluminum ribbon and copper wire.

9. A method for preparing a double-sided heat dissipation structure of a power semiconductor device, characterized in that: include: S1, obtaining a first type of hot end substrate (10), a first type of N-type semiconductor (12), a first type of P-type semiconductor (13), a first type of cold end substrate (15), a second type of hot end substrate (23), a second type of N-type semiconductor (25), a second type of P-type semiconductor (26), and a second type of cold end substrate (28); S2, interconnecting the lower surface of the first type of N-type semiconductor (12) and the first type of P-type semiconductor (13) with the first circuit layer of the upper surface of the first type of hot end substrate (10), interconnecting the upper surface of the first type of N-type semiconductor (12) and the first type of P-type semiconductor (13) with the second circuit layer of the lower surface of the first type of cold end substrate (15), interconnecting the upper surface of the second type of N-type semiconductor (25) and the second type of P-type semiconductor (26) with the fourth circuit layer of the lower surface of the second type of hot end substrate (23), and interconnecting the lower surface of the second type of N-type semiconductor (25) and the second type of P-type semiconductor (26) with the fifth circuit layer of the upper surface of the second type of cold end substrate (28); S3, interconnecting the lower surface of the power semiconductor chip (18) and the power terminal (19) with the third circuit layer on the upper surface of a type of cold end substrate (15) through the first solder layer (17); The upper surface of the power semiconductor chip (18) is electrically connected to the third circuit layer on the upper surface of a type of cold end substrate (15) via a bonding wire (20); S4, interconnecting the lower surface of the left end of the copper clip (21) with the upper surface of the power semiconductor chip (18) through the second solder layer (22), and interconnecting the lower surface of the right end of the copper clip (21) with the third circuit layer on the upper surface of a cold end substrate through the second solder layer (22); S5. The sixth circuit layer on the lower surface of the second type cold end substrate (23) and the upper surface of the left end of the copper clip (21) are interconnected via a thermal interface material (30), thereby obtaining a double-sided heat dissipation structure for a power semiconductor device.

Images