Semiconductor structure and test method of semiconductor structure

Abstract

The invention relates to a semiconductor structure and a test method of the semiconductor structure. The semiconductor structure comprises a substrate, an oxide layer, a tested structure and a test structure, and the oxide layer is located on the substrate; the tested structure comprises a tested groove, a first tested bonding pad and a second tested bonding pad; the tested bonding pad is located in the oxide layer, the tested groove is located between the first tested bonding pad and the second tested bonding pad, and part of the oxide layer located at the bottom of the tested groove has a first preset thickness; the test structure comprises a test groove, a test metal layer, a first test bonding pad and a second test bonding pad; the test bonding pad is located in the oxide layer, the test groove is located between the first test bonding pad and the second test bonding pad, the test metal layer is located between the bottom surface of the test groove and the substrate, the first test bonding pad is connected with the head end of the test metal layer, the second test bonding pad is connected to the tail end of the test metal layer, and the test metal layer has a second preset thickness; the second preset thickness is greater than the first preset thickness. The thickness of the oxide layer can be accurately monitored.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure and a testing method for the semiconductor structure. Background Art

[0002] In the field of semiconductor manufacturing technology, the thickness of the oxide layer may affect the capacitance or current characteristics, thereby affecting the performance of the transistor. For example, if the oxide layer is too thin, it may cause leakage, while if it is too thick, it may affect the switching speed of the device.

[0003] However, in the semiconductor manufacturing process, after the etching process, the oxide thickness is usually monitored by measuring the pad area at the edge of the structure. Since the pad is usually located at the edge of the wafer rather than in the etching area, traditional testing cannot directly monitor the oxide layer in the etching area, resulting in inaccurate monitoring results. Summary of the invention

[0004] Based on this, an embodiment of the present application provides a semiconductor structure and a method for testing the semiconductor structure.

[0005] According to some embodiments, the present application provides a semiconductor structure, which includes a substrate, an oxide layer, a structure to be tested and a test structure, wherein the oxide layer is located on the substrate; the structure to be tested includes a test groove, a first test pad and a second test pad; the test pad is located in the oxide layer, the test groove is located between the first test pad and the second test pad, and a portion of the oxide layer located at the bottom of the test groove has a first preset thickness; the test structure includes a test groove, a test metal layer, a first test pad and a second test pad; the test pad is located in the oxide layer, the test groove is located between the first test pad and the second test pad, the test metal layer is located between the bottom surface of the test groove and the substrate, the first test pad is connected to the head end of the test metal layer, the second test pad is connected to the end of the test metal layer, and the test metal layer has a second preset thickness; wherein the second preset thickness is greater than the first preset thickness.

[0006] In the semiconductor structure of the above embodiment, by setting the structure to be tested and the test structure, the thickness of the test metal layer in the test structure is greater than the partial oxide layer located at the bottom of the groove to be tested, and during synchronous etching, the test metal layer and the oxide layer will be removed by a certain thickness at the same time. Therefore, by obtaining the electrical parameters of the test metal layer, the remaining thickness of the oxide layer can be indirectly obtained, thereby realizing the monitoring of the first preset thickness of the oxide layer in the etching area, ensuring that the true thickness information of the oxide layer at the bottom of the groove to be tested in the etching area can be effectively captured, thereby improving the accuracy of monitoring, which is conducive to improving the stability of production and the reliability of products.

[0007] In some embodiments, there are multiple test grooves, and the multiple test grooves are arranged at intervals along the first direction; the test metal layer includes multiple test units connected end to end, the first test unit is connected to the first test pad, and the last test unit is connected to the second test pad; the number of test units is the same as the number of test grooves, and the test grooves are correspondingly located above the test units and extend along the second direction, and the second direction is perpendicular to the first direction.

[0008] In some embodiments, the test unit includes multiple metal strips connected end to end, and any two adjacent metal strips are perpendicular to each other; wherein the first metal strip in the first test unit is connected to the first test pad, the last metal strip in the first test unit is connected to the first metal strip in the next test unit, and the last metal strip in the last test unit is connected to the second test pad.

[0009] In some embodiments, the test unit includes a first test section and a second test section that are coupled to each other; the first test section includes a first branch extending along a first direction and a plurality of first metal strips arranged at intervals along a second direction, and the head ends of the plurality of first metal strips are respectively connected to the first branch; the second test section includes a second branch extending along the first direction and a plurality of second metal strips arranged at intervals along the second direction, and the head ends of the plurality of second metal strips are respectively connected to the second branch; wherein the first metal strips and the second metal strips are arranged alternately at intervals; the first branches in the plurality of test units are connected end to end, and the head end of the first branch in the first test unit is connected to the first test pad; the end of the second branch in the first test unit is connected to the head end of the second branch in the last test unit, and the ends of the second branches in the remaining test units are all connected to the second test pads.

[0010] In some embodiments, the second preset thickness is 1.5 to 3 times the first preset thickness.

[0011] In some embodiments, the first preset thickness is to

[0012] In some embodiments, the second preset thickness is

[0013] In some embodiments, the testing groove exposes a top surface of the testing metal layer; and a portion of the oxide layer between the bottom surface of the testing metal layer and the top surface of the substrate has a third preset thickness.

[0014] In some embodiments, the third preset thickness is to

[0015] In some embodiments, the structure under test also includes a buried metal layer located in the substrate, and the top surface of the buried metal layer is flush with the top surface of the substrate; the buried metal layer includes a first buried sub-metal layer, an intermediate buried sub-metal layer and a second buried sub-metal layer, the intermediate buried sub-metal layer is located at the bottom of the groove under test, and the first buried sub-metal layer and the second buried sub-metal layer are respectively located on both sides of the intermediate buried sub-metal layer and below the pad under test.

[0016] According to some embodiments, the present application further provides a method for testing a semiconductor structure, using the semiconductor structure in any of the above embodiments for testing; the method comprises:

[0017] obtaining initial electrical parameters of a test metal layer having an initial thickness;

[0018] Simultaneously etching the test metal layer and a portion of the oxide layer at the bottom of the groove to be tested for multiple times to obtain multiple measured electrical parameters of the test metal layer having different second preset thicknesses;

[0019] According to the difference between the initial electrical parameter and the measured electrical parameter, determining the corresponding relationship between the etching amount of the oxide layer and the difference;

[0020] According to the corresponding relationship, a first preset thickness of the oxide layer is determined.

[0021] In the semiconductor structure testing method of the above embodiment, the initial electrical parameters of the test metal layer with the initial thickness are obtained, and multiple measured electrical parameters of the test metal layer with different second preset thicknesses are obtained when the test metal layer and the partial oxide layer located at the bottom of the tested groove are etched multiple times at the same time. According to the difference between the initial electrical parameters and the measured electrical parameters, the corresponding relationship between the etching amount of the oxide layer and the difference is determined, thereby determining the first preset thickness of the oxide layer. Therefore, by obtaining the electrical parameters of the test metal layer before and after etching, the remaining thickness of the oxide layer after etching can be indirectly obtained, thereby realizing the monitoring of the first preset thickness of the oxide layer in the etching area, ensuring that the true thickness information of the partial oxide layer located at the bottom of the tested groove in the etching area can be effectively captured, thereby improving the accuracy of monitoring, which is conducive to improving the stability of production and the reliability of products. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 is a schematic top view of a semiconductor structure;

[0023] Figure 2 A schematic cross-sectional view of a semiconductor structure provided in one embodiment of the present application;

[0024] Figure 3 A schematic top view of a semiconductor structure provided in one embodiment of the present application;

[0025] Figure 4A schematic top view of another semiconductor structure provided in one embodiment of the present application;

[0026] Figure 5 A schematic diagram of a flow chart of a semiconductor structure testing method provided in one embodiment of the present application.

[0027] Explanation of the markings in the accompanying drawings: 10, substrate; 20, oxide layer; 30, structure under test; 31, groove under test; 32, first pad under test; 33, second pad under test; 34, buried metal layer; 341, first buried sub-metal layer; 342, middle buried sub-metal layer; 343, second buried sub-metal layer; 35, first through hole; 40, test structure; 41, test groove; 42, first test pad; 43, second test pad; 44, test metal layer; 440, test unit; 4401; metal strip; 441, first test part; 4411, first branch; 4412, first metal strip; 442, second test part; 4421, second branch; 4422, second metal strip; 45, second through hole; 46, connecting metal layer; 50, test area. DETAILED DESCRIPTION

[0028] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Preferred embodiments of the present invention are provided in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present invention more thorough and comprehensive.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0030] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0031] In addition, in order to clearly indicate the multiple layers and regions in the drawings, the thickness of each layer and each region in the drawings are enlarged to clearly illustrate the relative positions between the layers and the distribution of each region. When a layer, film, region, plate, etc. is expressed as being located on the "side" of another part, the expression includes not only the case where it is "directly" above the other part, but also the case where there are other layers in between. And, it is understood that when a layer, film, region, plate, etc. is expressed as being located on the "side" of another part, it generally refers to the side located directly above the other part.

[0032] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0033] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0034] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic representations of idealized embodiments (and intermediate structures) of the present disclosure, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shapes of the regions of the device, and do not limit the scope of the present disclosure.

[0035] See also Figure 1 In the semiconductor manufacturing process, monitoring of fuses and oxide layers is an important part of ensuring product quality and performance.

[0036] However, since the metal in the fuse test area 50 is relatively thin, the remaining thickness of the oxide layer thereon cannot be directly measured, resulting in the inability to monitor the remaining thickness of the oxide layer. Based on this, in order to solve the above problem, an embodiment of the present application provides a semiconductor structure and a testing method for a semiconductor structure.

[0037] See also Figures 2 to 4 Understand the following embodiments of the present application. According to some embodiments, the present application provides a semiconductor structure. The semiconductor structure includes a substrate 10 , an oxide layer 20 , a structure to be tested 30 , and a test structure 40 . The oxide layer 20 is located on the substrate 10; the structure to be tested 30 includes a tested groove 31, a first tested pad 32 and a second tested pad 33; the tested pad is located in the oxide layer 20, the tested groove 31 is located between the first tested pad 32 and the second tested pad 33, and the portion of the oxide layer 20 located at the bottom of the tested groove 31 has a first preset thickness H1; the test structure 40 includes a test groove 41, a test metal layer 44, a first test pad 42 and a second test pad 43; the test pad is located in the oxide layer 20, the test groove 41 is located between the first test pad 42 and the second test pad 43, the test metal layer 44 is located between the bottom surface of the test groove 41 and the substrate 10, the first test pad 42 is connected to the head end of the test metal layer 44, the second test pad 43 is connected to the end of the test metal layer 44, and the test metal layer 44 has a second preset thickness H2; wherein the second preset thickness H2 is greater than the first preset thickness H1.

[0038] In the semiconductor structure of the above embodiment, by setting the structure to be tested 30 and the test structure 40, the thickness of the test metal layer 44 in the test structure 40 is greater than the thickness of the partial oxide layer 20 located at the bottom of the groove to be tested 31. During the synchronous etching, the test metal layer 44 and the oxide layer 20 will be removed by a certain thickness at the same time. Therefore, by obtaining the electrical parameters of the test metal layer 44, the remaining thickness of the oxide layer 20 can be indirectly obtained, thereby realizing the monitoring of the first preset thickness H1 of the oxide layer 20 in the etching area, ensuring that the real thickness information of the partial oxide layer 20 located at the bottom of the groove to be tested 31 in the etching area can be effectively captured, thereby improving the accuracy of monitoring, which is conducive to improving the stability of production and the reliability of products.

[0039] As an example, in the embodiment of the present disclosure, the substrate 10 can be made of semiconductor material, insulating material, conductor material or any combination of their material types. The substrate 10 can be a single-layer structure or a multi-layer structure. For example, the substrate 10 can be a silicon (Si) substrate 10, a silicon germanium (SiGe) substrate 10, a silicon germanium carbon (SiGeC) substrate 10, a silicon carbide (SiC) substrate 10, a gallium arsenide (GaAs) substrate 10, an indium arsenide (InAs) substrate 10, an indium phosphide (InP) substrate 10 or other III / V semiconductor substrates 10 or II / VI semiconductor substrates 10. Alternatively, for example, the substrate 10 can be a layered substrate 10 including a stack of Si and SiGe, a stack of Si and SiC, a silicon on insulator (SOI) or a silicon germanium on an insulator. Those skilled in the art can select the type of substrate 10 according to the type of transistor formed on the substrate 10, so the type of substrate 10 should not limit the scope of protection of the present disclosure.

[0040] In some embodiments, the test metal layer 44 is made of a conductive material. For example, the conductive material may be a metal material, such as tin, titanium, tungsten, tantalum, molybdenum, cobalt, platinum, titanium tungsten or a combination thereof, for example, ruthenium, tungsten, gold or silver are all low-resistance metals, which can reduce the resistance of the test metal layer 44, and help improve the test accuracy of the semiconductor structure.

[0041] Combination Figure 3 and Figure 4 It is understood that in some embodiments, there are multiple test grooves 41, and the multiple test grooves 41 are arranged at intervals along the first direction. The first direction can be understood as Figure 3 In the Y direction shown, the plurality of test grooves 41 are parallel to each other.

[0042] In some embodiments, the test metal layer 44 includes a plurality of test units 440 connected end to end, the first test unit 440 is connected to the first test pad 42, and the last test unit 440 is connected to the second test pad 43; the number of the test units 440 is the same as the number of the test grooves 41, and the test grooves 41 are correspondingly located above the test units 440 and extend along the second direction, which is perpendicular to the first direction. The second direction can be understood as Figure 3 The X direction is shown.

[0043] like Figure 3 As shown, in some embodiments, the test unit 440 includes a plurality of metal strips connected end to end, and two adjacent metal strips are perpendicular to each other; wherein, the first metal strip in the first test unit 440 is connected to the first test pad 42, the last metal strip in the first test unit 440 is connected to the first metal strip in the next test unit 440, and the last metal strip in the last test unit 440 is connected to the second test pad 43. It can be understood that in the above embodiments, the resistance value of the test unit 440 can vary with its thickness, and therefore, the remaining thickness of the oxide layer 20 can be obtained by testing the resistance values ​​of the plurality of test units 440 in the metal layer 44, that is, the first preset thickness H1 of the partial oxide layer 20 located at the bottom of the tested groove 31 can be obtained.

[0044] like Figure 4As shown, in some embodiments, the test unit 440 includes a first test portion 4401 coupled to each other; a metal strip; 441 and a second test portion 442; the first test portion 4401; the metal strip; 441 includes a first branch 4411 extending along a first direction and a plurality of first metal strips 4412 arranged at intervals along a second direction, and the head ends of the plurality of first metal strips 4412 are respectively connected to the first branch 4411; the second test portion 442 includes a second branch 4421 extending along the first direction and a plurality of second metal strips 4422 arranged at intervals along the second direction, and the plurality of second metal strips 4422 are respectively connected to the first branch 4411; The head ends of the strips 4422 are respectively connected to the second branches 4421; wherein the first metal strips 4412 and the second metal strips 4422 are arranged alternately; the first branches 4411 in the plurality of test units 440 are connected end to end, and the head end of the first branch 4411 in the first test unit 440 is connected to the first test pad 42; the end of the second branch 4421 in the first test unit 440 is connected to the head end of the second branch 4421 in the last test unit 440, and the ends of the second branches 4421 in the remaining test units 440 are all connected to the second test pad 43. It can be understood that in the above embodiment, the capacitance value of the test unit 440 can vary with its thickness, and the isolation performance between the first metal strip 4412 and the second metal strip 4422 is weakened after etching, making it easier to be broken down by voltage. Therefore, the remaining thickness of the oxide layer 20 can be obtained by testing the capacitance values ​​and isolation voltages of the plurality of test units 440 in the metal layer 44, that is, the first preset thickness H1 of the partial oxide layer 20 located at the bottom of the groove 31 to be tested can be obtained.

[0045] In some embodiments, in the same test unit 440 , the number of the first metal strips 4412 and the number of the second metal strips 4422 are the same.

[0046] like Figure 2 As shown, in some embodiments, the second preset thickness H2 is 1.5 to 3 times the first preset thickness H1. For example, the second preset thickness H2 is 1.5 times, 2 times, 2.5 times or 3 times the first preset thickness H1.

[0047] In some embodiments, the first preset thickness H1 is to For example, the first preset thickness H1 is or wait.

[0048] In some embodiments, the second preset thickness H2 is

[0049] like Figure 2As shown, in some embodiments, the test groove 41 exposes the top surface of the test metal layer 44 ; the portion of the oxide layer 20 between the bottom surface of the test metal layer 44 and the top surface of the substrate 10 has a third preset thickness H3 .

[0050] In some embodiments, the third preset thickness H3 is to For example, the third preset thickness H3 is or It can be understood that the third preset thickness H3 is smaller in magnitude than the first preset thickness and the second preset thickness, so during measurement, the influence of the third preset thickness H3 can be ignored.

[0051] like Figure 2 As shown, in some embodiments, the structure under test 30 also includes a buried metal layer 34 located in the substrate 10, and the top surface of the buried metal layer 34 is flush with the top surface of the substrate 10; the buried metal layer 34 includes a first buried sub-metal layer 341, an intermediate buried sub-metal layer 342 and a second buried sub-metal layer 343, the intermediate buried sub-metal layer 342 is located at the bottom of the groove under test 31, and the first buried sub-metal layer 341 and the second buried sub-metal layer 343 are respectively located on both sides of the intermediate buried sub-metal layer 342 and below the pad under test.

[0052] In some embodiments, the structure under test 30 further includes at least two first through holes 35 , and the two first through holes 35 are respectively located between the first pad under test 32 and the first buried sub-metal layer 341 , and between the second pad under test 33 and the second buried sub-metal layer 343 .

[0053] In some embodiments, the test structure 40 further includes at least two second through holes 45 , and the two second through holes 45 are respectively located between the first test pad 42 , the second test pad 43 and the test metal layer 44 .

[0054] In some embodiments, the test structure 40 further includes a connection metal layer 46 located within the substrate 10 .

[0055] Please combine Figures 2 to 5 It is understood that according to some embodiments, the present application also provides a method for testing a semiconductor structure, using the semiconductor structure in any of the above embodiments for testing; the method includes:

[0056] Step S10, obtaining initial electrical parameters of the test metal layer 44 having an initial thickness;

[0057] Step S30, etching the test metal layer 44 and the portion of the oxide layer 20 located at the bottom of the tested groove 31 for multiple times simultaneously to obtain multiple measured electrical parameters of the test metal layer 44 with different second preset thicknesses;

[0058] Step S50, determining the corresponding relationship between the etching amount of the oxide layer 20 and the difference according to the difference between the initial electrical parameter and the measured electrical parameter;

[0059] Step S70 , determining a first preset thickness H1 of the oxide layer 20 according to the corresponding relationship.

[0060] In the semiconductor structure testing method of the above embodiment, the initial electrical parameters of the test metal layer 44 with the initial thickness are obtained, and multiple measured electrical parameters of the test metal layer 44 with different second preset thicknesses are obtained when the test metal layer 44 and the partial oxide layer 20 located at the bottom of the tested groove 31 are etched multiple times at the same time. According to the difference between the initial electrical parameters and the measured electrical parameters, the corresponding relationship between the etching amount of the oxide layer 20 and the difference is determined, thereby determining the first preset thickness of the oxide layer 20. Therefore, by obtaining the electrical parameters of the test metal layer 44 before and after etching, the remaining thickness of the oxide layer 20 after etching can be indirectly obtained, thereby realizing the monitoring of the first preset thickness H1 of the partial oxide layer 20 located at the bottom of the tested groove 31 in the etching area, ensuring that the real thickness information of the partial oxide layer 20 located at the bottom of the tested groove 31 in the etching area can be effectively captured, thereby improving the accuracy of monitoring, which is conducive to improving the stability of production and the reliability of products.

[0061] In some embodiments, in step S50, the correspondence between the etching amount of the oxide layer 20 and the difference is determined based on the difference between the initial electrical parameters and the measured electrical parameters. The correspondence between the etching amount of the oxide layer 20 and the difference can be determined by establishing a scale between the etching amount of the oxide layer 20 and the difference.

[0062] For example, the electrical parameters include resistance values, capacitance values ​​or voltage values, and appropriate electrical parameters can be selected for measurement according to different test structures and settings of the structure under test.

[0063] In some embodiments, the test metal layer 44 includes a plurality of test units 440 connected end to end, the first test unit 440 is connected to the first test pad 42, and the last test unit 440 is connected to the second test pad 43; the number of the test units 440 is the same as the number of the test grooves 41, and the test grooves 41 are correspondingly located above the test units 440 and extend along a second direction, and the second direction is perpendicular to the first direction.

[0064] like Figure 3 As shown, in some embodiments, the test unit 440 includes multiple metal strips connected end to end, and two adjacent metal strips are perpendicular to each other; wherein, the first metal strip in the first test unit 440 is connected to the first test pad 42, the last metal strip in the first test unit 440 is connected to the first metal strip in the next test unit 440, and the last metal strip in the last test unit 440 is connected to the second test pad 43.

[0065] In such Figure 3 In the illustrated embodiment, step S10, obtaining initial electrical parameters of the test metal layer 44 having an initial thickness, comprises:

[0066] Step S11 : obtaining an initial resistance value of the test metal layer 44 having an initial thickness.

[0067] In such Figure 3 In the illustrated embodiment, step S30, etching the test metal layer 44 and the portion of the oxide layer 20 at the bottom of the tested groove 31 for multiple times simultaneously to obtain multiple measured electrical parameters of the test metal layer 44 having different second preset thicknesses, includes:

[0068] Step S31 , etching the test metal layer 44 and the portion of the oxide layer 20 at the bottom of the tested groove 31 for multiple times simultaneously to obtain multiple measured resistance values ​​of the test metal layer 44 with different second preset thicknesses.

[0069] In such Figure 3 In the illustrated embodiment, step S50, determining the corresponding relationship between the etching amount of the oxide layer 20 and the difference between the initial electrical parameter and the measured electrical parameter, includes:

[0070] Step S51 : determining a corresponding relationship between an etching amount of the oxide layer 20 and the difference value according to a difference value between an initial resistance value and a measured resistance value.

[0071] like Figure 4 As shown, in some embodiments, the test unit 440 includes a first test portion 4401 coupled to each other; a metal strip; 441 and a second test portion 442; the first test portion 4401; the metal strip; 441 includes a first branch 4411 extending along a first direction and a plurality of first metal strips 4412 arranged at intervals along a second direction, and the head ends of the plurality of first metal strips 4412 are respectively connected to the first branch 4411; the second test portion 442 includes a second branch 4421 extending along the first direction and a plurality of second metal strips 4422 arranged at intervals along the second direction, and the plurality of second metal strips 4422 are respectively connected to the first branch 4411; The head ends of the strips 4422 are respectively connected to the second branches 4421; wherein the first metal strips 4412 and the second metal strips 4422 are arranged alternately; the first branches 4411 in the multiple test units 440 are connected end to end, and the head end of the first branch 4411 in the first test unit 440 is connected to the first test pad 42; the end of the second branch 4421 in the first test unit 440 is connected to the head end of the second branch 4421 in the last test unit 440, and the ends of the second branches 4421 in the remaining test units 440 are all connected to the second test pad 43.

[0072] In such Figure 4In the illustrated embodiment, step S10, obtaining initial electrical parameters of the test metal layer 44 having an initial thickness, comprises:

[0073] Step S11 : obtaining an initial capacitance value or an initial voltage value of the test metal layer 44 having an initial thickness.

[0074] In such Figure 4 In the illustrated embodiment, step S30, etching the test metal layer 44 and the portion of the oxide layer 20 at the bottom of the tested groove 31 for multiple times simultaneously to obtain multiple measured electrical parameters of the test metal layer 44 having different second preset thicknesses, includes:

[0075] Step S31 , etching the test metal layer 44 and the portion of the oxide layer 20 at the bottom of the tested groove 31 for multiple times simultaneously to obtain multiple measured capacitance values ​​or measured voltage values ​​of the test metal layer 44 with different second preset thicknesses.

[0076] In such Figure 4 In the illustrated embodiment, step S50, determining the corresponding relationship between the etching amount of the oxide layer 20 and the difference between the initial electrical parameter and the measured electrical parameter, includes:

[0077] Step S51 : determining a corresponding relationship between an etching amount of the oxide layer 20 and the difference according to a difference between an initial capacitance value and a measured capacitance value, or a difference between an initial voltage value and a measured voltage value.

[0078] In the above embodiments of the present disclosure, unless otherwise specified herein, the execution of each step in the method is not strictly limited in order, and these steps may not necessarily be executed in the order described, and may be executed in other ways. Moreover, at least a part of any step may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but may be executed at different times, and the execution order of these sub-steps or stages is not necessarily sequential, but may be executed in turn or alternately with other steps or at least a part of the sub-steps or stages of other steps.

[0079] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0080] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A semiconductor structure, characterized in that: It includes a substrate, an oxide layer, a structure to be tested and a test structure, wherein the oxide layer is located on the substrate; The structure to be tested includes a tested groove, a first tested pad and a second tested pad; the tested pad is located in the oxide layer, the tested groove is located between the first tested pad and the second tested pad, and the oxide layer at the bottom of the tested groove has a first preset thickness; The test structure comprises a test groove, a test metal layer, a first test pad and a second test pad; the test pad is located in the oxide layer, the test groove is located between the first test pad and the second test pad, the test metal layer is located between the bottom surface of the test groove and the substrate, the first test pad is connected to the head end of the test metal layer, the second test pad is connected to the end of the test metal layer, and the test metal layer has a second preset thickness; Wherein, the second preset thickness is greater than the first preset thickness.

2. The semiconductor structure according to claim 1, characterized in that: There are a plurality of test grooves, and the plurality of test grooves are arranged at intervals along a first direction; The test metal layer includes a plurality of test units connected end to end, the first test unit is connected to the first test pad, and the last test unit is connected to the second test pad; The number of the test units is the same as the number of the test grooves. The test grooves are correspondingly located above the test units and extend along a second direction, and the second direction is perpendicular to the first direction.

3. The semiconductor structure according to claim 2, characterized in that: The test unit includes a plurality of metal strips connected end to end, and two adjacent metal strips are perpendicular to each other; Among them, the first metal strip in the first test unit is connected to the first test pad, the last metal strip in the first test unit is connected to the first metal strip in the next test unit, and the last metal strip in the last test unit is connected to the second test pad.

4. The semiconductor structure according to claim 2, characterized in that: The test unit includes a first test section and a second test section coupled to each other; The first testing portion includes a first branch extending along the first direction and a plurality of first metal strips arranged at intervals along the second direction, and the head ends of the plurality of first metal strips are respectively connected to the first branch; The second testing portion includes a second branch extending along the first direction and a plurality of second metal strips arranged at intervals along the second direction, and the head ends of the plurality of second metal strips are respectively connected to the second branch; Among them, the first metal strips and the second metal strips are arranged alternately at intervals; the first branches in multiple test units are connected end to end, and the head end of the first branch in the first test unit is connected to the first test pad; the end of the second branch in the first test unit is connected to the head end of the second branch in the last test unit, and the ends of the second branches in the remaining test units are all connected to the second test pad.

5. The semiconductor structure according to any one of claims 2 to 4, characterized in that: The second preset thickness is 1.5 to 3 times the first preset thickness.

6. The semiconductor structure according to claim 5, characterized in that: The first preset thickness is to And / or the second preset thickness is 7. The semiconductor structure according to any one of claims 2 to 4, characterized in that: The testing groove exposes the top surface of the testing metal layer; A portion of the oxide layer between the bottom surface of the testing metal layer and the top surface of the substrate has a third preset thickness.

8. The semiconductor structure according to claim 7, characterized in that: The third preset thickness is to 9. The semiconductor structure according to any one of claims 2 to 4, characterized in that: The structure under test further comprises a buried metal layer located in the substrate, wherein a top surface of the buried metal layer is flush with a top surface of the substrate; The buried metal layer includes a first buried sub-metal layer, an intermediate buried sub-metal layer and a second buried sub-metal layer. The intermediate buried sub-metal layer is located at the bottom of the groove to be tested. The first buried sub-metal layer and the second buried sub-metal layer are respectively located on both sides of the intermediate buried sub-metal layer and below the pad to be tested.

10. A method for testing a semiconductor structure, characterized in that: A method for testing a semiconductor structure according to any one of claims 1 to 9, wherein the method comprises: Acquiring initial electrical parameters of the test metal layer having an initial thickness; Simultaneously etching the test metal layer and a portion of the oxide layer located at the bottom of the tested groove for multiple times to obtain multiple measured electrical parameters of the test metal layer having different second preset thicknesses; Determining a corresponding relationship between an etching amount of the oxide layer and the difference between the initial electrical parameter and the measured electrical parameter according to the difference between the initial electrical parameter and the measured electrical parameter; According to the corresponding relationship, a first preset thickness of the oxide layer is determined.

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